1、DC-MHS Overview&UpdateIT Ecosystem:Server&StorageDC-MHS Overview&UpdatePaul Artman,Director System Design,AMDDirk Blevins,Senior Platform Architect&Principal Engineer,Intel CorporationRob Nance,Director of Technology,JabilNew Model w/DC-MHSM-XIO/PESTIWorkstreamCharlie Z.(Dell)Javier L.(Intel)Open Co
2、mpute DC-MHS Sub-ProjectBrian Aspnes(Intel)Shawn Dube(Dell)M-PICWorkstreamTim L.(Dell)Cliff D.(Intel)M-CRPSWorkstreamJon L.(Dell)Aurelio R.(Intel)M-HPMWorkstreamCorey H.(Dell)Brian A.(Intel)M-FLWSpecificationCorey H.(Dell)Brian A.(Intel)Mechanics of CollaborationM-SIFWorkstreamGreg S.(AMD)Dirk B.(In
3、tel)M-DNOSpecificationMike G.(Dell)Dirk B.(Intel)M-HPM.nextSpecificationTBD(TBD)TBD(TBD)DC-MHS=Datacenter Modular Hardware System1.Modular Host Processor Modules(M-HPM)oModular FulL Width HPMs(M-FLW)oModular DeNsityOptimized HPMs(M-DNO)oModular Next HPMs(M-HPM.next)2.Modular PlatformInfrastructure C
4、onnectivity(M-PIC)3.Modular Common Redundant Power Supply(M-CRPS)4.Modular eXtensibleI/O(M-XIO)+Modular PEripheralSideband Tunneling Interface(M-PESTI)5.Modular SharedInFrastructure(M-SIF)Six v1.0 specifications were released to the OCP Contribution Database in September 2022Plan to continue develop
5、ing the v1.x specificationsDC-MHS WIKI contains specification updates,eratta,updated modeshttps:/www.opencompute.org/wiki/Server/DC-MHS2023 focused on three new specifications in addition to spec updatesM-HPM.nextSpecificationSpecification optimized around wider HPMs and ORv348V System Architecture
6、SpecificationM-SIF SpecificationShared infrastructure focused on shared Cooling,Power,I/O and ManagementDC-MHS Update for 2023Next HPM Form Factors ScopeDC-MHS Home Page:https:/www.opencompute.org/projects/dc-mhsDC-MHS WIKI:https:/www.opencompute.org/wiki/Server/DC-MHSDC-MHS Mailing List:https:/ocp-
7、all.groups.io/g/OCP-DC-MHSMonthly open meetings start March 15th 8am PT reoccur 3rdWED monthlyMeeting logistics provided on DC-MHS Home Page Call CalendarMeeting Minutes/Agenda sent to:OCP-DC-MHSOCP-All.groups.ioDC-MHS Official SubprojectJabil Builds with DC-MHSProducts Jabils Building-1S/2S Cloud s
8、ervers in 1U/2U chassis-Potential for Edge/Telco serversLeveraging DC-MHS building blocks-Chassis,HPM(s),DC-SCM,OCP Mezz,I/O riser,PDB,fan board,drive mid-plane,power supplies2S Products(FLW HPM)and 1S Products(DNO HPM)-A single FLW HPM and a single DNO HPM leveraged for all current generation produ
9、ctsChassis-leverage between FLW and DNO is required by Jabil solutionsBuilding blocks“future proofed”to be leveraged into future generations High-level Product Architecture-Boards,except risers,are shared between 1U and 2U chassis-Fan,PDB,risers and I/O card are not leveraged between FLW and DNOProg
10、rammable Parts-LTPI and HWROT are implemented using varied solutions(FPGA,ASIC,CPLD,etc.)-LTPI and HWROT may be combined on DC-SCM-Not all LTPI implementations are created equal,pay attention to plug and recode considerationsPLDPLDLTPISignalsOther ConsiderationsDC-SCM form-factor-Vertical vs Horizon
11、tal(look to help resolve in HPM.Next&DC-SCM 3.0)-Short Depth solutions drive embedded SCM considerations PESTI implementation-Jabil chose to fully implement PESTI in HW but transition from VPD to PESTI over time in FWLeverage Enabled by DC-MHS Architecture-DC-MHS significantly reduces the effort req
12、uired to achieve generation-to-generation leverage-Reduced development time and cost-Increased reliability and stability with leverage generation-to-generationGen-to-Gen Leverage Is Critically ImportantGoal:The goal of M-SIF is to extend the scope of DC-MHS and to comprehend what platforms built for
13、 shared infrastructure may look like.M-SIF aims to improve interoperability related to shared infrastructure enclosures with multiple,serviceable modules.Modules containing elements(HPMs,DC-SCMs,peripherals,etc.)may be blind-matable and/or hot-pluggable within a shared infrastructure enclosure.Outpu
14、t:Define a logical,super-set model of a shared infrastructure solutionDefine interfaces between modules and shared infrastructure including signaling and physical connectivity for power,cooling,management,and I/O links,specifically PCIe/CXLDefine use cases and block diagrams of specific solutionsEna
15、ble HPMs to natively support shared infrastructure capabilities in future versions of HPM specificationsShow module/sled form factors that may be used in different enclosuresShow example enclosures that may use the above example sled form factorsM-SIF Tenets/Overviewperipheral asan elementperipheral
16、 asan elementNote:Not and exhaustive list of possible systems or configurationsExample Shared Infrastructure PlatformsHigh-Speed InterconnectChassisManagementNode 1Node 2Node 3Node“n-1”PowerShared ChassisInfrastructure ElementsMulti-Host PCIe/CXL ElementMulti-Host PCIe/CXL ElementShared ElementsCore
17、 ElementsMulti-Host PCIe/CXL ElementNode“n”Examples:NICDPUIPUGPUAcceleratorsSwitchesMemoryStorageExamples:Host ComputePeripheralsAccelerationShared Infrastructure BoundaryPCIe/CXL based Intra-chassis fabric“External”Fabric InterfacesCoolingExternal Fabric(Outside of M-SIF Scope)Management PlaneChass
18、isManagerNode 1Node 2Node 3Node“n-1”PowerShared ChassisInfrastructure ElementsShared ElementsCore ElementsNode“n”Shared Infrastructure BoundaryCore/Shared Element Mgmt InterfacePower Control Interface LTPIThermal Control Interface I2CManagement Network Into PlatformCoolingAggregatorManagement Networ
19、kThermalControlPowerControlMulti-Host PCIe/CXL ElementMulti-Host PCIe/CXL ElementMulti-Host PCIe/CXL ElementHSI&Management CoreElementSledMNGMNT InterfacePower InterfaceDataSlice 0I/FDataSlice nI/FDataSliceInterfaceOn HPM16 PCIe/CXL lanesREFCLK_OUT_p/n3:0REFCLK_IN_p/n3:015:1211:87:43:0 x4x4x4x4x4x4x
20、4x4x8x8PCIe Lane Mappingx16x8x8Management InterfaceOn HPMPESTI/PRESENTKX_KR_TX_p/n2-WIRE(I2C/I3C)PRESENTPERST_OUT_N3:0PERST_IN_N3:0Data Slice Bifurcation&Directionality is negotiated over the management interfacesKX_KR_RX_p/nUSB_D+USB_D-FORCE_THROTTLELooking to reduce signal count further!How to get
21、 involved in the DC_MHS Community dcmhsopencompute.orgattn.Shawn Dube(Dell)&Brian Aspnes(Intel)Current Available Specifications-https:/www.opencompute.org/wiki/Server/DC-MHSM-DNO-https:/www.opencompute.org/documents/m-dno-r1-v1p0-rc5-pdfM-FLW-https:/www.opencompute.org/documents/m-flw-r1-v1p0-rc5-pdfM-XIO-https:/ NIC 3.0-https:/ StepsThank you!Please direct comments and questions to:M-SIF Leads m-sif_leadsopencompute.org-or-Dirk Blevins(M-SIF Co-lead)Greg Sellman(M-SIF Co-lead)Gregory.SFeedback