A Chiplet Reference Platform Utilizing OCP Bunch-of-Wires.pdf

1、A Chiplet Reference Platform Utilizing OCP Bunch-of-WiresChipletsA Chiplet Reference Platform Utilizing OCP Bunch-of-WiresAndy Heinig,Head of Department Efficient ElectronicsFabian Hopsch,Advanced System IntegrationPresentation Starts HereTechnical content is desiredOpen,collaborative in nature,mate

2、rial must be relevant to an open-source communityMust not be a product advertisement or too“commercial”in the messagingProducts,Specs,and any contributions that have NOT been previously discussed in a monthly call,workshop,or previously approved by the foundation should NOT be disclosed in an engine

3、ering workshop.No future discussions about contributions without a Contribution License Agreement in placePresentation Starts HereTechnical content is desiredOpen,collaborative in nature,material must be relevant to an open-source communityMust not be a product advertisement or too“commercial”in the

4、 messagingProducts,Specs,and any contributions that have NOT been previously discussed in a monthly call,workshop,or previously approved by the foundation should NOT be disclosed in an engineering workshop.No future discussions about contributions without a Contribution License Agreement in placeBui

5、lding a Chiplet Ecosystem Work for youCollaborate:Samsung,Cadence&FraunhoferWorking with YOU!5Innovate:Silicon Proven HPC/ChipletDevelopment Platform Silicon&SW Customized for you specific needs Grow:Accelerate Designs and Build Products Faster with lower Costs and RiskNNA110(x2)PCIe6LX-SSVQ8(2MC)NX

6、MemDDR5BoWD2DBoW Chiplet PlatformVQ8(2MC)BoW-Bunch of Wires:Industry standard D2D interfaceFraunhofers Design Strength and Capabilities Worlds leading organization for applied researchIdentification of newest research results for next generation customer productsDesign and manufacturing of customer-

7、related demonstrators as showcases for the usage of the selected new technologiesOptimization of the demonstrators toward productsResearch in the field of advanced packaging(e.g.Chiplets,Antenna in Package,3D stacking)since more than 10 yearsConcept developmentDesign from system up to transistor lev

8、elDevelopment of customizeddesign methodologiesand design flowsRapid prototyping6Cadence:The Leader in Intelligent Systems DesignAI/MLData AnalyticsIP and Chip EDADigital,Custom,System Verification,and PackagingSystem DesignAlgorithm,SW,Multiphysics,CFD,PCBIntelligent System DesignMerger of EDA,syst

9、em design,AIPervasive intelligence throughout designGrounded in computational engineeringCo-optimizing system,hardware,softwareSpanning multiple system domainsSYSTEMINTELLIGENT DESIGNSamsung:World Leading FoundryAdvanced 300mm(12”)fabs in 5 locations(3 in Korea,2 in US)Matured 200mm(8”)fab for 180nm

10、65nm in KoreaBack-end(Test&Package)facilities in 3 locations(2 in Korea,1 in China)Fab S2Austin4),Texas,USATSP OY(Conventional PKG)Onyang7)Fab S4Fab S3Hwaseong2)Fab S5Pyeongtaek3)TSPCA(Advanced PKG)Cheonan6)Austin4)Pyeongtaek3)Hwaseong2)Giheung1)Cheonan6)Onyang7)Fab S6Taylor5),Texas,USATaylor5)Fab S

11、1Giheung1)Proven&Ready solution to customize to your specific needsIntegrationTechnologyScaleFaster time to market Accelerate Designs Enable early test vehicles Earlier product definition Co-development HW&SW Faster product bring-upLower risk supply chainBetter performance/power Integrated Solutions

12、-design to mfg.Leading edge Tools&Process Tech Proven IP:D2D,DDR,PCIe(CXL),AI,Vision DSPs Advanced Packaging:2.5D&3D Proven Platform Solution Proven SoC Silicon Integrated Flows,Technology&Manufacturing Customization capabilityAdvantages:Benefits:Leading edge technologies designed to work together E

13、DA,IP,Design Services,Foundry,PackagingAbility to access the best Integrated manufacturing at world-class scale7EDA enablementDK/PDKFoundationFlowsDesign ServicesComplexFabricationAssembly/testDesignManufacturingIPA Chiplet Reference Platform:Enabling the EcosystemEnabling the Chiplet EcosystemSamsu

14、ng Advanced SF5E ProcessMature 5nm processIn full productionCadence NNA110&Q8 Vison CoreNNA110 VP1 1K+VP6 2KVision Q8 AO Dual Core+TIEIO/Memory Core:PCIe6 and DDR5PCIe 6 Ctrl&PHYDDR5/4 Ctrl&PHYSystem Memory:XenergicL2 System MemoryChipletI/F:BoW D2DChiplet SoC Block DiagramNNA110(x2)PCIe6LX-SSVQ8(2M

15、C)NXMemDDR5BoWD2DA Working“Proof of Concept”ChipletVQ8(2MC)Complete SoC system or ChipletSamsung Advanced SF5E ProcessSoC/Chiplet System ArchitectRTL Design and IntegrationSynthesis and DFT(Scan,BIST)Packaging designManufacturingBring up and validationA Chiplet Platform-Flexible&Custom SoC DesignChi

16、pletSoCScalable:Multi-die per packageConfigurable:IO Hub,AI/ML or VisionBoot&management:NX&LX CoreIP and Design ReuseNNA110(x2)PCIe6LX-SSVQ8(2MC)NXMemDDR5BoWD2DNNA110(x2)PCIe6LX-SSVQ8(2MC)NXMemDDR5BoWD2DVQ8(2MC)VQ8(2MC)Samsung Advanced SF5E ProcessCadence NNA110&Q8 Vison CoreIO/Memory Core:PCIe6 and

17、 DDR5System Memory:XenergicChipletI/F:BoW D2DBuilding your own Custom ChipletNNA110(x2)PCIe6LX-SSVQ8(2MC)NXMemDDR5BoWD2DCustom“Compute”or“Accelerator”BoWD2DChipletSoCCustom Compute/Accelerator ChipletSamsung Process SF5,SF4X,SF3,othersBoW interoperability testing BoW interface with other vendorTrue

18、Heterogeneous System IntegrationVQ8(2MC)A Samsung 5nm IO Hub PlatformProven architecture and interoperabilityLeverage SW built on Tensilica DSPAbility to change/customize blocksA IO Hub Platform Solution:CustomizationNNA110(x2)PCIe6LX-SSVQ8(2MC)NXMemDDR5UCIeD2DCustom“Compute”or“Accelerator”UCIeD2DCh

19、ipletSoCD2D:BoW UCIePCIe:PCIe6 PCIe5 or more lanesDDR:5600 6400/7200/8400 or LPDDR/GDDR/HBMSystem Memory:change size or config.Cores:select from AI/ML to Vision to AudioVQ8(2MC)Multi-Die package with Compute and IO ChipletsLow cost,mature MCM package optionVision/AL Chiplet with DDR5,PCIe6 and BoW D

20、2D interfaceAdvanced Packaging CapabilityCompute DieNNA110 Dual Q8Vision/AI 5nm diePackageMulti-Die PackageDDR5PHYPCIEPHYD2D BoWPCBoard with PCIE interfaceFPGAPCIE counterpartOptionalOptionalPCIe InterfaceD2D BoWD2D InterfaceCustomer Chiplet DieChipletSoCDevelopment Platform Sample ApplicationsChipl

21、et/SoCdaughter boardLeverage 3rdparty development platformsPlug in expansion enables accelerated HW/SW co-developmentExisting BSP for fast bring upDevelop Firmware,DSP code,Application StackDaughter Board-ChipletSoCOff-the-Shelf Host SystemPCIeUtilize existing Ecosystem:cameras,monitors running on i

22、ndustry control systemsTensilicaVision and AI software demos via PCIe boardsSoftware running on Cadence Palladium and Protium platformsComplete Solution:Design Flow to HW/SW PlatformDevelopment Platform“running software”Protium PrototypingPalladiumEmulationSilicon Proven Digital Reference FlowMulti-

23、Die 3DIC Flow and System-Level AnalysisSi Proven IPsCustom AMS Reference FlowTeraOps/mWDesign FlowPlatform SolutionPerformanceWorking SiliconSoC Design Services&CustomizationSilicon Proven Platform enabling customization and developmentEnabling innovationAccelerating designLowering riskBuilding an dynamic ecosystemFraunhofer Design and IPCadence IP,System and ToolsSamsung Manufacturing and packagingEnabling the Chiplet Ecosystem Driving the IndustryNNA110(x2)PCIe6LX-SSVQ8(2MC)NXMemDDR5BoWD2DVQ8(2MC)Thank you!Open Discussion