1-12608-Edge 13.45 AI Computing for Smart PC with Low Power FPGA.pdf

1、1|Lattice Semiconductor ConfidentialEdge AI Computing for Smart PC with Low Power FPGALattice SemiconductorLattice Semiconductor Confidential2|Lattice Semiconductor ConfidentialAgenda Edge AI for Smart PC System Challenges Fully Flexible Solution With Lattice Low Power FPGA SummaryLattice Semiconduc

2、tor Confidential3|Lattice Semiconductor ConfidentialEdge Computing in Next Generation Smart PC TrendsAI CapableAware of surroundingUser detection&wellnessLattice Semiconductor Confidential4|Lattice Semiconductor ConfidentialEssential FeaturesWake on ApproachAttention TrackingLattice Semiconductor Co

3、nfidential5|Lattice Semiconductor Confidential5|Lattice Semiconductor ConfidentialPrivacy&SecurityLattice Semiconductor Confidential6|Lattice Semiconductor Confidential6|Lattice Semiconductor ConfidentialWellnessLattice Semiconductor Confidential7|Lattice Semiconductor ConfidentialAgenda Edge AI for

4、 Smart PC System Challenges Fully Flexible Solution With Lattice Low Power FPGA SummaryLattice Semiconductor Confidential8|Lattice Semiconductor ConfidentialContinuously evolutional AI features Gen 1 User presenceGen 2 User presence User attention Onlooker detectionGen 3 User presence User attention

5、 Onlooker detection User authentication Environment sensingGen 4 User presence User attention Onlooker detection User authentication Environment sensing Portrait segmentation User biological status More and more AI features are being explored by the industry Performance requirements are also upgradi

6、ngLattice Semiconductor Confidential9|Lattice Semiconductor ConfidentialExtremely strong system flexibilityHardware flexibilitySoftware flexibility Different image sensors Different AI feature requirements Seamless interfacing different modules Optional enhanced security Compliant with ECO system Di

7、fferent service framework Collaboration with different key playersLattice Semiconductor Confidential10|Lattice Semiconductor ConfidentialUltra-low power consumption constraintsBattery powered mobile platformHigh computation and power requirements from AI workloadsAlways-on featureVS.Lattice Semicond

8、uctor Confidential11|Lattice Semiconductor ConfidentialAgenda Edge AI for Smart PC System Challenges Fully Flexible Solution With Lattice Low Power FPGA SummaryLattice Semiconductor Confidential12|Lattice Semiconductor ConfidentialFootstone 1:Video Connectivity and Ultra Low Power FPGAs2022-20232.5

9、Gbps/Lane MIPI DPHYDSP&Memory for ML/AI processingSecurity BlockAlways on Applications(30 mW)All CrossLink FeaturesCrossLink-NX17/40Enhanced AI performanceAdditional Device MemoryRefreshed Video InterfacesAlways on Applications(10 mW)Next Gen Bridge and Processing2019-20212024+2017-20181.5 Gbps/Lane

10、 MIPI DPHYFlexible I/OAlways on Applications(1 mW)5k 6k LUTiCE40UP/CrossLinkMore MemoryMore DSPUSB 2.0/3.1Low Power IslandAlways on Applications(10 mW)All CrossLink-NX17/40 FeaturesCrossLink-NX33/UPerformanceReleasedPlanningExploration+High Performance ML/AIISP+ML/AI Processing with Low Power Mode+M

11、L/AI ProcessingVideo/Data BridgingTMTMTMLattice Semiconductor Confidential13|Lattice Semiconductor ConfidentialFootstone 2:Lattice SensAI Stack Lattice Semiconductor Confidential14|Lattice Semiconductor ConfidentialA fully configurable Lattice AI inference framework Hardware configurable each RTL mo

12、dule can be configured per specific requirements continuously iterative SensAI accelerator:from SensAI 1.0 to SensAI 6.0 Software configurable dynamic scheduling among different modules for different scenarios deterministic and optimized AI pipelineRISC-VCPUAHBUARTI2CSPI.SensAI EngineSensor Interfac

13、e(MIPI,SLVS-EC,etc.)Pre-Proc AcceleratorAPBPost-Proc AcceleratorLattice Semiconductor Confidential15|Lattice Semiconductor ConfidentialFlexible configurations for different customer requirementsCommon for different platformsCustomer specific configurationCore AI processing pipelineMIPI pathDiscrete

14、controlConfig/OTA interfaceDebug/Val interfaceMFT supportI/O configurationRISC-VCPUAHBUARTI2CSPI.SensAI EngineSensor Interface(MIPI,SLVS-EC,etc.)Pre-Proc AcceleratorAPBPost-Proc AcceleratorLattice Semiconductor Confidential16|Lattice Semiconductor ConfidentialAI accelerator and Model Co-optimization

15、 in Lattice FPGA AlgorithmOptimizationHardwareOptimizationExtreme AI inference efficiency=&Lightweight AI modelSensAI EngineOptimize via ML techniquesAI engine optimization directiveLattice Semiconductor Confidential17|Lattice Semiconductor ConfidentialPower saving with Lattice FPGASystem specific H

16、W optimization Dynamic AI pipeline schedule Dynamic image sensor configuration RTL runtime optimization 28nm FD-SOI much lower leakage current 100 x smaller SER power-efficient architecture high embedded memory density for AI computationLattice:the low power programmable leaderLattice Semiconductor

17、Confidential18|Lattice Semiconductor ConfidentialAgenda Edge AI for Smart PC System Challenges Fully Flexible Solution With Lattice Low Power FPGA SummaryLattice Semiconductor Confidential19|Lattice Semiconductor ConfidentialSummary Client PCs are becoming smart inPrivacy&SecurityWellnessProductivit

18、y Efficient edge AI capability is requiredContinuously evolutional AI featuresExtremely strong system flexibilityUltra-low power consumption constraints Lattice presents an end-to-end solutionBased on Lattices industry-leading low power FPGAs and SensAI stackA fully flexible lightweight multi-task edge AI inference system Flexibility nature of Lattice FPGA enables both hardware and software evolution Optimization from different levels for power savingThank you!