Session 24High-Frequency ADCs.pdf

1、Session 24 Overview:High-Frequency ADCs DATA CONVERTERS SUBCOMMITTEEDespite a long history and well-established design techniques,ADC architectures and circuit technologies f or high-speed operation continue to evolve.The conversion rates presented in this session range f rom 1 to 72GS/s,demonstrati

2、ng innovative ADC structures and circuit techniques aimed at achieving not only high speed but also exceptional energy ef ficiency.Key advancements introduced include piecewise-linear nonlinearity calibration,dual-path amplification,sub-quantizer design,a mutually exclusive selection technique to re

3、duce metastability,wideband input buf f ers,a hierarchical TI ADC in 4nm CMOS,passive gain combined with automatic buf f er power gating,and more.Session Chair:Seung-Tak Ryu KAIST,Daejeon,Korea Session Co-Chair:Vanessa Chen Carnegie Mellon University,Pittsburgh,PA 426 2025 IEEE International Solid-S

4、tate Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE8:00 AM 24.1 A 12b 3GS/s Pipelined ADC wit h Gat ed-LMS-Based Piecewise-Linear Nonlinearit y Calibrat ion Mingyang Gu,Tsinghua University,Beijing,China In Paper 24.1,Tsinghua University in

5、troduces a gated-LMS-based PWL nonlinearity calibration and dual-path amplification f or better accuracy and ef ficiency.The prototype ADC achieves 58.8dB SNDR at 3GS/s with 32.5mW power consumption,corresponding to a FoMs of 165dB.8:25 AM 24.2 A 14b 1GS/s Single-Channel Pipelined ADC wit h a Parall

6、el-Operat ion SAR Sub-Quant izer and a Dynamic-Deadzone Ring Amplifier Yue Cao,Xidian University,Xian,China In Paper 24.2,Xidian University presents a 14b 1GS/s pipelined ADC with SAR sub-quantizer,achieving 68.2dB SNDR,85.8dB SFDR,and 173.3dB FoMS.A dynamic dead-zone ring amplifier enhances ef fici

7、ency without bias tuning.8:50 AM 24.3 A PVT-Robust 2 Int erleaved 2.2GS/s ADC wit h Gat ed-CCRO-Based Quant izer Shared Across Channels and St eps Achieving 4.5GHz ERBW Junlin Zhong,University of Macau,Macau,China In Paper 24.3,University of Macau presents a 2 interleaved 2.2GS/s ADC using a gated-C

8、CRO quantizer with improved energy ef ficiency and PVT robustness,achieving 45.8dB SNDR,65.7dB SFDR,and 19.7f J/step FoMw.10:55 AM 24.7 An 8b 10GS/s 2-Channel Time-Int erleaved Pipelined ADC wit h Concurrent Residue Transfer and Quant izat ion,and Aut omat ic Buffer Power Gat ing Yunsong Tao,Tsinghu

9、a University,Beijing,China In Paper 24.7,Tsinghua University presents an 8b 10GS/s time-interleaved pipelined ADC,achieving a sampling rate of 5GS/s per channel.Automatic buf f er power gating improves ef ficiency,achieving an FoMW of 22f J/conv-step.11:20 AM 24.8 A 12GS/s 9b 16 Time-Int erleaved SA

10、R ADC in 16nm FinFET Junhua Shen,Analog Devices,Wilmington,MA In Paper 24.8,Analog Devices presents a 12GS/s 9b 16 time-interleaved SAR ADC in 16nm FinFET,achieving 48.1dB SNDR at 5.33GHz,consuming 160mW,with one reservoir capacitor per bit and SAR loop f eedback innovations.10:30 AM 24.6 A Power-an

11、d Area-Efficient 4nm Self-Calibrat ed 12b/16GS/s Hierarchical Time-Int erleaving ADC Cheng-En Hsieh,MediaTek,Hsinchu,Taiwan In Paper 24.6,MediaTek presents a 4nm FinFET 12b 16GS/s time-interleaving ADC,consuming 570mW and occupying 0.430mm,achieving-155dBFS/Hz noise spectral density and reducing spu

12、rs lower than-68dBFS at 7.4GHz input with digital calibration.ISSCC 2025/February 19,2025/8:00 AM427 DIGEST OF TECHNICAL PAPERS 10:05 AM 24.5 A 72GS/s 9b Time-Int erleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Input s in 16nm FinFET Yannan Zhang,University of Macau,Macau,China

13、 In Paper 24.5,University of Macau presents a 16nm FinFET 72GS/s 9b time-interleaved pipeline SAR ADC with wideband input buf f ers and a dual-path bootstrapped switch,achieving 55.3dB SFDR and 41.9dB SNDR at 20GHz input.9:15 AM 24.4 A 10b 3GS/s Time-Domain ADC wit h Mut ually Exclusive Met ast abil

14、it y Correct ion and Wide Common-Mode Input Zijian Liu,University of Macau,Macau,China In Paper 24.4,University of Macau presents a 10b 3GS/s time-domain ADC with mutually exclusive selection technique to reduce metastability errors.It achieves 47.2dB SNDR in low metastability mode and 49.3dB in spl

15、it ADC mode at Nyquist input.24428 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/24.1979-8-3315-4101-9/25/$31.00 2025 IEEE24.1 A 12b 3GS/s Pipelined ADC wit h Gat ed-LMS-Based Piecewise-Linear Nonlinearit y Calibrat ion Mingyang Gu,Yi Zhong,Lu Jie,

16、Nan Sun Tsinghua University,Beijing,China The pipelined ADC is an attractive choice f or high-speed and high-resolution applications.Its most important building block is the residue amplifier.Compared with conventional closed-loop amplifiers,open-loop amplifiers are advantageous in speed,energy ef f

17、iciency,design simplicity,and scaling f riendliness 1.However,they suf f er f rom large gain errors and severe gain nonlinearity.Addressing these nonidealities conventionally requires polynomial-based calibration 1-3.Although the calibration coef ficients can be easily extracted in the background th

18、rough dither injection and gated LMS filters 3,the polynomial computation introduces significant power and area overhead,especially at sampling rates over 1GS/s.The piecewise-linear(PWL)nonlinearity calibration scheme is an attractive alternative to reduce the computational complexity 4.However,exis

19、ting PWL calibration techniques extract the calibration coef ficients in the f oreground with large analog circuitry overhead 4 or in a queue scheme that limits the sampling rate 5.To overcome these challenges,this paper proposes a novel PWL nonlinearity calibration technique that digitally extracts

20、 the calibration coef ficients in the background through gated LMS filters with adaptive thresholds.A dual-path amplification scheme is also proposed to improve power ef ficiency and settling accuracy.Using these techniques,a prototype 12b 3GS/s pipelined ADC achieves a 58.8dB SNDR with a 1.5GHz inp

21、ut and consumes 32.5mW with an on-chip background calibration engine.This corresponds to an FoMS of 165dB and an FoMW of 15.2f J/conv-step.Figure 24.1.1 shows the block diagram of the pipelined ADC.The 1st stage consists of a 3b flash,a CDAC,and 2 open-loop amplifiers.Considering both the driving ca

22、pability and the target SNR,the ADC f ull swing is set to 1Vpp,and the single-ended sampling capacitor is sized at 480f F.Notice that the input of the 2nd stage CDAC needs to settle to 10b accuracy,while only 3b accuracy is required f or the flash.Conventionally,they are driven together by a high-ba

23、ndwidth amplifier,and both settle to 10b accuracy,which leads to large power overhead.In this work,the flash is driven separately by a low-bandwidth auxiliary amplifier to save power.The errors due to mismatches between the 2 amplifiers can be easily tolerated by the redundancy.More importantly,when

24、 driven together with the flash,the CDAC must sample bef ore firing the flash to avoid the kickback.In contrast,the dual-path amplification isolates the CDAC f rom the kickback,allowing the sampling instant of the CDAC to be delayed until af ter the flash is fired.This extends the settling time and

25、improves the settling accuracy.Simple complementary gm-R amplifiers are used f or high bandwidth and low power consumption.The gm of the main amplifier is set to 70mS,and the RL is designed to 80.Considering an attenuation f actor of 0.7 due to the parasitic capacitance at the amplifier input node,t

26、he nominal gain of the 1st stage is roughly 4.The size of theauxiliary amplifier is 1/5 of that of the main amplifier.The sampling capacitance of the 2nd stage is designed to be 80f F.With the parasitic capacitance of 80f F,the bandwidth of the main amplifier is about 12GHz,allowing it to settle to

27、10b accuracy within 100ps at 3GS/s.The third stage is an energy-ef ficient 4-channel time-interleaved SAR ADC with 8b resolution.When converting a held signal,the interleaved ADC is f ree f rom timing skew 6.The gain mismatch is calibrated as part of the inter-stage gain error,while the of f set mis

28、match is eliminated through simple averaging.The gain of the open-loop amplifier is highly nonlinear.Simulation shows that the THD of the ADC is limited to-60dB with only gain error calibration.Thus,gain nonlinearity calibration is required.Two 1b dither signals are injected into the first two stage

29、s to calibrate both the gain error and gain nonlinearity.Their magnitudes take 1/16 of the backend f ull signal swing.An on-chip gated-LMS-based PWL calibration engine extracts and corrects the gain error and gain nonlinearity of the open-loop amplifiers in the background.The calibration engine cons

30、ists of a correction block and a coef ficient extraction block.Figure 24.1.2 shows the correction block and its working principle.The residue voltage of the 1st stage,Vres,is amplified by the open-loop amplifier and quantized by the 10b backend stage to yield the raw digital output Dres,raw.Since th

31、e even-order nonlinearity of the dif f erential gm-R amplifier is negligible,only the positive side(9 bits)of the transf er curve between Vres and Dres,raw is shown f or simplicity.For negative Dres,raw,the absolute value is used f or the nonlinearity correction.The correction block consists of 1 mu

32、ltiplier,1 adder,and 2 4-to-1 multiplexers.By dividing Dres,raw into MSB(the first 2 bits with the weight of b0)and LSB(the remaining 7 bits),it is observed that each LSB segment approximates a linear f unction of Vres.Hence,the overall nonlinear transf er curve can be modeled as a PWL f unction who

33、se slope varies with MSB.The distortion can be removed by equalizing the slopes of 4 LSB segments.Based on this principle,the correction block multiplies LSB by the MSB-dependent coef ficient ki(i=14)to obtain LSBcal.With the slopes of the LSBsegmentschanged,the corresponding MSBweights need to bead

34、justed to MSBcal to maintain the continuity of the curve.For instance,since the slope of the 1st LSB segment is multiplied by k1,the corresponding MSB weight b1(starting point of the 2nd LSB segment)should be set to k1b0.By combining LSBcal and MSBcal,the final result Dres,cal is obtained with the n

35、onlinearity calibrated.Simulation shows that the 4-slice PWL approximation can suppress the THD down to-80dB with a f ull-swing input,which is suf ficient f or the target ADC perf ormance.Figure 24.1.3 shows the background coef ficient extraction block and its working principle.A dither signal Vd is

36、 added to the residual voltage Vres in the analog domain.Af ter nonlinear amplification,quantization,and nonlinearity correction discussed earlier,the digital code of the dither signal Dd is subtracted to obtain the final result Dres,cal.If the gain error and the gain nonlinearity are not correctly

37、calibrated,Dres,cal and Dd would still be correlated.The calibration coef ficients are updated through 4 LMS filters to decorrelate Dres,cal and Dd,thereby achieving complete elimination of errors.Each LMS filter is gated by a range detector with an adaptive threshold.Gated LMS filters with fixed th

38、resholds can be used to extract the polynomial coef ficients 3.However,they do not apply to the proposed PWL calibration because the signal range af f ected by a certain coef ficient has a variable boundary.This work uses adaptive thresholds to track the boundaries and guarantee convergence.For inst

39、ance,k4 solely af f ects samples with absolute values larger than b3,which is variable and determined by k1,k2,and k3.Thus,only these samples are used to update k4.By contrast,k1 af f ects not only samples with absolute values less than b1 when calculating LSBcal but also samples with absolute value

40、s larger than b1 because it is involved in calculating MSBcal.Consequently,all samples are f ed into the LMS filter to update k1.Af ter updating k1 to k4,b1 to b3 are updated accordingly.In this way,all calibration coef ficients are extracted.Compared with conventional PWL calibration that relies on

41、 f oreground analog extraction 4,the proposed gated-LMS-based PWL calibration digitally extracts all calibration coef ficients in the background.The range detectors with adaptive thresholds select appropriate samples to update corresponding coef ficients,which is the key to achieving background coef

42、 ficient extraction.The prototype 12b 3GS/s pipelined ADC is f abricated in a 28nm CMOS process and occupies an active area of 0.04mm2.The corrected data are decimated by 120 bef ore output f or an easy measurement setup.Figure 24.1.4 shows the measured spectra of the ADC with a 1GHz input.With gain

43、 error calibration only,the SNDR and the SFDR are 54.0dB and 62.7dB,respectively,limited by the gain nonlinearity of amplifiers.Af ter applying the proposed PWL nonlinearity calibration,the SNDR and the SFDR are improved to 60.3dB and 76.0dB,respectively.The remaining harmonic distortions are caused

44、 by sampling nonidealities.Figure 24.1.4 also shows the measured SNDR/SFDR with input f requency sweeping.Af ter calibration,the ADC maintains SNDR60dB and SFDR75dB with fin1GHz.The f ront-end driver af f ects the ADC perf ormance with higher input f requencies,limiting the SNDR to 58.8dB and the SF

45、DR to 70.7dB with a Nyquist f requency input.Figure 24.1.5 shows the measured INL curves,the convergence process,and the SNDR under supply,temperature,and sampling rate variations with a 10MHz,-1dBFS input.The proposed nonlinearity calibration improves the INL f rom+2.2/-2.5LSB to+0.8/-0.7LSB.It tak

46、es about 107 points to converge.The SNDR variation is less than 0.4dB under 5%supply variation and less than 1.3dB under-40C85C temperature variation.The ADC maintains an SNDR of 59dB at a sampling rate of 3.4GS/s.The ADC consumes 32.5mW in total,including 9.0mW f or the amplifier,5.6mW f or the fla

47、sh and CDAC,2.5mW f or the backend SAR,4.3mW f or the clock generation,4.7mW f or the ref erence buf f er,and only 6.4mW f or the on-chip digital calibration engine thanks to the computational simplicity of the PWL calibration.Figure 24.1.6 shows the summary of the ADC perf ormance and comparison wi

48、th the state of the art.The prototype ADC achieves an FoMS of 165dB and an FoMW of 15.2f J/conv-step with an on-chip PWL calibration engine.Acknowledgement:This work is supported in part by the NSFC under Grant 62090042,62374098 and 62434005,National Key R&D Program of China(No.2019YFB2205003),the B

49、eijing National Research Center f or Inf ormation Science and Technology,and the Beijing Innovation Center f or Future Chip.Figure 24.1.1:Block diagram of t he pipelined ADC,working principle of t he dual-pat h amplificat ion,and schemat ic of t he int er-st age amplifier.Figure 24.1.2:Block diagram

50、 of t he PWL nonlinearit y correct ion block and it s working principle.Figure 24.1.3:Block diagram of t he PWL nonlinearit y ext ract ion block wit h gat ed LMS filt ers,and comparison wit h t he convent ional PWL calibrat ion.Figure 24.1.4:Measured out put spect ra wit h and wit hout nonlinearit y

51、 calibrat ion,and SNDR/SFDR versus input frequency.Figure 24.1.5:Measured INL curves,convergence process,and performance variat ion wit h a 10MHz,-1dBFS input.Figure 24.1.6:Performance summary and comparison wit h t he st at e of t he art.ISSCC 2025/February 19,2025/8:00 AM429 DIGEST OF TECHNICAL PA

52、PERS 24 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 24.1.7:Chip micrograph.Refer ences:1 B.Murmann and B.E.Boser,“A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,”in IEEE Jour na

53、l of Solid-St at e Cir cuit s,vol.38,no.12,pp.2040-2050,Dec.2003.2 A.Panigada and I.Galton,“A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.44,no.12,pp.3314-3328,Dec.2009.3 A.M.A.Ali et al.,“A 12-b 18

54、-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.55,no.12,pp.3210-3224,Dec.2020.4 M.Daito,H.Matsui,M.Ueda and K.Iizuka,“A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration,”in IEEE J

55、our nal of Solid-St at e Cir cuit s,vol.41,no.11,pp.2417-2423,Nov.2006.5 J.K.-R.Kim and B.Murmann,“A 12-b,30-MS/s,2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.47,no.9,pp.2141-2151,Sept.2012.6 M

56、.Brandolini et al.,“A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC f or Direct-Sampling Systems in 28 nm CMOS,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.50,no.12,pp.2922-2934,Dec.2015.7 Y.Cao,M.Zhang,Y.Zhu,R.P.Martins and C.-H.Chan,“A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined AD

57、C With Sturdy Ring Amplifier and Time-Domain Quantizer,”in IEEE Jour nal of Solid-St at e Cir cuit s.8 J.Hao et al.,“A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness,”2023 IEEE Int er nat ional Solid-St at e Cir cuit s

58、 Confer ence(ISSCC),San Francisco,CA,USA,2023,pp.168-170.9 A.M.A.Ali et al.,“A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither,”2016 IEEE Sy mpos ium on VLSI Cir cuit s (VLSI-Cir cuit s),Honolulu,HI,USA,2016,pp.1-2.10 Y.Cao,M.Zhang,Y.Zhu,R.P.Martins and C.-H.Chan,“A 1

59、2GS/s 12b 4 Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buf f er,”2024 IEEE Int er nat ional Solid-St at e Cir cuit s Confer ence(ISSCC),San Francisco,CA,USA,2024,pp.388-390.430 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SES

60、SION 24/HIGH-FREQUENCY ADCS/24.2979-8-3315-4101-9/25/$31.00 2025 IEEE24.2 A 14b 1GS/s Single-Channel Pipelined ADC wit h a Parallel-Operat ion SAR Sub-Quant izer and a Dynamic-Deadzone Ring Amplifier Yue Cao1,Yi Shen1,2,Shubin Liu1,2,Haolin Han1,Hongzhi Liang1,Li Dang1,Dengquan Li1,Ruixue Ding1,2,Zh

61、angming Zhu1,2 1Xidian University,Xian,China 2Hangzhou Institute of Technology,Xidian University,Hangzhou,China Pipelined ADCs with high speed(1GS/s)and high resolution(14b)are required f or wireless communication and instrumentation applications.The conventional pipelined architecture is usually po

62、wer-hungry due to the substantial use of residue amplifiers(RAs)and flash quantizers.In 1,a low-power ring amplifier(ringamp)is exploited as the RA in a 15b 1GS/s pipelined ADC,achieving excellent power ef ficiency(67dB).However,the ringamp requires bias tuning to track PVT variations,and the five p

63、ipelined stages with multi-bit flash are still potential power bottlenecks.2 adopts current biasing and split MDAC to improve the PVT robustness of the ringamp and utilizes a backend time-interleaved(TI)SAR to reduce the number of stages,and thereby the RAs and flashes.However,its AC-coupling capaci

64、tor biasing scheme suf f ers f rom a tradeof f between bandwidth and noise,while the TI mismatches need to be calibrated.Adopting a single-channel SAR sub-quantizer instead of a flash is an attractive approach to reduce power and circuit overhead 3.Nevertheless,its serial conversion process inevitab

65、ly increases the timing budget f or sub-conversion(Fig.24.2.1,top).To maintain ADC speed,the amplification time has to be reduced,leading to increased RA power.3 utilizes a high-speed open-loop amplifier to reduce power,but the amplifier non-linearity limits the ADC SNDR.This design tradeof f become

66、s particularly critical when the resolution is 14b due to the stricter design requirement f or RA.4 amplifies the f ull-swing signal instead of the residue,parallelizing conversion and amplification.However,it significantly limits the ADC input swing.In this work,we present a 14b 1GS/s single-channe

67、l pipelined ADC that addresses the above challenges,thus simultaneously achieving excellent SNDR,SFDR,and power ef ficiency.A parallel-operation SAR sub-conversion scheme is proposed to parallelize the residue conversion and amplification,which reduces the number of stages and improves the ADC power

68、 ef ficiency.A low-noise dynamic deadzone ring amplifier is proposed to achieve low power and improve SNDR.The 28nm prototype ADC achieves 68.2dB SNDR and 85.8dB SFDR with a Nyquist input while only consuming 15.3mW,resulting in a Schreier FoM of 173.3dB.Figure 24.2.1(bottom)shows the concept of the

69、 prototype ADC.The 1st stage adopts flash to minimize its conversion time,while the subsequent stages adopt a SAR to save power.Unlike the conventional pipelined ADC,where the residue conversion must wait f or its amplification completion,this work proposes the parallel-operation SAR to sample and c

70、onvert the residue rather than the amplified one with the non-attenuated passive residue transf er 5.Theref ore,the residue conversion and amplification can run in parallel,of f ering large timing budgets f or both SAR conversion and amplification without reducing ADC speed.This allows the backend s

71、tage to utilize the f ull period to resolve more bits,and thus,this work only requires three stages to realize 14b resolution,leading to power and area saving.Suf ficient amplification time allows the ringamp to implement the RAs f or low power and high linearity.With the same timing budgets,the pro

72、totype achieves about a 1.4 speed improvement over the architecture without parallel operation.Figure 24.2.2 shows the overall architecture of the prototype ADC.It consists of a 4b 1st-stage flash ADC,a 4b 2nd-stage parallel-operation SAR ADC,an 8b 3rd-stage subranging SAR ADC(including a 4b paralle

73、l-operation SAR and a 5b fine SAR),and two 8 ringamp-based MDACs.Three redundant bits are introduced to tolerate conversion errors.The 1st-stage MDAC employs top-plate sampling with a 0.85pF input capacitance f or high sampling bandwidth with well-balanced sampling noise.The 1st-stage flash resolves

74、 4 bits to guarantee the ADC linearity and adopts interpolation at its dynamic preamplifiers outputs to reduce comparator power and area 6,7.The bandwidth mismatch is addressed by suf ficient bandwidth and redundancy.The SAR sub-ADCs and MDACs adopt the split capacitor switching scheme f or f ast DA

75、C switching 8,where the DAC of fine SAR is halved by a single-side switching LSB capacitor.To f urther shorten the DAC settling time,this work uses 1V ref erence voltage and scales it down to 0.75V f or 1.5VPP by capacitance attenuation because it of f ers a larger VGS f or Vref switches.During the

76、MDAC sampling and residue generation phases,the parallel-operation SAR of the next stage connects to this MDAC.Once the MDAC residue generation is completed,the SAR disconnects f rom the MDAC and immediately acquires the residue.Af terward,it converts the residue during the amplification phase.With

77、over 450ps amplification time,4b SAR conversion can be perf ormed during the 2nd-and 3rd-stage sampling(i.e.,the 1st-and 2nd-stage amplification).Af ter sampling,the 2nd and 3rd stages can immediately generate residue,thus significantly reducing timing budgets.The 3rd-stage fine SAR then resolves th

78、e last 5 bits.Note that the 4b parallel-operation SAR and 5b fine SAR have an 8 increased design requirement because they process the non-amplified residues,which requires higher power to suppress noise.However,their energy ef ficiency is not a concern because SAR ADC is usually low power when the d

79、esign requirement is 8b.In addition,this work uses 53%redundancy to tolerate the noise of the parallel-operation SAR.Adopting the three-stage dynamic comparator in 9,each parallel-operation SAR consumes only 1.2mW,while the fine SAR consumes only 1.5mW.The parallel-operation SAR utilizes scaling and

80、 bridge capacitors(Cs&Cb)to downscale its quantization range to match the MDAC f ull-scale range.A 6b Cal-DAC calibrates the range mismatch between the SAR and MDAC due to process variation and device mismatch 10.The Cal-DAC unit capacitor is selected as 0.3f F,providing a 0.5%adjustment accuracy.Th

81、e top plate of the Cal-DAC is reset to Vcm during the parallel-operation SAR sampling and disconnects f rom Vcm during SAR conversion.This ensures that the Cal-DAC only adjusts the SAR quantization range and does not af f ect the MDAC.In addition,extra comparator input pair and of f set trimming DAC

82、 are used to compensate f or the of f sets of comparator and RA,respectively.A VFS/256 dither is injected during the amplification phase f or background interstage gain calibration.Figure 24.2.3 shows the proposed dynamic deadzone ringamp.It is a modified version f rom 1,11 by introducing dynamic de

83、adzone biasing and current biasing schemes,thus achieving reduced noise and improved PVT variation tolerance compared to 1,11.The ringamp noise is proportional to ro1G2gm3 12,13,where ro1 is the output resistance of A1,G2 is the gain of A2,and gm3 is the transconductance of A3.The proposed dynamic d

84、eadzone biasing scheme continuously increases the deadzone Voltage VDZ during amplification,which leads to decreasing G2 and gm3,thereby resulting in improved noise perf ormance.Figure 24.2.3(top-right)shows the dynamic bias circuit,which provides the dynamic bias VBH and VBL f or the CMOS resistor

85、of the 2nd stage,thus realizing dynamic VDZ.During the reset phase R,VBH,and VBL are reset to VDD and ground,respectively.During the amplification phase A,VBH gradually f alls with the discharging current IN,while VBL gradually rises with the charging current IP,leading to an increasing VDZ.Theref o

86、re,the noise power continuously decreases during A,resulting in 7.47nV2 low noise f or the 1st-stage RA(RA1),as shown in Fig.24.2.3(bottom-lef t).It achieves a 37%noise reduction compared to 1,11.Note that the variation ranges of VBH and VBL are determined by IN and IP,given a relatively fixed A,pot

87、entially leading to a PVT robustness issue.To address this,the sizes of MN and MP are optimized to ensure a suitable variation range f or VDZ across PVT.In addition to the merit of noise reduction,the proposed dynamic deadzone biasing scheme also makes A3 current(gm3)more stable over PVT variations.

88、IN and IP can track PVT variations and adjust VDZ to alleviate the impact of PVT variations on the A3 current.To enhance the PVT tracking ability,this work uses a high-Vth transistor to implement MN and MP due to the lower overdrive voltage.To stabilize A1 and A2,this work employs a current mirror t

89、o define the A1 current.With a stable A1 current,the VBE variation of A1 can alleviate the ef f ect of PVT variations on the A2 current.Theref ore,the proposed ringamp can achieve better stability under PVT variations compared to 1,11.Figure 24.2.3(bottom-right)shows the simulated THD of RA1 under 1

90、00%f ull-scale output(1.5Vpp)across PVT variations.It stays below-61.8dB without any bias tuning.Unlike previous ringamps with dynamic biasing,which provide mismatch and PVT variation tolerance in 14,or improve the large signal slewing in 15,the proposed ringamp achieves both noise reduction and imp

91、roved PVT robustness.The prototype ADC is f abricated in 28nm CMOS and occupies an active area of 0.0219mm2(Fig.24.2.7).It consumes 15.3mW f rom a 1V supply when running at 1GS/s.The MDAC capacitor weights are f oreground calibrated of f-chip.The of f sets(f rom comparators and RAs)and f ull-scale r

92、ange mismatch(between the parallel-operation SAR and MDAC)are f oreground-corrected on-chip via of f-chip tuning algorithms.These f oreground calibrations are done once bef ore all measurements.The reemerging f ull-scale range mismatch due to supply voltage and temperature variations is 4.5GHz ERBW

93、Junlin Zhong1,Minglei Zhang1,Yan Zhu1,Rui P.Martins1,2,Chi-Hang Chan1 1University of Macau,Macau,China 2Instituto Superior Tecnico/University of Lisboa,Lisbon,Portugal The demand f or medium-resolution GS/s ADCs is increasing in DSP-based wireline communication.Enhancing energy and area ef ficiency

94、of the unit ADC is crucial f or f acilitating a higher data throughput with massive interleaving.Ring oscillator(RO)-based ADCs 1-4 are promising due to their compact and scaling-f riendly nature,but they f ace challenges,as reviewed in Fig.24.3.1.A voltage-controlled RO(VC-RO)with a counter 1 simpl

95、ifies ADC conversion by directly converting the sampled input voltage into digital codes.However,the nonlinear tuning curve of VC-RO necessitates extra calibration.Additionally,since the sampled voltage directly modulates the f requency of VC-RO,each sub-channel ADC requires an individual VC-RO,whic

96、h undermines ef f orts to minimize the overall energy and area.Gated RO(GRO)-based ADCs 2 have better energy ef ficiency by intermittently enabling the RO,with the gated signal generated through a ramp generator(RG)and a zero-crossing detector(ZCD),an integer counter f urther extends the quantizatio

97、n levels of the GRO.Nonetheless,implementing the shareable capability of the GRO among multiple channels is challenging due to the long integer-counting.Moreover,the RG directly discharges the sampling capacitor,leading to a time-varying input path impedance.Cyclic coupled ROs(CCROs)5-6 exhibit wide

98、 oscillation phases,which consist of M coupling-connected N-level ROs,providing 2MN quantization levels through 2M-f old phase interpolation.This work presents a 2 interleaved two-step ADC utilizing a unif orm gated CCRO(G-CCRO)-based quantizer to address the challenges above.It allows the quantizer

99、 and RG to be shared across channels and conversion steps,thereby improving the energy and area ef ficiencies in a PVT-robust manner.It decouples the RO operation f rom the sampled input amplitude,providing compact and flexible oscillation phases f or the time division configuration.The G-CCRO also

100、of f ers inherent phase interpolation,significantly mitigating phase errors f rom prior art 7.Furthermore,this work reallocates the RG f rom the input to the ref erence path,which provides a constant input path impedance and reduces kickback,thus preserving the high-f requency signal integrity.The 2

101、.2GS/s ADC prototype,f abricatedin a 28nm CMOS process,occupies an area of 0.004mm.It demonstrates strong PVT robustness,achieving a 7b ENOB under a 4.5GHz input and a 19.7f J/conv.-step Walden FoM.Figure 24.3.2 illustrates the overall architecture of the proposed two-step ADC,which consists of 2 vo

102、ltage-to-time(V-T)f ront-ends and an inter-channel/step-shared block,including an RG,a time demux,and a 37 G-CCRO with associated comparison units.In the 1st conversion step,the V-T f ront-end converts the sampled voltages into time dif f erences(TP/N,CHA/TP/N,CHB)using the 4 discharging branch of t

103、he RG and a pseudo-dif f erential ZCD similar to 7.The G-CCRO-based quantizer subsequently perf orms 4b(including 1b sign)coarse quantization(D1),which is then used to configure the CDAC to generate the residue at the ref erence path of the V-T f ront-end.In the 2nd conversion step,the same V-T f ro

104、nt-end is fired again to convert the residue voltages to residue time dif f erences but using the 1 discharging branch of the RG instead of the 4 one.Benefiting f rom the two-step conversion,the RG only needs to meet the linearity requirement of the sub-conversion steps instead of the entire ADC res

105、olution.Reusing the V-T f ront-end across the two steps improves the conversion consistency,which is superior to the separated topologies 3.The inherent phase interpolation implemented by the CCRO in the 2nd conversion step also reduces the inter-step ratio of the discharging branch by 6,enhancing t

106、he conversion speed while relaxing the matching requirements.Af ter that,the CCRO-based quantizer perf orms 5.4b(42 levels)fine quantization.A 1b redundancy is included between the two steps to correct the quantization errors that may occur during the 1st conversion step,resulting in an 8.4b ADC.The

107、 time demux responds to the sharable characteristic of the G-CCRO quantizer.It distributes the V-T f ront-end outputs(TP/N,CHA/TP/N,CHB)f rom dif f erent channels and steps into a unif orm G-CCRO through SP/N,1st/SP/N,2nd.In the timing diagram of Fig.24.3.2,the 1st conversion step of channel A is al

108、igned with the 2nd conversion step of channel B,which allows f or simultaneous coarse and fine quantization by utilizing the two-dimensional phase extension capability of the CCRO.It is important to note that the G-CCRO quantizer can be shared among more channels,as disclosed in Fig.24.3.1,if the CC

109、RO f requency is increased.RO enables the G-CCRO,with the rising edge generated by SP,1st and the f alling edge by the latest rising edge among SN,2nd,SP,2nd,and SN,1st using the pulse generator.The pulse generator has an adjustable delay,which extends the pulse width of RO,ensuring that the G-CCRO

110、is available until the phase comparisons are completed.Compared to the f ree-running CCRO 58,the resetting operation fixes the initial phases of the G-CCRO,simplif ying the quantization logic and obviating the accuracy loss f rom extra quantization noise induced by the random initial states.Addition

111、ally,it saves considerable power consumption.During the resetting,P2 are sequentially connected to the ground and supply voltage levels through switches.Since M and N are odd numbers,there are cases where two adjacent nodes are configured to the same voltage level,which then activates the first volt

112、age transition.Af ter RO enables the G-CCRO,the edge selector identifies 7 phases f rom one row of the G-CCRO(P1),enabling the coarse quantization.Simultaneously,SP,2nd and SN,2nd sample P2 using time comparators based on sense amplifiers.The results(D2p and D2n)are processed through a group of XOR

113、logic to convert the outputs of the time comparators into digital codes.The open-loop phase interpolation(PI)7 presents finer time resolution with a multi-layer structure.However,it suf f ers f rom significant power consumption and interpolation errors as the layer number increases f or a higher int

114、erpolation f actor.Alternatively,the closed-loop and cyclic coupled(CC)structure of the CCRO provides an inherent interpolation capability through a two-dimensional topology.Figure 24.3.3 compares them in detail,where their time intervals bef ore interpolation are both 25ps.The interpolation error i

115、s in an LSB f ormat,f acilitating a f air perf ormance comparison.There are several design considerations of the MN CCRO 5 8:1)M must be a prime number,while N should be a dif f erent odd number to maximize the total phase(2MN);2)the power consumption is M times that of a one-row RO,but the phase no

116、ise is improved by 10log10(M)dB;3)the phase noise improvement is positively correlated with the coupling f actor(k),however,a larger k elevates the power-delay product due to an increasing node capacitance.For a similar number of total phases,the G-CCRO significantly reduces the required inverters a

117、nd conserves substantial power,while its CC f eature helps suppress interpolation phase error.This work adopts a 37 configuration,achieving 6 inherent interpolation to increase the time resolution of the G-CCRO.Compromising between the phase error and power-delay products,the coupling f actor k is 0

118、.25 in this work by setting the vertical/horizontal inverter ratio.The power consumption is theoretically divided by half when sharing the G-CCRO between two channels.Compared to a PI unit with 31 output phases,the G-CCRO unit reduces the interpolation phase error by 30%and simultaneously saves 2.3-

119、f old power consumption,even with more output phases(42).The G-CCRO is also considerably lightweight compared to the open-loop PI and of f ers extra phase extension over the one-row GRO 2-3,demonstrating promising potential f or sharing more output phases with more interleaved channels.The CCRO suf

120、f ers f rom systematic mismatches during layout f rom inconsistent parasitics,which are minimized by a merged vertical/horizontal inverter cell layout and the matched routing length.In addition,there are two conversion f actors in two conversion steps,originating f rom the ratio between the RG slope

121、(V-T conversion)and the time resolution of the G-CCRO(T-D quantization).The 4/1 current ratio and the inherent interpolation f actor(6)ensure strong PVT stability.The simulation,which combines 5%supply and 40 to 85C variations,shows that the ADC prototype maintains over 48dB SNDR without calibration

122、.This work generates the ramp signal by discharging the ref erence path instead of the input path in prior works 2-3,as shown in Fig.24.3.4.This mitigates the input path impedance variations,thereby decreasing the input kicking and inf erence f or higher linearity.The single-ended sampling capacitan

123、ce of the prototype ADC is 64f F,while its f ull-scale input swing is 0.8Vppd.The proposed G-CCRO-based ADC is f abricated with a 28nm CMOS process,with a small area of 0.004mm.Figure 24.3.7 provides its die photograph.A one-time of f-chip f oreground calibration aligns the conversion f actors of tw

124、o steps,and such f actors are f rozen during all measurements.The mismatches between two interleaved V-T f ront-ends are calibrated in the of f-chip background.The measured spectrum of the 2.2GS/s ADC(Fig.24.3.4)achieves 45.8dB SNDR and 65.7dB SFDR with a Nyquist-f requency input.The DNL and INL ran

125、ge f rom 0.56 to 0.60 LSBs and f rom 0.60 to 0.59 LSBs,respectively.Figure 24.3.5 depicts the SNDR and SFDR versus input f requencies,sampling rates,input common-mode voltage variation,and combined supply voltage and temperature variations of three samples.All samples achieve 4.5GHz ERBW and 7b ENOB

126、 with a 4.5GHz input,benefiting f rom the input-path-f ree RG.The strong PVT robustness is attributed to the current ratio-based RG and the inherent interpolated G-CCRO.Figure 24.3.6 summarizes this work and compares it with state-of-the-art time/voltage-domain ADCs,particularly those based on the R

127、O architecture.The proposed ADC,f eaturing RO sharing,consumes 6.9mW2.2GS/s under a 0.9V supply,resulting in a Walden FoM of 19.7f J/conv.-step.It demonstrates an outstanding SNDR and FoM among the RO-based ADCs while achieving an attractive area,benefiting f rom the shared G-CCRO-based quantizer.Th

128、e proposed ADC demonstrates the RO-sharing capability across interleaved channels and conversion steps.It also presents the advantages of constant input path impedance and strong PVT robustness.Acknowledgement:This work was supported by Macau FDCT(File no.0129/2024/AMJ and 004/2023/SKL)and in part b

129、y the University of Macau Research under Grant MYRG-GRG2024-00257-IME.Figure 24.3.1:Comparison bet ween prior and proposed RO-based ADCs,t ypology and t iming diagram of t he M N gat ed-CCRO.Figure 24.3.2:Overall archit ect ure and t iming diagram of t he proposed G-CCRO based t wo-st ep ADC.Figure

130、24.3.3:Comparison of PI/G-CCRO-based phase int erpolat ion,t ot al phase number of CCRO/RO;t he PVT st abilit y of t he proposed G-CCRO-based t wo-st ep ADC.Figure 24.3.4:Block diagram and t he simulat ed input impedance of Ramp Gen.Vin/Vref;measured spect rum wit h Nyquist input signal at Fs=2.2GHz

131、 and DNL/INL curve.Figure 24.3.5:Measured SNDR/SFDR vs input frequencies,sampling rat es,input VCM variat ion,and t he combined variat ions in supply and t emperat ure across 3 samples.Figure 24.3.6:Performance summary and comparison of t he previous art s on RO-based ADCs and ot her t ime/volt age-

132、based ADCs.ISSCC 2025/February 19,2025/8:50 AM433 DIGEST OF TECHNICAL PAPERS 24 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 24.3.7:Die phot ograph.Refer ences:1 M.Baert et al.,”A 5GS/s 7.2 ENOB time-

133、interleaved VCO-based ADC achieving 30.5f J/conv-step,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2019,pp.328-329.2 A.S.Yonar et al.,“An 8b 1.0-to-1.25GS/s 0.7-to-0.8 V single-stage time-based gated-ring-oscillator ADC with 2 interpolating sense-amplifier-latches,”in IEEE Int.S

134、olid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2023,pp.266-267.3 Y.Lyu et al.,“A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedf orward Ring Oscillator-Based TDCs,”IEEE J.Solid-State Circuits,vol.55,no.7,pp.1807-1818,Jul.2020.4 S.Zhu et al.,“A 2-GS/s 8-bit non-interleave

135、d time-domain flash ADC based on remainder number system in 65-nm CMOS”,IEEE J.Solid-State Circuits,vol.53,no.4,pp.1172-1183,Apr.2018.5 M.M.Abdul-Latif et al.,“Low phase noise wide tuning range N-Push cyclic-coupled ring oscillators,”IEEE J.Solid-State Circuits,vol.47,no.6,pp.1278-1294,Jun.2012.6 H.

136、Shibata et al.,“An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2020,pp.260-262.7 M.Zhang et al.,“A 4 Interleaved 10GS/s 8b Time-Domain ADC with 16 Interpolatio

137、n-Based Inter-Stage Gain Achieving 37.5dB SNDR at 18GHz Input,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2020,pp.252-254.8 O.Jarvinen et al.,“Design of Cyclic-Coupled Ring Oscillators with Guaranteed Maximal Phase Resolution.”in IEEE International Symposium on Circuits and Sys

138、tems(ISCAS),May.2022,pp.1453-1456.9 A.Whitcombe et al.,“A VTC/TDC-assisted 4 interleaved 3.8 GS/s 7 b 6.0 mW SAR ADC with 13 GHz ERBW,”IEEE J.Solid-State Circuits,vol.58,no.4,pp.972-982,Apr.2023.10 D.-R.Oh et al,“A 7-bit two-step flash ADC with sample-and-hold sharing technique,”IEEE J.Solid-State C

139、ircuits,vol.57,no.9,pp.2791-2801,Sep.2022.11 Y.Tao et al.,“A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Of f set Calibration,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.

140、2024,pp.394-396.Refer ences:434 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/24.4979-8-3315-4101-9/25/$31.00 2025 IEEE24.4 A 10b 3GS/s Time-Domain ADC wit h Mut ually Exclusive Met ast abilit y Correct ion and Wide Common-Mode Input Zijian Liu1,Mi

141、nglei Zhang1,Wei Zhang1,Yan Zhu1,Rui P.Martins1,2,Chi-Hang Chan1 1University of Macau,Macau,China 2Instituto Superior Tecnico/University of Lisboa,Lisbon,Portugal Metastable trajectories in comparators pose unpredictable and non-Gaussian error behaviors in the A/D conversion,which cannot be tolerate

142、d by applications such as low-bit-error-rate serial link receivers,radar,and instrumentation 1-5.Time-domain(TD)ADCs 6-11 have demonstrated a superior speed to their voltage-domain(VD)SAR and pipeline counterparts thanks to the technology scaling.However,the metastability artif act of the TD ADC is

143、of ten overlooked,which can be severe under a stringent time deadline and is worth great attention.In literature,TD circuits are of ten leveraged to f acilitate the“metastability detector”1,while the metastability events indeed cannot be detected because the detector itself can experience metastabil

144、ity.They of ten detect the error within the loop time,which theref ore involves limited additional gain and decision time with extra load on the critical path,leading to a potentially diminished return on error probability(Pmeta).Prior work 2,3 decouples such constraints by pipelining the comparator

145、 decisions with additional latches,thus allowing extra gain and time on the detection.This proper unresolved-decision(UD)detection demonstrates an outstanding Pmeta in a time-interleaved SAR architecture 3.However,it compromises latency with Pmeta,which is f easible in SARs but not in multi-step ADC

146、s.With the multi-step pipeline operation,the 1st step conversion and residue generation undergo the most critical time constraint with dominated Pmeta 4.Its low precision comparator f rom the sub-quantizer jeopardizes the UD detection 2,3 as it shapes the metastability input interval by noise 12,as

147、shown in Fig.24.4.1.Consequently,the detection results are vastly driven by noise rather than the metastable events,thereby rendering a large error in the corrections.An example with 10LSB input is shown f or a f ailed correction,as the noisy comparator can lead to a larger metastability region than

148、 it.Besides,even with low-noise comparators,the UD detector f ails to identif y the non-deeply metastable artif acts,in which the comparator can still generate a certain output dif f erence but is not strong enough to make the residue DAC f ully settle.Such an impairment is still considerable when i

149、t appears in the 1st step 4 and cannot be well suppressed by the mild gain f rom the succeeding logic circuits.This paper develops a mutually exclusive selection(ME-SEL)technique to eliminate the metastability errors f rom the 1st step conversion.The ME-SEL method f eatures the inherent mutually exc

150、lusive nature of the sub-quantizer and a dual-path residue generation scheme to ensure a metastability-f ree residue generation and 1st stage decision.To verif y the concept,the proposed ME-SEL technique is adopted in a two-step TD ADC.The 1st step is a regular interpolation TD Flash ADC,and the 2nd

151、 step utilizes a pipelined SAR time-to-digital converter(TDC)6,where its timing constraint is eased by the asynchronous pipeline and the timeout assistor embedded in the time comparators.The measurement results demonstrate that the Pmeta is improved f rom 10-4 to 400mV.The single-ended input capacit

152、ance of the TD ADC is 202.5f F,where CS,P/N is 45f F and CS,CM,P/N is 22.5f F in the VTC1 path.The VTC2 path has a double-size capacitance configuration over the VTC1 path.The 28nm ADC prototype occupies 0.032mm2,with a die photo in Fig.24.4.7.The ME-SEL is implemented on-chip while the CCL is of f-

153、chip.The of f sets/gains of the VTCs and the of f sets/radix errors of the SAR TDCs are corrected in the f oreground.Figure 24.4.4 shows the measured spectra of the decimated output(175)with a Nyquist input,achieving a 49.3dB SNDR and a 70.9dB SFDR in the split-ADC mode,a 47.2dB SNDR and a 66.4dB SF

154、DR in the low metastability mode,both sampled at 3GS/s.The ME-SEL technique reduces the measured Pmeta f rom 10-4 to 23GHz BW and sparkle-code error correction,”IEEE Symp.on VLSI Circuits,pp.C162-C163,June 2015.3 J.P.Keane et al.,“An 8GS/s time-interleaved SAR ADC with unresolved decision detection

155、achieving 58dBFS noise and 4GHz bandwidth in 28nm CMOS,”ISSCC,pp.284-285,Feb.2017.4 S.Hashemi et al.,“Analysis of Metastability in Pipelined ADCs,”IEEE JSSC,vol.49,no.5,pp.1198-1209,May 2014.5 S.Cai et al.,“Statistical modeling of metastability in ADC-based serial I/O receivers,”2014 IEEE EPEPS,pp.3

156、9-42,Oct.2014.6 J.Liu et al.,“A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS,”IEEE Symp.on VLSI Circuits,Hawaiian,pp.1-2,July 2024.7 A.S.Yonar et al.,“An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage

157、 Time-Based Gated-Ring-Oscillator ADC with 2 Interpolating Sense-Amplifier-Latches,”ISSCC,pp.266-267,Feb.2023.8 I.-M.Yi et al.,“A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS,”IEEE JSSC,vol.56,no.2,pp.465-475,Feb.2021.9 M.Zhang et al.,“A

158、4 Interleaved 10GS/s 8b Time-Domain ADC with 16 Interpolation-Based Inter-Stage Gain Achieving 37.5dB SNDR at 18GHz Input,”ISSCC,pp.252-254,Feb.2020.10 D.-R.Oh et al.,“A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Of f set Calibration,”IEEE J

159、SSC,vol.54,no.1,pp.288-297,Jan.2019.11 A.Whitcombe et al.,“A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking,”ISSCC,pp.392-394,Feb.2024.12 P.M.Figueiredo,“Comparator Metastability in the Presence of Noise,”IEEE TCASI,vol.60,no.5,pp.1286-1299,May 2013.13

160、 D.Bankman et al.,“Understanding Metastability in SAR ADCs:Part I:Synchronous,”IEEE SSCM,vol.11,no.2,pp.86-97,Spring 2019.14 J.Hao et al.,“A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness,”ISSCC,pp.168-170,Feb.2023.436

161、 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/24.5979-8-3315-4101-9/25/$31.00 2025 IEEE24.5 A 72GS/s 9b Time-Int erleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Input s in 16nm FinFET Yannan Zhang1,Minglei Zhang1,Zehang Wu1,Y

162、an Zhu1,Rui P.Martins1,2,Chi-Hang Chan1 1University of Macau,Macau,China 2Instituto Superior Tecnico/University of Lisboa,Lisbon,Portugal The ever-increasing demands of communication traf fic have driven optical modules to scale beyond 100Gb/s.This evolves aggressive bandwidth and SNDR f rontiers f

163、or their ADCs in the receiver to cope with advanced modulations and oversampling rates.Time-interleaving(TI)is indispensable f or such the near-hundred GS/s envelope,but a massive TI f actor confines the achievable SFDR as well as ENOB at wideband inputs over 20GHz 1.The constraint primarily stems f

164、 rom two regimes,which are the bandwidth mismatch and implicit distortion in the interleaver.Relying solely on timing skew calibration 1-3 f or skew-associated impairments is not suf ficient since it only provides first-order correction f or bandwidth mismatch.An additional order of amendment can be

165、 achieved by tuning the sampling capacitors 1,but the error detection mechanism remains unsound.Furthermore,the input buf f ers of the ADC,interf acing with high-f requency signals and short track time,give rise to distortions and gain attenuation,considerably ruining ADC perf ormance.Minimizing the

166、 TI f actor f or a given sampling rate inherits a better interleaver perf ormance by mitigating the mismatch and distortion sources.The unit-ADC composites SAR with pipeline can push the single-channel to 1GS/s+3,which in turn requires additional background inter-stage gain(ISG)calibration compared

167、to its pure SAR counterparts.This work presents a 72GS/s time-interleaved pipeline-assisted SAR ADC,which leverages linearized wideband input buf f ers and a dual-path bootstrapped switch(BS)to f acilitate 55dB SFDR f or a 20GHz input.Furthermore,an R/R-based open-loop amplifier is introduced,omitti

168、ng the ISG calibration in the 1.125GS/s unit pipeline-SAR ADC.The prototype achieves 46.4dB SNDR and 63.6dB SFDR at low input f requencies and 37.0dB SNDR and 49.3dB SFDR at Nyquist input.Fabricated in a 16nm FinFET technology,it consumes 393.6mW of power,yielding a 53.7f J/conv.-step FoMw with a 20

169、GHz input.Figure 24.5.1 overviews the 64 TI-ADC architecture.The input(VIN)is terminated,bandwidth-extended,and protected by an on-die T-Coil,integrated with the ESD diodes and a 50 termination resistor.Dual input buf f ers drive a two-rank hierarchical interleaver,where the first and second rank ar

170、e with 16-way and 64-way interleaving,respectively.The 1st rank sampled inputs are buf f ered by the 2nd rank sub-buf f ers,each of which supports 4 unit-ADCs.The buf f ered inputs are f urther sampled and quantized by the 64 unit-ADCs,and their outputs are combined and then decimated by a f actor o

171、f 2295 f or measurement.The clock generator receives a dif f erential 36GHz external clock,which is divided by the low jitter current divider to render f our 90-spaced 18GHz clocks(CK18G0-3).These 4-phase clocks are f urther divided into eight and sixteen-phase selection signals EN0 and EN1.The CK18

172、G0-3 are consecutively selected by EN0 and EN1,generating the sampling clocks TH0-15 f or 1st rank track-and-holds(T/Hs).Their clock skews are adjusted by coarse and fine skew tuning delay lines(STDL),with a fine step of 12f s,and additional buf f ers are inserted to reshape the jitter critical edge

173、s.The unit-ADC sampling clocks S0-63 are produced by counting the 1st rank sampling clocks.The reset logic ensures a proper output sequence f or the 16-way TH0-15 and 64-way S0-63.The track time of the 1st rank T/Hs is 27.78ps,and the sampling clocks within a group,driven by the same input/sub-buf f

174、 ers,are non-overlapping,which prevents undesired crosstalk among channels.Wideband-linearized source-f ollower(SF)buf f ers and dual-path bootstrapped switches(Fig.24.5.2)are exploited in the input-associated buf f ers and T/Hs to f acilitate a high SFDR over wideband input.The SF 4-5 retains decen

175、t energy ef ficiency but suf f ers f rom lower-than-unity gain,poor linearity,and slew rate.Dif f erent f rom 5,which leverages a cross-connected(CC)-NMOS pair solely f or gain enhancement,this design employs an AC-coupled CC-PMOS pair(comprising R,C,M3,and M4)to compensate f or the compressing-type

176、 of nonlinearity of the P-type SF over wideband input.Since the distortion of the SF exacerbates at high input f requencies,the compensation must also be adaptive.The common-source(CS)f eature f rom M3/4 of f ers a process-stable expanding-type of compensation,but the dynamic distortion characterist

177、ics of the CS and SF are f undamentally dif f erent across a wide input f requency range.Theref ore,an additional“knob”enabled by the high-pass filter(HPF,comprising R and C)is introduced,which allows the compensation to be 1st order adaptive to the input f requency.In the actual design,the size of

178、the AC-coupled CC pair and the corner f requency of the HPF are designed to ensure 60dB SFDR up to 20GHz input.The additional capacitance introduced by the compensation pair is less than 5%of the total input capacitance of the buf f er,ensuring negligible bandwidth degradation.Figure 24.5.2 also dep

179、icts the simulated SFDR improvement compared to the conventional SF under the same load and bias current,where the technique maintains 4dB+SFDR improvement up to 40GHz 0dBFS inputs.The additional pushing ability also enhances the slew rate and bandwidth by 20%and 12%,respectively.A similar lineariza

180、tion scheme also applies to the sub-buf f er,as given in Fig.24.5.2;while the HPF is omitted,and the compensation ability is stabilized by the degeneration resistor RD.The direct-coupled pair in the sub-buf f er potentially aggravates kickbacks to the preceding T/H within the settling process,dimini

181、shing the linearity improvement.In this configuration,caref ul design of the succeeding T/H and CC pair ensures a 4dB+SFDR improvement over various input tracking f requencies.Utilizing a simple and ef ficient NMOS as the sampling switches in the T/H is a common choice 1,4 under a short track time,b

182、ut it necessitates a low input common mode and high clock driving voltages 4,constraining the peripheral circuit designs.The realized T/H bandwidth is also prone to these voltage variations,thereby exhibiting undesired large bandwidth mismatch and limiting the achievable SFDR at high input f requenc

183、y.The bootstrapped switches are more robust,but maintaining a f ast tune-on/of f becomes the major obstacle f or 27ps-only track time in this design.Figure 24.5.2 illustrates the presented dual-path BS switch that unrolls the input level-shif ting controls with a duplicated path.In consequence,the c

184、ritical node VBST accommodates significantly less parasitic capacitance(CP)by removing M2 and its associated control devices f rom the main path,thus allowing a f ast turn-on/of f.Splitting the boosting capacitor(CB1 and CB2)while maintaining total capacitance f acilitates dif f erent manipulations

185、of the overdrive voltage(Vov)f or M1 and M2.This design assigns a higher Vov f or M1 within the same total boosting capacitance budget as the conventional one.Compared to 6,the rise time and f all time at VBST are improved by 1.5 and 1.2,respectively.It also enhances the nominal boosted voltage by 1

186、50mV and track time by 5.2ps,advancing the high-input-f requency SFDR by 10dB.Cross-coupled dummy switches with dummy BSs mitigate signal f eedthrough f rom the drain-to-source and drain-to-gate nodes of the BS switches at high-f requency input.A simple pull-down dummy in 7 f ails to suppress the ga

187、te-associated signal f eedthrough within 1LSB;theref ore,a complete dummy without CB1/CB2 is presented.The unit-ADC in Fig.24.5.3 is a two-stage 9b pipeline SAR ADC where the 1st and 2nd stages resolve 4b and 6b,respectively,with 1b redundancy between stages.The R/R-based residue amplifier realizes

188、a PVT-stable inter-stage gain of 6.This amplifier consists of a CS cascaded stage(M1,M3,M5,and M7)and a resistive f eedback network(R1 and R3).The output of the cascaded amplifier is f ed back to its negative input(source of M1)through the resistive network,bootstrapping its gain(GAMP)to 1+R1/R3 in

189、a negative f eedback manner,and thereby eliminating the need f or ISG calibration.Simulation results demonstrate 36GS/s(half-f old of 72GS/s)prior arts.It achieves an outstanding SNDR and SFDR at 20GHz fin,and yields a 151.5dB FoMS.It also reports up to 40GHz input SFDR.Acknowledgement:This work was

190、 supported by Macau FDCT(File no.0050/2022/A1 and 004/2023/SKL)and in part by the University of Macau Research under Grant MYRG2022-00133-IME.Figure 24.5.1:Time-int erleaved ADC archit ect ure(t op left),clock generat ion archit ect ure(t op right),and t iming diagram(bot t om).Figure 24.5.2:Impleme

191、nt at ion of linearized buffers(t op left),dual-pat h boot st rapped swit ch(t op right),SFDR improvement compared t o SF(bot t om left),and BS performance comparison(bot t om right).Figure 24.5.3:Single-channel archit ect ure(t op),VCM-regulat ed swit ching(bot t om left),proposed residue amplifier

192、(bot t om right).Figure 24.5.4:Measured out put spect ra.Figure 24.5.5:Measured SNDR/SFDR versus input frequency(t op left),supply variat ion(t op right),measurement amplit ude(bot t om left),and DNL/INL(bot t om right).Figure 24.5.6:Performance summary and comparison.ISSCC 2025/February 19,2025/10:

193、05 AM437 DIGEST OF TECHNICAL PAPERS 24 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 24.5.7:Die phot o of t he t ime-int erleaved ADC.Refer ences:1 L.Kull et al.,“A 10-Bit 20-40 GS/S ADC with 37 dB SND

194、R at 40 GHz Input Using First Order Sampling Bandwidth Calibration,”2018 IEEE Sy mpos ium on VLSI Cir cuit s,Honolulu,HI,USA,2018,pp.275-276.2 W.Zhang,M.Zhang,Y.Zhu,R.P.Martins and C.-H.Chan,“A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buf f er and Dif f e

195、r-Based Dither Timing Skew Calibration,”2024 IEEE Cus t om Int egr at ed Cir cuit s Confer ence(CICC),Denver,CO,USA,2024,pp.1-2.3 A.Whitcombe et al.,“A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking,”2024 IEEE Int er nat ional Solid-St at e Cir cuit s

196、Confer ence(ISSCC),San Francisco,CA,USA,2024,pp.392-394.4 A.S.Yonar et al.,“An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buf f er in 4nm CMOS,”2022 IEEE Sy mpos ium on VLSI Technology and Cir cuit s (VLSI Technology and Cir cuit s),Honolulu,HI,USA,2022,pp.168-169.5

197、 S.Kiran,S.Cai,Y.Luo,S.Hoyos and S.Palermo,“A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.54,no.3,pp.659-671,March 2019.6 A.T.Ramkaj,J.C.Pena Ramos,M.J.M.Pelgrom,M.S.J.Steyaer

198、t,M.Verhelst and F.Tavernier,“A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.55,no.6,pp.1553-1564,June 2020.7 Y.Zhu et al.,“A 38-GS/s 7-bit Pipelined-SAR ADC Wi

199、th Speed-Enhanced Bootstrapped Switch and Output Level Shif ting Technique in 22-nm FinFET,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.58,no.8,pp.2300-2313,Aug.2023.8 K.Sun,G.Wang,Q.Zhang,S.Elahmadi and P.Gui,“A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-n

200、m CMOS,”in IEEE Jour nal of Solid-St at e Cir cuit s,vol.54,no.3,pp.821-833,March 2019.9 L.Kull et al.,“A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and 30dB SNDR at nyquist in 14nm CMOS FinFET,”2018 IEEE Int er nat ional Solid-St at e Cir cuit s Confer ence-(ISSCC),San Fr

201、ancisco,CA,USA,2018,pp.358-360.10 R.L.Nguyen et al.,“A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35f J/conv-step f or 400Gb/s Coherent Optical Applications in 7nm FinFET,”2021 IEEE Int er nat ional Solid-St at e Cir cuit s Confer ence(ISSCC),San Francisco,CA,USA,20

202、21,pp.136-138.11 C.Nani et al.,“A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz,”2024 IEEE Sy mpos ium on VLSI Technology and Cir cuit s (VLSI Technology and Cir cuit s),Honolulu,HI,USA,2024,pp.1-2.12 R.L.Nguyen et al.,“A 200GS/s 8b 20f J/c-s Rec

203、eiver with 60GHz AFE Bandwidth f or 800Gb/s Optical Coherent Communications in 5nm FinFET,”2024 IEEE Int er nat ional Solid-St at e Cir cuit s Confer ence(ISSCC),San Francisco,CA,USA,2024,pp.344-346.438 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS

204、/24.6979-8-3315-4101-9/25/$31.00 2025 IEEE24.6 A Power-and Area-Efficient 4nm Self-Calibrat ed 12b/16GS/s Hierarchical Time-Int erleaving ADC Cheng-En Hsieh*1,Gabriele Manganaro*2,Sheng-Hui Liao*1,Jack Weng*1,Tsun-Yuan Fan1,Alec Chin1,Tsung-Chih Hung1,Jonathan X Wu2,Chi-Lun Lo2,Andy Pan1,Ming-Hang H

205、sieh1,Yun-Shiang Shu1,Wei-Hsin Tseng1,Kuan-Dar Chen1 1MediaTek,Hsinchu,Taiwan 2MediaTek,Woburn,MA *Equally Credited Authors(ECAs)Array processing systems f or wideband communication and sensing applications are progressively using a growing number of analog/RF elements.These systems require multiple

206、 identical analog-to-digital converters(ADCs)in fine lithography systems-on-a-chip(SoCs)f or digital processing.Thermal and area constraints lead to increasingly stringent requirements on the individual power consumption(hence ef ficiency),physical size(hence cost),of all the integrated f unctions,i

207、ncluding the data converters.This paper introduces an interleaved 12b/16GS/s ADC,implemented in a 4nm FinFET process,which addresses power and area challenges by incorporating innovations at both architecture and circuit levels.The ADC consumes 570mW,including calibration,on-chip supply regulation,r

208、ef erence buf f ers etc.,with a Schreier figure of merit(FoMS)of 148dB at Nyquist and an area of 0.430mm2.It achieves a small-signal(-30dBFS)noise spectral density of -155dBFS/Hz,non-harmonic spurs better than-68dBFS(f or a-1dBFS input tone at 7.4GHz),and a high-f requency SFDR of 58dBc(also-1dBFS i

209、nput tone at 7.4GHz)limited by HD2(-58dB)and HD3(-64dB),advancing the state-of-the-art.Time-interleaved(TI)ADCs with comparable dynamic perf ormance have been presented 1-6.While each one has distinct aspects,in a top-down architecture design process,these ADCs aim to reduce complexity,mismatches,an

210、d calibration ef f orts by minimizing the number(N)of interleaved sub-ADCs 1-6.For that,the core sub-ADC is designed to sample at the highest rate allowed bef ore its power ef ficiency is substantially compromised.Sophisticated TI architectures and companion calibration algorithms have been develope

211、d to address interleaving artif acts 6.A dif f erent approach has been adopted here.In a technology like 4nm,the physical implementation is crucial since interconnect nonidealities significantly impact the perf ormance of sub-ADCs and the overall TI architecture.Because of the increasingly large dif

212、 f erence in metal thickness among levels,dif f erences in design rules on distance,pitch,etc.,interconnect physical dimensions and relative strays can dif f er f rom 2 to 10 among the metal levels and among vias between levels 7,8.Our approach prioritizes local and low-level interconnects f rom the

213、 outset,while also reducing global interconnects at all design levels leading to a distributed,compact,and power-ef ficient architecture with high multiplicity N.Sub-ADCs and analog stages are designed to be simplest f or a compact physical implementation,minimizing distances and level transitions,w

214、hile acknowledging the impact to static analog errors.Scaling-f riendly digital calibration is employed to address mismatches and static non-idealities.A hierarchical TI architecture with N=16 sub-ADCs and L=4 track-and-hold amplifiers(THAs),as depicted in Fig.24.6.1,has been identified as the optim

215、al compromise choice f or this process,path mismatch,parametric spread and target dynamic specifications.This determination is based on exploring trade-of f s at dif f erent abstraction levels,guided by comprehensive mixed-abstraction-level simulations of various architecture options,combining f unc

216、tional and transistor-level models together with layout-extracted models of key interconnect structures.While area/power ef ficiencies can be obtained in this technology with relatively high N,it is essential to capture upf ront the f ront-end signals/clock trees as well as the path mismatches,other

217、wise growing unmanageable.The dependence of the architecture choices,and their underlying trade-of f s,f rom the process technology characteristics,particularly when contrasting planar CMOS versus deep nanometer FinFET,could not be overstressed(see e.g.2 versus 3).For fixed SNDR and neglecting TI ov

218、erhead,mismatch and stray losses,the power ef ficiency of a single THA sampling at fs=1/Ts versus combining L=2 TI THAs,each one sampling at fs/2,is the same.The same is true f or L=4,with 50%duty-cycle THAs track phases clocked at fs/4.But,using the s1-s4 25%duty-cycle clocks in Fig.24.6.1,while th

219、e track phase(s1-s4 high)lasts Ts(as f or L=2),the hold phase(s1-s4 low)lasts 3Ts,enhancing the total ef ficiency of the 4 TI THA by 33%compared to previous cases.When simulating f or the actual amplifier drive capability and all the strays(including routing into the f our THAs and out to the f ollo

220、wing sub-ADCs),the extended hold time of each THA results in greater net saving.The f our THAs are driven by a push-pull class-AB buf f er shown in Fig.24.6.2 providing a controlled input impedance of 100 dif f erential to the of f-chip signal source,consuming about 22mW f or f ull-scale input signa

221、l power,including its bias circuit and dedicated on-chip LDO.Each sub-ADC,clocked at fs/16,is a pipeline-SAR hybrid with five pipelined 1.5b/stage MDACs,employing the pre-sampling technique 9,f ollowed by a 7b SAR.For each THA driving f our sub-ADCs,the above 4-phase clock strategy could apply with

222、a 3Ts sub-ADC acquisition time and a long 13Ts conversion phase.But transistor-level simulations show diminishing relative benefits.Instead,the MDAC amplifiers are time-shared between pairs of sub-ADCs,as in Fig.24.6.2.That is,they are 2 interleaved,clocking at fs/8,while the back-end quantizer 7b S

223、ARs(SAR-A,SAR-B)are individually clocked at fs/16 without sharing.For 7b resolution,a SAR back-end provides a moderate capacitive loading to the previous stage and the ref erence buf f ers,it is power-ef ficient and considerably simplifies routing complexity.Individual sub-ADCs are digitally calibra

224、ted f or radix errors.To address interleaving errors,blind autocorrelation-based background calibration is used f or of f set mismatches,gain error mismatches,and sampling time skew.While of f set and gain error mismatch calibration of the 16 interleaved paths is entirely digital,automatic correctio

225、n of each of the 4 sampling skews is achieved by adjusting each THAs sampling edge with digitally controlled delays(DCDL).To mitigate singular error conditions of the correlation blind algorithms due to non-modulo N quasi-stationary inputs 6,new digital singularity detectors have been introduced.The

226、se detectors identif y singularities by observing significant dif f erences in the peak autocorrelations of the TI paths as the input approaches a singular condition.When the magnitude of such dif f erences crosses a set threshold,a singularity is detected,temporarily halting the background update o

227、f calibration coef ficients until the input signal returns to a regular state.The schematic of one of the f our flip-around THAs is shown in Fig.24.6.3.The sampling switches S1 and the f eedback switches S2 are bootstrapped using a near-conventional topology shown in Fig.24.6.3 f or S1.The amplifier

228、 is a complementary pseudo-dif f erential amplifier with two input pairs(Vih+,Vih-)and(Vil+,Vil-)operating at distinct common mode levels Vcmh(high)and Vcml(low)10.The split sampling capacitors Cs/2 also perf orm level shif ting.This gives an advantage f or the bottom plate switches S3 using a new b

229、ootstrapping topology shown in the lower right corner of Fig.24.6.3.The lower-half switch operates near Vcml f or the amplifiers lower-half (n-type).The actual switch is the composite 3-nMOS MBP,setting the amplifiers inputs(Vil+,Vil-)to Vcml when e is high and sampling at its f alling edge.MBPs gat

230、e voltage Vbtsn is bootstrapped by CPMP3,shorting to Vcml through a pass gate when e is low,turning MBP of f,while the top plate of CPMP3 is grounded.When e goes high,Vbtsn jumps up to Vcml+VDD,bootstrapping MBP.Finally,the dummies MFTR cancel MBPs clock f eedthrough.This topology is simpler,f aster

231、,smaller and more power ef ficient than a conventional bootstrapped switch,because MBP is always near the constant voltage Vcml and this is close to ground,minimizing the charge transf er required f or CPMP3.But higher voltage transistors are required f or the pass gates since these experience trans

232、ients above VDD.Using the same ideas,a complementary topology f or the companion higher-half common-mode switch that has Vcmh close to VDD,bootstraps the gates of the corresponding common-mode pMOS switches to Vcmh-VDD.An even simpler structure is employed f or the output reset switch S4 also requir

233、ing a high voltage switch.The shared amplifiers of the sub-ADC MDACs also use a dual-input complementary amplifier.All supplies are regulated by dedicated on-chip LDOs,embedded with each block.Their power consumption is lumped with the blocks.The same is true of the ref erence voltage buf f ers and

234、their power consumption.The total ADC power consumption,f or f ull-scale input(1.1Vppd),including LDOs,calibration,buf f ers,ref erences,etc.is 570mW.The sub-ADCs consume 40%of this,the clock generation and distribution accounts f or 27%,the THAs take 23%,the f ront-end buf f er consumes 4%,and the

235、background TI calibration uses the residual 6%.Exemplary spectra f or a-1dBFS tone input at dif f erent f requencies fin,sampled at 16GS/s,are shown in Fig.24.6.4,together with the SNDR and SFDR versus fin and fs.The non-harmonic spurious perf ormance,with TI calibration on and of f,is also shown in

236、 Fig.24.6.4.The harmonic distortion limits the SFDR.This is due mainly to the class AB f ront buf f er and,to a lesser extent,the ADC THAs.But(quasi)-static harmonic distortion is becoming less of a concern as ef ficient post-distortion linearization is adopted f or embedded ADCs 1,4,10-12.The noise

237、 spectral density is limited mainly by the sampling jitter,as seen by comparing it f or small-vs-large signal at high f requency.The sampling clock f or these measurements has been generated by an on-chip PLL with an estimated rms jitter of 80f s rms.An example of digitized spectra f or a 400MHz-wid

238、e modulated 64QAM input centered at fc=4.4GHz,with TI calibration disabled and enabled is reported in Fig.24.6.5.A table summarizing the ADC perf ormance,and a comparison with ADCs of similar specifications,is shown in Fig.24.6.6.A die micrograph is shown in Fig.24.6.7.Figure 24.6.1:Time-int erleave

239、d(TI)archit ect ure.Figure 24.6.2:Det ailed archit ect ure implement at ion,including sub-ADCs,pre-sampling MDAC and front-end push-pull buffer.Figure 24.6.3:Track-and-hold circuit,including complement ary amplifier and boot st rapped swit ches.Figure 24.6.4:Measured out put spect ra,SNDR/SFDR at 16

240、GS/s vs fin,SFDR vs fin excluding HD wit h and wit hout TI calibrat ion,SNDR/SFDR for fin=1.2GHz vs fs.Figure 24.6.5:Measured spect ra for a 64QAM modulat ed signal wit h cent er frequency fc=4.4GHz,400MHz bandwidt h,120KHz sub-carrier spacing.The t ables show t he power of t he int erleaving spurs

241、due t o offset mismat ch.Figure 24.6.6:Performance summary and comparison wit h comparable st at e-of-t he-art ADCs.ISSCC 2025/February 19,2025/10:30 AM439 DIGEST OF TECHNICAL PAPERS 24 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-41

242、01-9/25/$31.00 2025 IEEEFigure 24.6.7:Die micrograph.Refer ences:1 S.S.Kumar et al.,“A 750mW 24GS/s 12b Time-Interleaved ADC f or Direct RF Sampling in Modern Wireless Systems,”2023 IEEE International Solid-State Circuits Conf erence(ISSCC),San Francisco,CA,USA,2023,pp.1-3.2 Y.Cao,M.Zhang,Y.Zhu,R.P.

243、Martins and C.-H.Chan,“A 12GS/s 12b 4 Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buf f er,”2024 IEEE International Solid-State Circuits Conf erence(ISSCC),San Francisco,CA,USA,2024,pp.388-390.3 K.-J.Moon et al.,“A 12-bit 10GS/s 16-Channel Time-Int

244、erleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET,”2022 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Honolulu,HI,USA,2022,pp.172-173.4 A.M.A.Ali et al.,“A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Ampli

245、fier and Background Calibration,”2020 IEEE International Solid-State Circuits Conf erence-(ISSCC),San Francisco,CA,USA,2020,pp.250-252.5 S.Devarajan et al.,“A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology,”in IEEE Journal of Solid-State Circuits,vol.52,no.12,pp.3204-3218,Dec.2017.6

246、G.Manganaro,“An Introduction to High Sample Rate Nyquist Analog-to-Digital Converters,”in IEEE Open Journal of the Solid-State Circuits Society,vol.2,pp.82-102,2022.7 K.Park and H.Simka,“Advanced interconnect challenges beyond 5nm and possible solutions,”2021 IEEE International Interconnect Technolo

247、gy Conf erence(IITC),Kyoto,Japan,2021,pp.1-3.8 Y.Lee et al.,“Investigation on the Ef f ects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit,”in IEEE Access,vol.10,pp.80695-80702,2022.9 S.-E.Hsieh,T.-C.Wu and C.-C.Hou,“A 1.8GHz 12b Pre-Sampling Pipelined ADC with Ref e

248、rence Buf f er and OP Power Relaxations,”2023 IEEE Int er nat ional Solid-St at e Cir cuit s Confer ence(ISSCC),San Francisco,CA,USA,2023,pp.166-168.10 C.Jabbour,P.Desgreys,D.Dallet(Ed.s),“Digitally Enhanced Mixed Signal Systems,”London,U.K.:IET Press,2019.11 B.Clment,Y.Serrestou,K.Raoof and P.Urard

249、,“Static nonlinear errors compensation f or RF f ront-end circuit on high speed RF sampling(Ti)ADCs,”2023 IEEE International Conf erence on Design,Test and Technology of Integrated Systems(DTTIS),Gammarth,Tunisia,2023,pp.1-7.12 A.Salib,M.F.Flanagan and B.Cardif f,“A Generic Foreground Calibration Al

250、gorithm For ADCs With Nonlinear Impairments,”in IEEE Transactions on Circuits and Systems I:Regular Papers,vol.66,no.5,pp.1874-1885,May 2019.440 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/24.7979-8-3315-4101-9/25/$31.00 2025 IEEE24.7 An 8b 10GS/

251、s 2-Channel Time-Int erleaved Pipelined ADC wit h Concurrent Residue Transfer and Quant izat ion,and Aut omat ic Buffer Power Gat ing Yunsong Tao,Mingtao Zhan,Mingyang Gu,Xiyu He,Yuxuan He,Zhishuai Zhang,Yi Zhong,Lu Jie,Nan Sun Tsinghua University,Beijing,China High-speed(10GS/s)medium-resolution(8b

252、)ADCs are key blocks f or wideband applications.Time-domain ADCs can achieve 5GS/s single-channel speed 1,2,but their reliance on matched gate delays leads to high sensitivity to PVT variations and device mismatches.By comparison,voltage-domain(flash/SAR/pipeline)ADCs are more robust against PVT and

253、 mismatches.However,flash ADCs are limited to 6b f or their exponentially growing complexity with resolution 3.SAR ADCs are ef ficient at 8b,but their limited single-channel speed(6GS/s.The concept of the proposed high-speed dif f erential-sampling pipelined stage is shown in Fig.24.7.1.Taking the N

254、th stage as an example,the dif f erential sampling occurs in 1.It integrates the sampling and amplification into 1 operation and achieves a 2 passive gain 6,7.At the start of 2,the quantization result f rom the previous stage is f ed to the DAC,generating the residue.Then,the residue is buf f ered t

255、o the next stage.Concurrently,the comparator is triggered and its digital output is sent to the next stage.Thus,the speed of the proposed pipelined stage is accelerated by having only 2 operations in a clock period(sampling/amplification and quantization/residue buf f ering).Moreover,since the gain

256、is achieved by dif f erential sampling,the power-consuming high-speed linear RA can be eliminated,and instead,a unity-gain buf f er is used to transf er the residue.Theref ore,unlike 5 where the RA requires complex linearization methods and suf f ers f rom saturation,the unity-gain buf f er inherent

257、ly shows better linearity,and guarantees an in-range output.Furthermore,it has a wider bandwidth compared to an RA,assuming the same gain-bandwidth product,and hence,the speed of the proposed pipelined stage is notably enhanced.Figure 24.7.2 shows the detailed schematic and timing diagram of the pro

258、posed ADC.It consists of an input buf f er and 2 TI pipelined channels.Each channel is composed of ten 1b stages.The SF is adopted as the input buf f er as well as each inter-stage unity-gain buf f er.The detailed timing operation is as f ollows.During 1,the input signal VIN is buf f ered to stage 0

259、 in channel 1.A dif f erential signal V is sampled on the capacitor CS0 at the end of 1,where V=VRP0 VRN0(assuming V 0).Then the bottom plate of CS0 is boosted to VREFCM to set the suitable CM voltage f or the SF0 input at the start of 2.During 2,VRP/N0 is conveyed to the capacitor CS1 in stage 1 th

260、rough SF0 with the dif f erential-sampling arrangement,and simultaneously,the comparator in stage 0 is fired f or the MSB decision D0.Note that the dif f erential signal V is sampled on both plates of CS1,but with a flipped sign on positive and negative sides of the channel.At the start of next 1,it

261、 is subtracted with ref erence VREFP/N f or residue generation depending on D0.Specifically in this case,the positive side VRP1 with sampled signal V is raised by VREFN,i.e.,VRP1=VREFN+V,while the negative side VRN1 with sampled signal V is added by VREFP,i.e.,VRN1=VREFP V.Theref ore,the 2 passive g

262、ain is obtained and the residue is generated,i.e.,VRP1 VRN1=2V VREF.Figure 24.7.2 corresponds to an example of V=0.7VREF.Then during 1,the residue is delivered f rom stage 1 to stage 2 using dif f erential sampling through SF1,and the comparator works in parallel to generate D1.The whole procedure o

263、f stage 1 is repeated in all remaining stages.Considering the parasitic capacitance CP coming f rom the sampling capacitor CS(10f F single-ended),the sampling switches,and the input transistors of the SF and comparator,the actual passive gain achieved by dif f erential sampling is calculated as GDS=

264、(2CS+CP)/(CS+CP)1.6.In addition,the residue transf er by the SF of f ers a gain of around 0.8,less than unity due to the finite intrinsic gain.To increase the inter-stage gain and reduce the number of pipelined stages,the ref erence voltages f or all dif f erential-sampling stages are generated f ro

265、m a modified“R-2R”DAC with a scaling f actor of 0.75.Theref ore,combining dif f erential sampling,residue transf er,and ref erence scaling results in the actual inter-stage gain,i.e.,GSTG=GDSGSFGREF 1.60.81/0.75=1.7.This provides inter-stage redundancy in a 1b stage and aggregates to 8b resolution w

266、ith 10 stages.To f urther reduce the power consumption of the SF in the dif f erential-sampling phase 1,an automatic CM-regulated power-gating mechanism is added to the SF,as shown in Fig.24.7.3.Without power gating,the SF operates in both 1 and 2,and consumes constant static current in the whole cl

267、ock period.Thus,about half of the static power is wasted.One commonly used switch-based power-gating method is to cut of f the current with a switch inserted in the main branch of the SF 8.During 1 when the SF is idle,the switch is turned of f and the static power is saved.However,the switch size ne

268、eds to be as large as the main transistor M1 to reduce the on-resistance RON and occupy as little headroom as possible,especially in advanced technology nodes with low power supply.This means that large extra switching power f or driving this switch needs to be paid under high-speed operation,and he

269、nce,the total power consumption still remains high.To remove the extra switch,the proposed automatic CM-regulated power-gating technique reuses the transistor M1 as the switch to cut of f the SF current.Af ter dif f erential sampling and residue generation,the SF buf f ers the residue VR to the next

270、 stage.Since dif f erential sampling cancels the CM voltage on both plates of CS,the CM voltage at the SF input can be directly determined by the ref erence voltage during ref erence subtraction.To avoid reliability issues,it is set to guarantee that VR is below VDD in all stages,i.e.,VRk VDD f or a

271、ny k.This condition applies to stage 2N1 when the residue VR2N1 is buf f ered to its f ollowing stage 2N through the SF during 1,i.e.,VR2N1 VDD.Then VR2N will experience a VGS level-down shif t,i.e.,VR2N=VR2N1 VGS VDD VGS,where VGS is the gate-source voltage of the transistor M2.In this design with

272、VDD at 1V and the internal single-ended signal swing around 0.25V,the threshold voltage Vth and VGS are chosen to be 500mV and 550mV,respectively.This means that VR2N will switch of f the transistor M1 in stage 2N because VR2N VDD VGS=450mV 36.4dB SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchr

273、onous Successive Approximation in 28nm CMOS,”ISSCC,pp.278-280,Feb.2023.3 V.H.-C.Chen and L.Pileggi,“An 8.5mW 5GS/s 6b Flash ADC with Dynamic Of f set Calibration in 32nm CMOS SOI,”IEEE Sy mp.VLSI Cir cuit s,pp.C264-C265,June 2013.4 Y.Tao et al.,“A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-

274、Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Of f set Calibration,”ISSCC,pp.394-396,Feb.2024.5 Z.Zheng et al.,“A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation,”ISSCC,pp.254-256,Feb.2020.6

275、S.-E.Hsieh et al.,“A 1.8GHz 12b Pre-Sampling Pipelined ADC with Ref erence Buf f er and OP Power Relaxations,”ISSCC,pp.166-168,Feb.2023.7 T.Oshima et al.,“A 0.75V 0.016mm2 12ENOB 7nm CMOS Cyclic ADC with 1.5bit Passive Amplification Stage and Dynamic Capacitance Scaling,”IEEE Sy mp.VLSI Cir cuit s,p

276、p.1-2,June 2023.8 X.Pan et al.,“A 12b 1GS/s ADC with Lightweight Input Buf f er Distortion Background Calibration Achieving 75dB SFDR over PVT,”IEEE CICC,pp.1-2,April 2023.442 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/24.8979-8-3315-4101-9/25/$

277、31.00 2025 IEEE24.8 A 12GS/s 9b 16 Time-Int erleaved SAR ADC in 16nm FinFET Junhua Shen1,Wei-Hung Chen2,Ef ram Burlingame3,Stephen Weinreich1,Michael Elliott4,Stuart McCracken1,Jack Kenney2,Janet Brunsilius3,Anil Korkmaz5,Enrique Alvarez Fontecilla3,Nevena Rakuljic3,Ushma Mehta3,Ben Sullivan1,Jeremy

278、 Scuteri5,Bac Binh Luu3,Mitchell Nichols3,Dara Martin6,Richard Sullivan5,Daniel DeBolt1,Ron Kapusta1 1Analog Devices,Wilmington,MA 2Analog Devices,Somerset,NJ 3Analog Devices,San Diego,CA 4Analog Devices,Austin,TX 5Analog Devices,Durham,NC 6Analog Devices,Limerick,Ireland Time-interleaved(TI)SAR ADC

279、 architecture is pref erred in the low-to-moderate resolution space to achieve GS/s speed f or its excellent power and area ef ficiency 1-3,as well as to reduce design complexity,which may lead to f ewer tape-outs and f aster product development.High-speed and medium-resolution ADCs are used in appl

280、ications like wireless communications and portable instrumentation.Emerging applications such as RF direct sampling in f ully digital phased arrays require similarly high sample rates,but they also demand RF SNDR beyond 45dB.In 4-6,high-speed SAR ADCs with such SNDR were reported.Of ten,3 or more su

281、pply domains are utilized and tailored f or optimized analog perf ormance,as in 4,5,making integration into a larger transceiver system dif ficult.In this paper,we present a 12GS/s 16 TI SAR ADC that achieves 48.1dB SNDR at 5.3GHz input,consumes 160mW f rom integration-f riendly 1.8V and 0.8V standa

282、rd process supplies and occupies 0.25mm2 in 16nm FinFET.To achieve this perf ormance,several circuit techniques are introduced.First,ref erence reservoirs are used to maximize DAC settling speed 7,8,with an aggressive ratio not previously demonstrated.Second,a leakage reduction technique is proposed

283、 to maintain ref erence integrity on the small reservoir capacitors,allowing the ADC to maintain its perf ormance across extreme conditions of process and temperature variation.Finally,a new technique is introduced to minimize the delay induced when storing and transf erring comparator decisions to

284、the DAC.Figure 24.8.1 shows the top-level ADC and sub-ADC architectures.High-level modeling showed 16 interleaving and 750MS/s per sub-ADC was the right trade-of f to achieve 12GS/s to balance f ront-end input buf f er drivability and sub-ADC ef ficiency.A common f ront-end continuous-time input buf

285、 f er drives 16 sub-ADCs directly,with single-rank sampling.The sub-ADCs sample in non-overlapping round-robin f ashion to minimize coupling between them,each tracking the input f or 83ps,or one 12GHz period.Interleaving of f set,gain,and timing skew errors are calibrated,as well as bit-weight error

286、s within each sub-ADC.The SAR loop is self-timed,with a DAC timer that tracks DAC settling 7,to maximize conversion speed.Top-plate sampling is employed to improve ADC input-ref erred noise and reduce the first bit trial duration.Resolving a single bit per trial,when compared to a multi-bit design,m

287、inimizes input buf f er load,area,complexity,and maximizes the speed benefit f rom asynchronous operation.The SAR comparator is comprised of an integrator first stage f ollowed by a latch stage f or best noise ef ficiency 9.The segmented capacitive DAC in the sub-ADC has 12 bit trials including 9 re

288、gular bits,1 redundant bit,and 2 repeat bits which are included at the end to improve overall conversion noise and power ef ficiency 10.Each bit trial is allocated roughly 100ps which,combined with the tracking time,equals the 750MS/s period.For lowest noise,the comparator decision consumes most of

289、the 100ps bit trial,while DAC settling and control logic delay are af f orded 15-25ps each.To speed up DAC settling,a large reservoir capacitor can be used to serve as the ADC ref erence during bit trials and is replenished during the tracking phase 7,8.This technique utilizes on-chip-only charge re

290、distribution between the reservoir and bit capacitors without the need f or large decoupling capacitance.Importantly,it also eliminates coupling between sub-ADCs through the ref erence.Figure 24.8.2 illustrates one reservoir capacitor per bit capacitor technique proposed in 10.The error introduced f

291、 rom charge sharing is signal independent and thus calibratable as simple capacitor mismatch would be 10.The local-to-each-bit reservoir capacitor also minimizes interconnect and f urther speeds up DAC settling.In previous implementations,the ratio between the reservoir and bit capacitors could not

292、be too small,otherwise the associated voltage/temperature(V/T)dependent parasitic capacitors cause bit weights to shif t over V/T.In this work,an aggressive reservoir-to-bit capacitor ratio of down to 3:1 is used,saving area,and dither-based background calibration tracks bit-weight variation with V/

293、T.The cross-section in Fig.24.8.2 shows the compact unit structure f ormed between the reservoir-and bit-capacitors stacked over the switching network.The resulting DAC settles to the required accuracy within 20ps.One challenge with aggressively scaling reservoir capacitors smaller is the increased

294、error caused by leakage through nominally“of f”ultra-low Vth(ULVT)bit switches.A half circuit of Fig.24.8.2,comprising Cres,i and two of the f our bit switches,is re-drawn in Fig.24.8.3 along with a proposed circuit to mitigate of f-leakage.During ADC conversion,one of the switches bni and bpi will

295、always be on while the other remains of f.ULVT devices are used f or these switches to maximize speed,but the of f device will unf ortunately leak.To counteract this leakage,a tiny coupling capacitor Cc is added at the switching node Vg.Af ter the comparator decision propagates to the gates of bni a

296、nd bpi,the driving inverter is tri-stated via the low-active go_bi-1 signal,and the f alling edge of this signal also capacitively couples 100mV onto Vg to place the of f switch in deep turn-of f region.The added capacitor is a small f raction of the existing parasitic on the Vg node,theref ore havi

297、ng little impact on the signal delay.The control signal go_b is generated by the SAR control logic and is also used f or trial sequencing.The timing requirement of the control signal is relaxed as it is not critical to immediately reduce leakage af ter the comparator decision is made,but only to do

298、so bef ore appreciable charge is lost f rom the reservoir.To avoid leakage in the tri-stated inverter,larger series SVT devices are used.In addition,due to the asynchronous SAR ADC operation,the boosted Vg needs only to stay constant f or about 1ns,regardless of ADC operating speed.SAR direct decisi

299、on f eedback is proposed to minimize the delay between the comparator output and DAC input,while still perf orming the required control logic f unction.Conventionally,as shown in the lef t of Fig.24.8.4,dedicated latches capture each comparator decision prior to the comparator resetting and buf f er

300、 the captured decision to drive the DAC 11,12.The simulated delay of this storage plus buf f er f unction did not meet speed requirements,particularly across PVT.The right of Fig.24.8.4 shows the proposed direct decision f eedback method.Instead of latching the comparator decision prior to DAC f eed

301、back,the comparator decision is directly f ed to the DAC through a series switch.The series switch is then turned of f as soon as the decision has propagated through the switch,isolating the decision at the nodes bn-i with high impedance,similar to dynamic logic.Once bn-i is isolated,the comparator

302、decision can saf ely reset in preparation f or the next comparison.A decision latch,no longer in the critical path,will restore the logic level at bn-i and maintain it robustly,even in the presence of coupling or of f-leakage.Figure 24.8.4 also illustrates the timing relationship between the compara

303、tor decision and DAC,f or both the conventional and the proposed approaches.Post-layout simulation shows that direct decision f eedback saves about 10ps per decision,quite significant compared to the 25ps time allocated.The chip is manuf actured in 16nm FinFET.Calibration,both f oreground and backgr

304、ound,is implemented on chip to correct f or sub-ADC bit weights,interleaving of f set,gain,and timing mismatches.Figure 24.8.5 shows overall ADC AC perf ormance vs input f requency,as well as an example output spectrum at 12GS/s with a 5.337GHz input.The 2nd-and 3rd-order harmonics limit SFDR and ar

305、e af f ected by the input network of the test board,varying over Fin.The SNDR perf ormance over Fin is very consistent,with small drop of f f rom 49.3dB at low Fin to 48.1dB at high Fin,mostly due to CLK jitter.AC perf ormance was also measured across many parts f rom-40C to 125C and-5%to 5%supplies

306、 to demonstrate robustness.SNDR varies less than 2dB across parts and V/T combinations.Typical DNL and INL are within+/-0.5LSB and+/-0.8LSB respectively.Out of the 160mW ADC power consumption,the input buf f er takes about 15mW and digital,including calibration,consumes roughly 40mW.Figure 24.8.6 sh

307、ows the perf ormance comparison with 10-24GS/s TI SAR ADCs published in ISSCC/VLSI in the past 10 years.This work has the highest Schreier FoM.The power number also includes on-chip clock supply regulator,1.8V ref erence buf f er,and 1.8V input buf f er.We achieve 12GS/s operation and close to 50dB

308、SNDR,while only using two standard process supply voltages f or ease of SoC integration.Compared to 4 and 6 with similar SNDR,our area is also significantly smaller even with a relatively larger process node.In addition,we report the f astest voltage-domain SAR ADC slice with medium/high resolution(

309、SNDR 45dB+)versus 17(18 reported higher speed with time domain quantizer).Figure 24.8.7 shows the die micrograph.The ADC measures 500m by 500m as a complete macro,including ESD cells,all decoupling capacitors,and digital reconstruction and calibration hardware.Acknowledgement:The authors would like

310、to thank the design verification team,layout team,evaluation team,CAD team,and program manager Phil Brown who helped ensure the success of this design work,and Siddharth Devarajan f or support and guidance.Figure 24.8.1:Top-level ADC archit ect ure including simplified sub-ADC diagram and cap-DAC il

311、lust rat ion.Figure 24.8.2:One reservoir capacit or per bit capacit or for fast set t ling during bit t rial and t he compact unit cell layout wit h minimal area overhead.Figure 24.8.3:Bit swit ching wit h ULVT devices bni/bpi for fast set t ling and boost ed Vg t o minimize leakage.Figure 24.8.4:Pr

312、oposed SAR loop direct decision feedback met hod versus convent ional decision lat ch t hen feedback approach,and t he associat ed decision delay t iming.Figure 24.8.5:ADC out put spect rum wit h 5.337GHz input at 12GS/s,and SNDR/SNR/SFDR performance versus Fin.Figure 24.8.6:Performance comparison w

313、it h 10-24GS/s SAR ADCs in t he past 10 years.ISSCC 2025/February 19,2025/11:20 AM443 DIGEST OF TECHNICAL PAPERS 24 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 24.8.7:Die micrograph.Refer ences:1 C.-

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315、h.Papers,pp.168-169,Jun.2022.3 Y.Tao,M.Gu,et al.,“A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Of f set Calibration,”ISSCC,pp.394-395,Feb.2024.4 J.Park,J.Park,et al.,“A 12-bit 10GS/s Time-Int

316、erleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET,”in IEEE Symp.VLSI Circuits Dig.Tech.Papers,pp.1-2,Jun.2024.5 J.P.Keane,N.J.Guilar,et al.,“An 8GS/s Time-Interleaved SAR ADC with Unresolved Decision Detection Achieving-58dBFS N

317、oise and 4GHz Bandwidth in 28nm CMOS,”ISSCC,pp.284-285,Feb.2017.6 S.S.Kumar,M.Kudo,et al.,“A 750mW 24GS/s 12b Time-Interleaved ADC f or Direct RF Sampling in Modern Wireless Systems,”ISSCC,pp.270-271,Feb.2023.7 R.Kapusta,J.Shen,et al.,“A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS,”IEEE J.So

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321、b Time-Interleaved Hybrid Two-Step ADC in 28nm CMOS,”in IEEE Symp.VLSI Circuits Dig.Tech.Papers,pp.1-2,Jun.2016.14 S.Le Tual,P.N.Singh,et al.,“A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology,”ISSCC,pp.382-383,Feb.2014.15 A.Shafik,E.Z.Tabasy,et al.,“A

322、10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm CMOS,”ISSCC,pp.62-63,Feb.2015.16 D.Cui,H.Zhang,et al.,“A 320mW 32Gb/s 8b ADC-Based PAM-4 Analog Front-End with Programmable Gain Control and Analog Peaking in 28nm CMOS,”ISSCC,pp.58-59,Feb.2016.17 B.Murmann,“ADC Perf ormance Survey 1997-2024,”Online.Available:https:/ H.Zhao,M.Zhang,et al.,“A 52.5-dB 2 Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC,”IEEE J.Solid-State Circuits,vol.58,no.12,pp.3586-3597,Dec.2023.