SESSION 18 Noise-Shaping and SAR-Based ADCs.pdf

1、ISSCC 2025SESSION 18Noise-Shaping and SAR-Based ADCs18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW1 of 53 2025 IEEE International Solid-State Circuits ConferenceA Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BWHan Zhao*,Xu

2、anhao Zhang*,Qijin Deng,Jialin Hu,Zhenbing Li,Shiheng Yang,Jiaxin LiuUniversity of Electronic Science and Technology of China,Chengdu,China18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW2 of 53 2025 IEEE International Solid-State Circuits ConferenceOutline B

3、ackground Proposed fully dynamic NS SAR ADC Circuit implementations Measurement results Conclusion18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW3 of 53 2025 IEEE International Solid-State Circuits ConferenceApplication Application:Portable instrumentation I

4、mplantable devices Smart sensors Goals:High dynamic range and linearity Low static power consumption18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW4 of 53 2025 IEEE International Solid-State Circuits Conference1.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+06

5、1.E+07102030405060708090100110120P/fsnyqpJSNDR fin,hfdBISSCC 1997-2024VLSI 1997-2024FOMW=1fJ/conv-stepFOMS=185dBMotivationSNDR120dBFoMs185dBRef:B.Murmann,ADC Performance Survey 1997-2024”18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW5 of 53 2025 IEEE Intern

6、ational Solid-State Circuits ConferenceChallenge High linearity Sampling Integrator Mismatch Low power consumption Integrator power consumption Reference power consumption18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW6 of 53 2025 IEEE International Solid-St

7、ate Circuits ConferencePrior ADC with 120dB SNDRINPUTShoubhik Karmakar,ISSCC 2018 Dynamic zoom ADC 5b coarse SAR+1b fine FS=2MHz 2nd-order loop filter OSR=1000 SNDR=118.1dB Power=280W18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW7 of 53 2025 IEEE Internatio

8、nal Solid-State Circuits ConferenceLimitations of Dynamic zoom ADC High DWA complexity Bit of DAC 5b 3X Over-ranging Shoubhik Karmakar,ISSCC 2018DIN+1 bit Power and area x2 B2TDecoderAdderRotationalShifterDOUTDINZ-118.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kH

9、z BW8 of 53 2025 IEEE International Solid-State Circuits ConferenceLimitations of Dynamic zoom ADC High DWA complexity Bit of DAC 5b 3X Over-ranging Effective quantization resolution 60dB Low area cost Simple structure0.5pF18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoM

10、s in 1kHz BW37 of 53 2025 IEEE International Solid-State Circuits ConferenceOutline Background Proposed fully dynamic NS SAR ADC Circuit implementations Measurement results Conclusion18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW38 of 53 2025 IEEE Internati

11、onal Solid-State Circuits ConferenceDie Photo 180 nm CMOS 0.15mm2active area18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW39 of 53 2025 IEEE International Solid-State Circuits ConferencePower BreakdownAnalog(FIA+Comp.)9.9W(7.1%)Logic32.4W(23.3%)Level Shifte

12、r+Bootstrap48.5W(34.9%)Reference48.3W(34.7%)Total Power:139.1 W18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW40 of 53 2025 IEEE International Solid-State Circuits ConferenceMeasured Spectrum 5V/1.8V supply 2.048 MHz FS 120.6 dB SNDR 132.5 dB SFDR 1 kHz band

13、widthFCHFIN18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW41 of 53 2025 IEEE International Solid-State Circuits Conference2-Tone Test Two-tone input 804 Hz and 864 Hz 120.2 dB IMD37008009001000FrequencyHz-160-140-120-100-80-60-40-200PSD dBFSIMD3=-127.1 dBc-6

14、.9 dBFS804HzIMD3=-127.2 dBc-7.0 dBFS864Hz18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW42 of 53 2025 IEEE International Solid-State Circuits ConferencePower Scalable/SNR vs.Sampling Rate103104105106Sampling Rate Hz0.11101001000Power W110115120125130SNR dBPo

15、werSNR Fs from 1kHz to 2MHz Power Liner Range:400 x 18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW43 of 53 2025 IEEE International Solid-State Circuits ConferenceSFDR/SNDR vs.Input Amplitude-120-100-80-60-40-200Input Amplitude dBFS020406080100120140SNDR/SFD

16、R dBDR=123.5dBSNDRSFDR-3-2-10119120121 Measured DR:123.5 dB18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW44 of 53 2025 IEEE International Solid-State Circuits ConferencePSRR vs.Input Frequency Analog supply:1.8V+100mVppPSRR 95 dB up to 6 kHz1011021031041051

17、06Frequency Hz2030405060708090100PSRR dB18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW45 of 53 2025 IEEE International Solid-State Circuits ConferenceSFDR/SNDR with different chips120.3120.1120.6120.3120.4120.2120.1132.5133132.5134.5131.8133.5130.9115120125

18、1301351401234567SNDRSFDR dBNo.of ChipSNDRSFDR 7 samplesWithin 0.5 dB variation18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW46 of 53 2025 IEEE International Solid-State Circuits ConferenceSNDR/SFDR with AVDD variation120.1120.5120.6120.6120.2133.2134.3132.5

19、132134.41151201251301351401.61.71.81.92SNDRSFDR dBAVDD VSNDRSNFR Analog supply:1.6V 2VWithin 0.5 dB variation18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW47 of 53 2025 IEEE International Solid-State Circuits ConferencePerformance ComparisonParameterThis wo

20、rkISSCC-24Subramanian 22ISSCC-22Jie 23ISSCC-22Lee 24ISSCC-18Karmakar4ISSCC-16Steiner 1ISSCC-16Shu 8ISSCC-13Chae 2ArchitectureNS-SARCT-DSMZoom-Incremental-CountingDT-DSMDynamic Zoom(SAR+)Delta-SigmaNS-SARZoom(SAR+)Fully Dynamic?YNNNNNNNProcess nm1801302818016035055160FSMHz2.0483.0725005.820.6410.05BW

21、 kHz12010201110.012518.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW48 of 53 2025 IEEE International Solid-State Circuits ConferencePerformance ComparisonSupply V1.8/51.8/3.30.9/1.21.1/1.81.85.41.21.8Area mm20.150.480.0140.03750.2511.480.0720.375Power W139.13

22、180470203.52801270015.76.3SNDRMAXdB120.6107.7102.9105.4118.1116101.0119.8SFDR dB132.5-113.9-105.1-DR dB123.5115.1104.5108.8120.3136.3-FoMs1 dB189.2175.7176.2185.3183.6165.0178.9182.7FoMs2 dB192.1183.1177.8188.7185.8185.3-ParameterThis workISSCC-24Subramanian 22ISSCC-22Jie 23ISSCC-22Lee 24ISSCC-18Kar

23、makar4ISSCC-16Steiner 1ISSCC-16Shu 8ISSCC-13Chae 218.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW49 of 53 2025 IEEE International Solid-State Circuits ConferenceBenchmark:Energy Efficiency1.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+071020304050607080

24、90100110120P/fsnyqpJSNDR fin,hfdBISSCC 1997-2024VLSI 1997-2024FOMW=1fJ/conv-stepFOMS=185dBThis WorkThis Work18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW50 of 53 2025 IEEE International Solid-State Circuits Conference1201301401501601701801901.E+021.E+041.E

25、+061.E+081.E+10FOMS,hfdBfsnyqHzISSCC 1997-2024VLSI 1997-2024EnvelopeThis WorkBenchmark:Schreier FOM vs.SpeedThis Work18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW51 of 53 2025 IEEE International Solid-State Circuits ConferenceOutline Background Proposed fu

26、lly dynamic NS SAR ADC Circuit implementations Measurement results Conclusion18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW52 of 53 2025 IEEE International Solid-State Circuits ConferenceConclusion Proposed ADC 8-bit 1st-order NS-SAR Hybrid mismatch shaping

27、:DWA+MES 3-level switching+PAS System-level chopping First ADC achieves 120dB SNDR with 1kHz BW Best Schreier FoM among published ADCs18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW53 of 53 2025 IEEE International Solid-State Circuits ConferenceThanks for yo

28、ur Attention!18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference1 of 54A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped SamplerYaohui Luan,Xinhang Xu,Jihang Gao,Jiajia Cui,

29、Zhuoyi Chen,Siyuan Ye,Ru Huang,Linxiao ShenPeking University,Beijing,China,Email:,18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference2 of 54Outline Motivation Proposed Gain-Embedded Bootstrapped Sampler

30、System Implementation Measurement Results Conclusion18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference3 of 54Outline Motivation Proposed Gain-Embedded Bootstrapped Sampler System Implementation Measurem

31、ent Results Conclusion18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference4 of 54ADCs for Internet of Things(IoT)High Accuracy SNDR 90dB Low Power Consumption Battery Powered Devices Required Power 110dB1

32、8.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference34 of 54Small-Signal ModelGain-Embedded Bootstrapped SamplerSampler inside loop:Gain variation slightly changes NTF Calibration-free under PVT18.2 A 12.2

33、uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference35 of 54Small-Signal ModelSampler inside loop:Gain variation slightly changes NTF Calibration-free under PVT SQNR 1dB Gain-Embedded Bootstrapped Sampler18.2 A 12.2

34、uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference36 of 54Mismatch Error in DAC Mismatchnon-criticalMismatch-critical18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 202

35、5 IEEE International Solid-State Circuits Conference37 of 54Mismatch Error in DAC Mismatchnon-criticalMismatch-critical Coarse quantizer bits N:Higher :DEM power intense Lower:Sampler processing larger signal DEM appliedN=8 is chosen18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embe

36、dded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference38 of 54Segmented DEM Technique Direct DWANeed to handle 256 unit elementsUnacceptable power!18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-Sta

37、te Circuits Conference39 of 54Segmented DEM Technique Segmented DEM N.Sun TCASI 2012Split 8 bits into 5bits MSB+3 bits LSBNegligible MSA loss18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference40 of 54Seg

38、mented DEM Technique Segmented DEM DWA applied for MSB and LSB DACSegment mismatch error remainsMismatch between MSB and LSB DACs remains18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference41 of 54Segment

39、ed DEM Technique Segmented DEM High-pass shaped LSB code shapes segment mismatch error18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference42 of 54Segmented DEM Technique Segmented DEM High-pass shaped LSB

40、 code shapes segment mismatch error18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference43 of 54Coarse Segmented Digital Slope ADCL.Jie,ISSCC 2022Z.Wang,ISSCC 202318.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT

41、Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference44 of 54Coarse Segmented Digital Slope ADC 1storder prediction adopted Maximum 3 comparisons per conversion 18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped S

42、ampler 2025 IEEE International Solid-State Circuits Conference45 of 54Overall Architecture18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference46 of 54Outline Motivation Proposed Gain-Embedded Bootstrapped

43、 Sampler System Implementation Measurement Results Conclusion18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference47 of 54Chip Micrograph 55nm CMOS Core Area:0.029 mm2 1.2V Reference with 1V Supply Voltage

44、18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference48 of 54Measured Result Fs=1MHz,OSR=12518.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE Internatio

45、nal Solid-State Circuits Conference49 of 54Measured Result SNDR 1dB among 5 chips18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference50 of 54Measured Result SNDR 3dB over temperature variation18.2 A 12.2u

46、W 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference51 of 54Power Breakdown18.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Con

47、ference52 of 54Comparison with State-of-the-ArtThis WorkChandrakumarISSCC 18LeeISSCC 22ElandVLSI 20JieISSCC 22LoISSCC 21LiVLSI 24Processnm5540180160282865Supply VoltageV1/1.21.21.8/1.11.80.9/1.21.8/1.01Input SwingVp1.111.41.71.11.73.3Areamm20.0290.0530.03750.270.0140.070.28Driving FriendlyNoise pena

48、lty free*C_samppF1/7.313.6N.A/fsMhz10.45.83.5409.66.1447.2BandwidthkHz45202025 2424PoweruW12.24.5203.544059011680.7Peak SNDRdB99.693.5105.4106.5100.1100.699.2Dynamic RangedB10296.5108.8109.8102.2104.4100FOMsdB184185.3183.1176.4183.7184(CDAC switching kickback)(DT Sampling)(DT Sampling)(CDAC switchin

49、g kickback)184.818.2 A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference53 of 54Outline Motivation Proposed Gain-Embedded Bootstrapped Sampler System Implementation Measurement Results Conclusion18.2 A 12.2uW

50、 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler 2025 IEEE International Solid-State Circuits Conference54 of 54Conclusion Gain-Embedded Bootstrapped Sampler Provide linear,high-efficiency sampling with gain Driving-friendly High-efficiency pseudo-pseudo-differential z

51、oom ADC Segmented DEM+segmented Digital-Slope coarse ADC Results Achieves 99.6dB SNDR,12.2W 4kHz Bandwidth FoMs:184.8dBThanks for your attention!18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Ass

52、isted Residue Integrator 2025 IEEE International Solid-State Circuits Conference1 of 52A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue IntegratorJihang Gao,Yaohui Luan,Siyuan Ye,Xinhan

53、g Xu,Zhuoyi Chen,Jiajia Cui,Ru Huang,Linxiao ShenPeking University,Beijing,ChinaContact:,JihangG18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International

54、Solid-State Circuits Conference2 of 52 Motivation Proposed Calibration-Free ADCCross-Stage Gain-Mismatch Error Shaping(CS-GMES)Inherent Noise-shaping&Negative-R-Assisted Residue Integrator Circuit Implementation and operation Measurement Results ConclusionOutline18.3:A 93.3 dB SNDR,180.4dB FoMs Cali

55、bration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference3 of 52 Motivation Proposed Calibration-Free ADCCross-Stage Gain-Mismatch Error Shaping(CS-GMES)Inhere

56、nt Noise-shaping&Negative-R-Assisted Residue Integrator Circuit Implementation and operation Measurement Results ConclusionOutline18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue I

57、ntegrator 2025 IEEE International Solid-State Circuits Conference4 of 52 Power Efficient Architecture Combine SAR&PipelinePipelined-SAR ADC Challenges1.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07102030405060708090100110120SNDR fin,hfdBFOMW=1fJ/conv-stepFOMS=185dBOther typePipelined-SARB.Mur

58、mann,ADC Performance Survey 1997-2024,Online.Available:https:/ 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference5 of 52 C

59、DAC:Mismatch Error Residue Amplifier:Gain Error Pipelined-SAR ADC ChallengesDAC Mismatch ErrorInter-stageGain Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025

60、IEEE International Solid-State Circuits Conference6 of 52 Dynamic Weight Averaging(DWA)Isolate from normal operation Special selecting pattern Better shaping performance Bit-related cost Limited to 5 bits Previous Mismatch Error Solutions18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shapin

61、g Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference7 of 52 Mismatch Error Shaping(MES)Bit-number-unrelated cost Suitable for extension Switching change only No extra hardware cos

62、t Limited to single stage scenarioPrevious Mismatch Error SolutionsY.-S.Shu,ISSCC2016 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-Stat

63、e Circuits Conference8 of 52 Dither-based Real-time Calibration Continuously tracking gain change PVT Improvement Highly-digital implementation Tech-friendly Large hardware cost&Long Convergence timePrevious Gain Error Solutions18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipeline

64、d-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference9 of 52 Reduce Q1by 2ndstage result Auxiliary DAC for gain emulation Require truncation error shapingPrevious Gain Error Solutions Analog

65、 Gain Error Shaping(GES)Reduce Q1by sub-ADC Sub-ADC&DAC required Require quant.-error shapingC.-K.Hsu,JSSC2021 H.Zhang,ISSCC2023 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue In

66、tegrator 2025 IEEE International Solid-State Circuits Conference10 of 52 Motivation Proposed Calibration-Free ADCCross-Stage Gain-Mismatch Error Shaping(CS-GMES)Inherent Noise-shaping&Negative-R-Assisted Residue Integrator Circuit Implementation and operation Measurement Results ConclusionOutline18.

67、3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference11 of 52Gain-Mismatch Error Unification A typical Pipelined-SARTwo e

68、rror contributors:Mismatch&Gain Error=+Gain ErrorMismatch Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference12

69、 of 52Gain-Mismatch Error Unification A typical Pipelined-SAR with MESFeasible for the 1st-stageShaping 1st-stage LSBs mismatch errors(refer to MSB)18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-

70、Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference13 of 52Gain-Mismatch Error Unification A typical Pipelined-SAR with MESShaped 2nd-stage LSB mismatch(refers to 2nd-stage MSB)Remaining gain error issue Quantization noise leakage18.3:A 93.3 dB SNDR,180.4dB FoMs Calib

71、ration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference14 of 52Gain-Mismatch Error Unification A typical Pipelined-SAR with MESShape each stages Mismatch Rema

72、ining Gain Error=+()Remaining Gain ErrorShaped Mismatch ErrorShaped Mismatch ErrorCan we shape Gain Error with the 2nd-stage together?18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Resid

73、ue Integrator 2025 IEEE International Solid-State Circuits Conference15 of 52Gain-Mismatch Error Unification Slight transformationMerge gain with the 2nd-stage weight=+18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Techn

74、ique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference16 of 52Gain-Mismatch Error Unification Slight transformationTake as a whole:the unified weight=+Unified Gain&Mismatch Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined

75、-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference17 of 52Gain-Mismatch Error Unification Gain error Mismatch in the 2ndstageThe unified error also exists in the 2nd-stage MSBAll bits in t

76、he 2nd-stage must be involved in MES procedureCross-stage Gain-Mismatch Error Shaping(CS-GMES)Contain Gain&Mismatch Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator

77、 2025 IEEE International Solid-State Circuits Conference18 of 52CS-GMES Implementation The All-bits-involved 2nd-stage MESMES causes add-back voltage at the reset phaseAccumulated on the top-plate Saturation possibility 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR AD

78、C with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference19 of 52CS-GMES Implementation The All-bits-involved 2nd-stage MESMES only shapes relative error,not absolute errorMissing mismatch reference 18.

79、3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference20 of 52CS-GMES Implementation The All-bits-involved 2nd-stage MESAd

80、d feedback capacitor CFBas mismatch referenceSwitch according to 2nd-stage MSB:Convey mismatch info18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE Internation

81、al Solid-State Circuits Conference21 of 52CS-GMES Implementation The All-bits-involved 2nd-stage MESCFBswitched from VCM to DMSB2MSB2switched from DMSB2 to VCMCounterpart each other18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error

82、Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference22 of 52CS-GMES Implementation Connect CFB with the 1ststage CDACCFBalso contributes mismatch Missing connection between mismatch references 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibratio

83、n-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference23 of 52CS-GMES Implementation Connect CFB with the 1ststage CDACAdd CFBinto MES procedure:reset after sampl

84、ingShape CFBs own mismatch Convey all mismatch info to 1ststage MSB 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Confere

85、nce24 of 52Input Prediction for MES Signal range loss caused by MES Adding back voltage occupying input range Prediction and compensation required for DRY.Shen,JSSC2022 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Tech

86、nique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference25 of 52Input Prediction for MES Pre-comparison for signal polarityCompare and switch at the beginningPreventing kickback and settling issue 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise

87、-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference26 of 52 Motivation Proposed Calibration-Free ADCCross-Stage Gain-Mismatch Error Shaping(CS-GMES)Inherent Noise-shaping&

88、Negative-R-Assisted Residue Integrator Circuit Implementation and operation Measurement Results ConclusionOutline18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IE

89、EE International Solid-State Circuits Conference27 of 52Review of Noise-Shaping Previous noise-shaping requires extra costMain bottleneck Residue preservationCapacitor stacking Residue sampling buffer/Complex logicPassive charge sharing Multi-input comparator/Active Gain18.3:A 93.3 dB SNDR,180.4dB F

90、oMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference28 of 52Integrator-based Inherent Noise-shaping Focus on the 2nd-stage CDACFor MES procedure,t

91、he reset phase is moved after samplingNaturally preserved residue signal on the top plate18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-S

92、tate Circuits Conference29 of 52 Residue AmplificationSettling curve ruins the preserved residue Integrator-based Inherent Noise-shaping1520556065707580-0.6-0.4-0.20.00.20.4VTOP_S2 VTIME nsVres2(n-1)AmplificationConv.IDLEIDLEResidue AmplificationConv.18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free

93、 Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference30 of 52 Residue IntegrationReplace amplifier by integrator Preserved residue Summation of Input&Last-cycle residu

94、e Error-feedback NSIntegrator-based Inherent Noise-shaping1520556065707580-0.6-0.4-0.20.00.20.4VTOP_S2 VTIME nsVres2(n-1)=GVres1(n)IntegrationConv.IDLEIDLEResidue IntegrationConv.18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Sh

95、aping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference31 of 52Inter-stage Residue Integrator The Rout effect on Gm-C behavior18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Er

96、ror Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference32 of 52Inter-stage Residue Integrator Use negative-R to realize infinite RoutSplit current source degeneration Linearity&Volt.headroomPTAT current source Gain tracking under PVTB.

97、Nauta,JSSC1992 18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference33 of 52Inter-stage Residue Integrator Use negativ

98、e-R to realize infinite RoutRdmainly determines the negative-R valueLarge tolerant range for enough SQDR(-25%+75%)-25%0%25%50%75%707580859095100105110115120Simulated SQDR dBRelative Rd-3dBDesign PointRd 220k Available Range18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR

99、 ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference34 of 52Inter-stage Residue Integrator Risk of integration saturationIntegrator accumulating offset Saturation Chopping for the 1st-stage comp

100、arator&residue integrator4550556065707580859095 1000100200300400500 CountSimulated SQDR dB w chopping w/o chopping Monte Carlo Simulation1=20mV-20020406080 100 120 140 160 180 200 220-0.50.00.51.01.52.0VTOP_S2 Conv.VCycle w chopping w/o choppingSaturation LimitVos=10mV18.3:A 93.3 dB SNDR,180.4dB FoM

101、s Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference35 of 52Overall Architecture Pipelined-SAR structure1st-stage CDAC:1.5pF,7bit|2nd-stage CDAC:300

102、fF,7bitResidue Integrator:x16 Gain18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference36 of 52Detailed Operation Proc

103、ess(1)Prediction at the beginning Preserved LSB&CFBcode CMFB,Integrator&Comparator Chopping18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid

104、-State Circuits Conference37 of 52Detailed Operation Process(2)Bottom plates reset to VCM mismatch of cycle N-1Current Involved Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residu

105、e Integrator 2025 IEEE International Solid-State Circuits Conference38 of 52Detailed Operation Process(3)Subtracting current cycle LSB mismatch First-order shaping of mismatch errorsCurrent Involved Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Sta

106、ge Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference39 of 52Detailed Operation Process(4)Subtracting current cycle CFBmismatch Partially cancel the add-back voltage of the 2nd-stage(switched as DMSB2(n-1)Current I

107、nvolved Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference40 of 52Detailed Operation Process(5)Preserving resi

108、due voltage Vres2(n-1)Inherent noise shaping Preserved bottom-plate codesCurrent Involved Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International S

109、olid-State Circuits Conference41 of 52Detailed Operation Process(6)Bottom plates reset to VCM mismatch of cycle N-1 Add-back voltage partially canceled by CFBCurrent Involved Error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error S

110、haping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference42 of 52Detailed Operation Process(7)Subtracting current cycle unified mismatch(Gain&Mismatch)Once MSB converted Latched and passed to CFBCurrent Involved Error18.3:A 93.3 dB SNDR,180.4

111、dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference43 of 52Detailed Operation Process Signal flow in analog/digital domain18.3:A 93.3 dB SNDR

112、,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference44 of 52Detailed Operation Process Signal flow in analog/digital domainGMES Digital-

113、domain Signal ReconstructionShaped Error=+18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference45 of 52Measurement Res

114、ults Fabricated in 55nm CMOSOperating frequency 20MHzOversampling ratio x64Area occupation:0.0416 mm218.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE Internati

115、onal Solid-State Circuits Conference46 of 52Measurement Results Measured SNDR=93.3dB,SFDR=112.8dB18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International

116、 Solid-State Circuits Conference47 of 52Measurement Results Gain error emulationManually change the 2nd-stage reference voltageLarge tolerance range from-33%+50%gain error18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Te

117、chnique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference48 of 52Measurement Results Power Dissipation:306.88uW 20MHz,1.2Vdd Dynamic Range:95.02dB18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-M

118、ismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference49 of 52Measurement Results PVT TestNo calibration applied18.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch

119、 Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference50 of 52Comparison with State-of-the-ArtYoshioka ISSCC17Hsu JSSC20Hsu JSSC21Zhang ISSCC21Zhang ISSCC23This WorkArchitecturePipelined-SARNS Pipelined-SARNS Pipelined-SARGain-Erro

120、r SuppressionDigital AMP2nd-Order GES2nd-Order DEF-GES2-0 MASH2nd-Order QPU-GESCS GMESMismatch-Error SuppressionForeground Calibration4b DWA4b DWA&DASCS GMESCalibration-FreeNOYESYESTechnology nm284040282855Supply V0.711111.2Fs MS/s16010010040040020Power mW1.91.541.381.262.030.307Area mm20.0970.0610.

121、0540.0270.050.028OSR1488864-3dB SNDR Gain%N/A-5 to N.A.-25 to N.A.-16+12-24+18-33+50BW MHz8012.56.2525250.15625SNDR dB61.175.877.17577.293.3SNDR FoMs dB167.3174.9173.7178178.1180.418.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error S

122、haping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State Circuits Conference51 of 52Comparison with State-of-the-ArtShu ISSCC16Liu ISSCC20Shen JSSC22Hasebe VLSI22Li JSSC22This WorkArchitectureNS SAROS SARNS SARNS Pipelined-SARNo.of Stages12Mismatch-Error Suppre

123、ssionDWA+MES2nd-Order MES1st-Order MESDWA+MES1st-Order MESCS GMESCalibration-FreeYESYESTechnology nm554065406555Supply V1.21.10.81.11.21.2Fs MS/s120.12812.8120Power mW0.01570.06740.000981.9980.00730.307Area mm20.0720.0610.033/0.0430.028OSR1252516641664BW kHz440410031.25156.25SNDR dB96.190.584.598.38

124、093.3SNDR FoMs dB180178.2180.6175.3176.3180.4DR FoMs dB179.6182181.1178.2177.7182.118.3:A 93.3 dB SNDR,180.4dB FoMs Calibration-Free Noise-shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator 2025 IEEE International Solid-State C

125、ircuits Conference52 of 52Summary A 15-bit ENOB Calibration-free Pipelined-SAR ADCUnify Gain and Mismatch errorsExtending MES to multi-stage scenariosOne-bit feedback,auxiliary-free GESInherently preserved residue voltage for noise shapingNegative-R assisted high performance open-loop integrator Per

126、formance summary93.3dB SNDR,112.8dB SFDR,180.4dB FoMsHighest bandwidth over MES worksLargest gain error tolerance range,Highest FoMs and SNDR 2025 IEEE International Solid-State Circuits Conference1 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Bas

127、ed kT/C Noise Cancellation TechniqueA 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueZongnan Wang,Bingrui Li,Jiajun Tang,Zhongyi Wu,Haoyang Luo,Yuan Wang,Xiyuan TangPeking University,Beijing,China 2025 IEEE International S

128、olid-State Circuits Conference2 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueOutline Motivation Proposed Incremental NS Pipeline ADC Single-amplification-based kT/C noise cancellation Parallel coarse and fine

129、 conversions Circuit Implementation Measurement Results Conclusion 2025 IEEE International Solid-State Circuits Conference3 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueMotivation Many IoT applications demand

130、 ADCs with High resolution High energy efficiency Medium conversion speed 2025 IEEE International Solid-State Circuits Conference4 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueZoom ADC Combine efficient coars

131、e and precise quantizers Zoomed quantization High resolution and energy efficiency 2025 IEEE International Solid-State Circuits Conference5 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueNS-SAR Embedded Zoom AD

132、C NS-SAR fine quantizer Low conversion cycles and samplings Medium conversion speed Z.Wang,ISSCC23 2025 IEEE International Solid-State Circuits Conference6 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquePrior N

133、S ADC Large sampling kT/C noise with low OSR Large CDAC for high sampling resolution High driving cost Z.Wang,ISSCC23 2025 IEEE International Solid-State Circuits Conference7 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellati

134、on TechniquePrior NS ADC kT/C noise cancellation technique Small CDAC with high sampling resolutionZ.Wang,ISSCC23 2025 IEEE International Solid-State Circuits Conference8 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation T

135、echniquekT/C Noise Cancel.in NS ADC Sample phase Freeze the sampling noise on 2025 IEEE International Solid-State Circuits Conference9 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquekT/C Noise Cancel.in NS ADC

136、kT/C noise extraction phase Extract and store the sampling noise on 2025 IEEE International Solid-State Circuits Conference10 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquekT/C Noise Cancel.in NS ADC Conversio

137、n phase Amplify and convert with kT/C noise cancelled 2025 IEEE International Solid-State Circuits Conference11 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquekT/C Noise Cancel.in NS ADC Conversion phase N ampl

138、ifications for N comparisons 2025 IEEE International Solid-State Circuits Conference12 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquekT/C Noise Cancel.in NS ADC Loop filtering phase Amplify and loop filtering

139、with kT/C noise cancelled 2025 IEEE International Solid-State Circuits Conference13 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquekT/C Noise Cancel.in NS ADC(N+1)amplifications for 1-cycle N-bit conv.2025 IEEE

140、 International Solid-State Circuits Conference14 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquekT/C Noise Cancel.in NS ADC M x(N+1)amplifications for M-cycle N-bit conv.2025 IEEE International Solid-State Circ

141、uits Conference15 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquePrior NS ADC Challenge 1:Static amp.or repeatedly triggered dynamic amp.High kT/C noise cancellation-induced amplification cost Z.Wang,ISSCC23 20

142、25 IEEE International Solid-State Circuits Conference16 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniquePrior NS ADC Challenge 2:occupied in both the sampling and conv.phases Serial coarse and fine conversions Z

143、.Wang,ISSCC23 2025 IEEE International Solid-State Circuits Conference17 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueProposed Incremental NS Pipeline ADC Solution 1:Single-amplification-based kT/C noise cance

144、llation Multiple NS-SAR conversions after 1 residue amplification 2025 IEEE International Solid-State Circuits Conference18 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueProposed Incremental NS Pipeline ADC So

145、lution 2:Pipelined kT/C noise cancellation Parallel coarse and fine conversions 2025 IEEE International Solid-State Circuits Conference19 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueProposed kT/C Noise Cance

146、l.in NS ADC Residue amplification phase Amplify and store the sampling noise on 2025 IEEE International Solid-State Circuits Conference20 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueProposed kT/C Noise Cance

147、l.in NS ADC 2nd-stage conversion and loop filtering phases No amplification 2025 IEEE International Solid-State Circuits Conference21 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueProposed kT/C Noise Cancel.in

148、 NS ADC 1 amplification for 1-cycle N-bit conv.2025 IEEE International Solid-State Circuits Conference22 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueSkipped Residue Amplification Loop filter dynamic buffer+c

149、apacitor stacking Charges stored on and are preserved 2025 IEEE International Solid-State Circuits Conference23 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueSkipped Residue Amplification Reset phase Regenerat

150、e the backend input by resetting 2nd-stage 2025 IEEE International Solid-State Circuits Conference24 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueSkipped Residue Amplification 2nd-stage conversion and loop fi

151、ltering phases M consecutive 2nd-stage conversions 2025 IEEE International Solid-State Circuits Conference25 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueSingle-Amp.-Based kT/C Noise Cancel.1 amplification fo

152、r M-cycle N-bit conv.Low kT/C noise cancellation-induced amplification cost 2025 IEEE International Solid-State Circuits Conference26 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueParallel Coarse and Fine Conv

153、.Ping-pong for pipelined operation Parallel coarse and fine conversions Improved conversion speed 2025 IEEE International Solid-State Circuits Conference27 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueParalle

154、l Coarse and Fine Conv.In the even cycle Extract 1st-stage kT/C noise on kT/C noise stored Connect 2nd-stage and kT/C noise cancelled 2025 IEEE International Solid-State Circuits Conference28 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C

155、 Noise Cancellation Technique In the odd cycle Extract 1st-stage kT/C noise on kT/C noise stored Connect 2nd-stage and kT/C noise cancelledParallel Coarse and Fine Conv.2025 IEEE International Solid-State Circuits Conference29 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC w

156、ith Single-Amplification-Based kT/C Noise Cancellation TechniqueOutline Motivation Proposed Incremental NS Pipeline ADC Single-amplification-based kT/C noise cancellation Parallel coarse and fine conversions Circuit Implementation Measurement Results Conclusion 2025 IEEE International Solid-State Ci

157、rcuits Conference30 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueCircuit Implementation Simplified schematic 8b 1st-stage SAR 7b 2nd-stage variable-order NS-SAR Floating inverter amplifier 2025 IEEE Internati

158、onal Solid-State Circuits Conference31 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique1st-stage SAR Operation Sampling phase Total/capacitance=0.8pF kT/C noise extracted on/2025 IEEE International Solid-State C

159、ircuits Conference32 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique1st-stage SAR Operation 1st-step conv.phase 6b SAR conversion(async)Performed directly on the top of 2025 IEEE International Solid-State Circu

160、its Conference33 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique1st-stage SAR Operation 2nd-step conv.phase 2b SAR conversion(async)1b redundancy Performed with the FIA as pre-amplifier 2025 IEEE International

161、Solid-State Circuits Conference34 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique1st-stage SAR Operation 2nd-step conv.phase 110dB SFDR 5200kHz Two-tone testFin1=32kHz -6.5dBFSFin2=37kHz -6.5dBFSIM3=-104.3dB 20

162、25 IEEE International Solid-State Circuits Conference47 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueHigh-Freq.Input&Decimation Filter STF High-frequency input8x averagingFin=500kHzSFDR=100.9dBSNDR=90.6dB Dec

163、imation filter STF-0.2dB 200kHz-1.25dB 500kHz 2025 IEEE International Solid-State Circuits Conference48 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueMeasured DR&Power Breakdown Performance vs.input amp.SNDR,S

164、NRDR=93.1dB Power breakdownSupply=0.9VConversion rate=1.6MS/sTotal power=467.3uW 2025 IEEE International Solid-State Circuits Conference49 of 5118.4:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation TechniqueSNDR vs.Temperature/Volt

165、age SNDR vs.temperature5 chips-20 80 SNDR 1.5 dB SNDR vs.analog supply5 chips0.8 1 VSNDR 90dB)can be achieved sampling endOnly mild oversampling ratio(8)is neededCLS1CLS2VIPVINCCCCCF+-+-+-+-+-VCMCONVCLS1CLS1CLS2CLS2Pseudo RDC servo loopCLS1CLS2CF+-VCMCONVCLS1CLS2Pseudo RDC servo loopCLS1CLS2VANVAPVO

166、NVOPA1A2A318.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference26 of 58OutlineMotivationProposed Rail-to-Rail Input BufferProposed 3rdorder NS-SAR

167、 ADC ImplementationSystem and Circuit ImplementationMeasurement ResultsConclusion18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference27 of 58ADC

168、ImplementationNoise-Shaping(NS)SAR ADCLess comparator noise higher resolutionSimple comparator and NS filter low costSwitchesSAR LogicCDAC+-NS Loop FilterVINDO18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Leve

169、l Shifting 2025 IEEE International Solid-State Circuits Conference28 of 58ADC ImplementationNoise-Shaping(NS)SAR ADCkT/C sampling noise:a major part under mild OSR Large CSto suppress kT/C noiseSwitchesSAR LogicCDAC+-NS Loop FilterVINDOEkTC18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achievin

170、g 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference29 of 58ADC ImplementationkT/C noise cancellation in SARSeries output cancellation at comparators preampStandard SAR ADC approachJ.Liu,ISSCC 20CNCS2S2VIN

171、ACONVS1DOUTDDACS1S2CONV18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference30 of 58ADC ImplementationSeries kT/C cancellation in NS-SARNoise repl

172、ica will be shaped by H(z)Cannot directly apply to NS-SART.-H.Wang,ISSCC 2118.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference31 of 58ADC Implem

173、entationPrior art:move kT/C cancellation before comparator Hardware reuse Need amp gain matching with cap ratio for fully cancellationT.-H.Wang,ISSCC 21S2VinACONVS1DoutDDACCSCEFCNCS1S2EFS2CIFFCINTHEF(z)Vin(z)HCIFF(z)EkTC(z)Dout(z)Q(z)-z-1Vres(z)EkTC(z)-18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR

174、 ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference32 of 58ADC ImplementationInject at the quantization path kT/C noise unshaped/=+In band HEF(z)Vin(z)HCIFF(z)EkTC(z)Dout(z)Q(z)-EkTC(z)-z-1Vr

175、es(z)QuantizationResidueExtraction18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference33 of 58ADC ImplementationInject at the residue extraction

176、path kT/C noise shaping/=+In band HEF(z)Vin(z)HCIFF(z)EkTC(z)Dout(z)Q(z)-z-1Vres(z)EkTC(z)-QuantizationResidueExtraction18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Soli

177、d-State Circuits Conference34 of 58ADC ImplementationInject at both paths kT/C noise cancellation/=HEF(z)Vin(z)HCIFF(z)EkTC(z)Dout(z)Q(z)-z-1Vres(z)EkTC(z)-QuantizationResidueExtraction18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Conti

178、nuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference35 of 58ADC ImplementationImplementation-Preamp Reusing Hardware friendly Fully kT/C noise cancellation under PVTS1VREFPVCMVREFNPre-ampSARLogic+-CDAC array+-S1VREFPVCMVREFNCDAC arrayCOMPDOUTVIPVINS2CNCCNCkT/C

179、 CancellationPreamp ReusingLoopFilter+-Quantization PathResidue Extraction Path18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference36 of 58ADC Im

180、plementationImplementation-Preamp ReusingNoise of the loop filter suppressed by the preamp Reduced cap size compact loop filterVREFPVCMVREFNPre-ampSARLogic+-CDAC array+-VREFPVCMVREFNCDAC arrayCOMPDOUTVIPVINCNCCNCLoopFilter+-Reduced cap sizeS1S1S218.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Ac

181、hieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference37 of 58ADC Implementation3rdorder loop filter implementationHybrid EF-CIFF structure-1storder EF+2ndorder CIFF Single FIA&switch cap power efficie

182、nt solutionCEFPCINT1PCEX1PCEX1NCEX2PCEX2NFIACINT2P+-NSNSS2EXVCMVCMCEFNCINT1NCINT2NNSNSS2VCMCOMP1st-order EF Path+-+-2nd-order CIFF Path4x1x1x4xVCMS2S2EXFromPreampOutputToSARLogicMulti-inputComparator18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buff

183、er Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference38 of 58ADC Implementation2ndorder CIFF path implementationMultiple input comparator simple and dynamicNoise suppressed by the preamp1x4xVI1+VI1-VI2+VI2-COMPLatchDo+Do-CEFPCINT1PCEX1PCEX1NCEX2PC

184、EX2NFIACINT2P+-NSNSS2EXCEFNCINT1NCINT2NNSNSS2COMP1st-order EF Path+-+-2nd-order CIFF Path4x1x1x4xS2S2EXFromPreampOutputToSARLogicMulti-inputComparator18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shiftin

185、g 2025 IEEE International Solid-State Circuits Conference39 of 58OutlineMotivationProposed Rail-to-Rail Input BufferProposed 3rdorder NS-SAR ADC ImplementationSystem and Circuit ImplementationMeasurement ResultsConclusion18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with

186、 Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference40 of 58System ConsiderationBuffer driving a normal ADCThe driver NSD is limited by the driver bandwidth BWDRVThe BWDRVis determined by the settling requirement Large CS&la

187、rge BWDRV Large driver power=(/+)DriverCSBWDRVNSDADCDriverBWDRVBWADC18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference41 of 58Buffer driving a

188、kT/C canceled ADCSampling phase from the driver noise view Smaller CS reduced driver powerDriver noise PSD is limited by BWDRVDriverCNCCSPreampS2S2S1S2S1SamplingAS2S1S3NSDADCDriverBWDRVBWADCBWDRV VnDRV18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Bu

189、ffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference42 of 58Buffer driving a kT/C canceled ADCkT/C extraction phase from the driver noise viewDriver noise PSD is band-limited by the preamp bandwidth BWPRELower limit of BWPRE?DriverCNCCSPreampS2

190、S2S1S2S1AS2S1S3NSDADCDriverBWDRVBWADCVnDRVTkTCequivalent sampling edgeWide BWBWPRE=1/BWPRE18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference43

191、of 58Buffer driving a kT/C canceled ADCFactors determine the minimum BWPRE kT/C noise settleSampling noise amplified and settled on CNCLeft uncanceled kT/CSsampling noise:,2=2/Max max min BWPREDriverCNCCSPreampS2S2S1S2S1S3AVnSVnNCS1S2TkTCequivalent sampling edge18.5 A Rail-to-Rail 3rd-Order Noise-Sh

192、aping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference44 of 58Buffer driving a kT/C canceled ADCFactors determine the minimum BWPRE input changePreamp max output:=2 Max avoid preamp sat

193、uration Suitable for the oversampling ADC situationDriverCNCCSPreampVINVOUTS2S2S1S2S1S3AS1S2TkTCequivalent sampling edge18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Soli

194、d-State Circuits Conference45 of 58System OverviewCC=1pF CF=1pF/0.5pF CLS1=3.2pF CLS2=800fF CS=350fF CNC=500fFCLS1CLS2VIPVINCCCCCF+-+-+-+-+-CONVCLS1CLS1CLS2CLS2Pseudo RDC servo loopCLS1CLS2CF+-CONVCLS1CLS2Pseudo RDC servo loopCLS1CLS2VANVAPVONVOPLoopFilterA1A2A3Pre-amp+-SARLogicDoutS1S1CTCLS PGA 3rd

195、 order kT/C canceled Noise Shaping SARS2S2S2CSCS10b+2rCLS1CLS2CONVS1S2Timing DiagramkT/C ExtractCLS1CLS2ADC conversionSampling5ns4.5ns15.5ns2ns18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025

196、IEEE International Solid-State Circuits Conference46 of 58CGA Circuit ImplementationAmplifier structureSimple inverter-based amplifier structureDominant pole placed at the outputVCM-+A1&A2&A3IBVIPVINVONVOPCLS1CLS2VIPVINCCCCCF+-+-+-+-+-CONVCLS1CLS1CLS2CLS2CLS1CLS2CF+-CONVCLS1CLS2CLS1CLS2VANVAPVONVOPA

197、1A2A3CSCSADC18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference47 of 58ADC OverviewCNC=500fF CDAC=350fFCEF=480fF CEX1=30fF CINT1=240fF CINT2=45f

198、F CEX2=15fFS1VREFPVCMVREFNCEFPCINT1PCEX1PCEX1NCEX2PCEX2NPre-ampFIACINT2PSARLogic+-NSNSS2EX10b+2r(10+2)b+-S1VREFPVCMVREFNCEFNCINT1NCINT2NNSNSS210b+2r(10+2)bCOMPD1D11x12x12VIPVIN(10+2)bS2kT/C Cancellation1st-order EF Path-+-+-2nd-order CIFF Path4x1x1x4xS2Preamp ReusingS2EXLoop Filter+S1S2NSEXCOMPSampl

199、ingConversionResidueExtractionTiming diagram9.5ns7.5ns8ns18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference48 of 58OutlineMotivationProposed Ra

200、il-to-Rail Input BufferProposed 3rdorder NS-SAR ADC ImplementationSystem and Circuit ImplementationMeasurement ResultsConclusion18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE Internatio

201、nal Solid-State Circuits Conference49 of 58Chip Micrograph55nm CMOSActive area:0.043mm2Supply:1.2VFs:40MHzOSR:8BW:2.5MHz 18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Sol

202、id-State Circuits Conference50 of 58Measured SpectrumConfigured as the amplifier structure Large distortion under the full-swing inputVIPVINCCADC conversionCCCF+-+-CFCSCSADCVIPVINCCCCCF+-+-CFCSCSADCADC samplingVANVAPVONVOPVANVAPVONVOP18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.

203、4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference51 of 58Measured SpectrumConfigured as the CLS1 structure Improved performanceVIPVINCCCoarse phase ADC conversionCCCF+-+-CFCLSCSCSADCVIPVINCCCCCF+-+-CFCLSCSCSA

204、DCCLSFine phase ADC samplingCLSVCMVANVAPVONVOPVANVAPVONVOPVCM18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference52 of 58Measured SpectrumConfigu

205、red as the CTCLS structure82.9dB SNDR 105.4dB SFDR 500kHz inputVIPVINCCAMP Tracking-ConversionCCCF+-+-CFCLS1CLS2CSCSADCVIPVINCCCCCF+-+-CFCLS1CSCSADCVIPVINCCCCCF+-+-CFCSCSADCCLS1CLS2CLS2CLS1-SamplingCLS2-SamplingCLS1CLS2CLS2CLS2CLS1CLS1VCMVCMVANVAPVONVOPVANVAPVONVOPVANVAPVONVOPVCMVCMVCMVCMVCMVCM18.5

206、A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference53 of 58Measured SpectrumMeasured performance under 2X gain80.0dB SNDR 96.6dB SFDR 500kHz input18.

207、5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting 2025 IEEE International Solid-State Circuits Conference54 of 58Measured Chip VariationSNDR variation tdelay MTStready tdelay 1 018.6 An Easy-Drive 16MS

208、/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference19 of 48Opportunistic PN-Injection-Based Calibration tready tdelay MTStreadytdelay,MTS=1,DLSB=PNY.Zhou,JSSC1501PNDL

209、SBDLSB+1AMeta DetectorVos,RAVos,cmpLSBMSB LSB+1MTSeq2D2treadytdelay PVT DMSBGainMid Noise KK D2VVPN ALSBPNVVPN+A(Vos,RA-Vos,cmp)+eq2VVPN(MTS=1)tdelay MTStready tdelay MTStready tdelay MTStready tdelay MTStready tdelay MTStreadytdelay,MTS=1If tready tdelay MTStready tdelay 1 018.6 An Easy-Drive 16MS/

210、s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference28 of 48Proposed Inter-Stage Gain CalibrationFixed MTS probabilityPN=+1PN=-1VinVres2E+54E+56E+5455055606570758085SND

211、RNsample Fast and robust inter-stage gain calibration offset cancellation metastable probability control input dither injection18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE Internatio

212、nal Solid-State Circuits Conference29 of 48OutlineMotivationProposed Split Coarse-Fine Input Buffer SamplingProposed Inter-Stage Gain CalibrationADC ArchitectureMeasurement ResultsConclusion18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robu

213、st Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference30 of 48ADC ArchitectureCS,FInput Buffer&1st-stage SAR(1.8V/IO)11-bitSARDAResidue Amplifier(0.9V/core)2nd-stage ADC(0.9V/core)Vcm,DAVcm,S1MetaDetectorSARLogicD2,MSBVos,cancelVinCoarseSARD1,LSBsD1PND2PNG

214、ainDOUT=D1+D2/GainS1CoarseFineConvS1RAS2ConvS2RAcoarsefine s LSBs(4b)MSBs(4b)Dither(2b)FineBufferNegative-HalfCircuitCoarseBuffercoarse VrefpVrefnD1,MSBs0.5CCC8C8C64C2-bit Input ditherPNonly activated LSBLSB18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Sch

215、eme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference31 of 48Pre-charging Coarse Buffer:Pre-charge main CDAC and coarse SARCS,FInput Buffer&1st-stage SAR(1.8V/IO)11-bitSARDAResidue Amplifier(0.9V/core)2nd-stage ADC(0.9V/core)Vcm,DAVcm,S1M

216、etaDetectorSARLogicD2,MSBVos,cancelVinCoarseSARD1,LSBsD1PND2PNGainDOUT=D1+D2/GainS1CoarseFineConvS1RAS2ConvS2RAcoarsefine s LSBs(4b)MSBs(4b)Dither(2b)FineBufferNegative-HalfCircuitCoarseBuffercoarse VrefpVrefnD1,MSBs0.5CCC8C8C64C2-bit Input ditherPNonly activated LSBLSB18.6 An Easy-Drive 16MS/s Pipe

217、lined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference32 of 48Fine Sampling Fine Buffer:Sample the level-shifted signal on CS,F Input dither injection after samplingCS,FInput B

218、uffer&1st-stage SAR(1.8V/IO)11-bitSARDAResidue Amplifier(0.9V/core)2nd-stage ADC(0.9V/core)Vcm,DAVcm,S1MetaDetectorSARLogicD2,MSBVos,cancelVinCoarseSARD1,LSBsD1PND2PNGainDOUT=D1+D2/GainS1CoarseFineConvS1RAS2ConvS2RAcoarsefine s LSBs(4b)MSBs(4b)Dither(2b)FineBufferNegative-HalfCircuitCoarseBuffercoar

219、se VrefpVrefnD1,MSBs0.5CCC8C8C64C2-bit Input ditherPNonly activated LSBLSB18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference33 of 481stStage C

220、onversion Detect and Skip(MSBs)+Buffer Embedded SAR Conversion(LSBs)PN injection(LSB)when“metastability”occursCS,FInput Buffer&1st-stage SAR(1.8V/IO)11-bitSARDAResidue Amplifier(0.9V/core)2nd-stage ADC(0.9V/core)Vcm,DAVcm,S1MetaDetectorSARLogicD2,MSBVos,cancelVinCoarseSARD1,LSBsD1PND2PNGainDOUT=D1+D

221、2/GainS1CoarseFineConvS1RAS2ConvS2RAcoarsefine s LSBs(4b)MSBs(4b)Dither(2b)FineBufferNegative-HalfCircuitCoarseBuffercoarse VrefpVrefnD1,MSBs0.5CCC8C8C64C2-bit Input ditherPNonly activated LSBLSB18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast

222、-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference34 of 48Residue Amplification Residue amplification using dynamic amplifier Fast and robust background inter-stage gain calibrationCS,FInput Buffer&1st-stage SAR(1.8V/IO)11-bitSARDAResidue Amplifie

223、r(0.9V/core)2nd-stage ADC(0.9V/core)Vcm,DAVcm,S1MetaDetectorSARLogicD2,MSBVos,cancelVinCoarseSARD1,LSBsD1PND2PNGainDOUT=D1+D2/GainS1CoarseFineConvS1RAS2ConvS2RAcoarsefine s LSBs(4b)MSBs(4b)Dither(2b)FineBufferNegative-HalfCircuitCoarseBuffercoarse VrefpVrefnD1,MSBs0.5CCC8C8C64C2-bit Input ditherPNon

224、ly activated LSBLSB18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference35 of 48Circuit ImplementationOffset Cancellation LoopVDDLatchCLKVinVipVc

225、mVos,cancelADCS2MSB1st-stage comparatorCharge PumpMetastable Probability Control LoopDFFCharge PumpDelayCellDelayCellCLKxNCounterMetastability DetectorP(meta)=1/(N+1)VdelayDPDNMTSDelay CellVdelay Charge pump based calibration18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input B

226、uffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference36 of 48OutlineMotivationProposed Split Coarse-Fine Input Buffer SamplingProposed Inter-Stage Gain CalibrationADC ArchitectureMeasurement ResultsConclusion18.6 An Easy

227、-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference37 of 48Die photographCoarseBufferFineBuffer1st stage SARResidueAmplifier2nd stage SAR260um330um22-nm CM

228、OS ADC core area 0.06mm2 Supply Voltage1.8/0.9V18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference38 of 48Measurement Results Background gain c

229、alibration(PN injection on chip,correlation off chip)Foreground capacitor mismatch calibration(off chip)18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuit

230、s Conference39 of 48Measurement Results Background gain calibration(PN injection on chip,correlation off chip)Foreground capacitor mismatch calibration(off chip)18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gai

231、n Calibration 2025 IEEE International Solid-State Circuits Conference40 of 48Measurement Results Dynamic Range=81.8dB18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-

232、State Circuits Conference41 of 48Measurement Results SNDR 1dB among 5 chips18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration 2025 IEEE International Solid-State Circuits Conference42 of 48Measureme

233、nt Results SNDR 10dB18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference7 of 53SAR-Based ADC in ReceiverRequire high-order BBFLarge area Extra noise D

234、egraded linearity High driver power DSPLNATIASAR-based ADCBBF18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference8 of 53Alternative SolutionPassive Fi

235、lter-embedded SAR-based ADCHigh efficiency Compact area Robust STF DSPLNATIASAR-based ADCBBF18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference9 of 5

236、3Prior Filtering SAR ADC BW limits to MHz x4018.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference10 of 53Outline Motivation Progressive Conversion Fil

237、tering Pipe-SAR Proposed Amp:Floating-Charge-Transferrer(FCT)Implementation&Measurements Conclusion18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conferenc

238、e11 of 53Filtering SAR ReviewSpeed bottlenecks:Slow SAR conversionSequential operation of filter and SARLin,CICC,201018.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State

239、Circuits Conference12 of 53Speedup#1:Pipe-SAR for Higher Fconv18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference13 of 53Speedup#2:Progressive Conver

240、sion Parallel filtering and SAR operation18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference14 of 53Working Principle of Progressive ConversionStep 1

241、Cs1sampling1st-order IIR filter&FIR filter as example18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference15 of 53Working Principle of Progressive Conv

242、ersionStep 2Cs1IIR filteringCs2sampling1st-order IIR filter&FIR filter as example18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference16 of 53Working P

243、rinciple of Progressive ConversionStep 3Cs1connects with comp.Converts to CDACCs2IIR filteringCs3sampling1st-order IIR filter&FIR filter as example18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 I

244、EEE International Solid-State Circuits Conference17 of 53Working Principle of Progressive ConversionStep 4Cs2merges into CDACCs1-s2charge-sharing FIR filtering SAR logic flips Cs1Cs3IIR filtering1st-order IIR filter&FIR filter as example18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achi

245、eving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference18 of 53Working Principle of Progressive ConversionStep 5Cs3merges into CDACCs1-s3charge-sharing FIR filteringSAR logic flips Cs21st-order IIR filter&FIR filter

246、as example18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference19 of 53Working Principle of Progressive ConversionProgressive ConversionStep 5Cs3merges

247、 into CDACCs1-s3charge-sharing FIR filteringSAR logic flips Cs21st-order IIR filter&FIR filter as exampleFiltering time budget18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Sol

248、id-State Circuits Conference20 of 53Prototype Filter Design Passive Filter Target(802.11ax)BW 80MHzOut-of-band(OOB)suppression 30dB in first aliasing-band 8th-order FIR+3rd-order IIRFIR/IIRFilter2.8GS/s8350MS/s350MS/sADC18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs

249、with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference21 of 53Architecture Overview 8th-order FIR+3rd-order IIR 2x TI,5b Filter-Embedded SAR+10b SAR 18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs wit

250、h Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference22 of 53Detailed Operation Timing Parallel filtering and quantization Saves 70%of filtering time budget18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoM

251、s with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference23 of 53Outline Motivation Progressive Conversion Filtering Pipe-SAR Proposed Amp:Floating-Charge-Transferrer(FCT)Implementation&Measurements Conclusion18.7:A 70dB SNDR 80MHz B

252、W Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference24 of 53Residue Amplifier Desired amplifierLinear,efficientPVT robustLow complexity18.7:A 70dB SNDR 80MHz BW Filter-Embedd

253、ed Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference25 of 53Residue AmplifierClosed-LoopCharge-TransferrerOpamp High power Scaling unfriendlyRing Amp.Medium power Design complexityFIA Mediu

254、m power Low speedZhan,ISSCC,2022Tang,ISSCC,202118.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference26 of 53Residue AmplifierOpen-LoopVoltage Amplifier

255、Gm-R/Gm-C Low linearity PVT EfficiencyGm-R/Gm-C w/calibrations/compensations Medium linearity Extra power Design complexityVaz,ISSCC,2017 Jiang,ISSCC,2019Closed-LoopCharge-Transferrer18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Float

256、ing-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference27 of 53Desired Residue AmplifierImplementationClosed-LoopCharge-TransferrerOpen-LoopVoltage Amplifier?LinearityPVT RobustEfficiencySimplicity18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172d

257、B FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference28 of 53Desired Residue AmplifierImplementationClosed-LoopCharge-TransferrerOpen-LoopVoltage AmplifierOpen-LoopCharge-TransferrerLinearityPVT RobustEfficiencySimplicity18.

258、7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference29 of 53A Naive Open-Loop Charge-Transferrer Static Common-Gate(CG)High linearity PVT robust Insuffic

259、ient speed and gain 18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference30 of 53Evol.#1:Complementary Structure Complementary CGGmdoubled Static Commo

260、n-Gate(CG)High linearity PVT robust Insufficient speed and gain 18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference31 of 53Evol.#2:Folded Cascode Sta

261、tic Common-Gate(CG)High linearity PVT robust Insufficient speed and gain Folded Cascode CGBoosted ZOUT18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Confer

262、ence32 of 53The Really Tricky Problem:Bias Noise Folded Cascode CGHigh bias noise(over 80%)Source degeneration?Noise suppressed Higher supply Power overhead 18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplif

263、ier 2025 IEEE International Solid-State Circuits Conference33 of 53Proposed Solution:Floating Supply Floating Power SupplyNo bias noise High PSRR Folded Cascode CGHigh bias noise(up to 80%)18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and

264、 Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference34 of 53Practical Floating Supply Floating Reservoir CapCRESkT/C noise tolerated 18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-

265、Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference35 of 53Cross-Coupled Flying-Cap Biasing Dynamic operation High CMRR Cross-CoupledFloating-Charge-Transferrer(FCT)18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and

266、Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference36 of 53BootstrappedIntrinsic CMRR and Boosted GmCommon-ModeDifferential-ModeHigh CMRR Gmfurther doubled Cross-Coupled18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progres

267、sive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference37 of 53High Linearity w/Open LoopFloating-Charge-Transferrer(FCT)18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Cha

268、rge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference38 of 53PVT Sensitivity AnalysisPost-layout simulation w/o trimmingFor comparison,Jiang,ISSCC19 Gm-R amplifier:gain variation+3.5%to-10%w/o trim.and 2.3%w/trim.18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Ach

269、ieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference39 of 53Outline Motivation Progressive Conversion Filtering Pipe-SAR Proposed Amp:Floating-Charge-Transferrer(FCT)Implementation&Measurements Conclusion18.7:A 7

270、0dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference40 of 53ADC Implementation18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs

271、with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference41 of 53FCT and Replica Bias Gen.18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifie

272、r 2025 IEEE International Solid-State Circuits Conference42 of 53Chip Micrograph 28nm CMOS Active area:0.036mm218.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circui

273、ts Conference43 of 53Single-Tone TestCDAC mismatch,comparator offset,and inter-stage gain are one-time foreground calibrated.FS,filter=2.8GS/sFS,ADC=350MS/s18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifi

274、er 2025 IEEE International Solid-State Circuits Conference44 of 53Two-Tone Test18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference45 of 53STF Measure

275、d under Full-Scale Input Robust STF across devices w/o calibration18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference46 of 53STF Measured with Scaled

276、 FS,Filter BW is scalable with over 5 adjustment in FS,Filter18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference47 of 53Full-Scale Blocker Rejection

277、Performance is insusceptible under strong blocker injections18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference48 of 53Measured DR&Power Breakdown DR

278、=72.0dB Power=4.87mW FoMS=172.2dB-80-60-40-200Input Level dBFS020406080SNR/SNDR dBDR=72.0dBSNRSNDR-6-4-266687018.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuit

279、s Conference49 of 53Measured Supply VariationsInter-stage gain re-calibrated at each point.18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference50 of 5

280、3Comparison to Prior Filtering ADCsThis WorkISSCC-19Wang 2ISSCC-22Bolatkale 1ISSCC-17Huang 3JSSC-19Harpe 7TCASI-23Xin 5ArchitectureFilter-embeddedpipe-SARCTDSMCTDSMCTDSMFilter+SARFilteringSARScalable BWYesNoNoNoYesYesRobust STFYesNoNoNoYesYesMax BW MHz80801201251.71SNDR dB70.164.971.571.957.1b+4.7c5

281、8.7+7cSFDR dB83.480a11485a75.772.2FoMSddB172.2165.3162165.5168.2170.0aEstimated from figure bCalculated from ENOB cInclude OSR dFoMS=SNDR+10log10(BW/Power)18.7:A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifie

282、r 2025 IEEE International Solid-State Circuits Conference51 of 53Comparison to Prior Filtering ADCsThis WorkISSCC-19Wang 2ISSCC-22Bolatkale 1ISSCC-17Huang 3JSSC-19Harpe 7TCASI-23Xin 5Process nm282828166540Area mm20.0360.060.130.2170.00610.067FS,FilterMHz2800-4040FS,ADCMHz350960600021501010Max BW MHz

283、80801201251.71OSR2.26258.62.95SNDR dB70.164.971.571.957.1b+4.7c58.7+7cSFDR dB83.480a11485a75.772.2DR dB72.06872.374.8-Power mW4.877.33108.8540.03920.038FoMSddB172.2165.3162165.5168.2170.0aEstimated from figure bCalculated from ENOB cInclude OSR dFoMS=SNDR+10log10(BW/Power)18.7:A 70dB SNDR 80MHz BW F

284、ilter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference52 of 53Comparison with SOTA Filtering ADCs x40 BW boosting than prior filtering SAR Superior efficiencyx4018.7:A 70dB SNDR 8

285、0MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier 2025 IEEE International Solid-State Circuits Conference53 of 53Conclusion Progressive Conversion Filtering Pipe-SARParallel filtering and quantization Floating-Charge-Tran

286、sferrer(FCT)Dynamic open-loop amplifier Inherent high linearity,low noise,low power,PVT robust Prototype filtering ADC with 70dB SNDR under 80MHz BWRobust and scalable anti-aliasing STF 4.87mW,resulting in FoMS=172.2dB18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2

287、025 IEEE International Solid-State Circuits Conference1 of 82A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDRBram Veraverbeke,Filip TavernierKU Leuven ESAT-MICAS,Leuven,Belgium18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE Intern

288、ational Solid-State Circuits Conference2 of 82Why Quantum Computing?CryptographyData base searchesFinanceDrug developmentTraffic optimizationWeather forecasting18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference3 of

289、 82Quantum Bits(Qubits)n Superpositionl|=|0 +|1,|2+|2=1 l|=cos()|0+sin()ei|1 lBloch sphere representationn EntanglementlQubits can share states lCompute power doubles with every extra qubitn Very fragile lShort decoherence timeslOperating at mK stage|1|0 zyx18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with on

290、ly 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference4 of 82The Quantum-Classical InterfaceRoom Temperature10 mKQubitQuantum processor with millions of qubits Classical processor AWG,PSG,scope,etc.18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacit

291、ance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference5 of 82RT Electronics Are Not ScalableJ.C.Bardin et al.,ISSCC 19Lab instruments room temperature72 qubits 10 mKLong and lossy cablesDilution refrigerator18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64

292、dB SFDR 2025 IEEE International Solid-State Circuits Conference6 of 82Cryo-CMOS to Enable ScalingLeiden Cryogenics BVCooling power50 K,100 W 4 K,1 W10 mK,50 dB)G.Kiene et al.,JSSC,2023.DriverT=4 K18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International

293、 Solid-State Circuits Conference13 of 82The Bigger Picture:System Powern Prior art ADC power consumption:1.8-10 mW DACDigital controlLOT=10 mKT=6.5 KLNA.Frequency multiplexed qubitsDriver ADCG.Kiene et al.,ISSCC,2021.G.Kiene et al.,ESSCIRC,2022.J.Lee et al.,ESSCIRC,2023.G.Kiene et al.,TCAS-I,2024.Dr

294、iverT=4 K18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference14 of 82The Bigger Picture:System Powern Prior art ADC power consumption:1.8-10 mWn System power consumption:10-108 mW DACDigital controlLOT=10 mKT=6.5 KLN

295、A.Frequency multiplexed qubitsDriver ADCB.Prabowo et al.,ISSCC,2021.J.-S.Park et al.,ISSCC,2021.A.Ruffino et al.,ISSCC,2021.K.Kang et al.,ISSCC,2022.Y.Guo et al.,ISSCC,2024.B.Prabowo et al.,ISSCC,2024.DriverT=4 K18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IE

296、EE International Solid-State Circuits Conference15 of 82The Bigger Picture:System Power DACDigital controlLOT=10 mKT=6.5 KLNA.Frequency multiplexed qubitsDriver ADCn Prior art ADC power consumption:1.8-10 mWn System power consumption:10-108 mW Reduce ADC driver requirements to lower PSYSTEM DriverT=

297、4 K18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference16 of 82Exploit Low Thermal Noisen Low temperature Opportunity to reduce CIN and VFS n System-level power savingsPDriver CINVDDVFSfSNR=VFS/8kT/CIN2B.Nauta,ISSCC,

298、2024.VDDVFSCINDriverADC18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference17 of 82Exploit Low Thermal Noisen Low temperature Opportunity to reduce CIN and VFS n System-level power savingsPDriver CINVDDVFSfSNR=VFS/8k

299、T/CIN2B.Nauta,ISSCC,2024.VDDVFSCINDriverADCCINT18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference18 of 82Exploit Low Thermal Noisen Low temperature Opportunity to reduce CIN and VFS n System-level power savingsPDri

300、ver CINVDDVFSfB.Nauta,ISSCC,2024.VDDVFSCINDriverADCVFS2SNR=VFS/8kT/CIN2T18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference19 of 82Conventional SAR with CDACn CDAC cannot take full advantage of low temperatureVSSVRE

301、FVSSVREFVPVN.CFIXCFIXReducing CIN limited by matchingLowering VFS below 2 VDD requires CFIX or additional VREFHigh PsystemGood FoM18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference20 of 82THIS DESIGN:Charge Injecti

302、on(CI-)SARLow CINFlexible VFSLow PSYSTEMK.D.Choo et al.,ISSCC,2016.FSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPQDACCLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circ

303、uits Conference21 of 82Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPK.D.Choo et al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circui

304、ts Conference22 of 82Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPDACPDACN.DACPDACNK.D.Choo et al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Sol

305、id-State Circuits Conference23 of 82Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPDACPDACN.DACPDACNK.D.Choo et al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE In

306、ternational Solid-State Circuits Conference24 of 82Conventional CI-SARDACPDACN.DACPDACN.DACPDACNFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPMSBQMSBQLSBDACPDACNTRANSELRSTVB32CICCICCICCICK.D.Choo et al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s

307、 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference25 of 82Conventional CI-SARDACPDACN.DACPDACN.DACPDACNFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPMSBMSB 1QMSB-1QLSBDACPDACNTRANSELRSTVB16CICCICCICK.D.Choo et

308、al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference26 of 82Conventional CI-SARDACPDACN.DACPDACNFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.C

309、NCPK.D.Choo et al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference27 of 82Conventional CI-SARDACPDACN.DACPDACNFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN

310、.CICCICCICCIC.CNCPEasy to matchLow input capacitanceLow Psystem K.D.Choo et al.,ISSCC,2016.CLKCOMPFSM +timingBITLATCHP/NTRANS18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference28 of 82Tunable Charge Injection Celln

311、Tune QLSB with WTRAN or VBn No extra VREF or CFIX requiredDACPDACNTRANSELRSTIDACVBFlexible full scaleLow Psystem WTRANtIDACVB18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference29 of 82Tunable Charge Injection Celln

312、Tune QLSB with WTRAN or VBn No extra VREF or CFIX requiredDACPDACNTRANSELRSTIDACVBFlexible full scaleLow Psystem WTRANtIDACVBQLSB=IDAC dt!0WTRAN18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference30 of 82Challenges i

313、n the Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPBITLATCHP/N18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference31 of 82Challenges in the Conventional CI-SAR.FSM +tim

314、ingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPDACPDACNBITLATCHP/N18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference32 of 82Challenges in the Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/

315、NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPDACPDACN.VCM1.Decreasing VCMBITLATCHP/N18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference33 of 82Charge Injection Cellsn Can only sink chargen VCM decreases monotonicallyDACP

316、DACNVB1BITLATCHNBITLATCHPVDDVDDVDDENTRANSENBITLATCHP BITLATCHN TRANSDACPDACNBITLATCHNBITLATCHPBITLATCHPBITLATCHN18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference34 of 82Charge Injection Cellsn Can only sink charge

317、n VCM decreases monotonicallyDACPDACNVB1BITLATCHNBITLATCHPVDDVDDVDDENTRANSENBITLATCHP BITLATCHN TRANSDACPDACNQLSB1BITLATCHNBITLATCHPBITLATCHPBITLATCHN18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference35 of 82Charge

318、 Injection Cellsn Can only sink chargen VCM decreases monotonicallyDACPDACNVB1BITLATCHNBITLATCHPVDDVDDVDDENTRANSENBITLATCHP BITLATCHN TRANSDACPDACNQLSB12BITLATCHNBITLATCHPBITLATCHPBITLATCHN18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-

319、State Circuits Conference36 of 82Charge Injection Cellsn Can only sink chargen VCM decreases monotonicallyDACPDACNVB1BITLATCHNBITLATCHPVDDVDDVDDENTRANSENBITLATCHP BITLATCHN TRANSDACPDACN123BITLATCHNBITLATCHPBITLATCHPBITLATCHN18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB

320、 SFDR 2025 IEEE International Solid-State Circuits Conference37 of 82Charge Injection Cellsn Can only sink chargen VCM decreases monotonicallyDACPDACNVB1BITLATCHNBITLATCHPVDDVDDVDDENTRANSENBITLATCHP BITLATCHN TRANSDACPDACNDistortion123BITLATCHNBITLATCHPBITLATCHPBITLATCHN18.8:A Cryo-CMOS 800MS/s 7b C

321、I-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference38 of 82Sinking AND Sourcing ChargeDACPDACNVB1BITLATCHNBITLATCHPVDDVDDVDDENTRANSDACPDACNVB2BITLATCHPBITLATCHNVDDVDDVDDENVDDTRANSn Source charge with complementary CICn VCM stays constantDistort

322、ion Swap NMOS and PMOSBITLATCHPBITLATCHNBITLATCHNBITLATCHP18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference39 of 82Challenges in the Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICC

323、ICCICCIC.CNCPDACPDACN.VCM1.Decreasing VCMBITLATCHP/N18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference40 of 82Challenges in the Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICC

324、IC.CNCPDACPDACN.VCM1.Decreasing VCM2.Nonlinear parasitic capacitance from comparator and CI-DACBITLATCHP/N18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference41 of 82Bottom Plate SamplingVCMVCMBITPBITNCPVPFSM +timing

325、CNVNCI-DAC(sink+source)CI-DAC(sink+source)CLKCOMPDACPDACNDACPDACNVCMAt VCM during samplingn When sampling top-plates connected to VCM18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference42 of 82Bottom Plate SamplingVC

326、MVCMBITPBITNCPVPFSM +timingCNVNCI-DAC(sink+source)CI-DAC(sink+source)CLKCOMPDACPDACNDACPDACNVCMAt VCM during samplingn Transfer sampled voltage to top-plates18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference43 of 8

327、2Bottom Plate SamplingVCMVCMBITPBITNCPVPFSM +timingCNVNCI-DAC(sink+source)CI-DAC(sink+source)CLKCOMPn No influence of non-linear capacitance at the top-platesDistortion DACPDACNDACPDACNReturn to VCMVCMAt VCM during sampling18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB S

328、FDR 2025 IEEE International Solid-State Circuits Conference44 of 82Challenges in the Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPDACPDACN.VCM1.Decreasing VCM2.Nonlinear parasitic capacitance from comparator and CI-DACBITLATCHP/N18.8:A Cryo-CMOS 800MS/

329、s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference45 of 82Challenges in the Conventional CI-SARFSM +timingVPVNBITPTRANSBITLATCHP/NBITNENCLKCOMPDACPDACN.CICCICCICCIC.CNCPDACPDACN.VCM1.Decreasing VCM2.Nonlinear parasitic capacitance from c

330、omparator and CI-DAC3.Comparator kickbackBITLATCHP/N18.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference46 of 82Comparator with Static Preamplifiern Static preamplifier suppresses kickbackn Double tail comparator req

331、uires less voltage headroomCLKVDDDACPDACNCLKCLKDouble-tail comparatorPreamplifierD.Schinkel et al.,ISSCC,200718.8:A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference47 of 82Presented Architecture FSM +timingVPVNVDDVCM1 1

332、 2 1 1 VCM2 1 1 2 2 1 1 BITPTRANSTRANSBITLATCHP/NBITNBITLATCHP/NEN5:0EN5:0CLKCOMPCLKINOUTPOUTNVDDCI-DAC Sink(32 CICs,6 groups)CI-DAC Source(32 CICs,6 groups).CICCICCICCICCICCICCICCIC.CICCICCICCICCICCICCICCICBITLATCHP/NBITLATCHP/NCLKINCI-DAC Sink(32 CICs,6 groups)CI-DAC Source(32 CICs,6 groups)18.8:A

333、 Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR 2025 IEEE International Solid-State Circuits Conference48 of 82Presented Architecture FSM +timingVPVNVDDVCM1 1 2 1 1 VCM2 1 1 2 2 1 1 BITPTRANSTRANSBITLATCHP/NBITNBITLATCHP/NEN5:0EN5:0CLKCOMPCLKINOUTPOUTNVDDCI-DAC Sink(32 CICs,6 groups)CI-DAC Source(32 CICs,6 groups).CICCICCICCICCICCICCICCIC.CICCICCICCICCICCICCICCICBootstra