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1、第三屆中國第三屆中國Rust開開發發者大會者大會Rust Atomic Deep DivePu Wang DatenLord2023/06/17Rust原子操作高性能實踐What are atomic operations in Rust?WhatWhy need atomic operations?WhyHow010203Memory order in atomic operationsMemory ModelThe overhead of atomic operationsCache CoherenceSummary040506How to understand atomic operat
2、ions?Atomic operation best practiceOutlineWhat are Atomic Operations in Rust?fn compare_exchange(&self,/AtomicI8 current:i8,new:i8,success:Ordering,failure:Ordering)-ResultCompare and SwapFetch and Modifyfn fetch_add(&self,val:i8,order:Ordering)-i8fn fetch_and(&self,val:bool,order:Ordering)-bool01Lo
3、ck-free programmingWhy Atomic Operation?High PerformanceLock-context switchAtomic-no context switchShared Variable Access When Multi-threading02How to Understand Atomic Operations?Memory OrderThe order of load/store instructions accessing memory.Memory ModelCache CoherenceAtomic operation overheadAt
4、omic operations will change cache line status which might flush cache lines.03Program orderInstructions executed as the order defined in a threadMemory orderMemory access instructionsload&storeOut of orderInstruction reorder by compilersOut of order execution in CPUload v.s.loadload v.s.storestore v
5、.s.loadstore v.s.storeMemory Model04Instruction Reorder by Compilers04Write buffer/store bufferDelayed writeStore forwardingTotal store order(TSO)FIFO writer bufferOoO store v.s.loadPartial store order(PSO)Non-FIFO write bufferOoO store v.s.loadOoO store v.s.storeOut of Order Execution04Memory Order
6、 in C+/RustSequential ConsistencyAcquire04ReleaseAcqRelRelaxedConsumeEach processor issues memory operations in program orderThe switch provides the global serialization among all memory operationsSequential Consistency04A write-release guarantees that all preceding code completes before the releasi
7、ng writeA read-acquire guarantees that all following code starts after the acquiring readAcquire Release04Acquire Release Example04Consistency04Consistency in Non-TransactionalDistributed Storage Systemshttps:/arxiv.org/pdf/1512.00168.pdfCache05Cache Coherence05Exponential Backoff Retry05SeqCstAcquireReleaseAcqRelSummary Memory OrderCache line flush overheadExponential backoff retryCache Coherence06Thank you!