新思科技Synopsys (SNPS) 2004年年度報告「NASDAQ」.pdf

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1、2004 Annual ReportSystemic solutions delivering EDA productivityFiscal 2004 was an important transition year for Synopsys.From a technology standpoint,we made great strides in transforming our product line from a collection of point tools into complete,correlated platforms.Our focus on customer prod

2、uctivity brought us increased customer interest and benchmarking wins.We entered fiscal 2005 with increased confidence in our competitive technology strength.Financially,we made changes to our license model that put us on solid footing for sustained growth in revenue and profitability.We expect to b

3、uild significant backlog in 2005,which will provide predictability to our financial results.Fiscal Year ResultsFiscal 2004 was a challenging year for the Company financially.Revenue was$1.09 billion,down 7 percent from 2003.Our GAAP net income was$74.3 million,or$0.46 per share,for fiscal 2004,compa

4、red to$149.7 million,or$0.95 per share,for fiscal 2003.Non-GAAP*net income was$166.4 million,or$1.04 per share,in fiscal 2004,com-pared to$252.1 million,or$1.59 per share,for fiscal 2003.Lets put our results in perspective.The semiconductor industryour core customer basehas just emerged from its dee

5、pest downturn of the past 20 years.Throughout the downturn,our customers carefully controlled expenses.As a result,EDA industry growth was relatively flat from 2000 through 2004.At the beginning of fiscal 2004,we expected that healthy growth in the semiconductor industry would lead to in-creased spe

6、nding on EDA.Instead,as our customers revenue grew,they continued to focus on increasing their profitability by controlling expenses.During our third quarter,we saw a marked drop in customer demand,especially for term and perpetual licenses,which are paid for primarily up front.We responded immediat

7、ely.In our fourth quarter,we shifted our target license mix to consist almost entirely of subscription licenses.These permit the customer to make payments over time,and in turn,we recognize revenue from these licenses over time as well.This shift has many positive effects.Going forward,in each quart

8、er we expect that at least 90 percent of our quarterly revenue will come from backlog.This will give us better vis-ibility into our revenue results and will help us derive more value for the new technology we will roll out in fiscal 2005.Another effect of the shift is that our fiscal 2005 revenue pr

9、omises to be lower than it would have been under the old license model.However,we expect to add significantly to our backlog,which will help grow revenue in 2006 and beyond.Technology LeadershipCompanies today are focused on improving productivity.For chip design,this means balancing the three attri

10、butes of quality of results(QOR),time to results(TTR),and cost of results(COR).Synopsys has always provided the best QOR for our customers.Our solutions help designers make important trade-off decisions on deep technical issues such as timing closure,signal integrity,power management,design for test

11、,verification,manufacturability,and yield.As a result,Synopsys is involved in virtually every leading-edge chip in the world today.During 2004 we also made significant progress in address-ing TTR,improving the predictability of customers produc-tion schedules,and COR,containing the cost increases th

12、at come from spiraling complexity.Synopsys is involved in virtually every leading-edge chip in the world today.Dear Fellow Shareholders*See the table entitled“Income Statement Reconciliation”on the inside back cover of this Annual Report to Stockholders for a quantitative reconciliation of non-GAAP

13、net income to net income calculated in accordance with GAAP.Building a Complete Product Portfolio Optimized for Productivity.In 2004,we made major improvements to our Galaxy design platform and our Discovery verification platform.The Galaxy platform supports the complete design flow from high-level

14、chip specifications all the way to tape-out,when a finished design is sent to fabrication.The Discovery platform has all the verification tools that check to be sure no errors were made in the design.In June 2004 we rolled out products that strengthened these platforms and demonstrated the ongoing v

15、alue of our acqui-sition of Avant!Corporation in June 2002.We delivered Galaxy 2004,offering 2x or better increases in speed and capacity and significant improvements in quality of results and process technology support.We enhanced our PrimeTime timing analysis product,increasing speed and capacity

16、by up to 3x,compared to the prior version.We doubled the speed of our Astro place-and-route product and gave it up to a 40 percent increase in capacity.And we rolled out our Galaxy Power solution,offering improvements in the power efficiency of integrated circuits(ICs).In verification,we released a

17、new version of our VCS func-tional verification product in June 2004.It contains native testbench automation,speeding up runtime by up to 5x.Our new 2004 Vera testbench generator is up to 10 x faster than its predecessor,and is also available“native”to VCS.We released Discovery AMS,with verification

18、 optimized for analog and mixed-signal designs.For our HSPICE circuit simulator,we provided up to 20 x better performance,as well as support for high-frequency and RF IC designs.Growing our Market Up and Down the Value ChainAdjacent to our strong implementation and verification platforms,we have con

19、tinued to expand our positions in promising markets.Moving up the value chain,we help our customers design very large chips by using pre-designed and pre-verified building blocks.Synopsys provides a rich collection of these blocks in our DesignWare family.Our portfolio has been built over many years

20、,both by internal development and by acquisition.During fiscal 2004 we strengthened our offering by the release of our PCI Express physical layer IP core and by the acquisition of Accelerant Networks,Inc.,and Cascade Semiconductor Solutions,Inc.These developments give us complete portfolios of USB a

21、nd PCI Express IP blocks,and we have built a strong position in these growing segments.Overall,we have the largest IP business of any EDA company and are the third largest commercial IP vendor in the world.Moving down the value chain,with increasing chip complexity,design and manufacturing now must

22、be much more closely linked;thus,the new market of“Design for Manufacturing”(DFM).At Synopsys,we offer our customers solutions that reduce mask costs,improve quality,and take yield issues into consideration during the design process.In fiscal 2004 we enhanced our DFM solutions in a number of ways.We

23、 expanded our TCAD offering by acquiring ISE Integrated Systems Engineering AG.We also introduced our Taurus Process Atomistic product.In the area of optical prox-imity correction,in fiscal 2004 we announced improvements to our Proteus product to improve mask-making at very small geometries.These ne

24、west offerings make our DFM tools the most extensive of any EDA company.Delivering Real Value with Every New ChipBy helping our customers achieve success in their most complex projects,we have built a strong reputation with chip designers.In the 2004 EDA branding survey published by EE Times,we scor

25、ed more#1 rankings than all other EDA companies combined for the third year in a row.Here are a few of the survey highlights:The majority of all chip designers balancing the three productivity attributes of quality of results(QOR),time to results(TTR),and cost of results(COR).We strive for ethics an

26、d good citizenship in both our business dealings and our community service.polled by EE Times say that Synopsys is the best-managed company in EDA,is the technology leader today,will be the technology leader in three years,and offers the best after-sales support.An Ongoing Commitment to the Communit

27、yOne area of the EE Times survey that is particularly impor-tant to us is the feedback from customers that we are the most ethical company in the industry.We strive for ethics and good citizenship in both our business dealings and our community service.In fiscal 2004,the Synopsys Foundation donated$

28、1.4 million to 70 organizations working to advance our primary philan-thropic objective of improving science and math education.In addition,a majority of our Synopsys field offices helped improve their local educational system.Individual employees also donated over 11,000 personal hours as volunteer

29、s last year.They gave over$115,000 through our Matching Gift program and donated thousands of items,such as food,toys,books,backpacks,school supplies,and clothes,through employee-giving drives to make a positive difference in the world beyond Synopsys.During fiscal 2004,the Synopsys Silicon Valley S

30、cience&Technology Outreach Foundation supported over 79,000 students and teachers engaged in project-based learning at 267 schools.Outreach Foundation support continued for numerous school science fairs,including the Synopsys Cham-pionship,the regional science fair for Silicon Valley where over 1,00

31、0 students competed,and sciencepalooza!,which in four years has become one of the largest science fairs in California.In addition,Aart de Geus was recently honored to serve as Chairman of the Second Harvest Food Bank Holiday Food Drive.One of the largest food drives in the country,Second Harvest suc

32、ceeded in raising 1.7 million pounds of food and$3.9 million during the 2004 holiday season.ConclusionAll in all,fiscal 2004 was a year of important accomplishments for Synopsys.While the move to a ratable license model will im-pact our results during the transition period,it will serve us and our c

33、ustomers well in the long term.Most importantly,we rolled out new technology that satisfies our customers urgent needs for increased productivity.As we look forward,we are excited about more new technology to be rolled out in fiscal 2005.Once again,we wish to thank you for your continued invest-ment

34、 in our success.Dr.Aart J.de GeusChairman and ChiefExecutive OfficerDr.Chi-Foon ChanPresident and ChiefOperating OfficerIncome Statement Reconciliation Twelve Months Ended(in thousands)October 31,2004 2003GAAP net income(loss)$74,337$149,724Amortization of intangible assets and deferred stock compen

35、sation 137,463 128,174Merger termination fee 10,000-In-process research and development 1,638 19,850Realignment charges,net of those settled at a lower cost than estimated 510 14,856Collection of acquired accounts receivable originally assumed uncollectible-(3,000)Pre-merger liabilities resolved at

36、a lower cost than estimated-(5,330)Tax effect(57,517)(52,135)Non-GAAP net income$166,431$252,139Income Statement Reconciliation Per Share Twelve Months Ended(in thousands,except per share data)October 31,2004 2003GAAP earnings(loss)per share$0.46$0.95Amortization of intangible assets and deferred st

37、ock compensation 0.86 0.81Merger termination fee 0.06-In-process research and development 0.01 0.13Realignment charges,net of those settled at a lower cost than estimated 0.01 0.09Collection of acquired accounts receivable originally assumed uncollectible-(0.02)Pre-merger liabilities resolved at a l

38、ower cost than estimated-(0.03)Tax effect(0.36)(0.34)Non-GAAP earnings per share$1.04$1.59 UNITED STATESSECURITIES AND EXCHANGE COMMISSIONWashington,D.C.20549FORM 10-KANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d)OF THESECURITIES EXCHANGE ACT OF 1934For the year ended October 31,2004ORTRANSITION REPO

39、RT PURSUANT TO SECTION 13 OR 15(d)OF THESECURITIES EXCHANGE ACT OF 1934Commission File Number 0-19807SYNOPSYS,INC.(Exact name of registrant as specified in its charter)Delaware56-1546236(State or other jurisdiction of incorporation or(I.R.S.Employer Identification No.)organization)700 East Middlefie

40、ld Road,Mountain View,California 94043(Address of principal executive offices,including zip code)(650)584-5000(Registrants telephone number,including area code)Securities Registered Pursuant to Section 12(b)of the Act:NoneSecurities Registered Pursuant to Section 12(g)of the Act:Common Stock,$0.01 p

41、ar value(Title of Class)Preferred Share Purchase Rights(Title of Class)Indicate by check mark whether the Registrant(1)has filed all reports required to be filed bySection 13 or 15(d)of the Securities Exchange Act of 1934 during the preceding 12 months(or for suchshorter period that the Registrant w

42、as required to file such reports),and(2)has been subject to such filingrequirements for the past 90 days.Yes No Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is notcontained herein,and will not be contained,to the best of Registrants knowledge,in de

43、finitive proxy orinformation statements incorporated by reference in Part III of this Form 10-K or any amendment to thisForm 10-K.Indicate by check mark whether the Registrant is an accelerated filer(as defined in Rule 12b-2 of theAct).Yes No The aggregate market value of the voting and non-voting c

44、ommon equity held by non-affiliatescomputed by reference to the price at which the common equity was last sold as of the last business day ofthe Registrants most recently completed second fiscal quarter was approximately$2,971,050,000.Aggregatemarket value excludes an aggregate of 43,963,564 shares

45、of common stock held by officers and directors andby each person known by the Registrant to own 5%or more of the outstanding common stock on such date.Exclusion of shares held by any of these persons should not be construed to indicate that such personpossesses the power,direct or indirect,to direct

46、 or cause the direction of the management or policies of theRegistrant,or that such person is controlled by or under common control with the Registrant.On January 1,2005,146,017,235 shares of the Registrants Common Stock,$0.01 par value,wereoutstanding.DOCUMENTS INCORPORATED BY REFERENCENone.SYNOPSY

47、S,INC.ANNUAL REPORT ON FORM 10-KYear ended October 31,2004TABLE OF CONTENTSPage No.PART IItem 1.Business.1Item 2.Properties.13Item 3.Legal Proceedings.14Item 4.Submission of Matters to a Vote of Security Holders.15PART IIItem 5.Market for Registrants Common Equity,Related Stockholder Matters andIssu

48、er Purchases of Equity Securities.18Item 6.Selected Financial Data.18Item 7.Managements Discussion and Analysis of Financial Condition and Resultsof Operations.19Item 7A.Quantitative and Qualitative Disclosures About Market Risk.52Item 8.Financial Statements and Supplementary Data.55Item 9.Changes i

49、n and Disagreements with Accountants on Accounting andFinancial Disclosure.100Item 9A.Controls and Procedures.100Item 9B.Other Information.100PART IIIItem 10.Directors and Executive Officers of the Registrant.100Item 11.Executive Compensation.103Item 12.Security Ownership of Certain Beneficial Owner

50、s and Management andRelated Stockholder Matters.106Item 13.Certain Relationships and Related Transactions.109Item 14.Principal Accounting Fees and Services.110PART IVItem 15.Exhibits and Financial Statement Schedules.111SIGNATURES.115iPART IThis Annual Report on Form 10-K,particularly in Item 1.Busi

51、ness and Item 7.ManagementsDiscussion and Analysis of Financial Condition and Results of Operations,includes forward-lookingstatements within the meaning of Section 27A of the Securities Act of 1933(the Securities Act)andSection 21E of the Securities Exchange Act of 1934(the Exchange Act).These stat

52、ements include,but arenot limited to,statements concerning:our business,product and platform strategies expectations regardingprevious and future acquisitions;completion of development of our unfinished products or furtherdevelopment or integration of our existing products;expectations regarding boo

53、kings,revenue,earnings,changes in operating expenses,cash flows,gross margin and operating margin in fiscal 2005;continuation ofcurrent industry trends towards vendor consolidation;expectations regarding our license mix;expectationsregarding future maintenance revenue;expectations regarding customer

54、 interest in more highly integratedtools and design flows;expectations of the success of our intellectual property and design for manufacturinginitiatives;expectations regarding changes in our upfront and time-based revenue in fiscal 2005;expectationsregarding revenue seasonality;and our expectation

55、s of our future liquidity requirements.Our actual resultscould differ materially from those projected in the forward-looking statements as a result of a number offactors,risks and uncertainties discussed in this Form 10-K,especially under the caption Factors that MayAffect Future Results,in Item 7 i

56、n this Form 10-K.The words may,will,could,would,anticipate,expect,intend,believe,continue,or the negatives of these terms,or other comparableterminology and similar expressions identify these forward-looking statements.The information includedherein is given as of the filing date of this Form 10-K w

57、ith the Securities and Exchange Commission(SEC)and future events or circumstances could differ significantly from these forward-looking statements.Furthermore,we assume no obligation,and do not intend,to update these forward-looking statements exceptas required by law.Item 1.BusinessIntroductionSyno

58、psys,Inc.(Synopsys)is a world leader in electronic design automation(EDA)software forsemiconductor design.We deliver technology-leading semiconductor design and verification softwareplatforms and integrated circuit(IC)manufacturing software products to the global electronics market,enabling the deve

59、lopment and production of complex systems-on-chips(SoCs).We also provideintellectual property(IP)and design services to simplify the design process,and acceleratetime-to-market for our customers.We incorporated in 1986 in North Carolina and reincorporated in Delaware in 1987.Ourheadquarters are loca

60、ted at 700 East Middlefield Road,Mountain View,California 94043 and ourtelephone number is(650)584-5000.We have more than 60 offices throughout North America,Europe,Japan and Asia.Our Annual Reports on Form 10-K,Quarterly Reports on Form 10-Q,Proxy Statements relatingto our annual meetings of stockh

61、olders,Current Reports on Form 8-K and amendments to thesereports and filings made by our executive officers and directors are available on our Internet website().We post these reports to our website as soon as practicable after we file themwith the SEC.The contents of our website are not part of th

62、is Form 10-K.The Role of EDA in the Electronics IndustryTechnology advances in the semiconductor industry have steadily increased the feature density,speed,power efficiency and functional capacity of semiconductors(also referred to as integratedcircuits,ICs or chips).1 Since the early 1960s,steadily

63、 decreasing feature widths(the widths of the wires imprinted onthe chip that form the transistors)and other developments have enabled IC manufacturers tofollow Moores law,approximately doubling every two years the number of transistors that canbe placed on a chip.As a result,state-of-the-art ICs now

64、 hold over one hundred milliontransistors and have feature widths of 90 nanometers(billionths of a meter),going to 65nanometers and below.Microprocessors operating at more than 4 gigahertz,a speed unheard of only a few years ago,are readily available today.Chips have become more power efficient to a

65、ddress demand for smaller and more powerfulhandheld devices such as cell phones,digital cameras,music players and personal digitalassistants.Increasingly,single SoCs can handle functions formerly performed by multiple ICs attached to aprinted circuit board.Combined,these advances in semiconductor te

66、chnology have driven development of lower cost,higher performance computers,wireless communications networks,hand held devices,Internet routersand a wealth of other electronic devices.Each advance,however,has introduced new challenges for allparticipants in semiconductor production,from designers an

67、d manufacturers to equipmentmanufacturers and EDA software suppliers,such as Synopsys.The IC Design ProcessEDA software is central to the IC design process,enabling designers to design complexsemiconductors by using a high-level,abstract description of the function of the chip.EDA software isused to

68、 automatically translate this description into successively more detailed forms,and to verify ateach stage in the design process that the chips design is sound and that the chip when manufacturedwill function as originally intended.In simplified form,the IC design process consists of system design,r

69、egister transfer level design,logic design,functional verification,physical design and physical verification.System Design.In system design,the designer describes the chips desired functions in very basicterms using a specialized high-level computer language,typically C+or System C.This phase yields

70、 arelatively high-level behavioral model of the chip.Register Transfer Level(RTL)Design.RTL design is the process of capturing the intended designfunctionality created at the system level using a specialized high-level computer language,typicallyVerilog or VHDL.This is the stage where the functional

71、ity of the final design is captured in enoughdetail to begin simulation and verification and determine that the final product will function asexpected in the verification phase.Logic Design.Logic design,or synthesis,programs convert the RTL code into a logical diagramof the chip,and produce a data f

72、ile known as a net list describing the various groups of transistors,orgates,to be built on the chip.Related programs insert the additional circuitry into the design that willbe needed to test the chip after manufacture.In a growing number of designs,designers areincreasingly performing design plann

73、ing in which the designer determines the location of the majorfunctional blocks on the SoC prior to logic synthesis.Functional Verification.At the RTL and gate level of IC design,the designer uses functionalverification tools such as RTL simulators and testbench automation and other verification too

74、ls tosimulate large sets of inputs that a given IC design might confront in a real-life operation.By runningthese extensive tests,the designer can verify that the design will function as intended.2Physical Design.In the physical design stage,the designer plans the physical location of all of thetran

75、sistors and each of the wires connecting them with place and route products.The designer firstdetermines the location on the chip die for each block of the chip,as well as the location for eachtransistor within each block,a process known as placement.In many designs,placement is performedin conjunct

76、ion with logic synthesis,a process known as physical synthesis.After placement thedesigner adds the connections between the transistors,a process known as routing.The output ofplace and route programs is one or more data files that can be read by physical verification or maskdata preparation program

77、s.Physical Verification.Before sending the chip design files to a manufacturer for fabrication,thedesigner must perform a series of further verification steps,checking to make sure that the final designcomplies with the specific requirements of the fabrication facility that will manufacture the chip

78、.Thedesigner may need to add features to the design to ensure that the chip can be manufacturedsuccessfully.The completion of this final phase is called tapeout.In actual chip design,each of these steps has a number of additional elements,and designers oftenundertake the various design and verificat

79、ion steps in a different order than described above,andrepeat one or more steps(particularly functional and physical verification)multiple times.Further,several of the steps,especially logic design and physical design,are becoming more integrated witheach other.If at any stage of the process the des

80、igner determines the chip design will not perform asintended,the designer must go back one or more steps and correct the problem,then continue throughsubsequent steps.Recreating a chips logic design,performing simulation over again,and repeatingother steps all take time.Each such iteration adds sign

81、ificant costs and makes it more difficult for thedesigner to meet time-to-market goals.Current Issues Facing IC DesignersAs chip technology continues to advance,our customers are seeking to maximize the quality ofresults of their IC design efforts,while minimizing the costs of achieving these result

82、s and shorteningthe time needed to launch the manufactured IC,as follows:Quality of Results.Customers are concerned about differentiating their chips from theircompetitors in a number of areas,including size or area,speed,functionality,powerconsumption and performance.The designer must balance each

83、issue against the others,makingkey tradeoff decisionsoften through multiple iterationsto reach a final design.As chipsbecome more complex and manufacturing geometries shrink,this balancing of factors becomesdisproportionately more difficult,and requires designers to successfully address technical is

84、sues,including:Timing closure:achieving consistency between the speed of the chip at the logic designphase and the speed of the chip at the physical design phase;Signal integrity:ensuring chip performance is not affected by unintended electrical effects,like cross-talk and other forms of interferenc

85、e,that occur as the wires on a chip get morenarrow and closer together;Power management:reducing the chips power consumption,an important objective for chipsto be used in battery-operated devices,particularly in the case of laptop computers and cellphones where both longer battery life and lower pow

86、er drain in standby mode is critical;Design for test:embedding circuits in the design that allow the chip,once manufactured,tobe tested rapidly and at a reasonable cost;Verification:verifying that the chip will perform as intended,which has become the singlemost time-consuming and resource intensive

87、 aspect of overall design;3 Manufacturability:faithfully translating the design produced by EDA tools into amanufacturable pattern of wires and transistors on the chip has become significantly moredifficult as a result of decreasing feature widths and increasing feature density;and Yield:ensuring th

88、at an acceptable number of good chips per wafer can be manufacturedsuccessfully.Cost of Results.Customers are continually seeking to constrain their costs,including costs ofdesign,masks,equipment,facilities and support,all of which typically increase as chips becomemore complex.The higher the cost,t

89、he higher the expected volume of chips the customer mustsell to make a given chip project profitable.Faced with increasing costs,our customers continueto focus intensely on controlling their research and development and manufacturing costs,including their EDA software costs and maximizing their yiel

90、d in manufacture.As a result,manyof our customers have begun consolidating suppliers to improve their purchasing terms and,more importantly,to gain the benefits of better integrated products.Time to Results.Finally,customers are seeking to improve the predictability of their productionschedule.Econo

91、mic pressures,competition and continuing innovation continue to shorten thelife cycle of electronic products.Accordingly,time-to-market is critical to a products commercialsuccess.The design time for a products IC components is a major determining factor of thatproducts time-to-market.Accordingly,ou

92、r customers require EDA products that can address thechallenges described above while reducing overall design time.StrategyWe provide products and services that help our customers design leading-edge ICs whilemaximizing achievement of their quality of results,cost of results and time to results goal

93、s.Historically,customers have purchased individual point tools to complete one or more tasks orsets of tasks in the design process,dealing internally with moving from one design environment or dataset to the next,while integrating various productsor even developing design toolsthemselves wherenecess

94、ary.However,with the increasing complexity of IC design,cost pressures and ever smallermarket windows,customers require broader solutions with greater performance from fewer vendors atlower costs.To meet this need,we have combined our individual productsmany of which lead their respectivecategoriesi

95、nto platforms,or collections of products that are integrated through the use of commoninterfaces,data sets and other technologies,to deliver a comprehensive,faster and more reliable designflow.In fiscal 2003,we released our Galaxy Design and Discovery Verification platforms,whichtogether provide com

96、plete implementation and verification solutions to our customers.In fiscal 2004,we delivered the Galaxy 2004 platform,providing full,cross-platform correlation in area,timing,power,signal integrity and test,as well as significant speed and capacity improvement.We also deliveredsubstantial improvemen

97、ts to the capabilities,speed,capacity and accuracy of our Discovery Verificationplatform.To help our customers better manage time,cost and risk,we have also continued to invest inpre-designed,pre-verified and reusable intellectual property blocks our customers can use rather thanbuild internally.The

98、se blocks include our DesignWare Foundation Library of reusable,basic chipelements which can be pulled into designs during logic synthesis,our DesignWare Verification Libraryof reusable chip function models to accelerate simulation and verification,and our DesignWare Coresthat implement many of the

99、most important industry standards for digital and analog connectivity,including USB and PCI Express.We also provide professional services to assist our customers withtheir most difficult design challenges.4Finally,recognizing the challenges of manufacturing at feature widths smaller than the wavelen

100、gthof light,and envisioning the benefits of taking manufacturing and yield issues into account during thedesign process,we have also continued to invest in our portfolio of Design for Manufacturing tools andtechnologies.OrganizationWe operate in a single segment and are currently organized into four

101、 primary groups:Implementation,Verification,Silicon Engineering and Solutions.Implementation Group:develops and markets the products included in the Galaxy DesignPlatform and related products.Verification Group:develops and markets the products included in the Discovery VerificationPlatform and rela

102、ted products.Silicon Engineering Group:focuses on our Design for Manufacturing initiatives and analog/mixed-signal design and verification products.Solutions Group:develops and markets our DesignWare portfolio of pre-designed IP solutionsfor chip designers and provides turnkey IC design and on-site

103、design assistance,among otherservices.Our other groups include Finance,Human Resources and Facilities,Marketing,Worldwide Salesand Worldwide Application Services.Products and ServicesOur products and services focus on the principal needs of semiconductor designers and,at abusiness level,are divided

104、into our Implementation,Verification,Silicon Engineering and Solutionsgroups described above.We provide financial information regarding our products and services underPart II,Item 7.Managements Discussion and Analysis of Financial Condition and Results of OperationsResults of OperationsRevenueProduc

105、t Groups,incorporated by reference here.Implementation GroupGalaxy Design Platform.Our Galaxy Design Platform includes our logic synthesis,physicalsynthesis,physical design,timing analysis,signal integrity analysis and physical verification products,aswell as certain analog and mixed-signal tools,in

106、cluding:Design Compiler logic synthesis product,used by a broad range of IC design companies tooptimize their designs for performance and area.With our Galaxy 2004 platform release,ourDesign Compiler product is up to three times faster than last years release,has up to 25%moredesign capacity,and now

107、 supports System Verilog,an emerging hardware design language.Physical Compiler physical synthesis product,which unites logic synthesis and placementfunctionality and addresses critical timing problems encountered in designing advanced ICs andSoCs.In fiscal 2004,we significantly improved the Physica

108、l Compiler products run time andcapacity.Module Compiler data path design product,which allows designers to reuse their datapathstructures to obtain the best implementation for their designs.Power Compiler power management product,which helps designers manage and verify powerconsumption at different

109、 stages of the design process.The 2004 version of our Power Compilerproduct is up to ten times faster than the previous version.5 DFT Compiler design testing product,which inserts functional and test logic required to enableefficient,high-coverage testing of the chip after manufacture.JupiterXT desi

110、gn planning or floorplanning product,that allows designers to quickly partitiontheir chip design into functional blocks that can be separately optimized for logic and physicaldesign.The 2004 version of our JupiterXT product has two times the capacity,and creates adetailed floorplan three times faste

111、r,than the previous version.Apollo basic physical design product used for the placement and routing of a chip.Astro advanced physical design system,which enables optimization,placement and routingwhile concurrently accounting for physical effects.Our fiscal 2004 release of the Astro tool runsup to t

112、wo times faster and has up to a 40%increase in capacity.PrimeTime/PrimeTime SI timing analysis products that measure and analyze the speed at whicha design will operate when it is fabricated.The PrimeTime SI tool analyzes the effect ofcross-talk and noise on timing,an increasingly important issue at

113、 chip geometries below 180nanometers.The 2004 version of our PrimeTime tool runs up to three times faster and has up tothree times the capacity as the prior version.Tetra Max test pattern generation product family which automatically generates high-quality testvectors to improve the design process.S

114、tar-RCXT extraction solution for analyzing IC layout data and determining key electricalcharacteristics of a chip,such as capacitance and resistance.Hercules physical verification product family,which performs hierarchical design-rule checking,electrical rule checking,and layout versus schematic ver

115、ification.During fiscal 2004,we delivereda faster version of the Hercules tool with higher multi-CPU scalability and broader foundrysupport.Milkyway Database,a common design data repository which enables better interoperabilityamong implementation and analysis tools.Storing design data in this singl

116、e database with rapidread/write access can reduce data translation times between tools and inconsistentinterpretations of diverse data.Interfaces to our open Milkyway database have been madeavailable to our customers and other EDA vendors to reduce integration costs for our customersand advance tool

117、 interoperability in the industry.The Galaxy Design Platform provides our customers a single,integrated IC design solution basedon leading individual products and incorporating common libraries and consistent timing,delaycalculation and constraints throughout the design process.The platform uses our

118、 open Milkywaydatabase and allows designers the flexibility to integrate internally developed and third-party tools.Withthis advanced functionality,common foundation and flexibility,our Galaxy Design Platform helpsreduce design times,decrease integration costs and minimize the risks inherent in adva

119、nced,complexIC designs.During fiscal 2004,we released the Galaxy 2004 platform,the latest version of the GalaxyDesign Platform,which delivers significantly improved quality of results,time to results and cost ofresults through greater correlation among the platforms individual products in addressing

120、 area,timing,power,signal integrity and test issues.We also introduced our Galaxy Power solution in fiscal 2004,offering designers the ability to improve the power efficiency of their ICs.6Verification GroupDiscovery Verification Platform.Our Discovery Verification Platform includes our verification

121、 andsimulation products.The increasing size and complexity of todays ICs and SoCs have vastly increasedthe time and effort required to verify chip designs,with verification estimated to consume 60%to 70%of total design time.As a result,reducing verification risk(i.e.minimizing the possibility of fin

122、dingdesign bugs when the ICs are delivered from the foundry)has become increasingly important tocustomers.To manage and reduce this verification risk,our Discovery platform combines our simulationand verification products and design-for-verification methodologies,and provides a consistent controlenv

123、ironment to significantly improve the speed,breadth and accuracy of our customers verificationefforts.Our Discovery Verification Platform includes the following principal products:VCS functional verification product,the engine of the Discovery Verification Platform andoften used in simulation farms

124、consisting of hundreds of computers.The VCS productincludes technologies that support model development,testbench creation,coverage feedbackand debugging techniques.Our fiscal 2004 release of the VCS product expands support of ourVera product,making testbench automation native to VCS,and helping pos

125、t a two to fivetimes improvement in runtime.System Studio system level design product focused on system-level algorithm and architecturedesign and analysis,as well as the interaction between software and hardware and permitsdesigners to model various architectural alternatives for their chips at a s

126、ystem level.Vera testbench generator,which automates the creation of testbenches,custom models thatprovide simulation inputs and respond to simulated outputs from the design during verification.Automating this process significantly improves verification quality.The 2004 release of the Veraproduct is

127、 up to 10 times faster than its predecessor and is also available native to the VCSproduct,providing increased productivity benefits.LEDA design rule checker,which enhances a designers ability to check a design to ensure itcan be for synthesized,simulated,tested and reused.Formality formal verificat

128、ion solution,which compares two versions of a design to determine ifthey are equivalent.The use of formal verification reduces the need to perform functionalverification,which is substantially more time-consuming,thus potentially saving a significantamount of time in the overall design process.Magel

129、lan hybrid formal verification product,which combines functional and formal verificationtechnologies to allow engineers to find deep,corner-case design defects during verification.NanoSim simulation and analysis product for analog and mixed signal verification,which offerscircuit simulation,timing a

130、nd power analysis in a single solution.The NanoSim product is a keycomponent of our Discovery AMS verification solution.HSPICE circuit simulator,which offers high-accuracy,transistor-level circuit simulation,therebyenabling designers to better predict the timing,power consumption and functionality o

131、f theirdesigns.During fiscal 2004,we announced enhancements to the HSPICE tool resulting insignificant improvements in performance and support for high-frequency and RF IC designs.Verification IP reusable IP that are designed to test specific functions and adherence to industryprotocols in an IC des

132、ign,which we believe is becoming increasingly important to more quicklyachieving verification sign-off.In fiscal 2004,we delivered the Discovery AMS solution,a subset of our verification technologiesoptimized to perform verification on analog and mixed signal designs.7Silicon Engineering GroupOur Si

133、licon Engineering Group develops and markets our products and initiatives relating todesign for manufacturing and analog/mixed signal IC design and verification.Design for Manufacturing.We offer a variety of products and technologies used at the intersectionof IC design and manufacturing which addre

134、ss a number of issues,principally the need to preciselymodel structures in small geometry ICs and the problems encountered when using photolithographytechniques to manufacture ICs containing feature dimensions smaller than the wavelength of lightduring production.These products are designed to enhan

135、ce yield,which is becoming increasinglychallenging as chip geometries continue to shrink.In addition to our Hercules product,described aboveunder the Galaxy platform our Design for Manufacturing initiatives include our:TCAD products,which precisely model individual structures or devices within an IC

136、 design tohelp ensure manufacturability at small geometries.We see TCAD tools as increasingly importantto help customers shorten the time to ramp up their production yields,and therefore reducetheir manufacturing costs.In this regard,we have made significant investments to expand ourTCAD offering,in

137、cluding our November 2004 acquisition of ISE Integrated Systems EngineeringAG,a privately-held Swiss company which offered various TCAD products,including threedimensional devise simulators.We also introduced our Taurus Process Atomistic product whichmodels processes at the atomic level for improved

138、 performance.Proteus OPC/InPhase optical proximity correction(OPC)products which embed and verifycorrective features in an IC design and masks to improve manufacturing results forsubwavelength feature width design.OPC changes mask geometries to compensate fordistortions caused by optical diffraction

139、 and resist process effects.During fiscal 2004,weannounced improvements to Proteus to provide near linear scalability.Phase Shift Masking Technologies consist of mask design techniques that use optical interferenceto improve depth-of-field and resolution in subwavelength photolithography for designs

140、 at 90nanometers and below.SiVL(Silicon versus Layout)layout verification product that verifies the layout of asubwavelength IC against the silicon it is intended to produce by reading in the layout andsimulating lithographic process effects,including optical,resist and etch effects.CATS mask data p

141、reparation product that takes a final IC design and fractures or breaksit into the physical features that will be included in the photomasks to be used in manufacturing.Virtual Stepper mask qualification product,which checks mask quality and analyzes printabilityof mask defects,helping to separate t

142、rue defects from nuisance defects.Analog and Mixed-Signal Tools.The Silicon Engineering Group also manages a number ofproducts described above and functionally included in our Galaxy and Discovery platforms that haveadvanced analog and mixed-signal design capabilities.These products include the Nano

143、Sim andHSPICE circuit simulators.In addition,this category includes our Cosmos product,which usesschematic-driven layout technology to place and route full-custom ICs,and our Circuit Exploreroptimization and analysis product for complex analog designs.Solutions GroupSynopsys Solutions Group includes

144、 our portfolio of IP products and components and ourProfessional Services Group.Intellectual Property Products.As IC designs continue to grow in size,reusing proven designblocks has become an increasingly important way to reduce overall design cost and cycle time.Because8verification accounts for su

145、ch a large proportion of total chip design time,reusing pre-designed andverified IP components can keep projects on schedule by ensuring that the designed in portions ofthe chip are pre-verified and thus will not contain errors.The ability to reuse such IP allows ICcompanies to focus their design te

146、ams on designing the chip features that will give its products acompetitive advantage.For these reasons,IC designers are consolidating their IP purchases from fewervendors who can provide a reliable,comprehensive portfolio of proven IP.Our IP products include:DesignWare Foundation Library is an exte

147、nsive library of basic chip elements(for example,addersand multipliers)which Design Compiler incorporates into the design during the logic synthesisstage.DesignWare Verification Library is our library of popular chip function models used during theverification process of chip design.DesignWare Cores

148、 are pre-designed and pre-verified digital and mixed-signal design blocks thatimplement many of the most important industry standards,including USB(1.1,2.0 andOn-The-Go),PCI(PCI,PCI-X and PCI Express),Ethernet and JPEG.During fiscal 2004,weannounced availability of DesignWare PCI Express physical la

149、yer IP core,enabling lower costICs.We also acquired Accelerant Networks,Inc.,giving our customers access to SERDEStechnology and additional connectivity IP solutions.Finally,during the year we acquired CascadeSemiconductor Solutions,Inc.,adding their root-and-switch port IP.As a result,we believe we

150、offer the industrys most complete PCI Express portfolio.Professional Services.We provide a comprehensive portfolio of consulting services covering allcritical phases of the SoC development process,as well as systems development in wireless andbroadband applications.We offer customers a variety of en

151、gagement models,from on-site designassistance to help our customers design,verify and/or test their chips and improve their designprocesses,to full turnkey development and training.Customer Service and Technical SupportA high level of customer service and support is critical to the adoption and succ

152、essful use of ourproducts.We provide technical support for our products through both field-and corporate-basedapplication engineering groups.Customers who purchase Technology Subscription Licenses(TSLs)receive software maintenance services bundled with their license fee.Customers who purchase termli

153、censes and perpetual licenses may purchase these services separately.See Product Sales and LicensingAgreements below.Software maintenance services include minor product enhancements we develop,bug fixes andaccess to our technical support center for primary support.Software maintenance also includes

154、accessvia electronic mail and the World Wide Web to SolvNet,our web-based support solution that letscustomers quickly seek answers to design questions or more insight into design problems.Our SolvNetsolution gives customers access to Synopsys complete design knowledge database using sophisticatedinf

155、ormation retrieval technology.Updated daily,it includes documentation,design tips and answers touser questions.Customers can also engage,for additional charges,our application consultants,ourworldwide network of product experts,for additional support needs.Customer Education ServicesWe offer trainin

156、g workshops designed to increase customer design productivity while using ourproducts.Workshops cover Synopsys products and methodologies used in our design and verificationflows,as well as specialized modules addressing system design,logic design,physical design,simulationand test.We offer regularl

157、y scheduled workshops in Mountain View,California;Austin,Texas;9Marlboro,Massachusetts;Reading,England;Rungis,France;Munich,Germany;Tokyo and Osaka,Japan;Seoul,Korea and other locations.We also schedule on-site workshops worldwide at ourcustomers facilities or other locations.Approximately 8,750 eng

158、ineers attended Synopsys workshopsduring fiscal 2004,compared to approximately 8,500 in fiscal 2003.Product WarrantiesWe generally warrant our products to be free from defects in media and to substantially conformto material specifications for a period of 90 days.We also typically provide our custom

159、ers limitedindemnities with respect to claims that their use of our design and verification software productsinfringe on United States patents,copyrights,trademarks or trade secrets.We have not experiencedmaterial warranty or indemnity claims to date,although we are currently defending some of ourcu

160、stomers against claims that their use of one of our products infringes a patent held by a Japaneseelectronics company.Support for Industry StandardsWe actively create and support standards that will help our customers increase productivity,improve interoperability of tools from different vendors,and

161、 solve design problems.Standards in theEDA industry can be established by formal accredited committees,by licensing made available to all,orthrough open source licensing.Synopsys products support many formal standards,including the most commonly used hardwaredescription languages,VHDL,Verilog HDL,Sy

162、stemVerilog and SystemC,as well as numerous industrystandard data formats for the exchange of data between our tools,other EDA vendors products andapplications customers develop internally.Synopsys is a board member and/or participant in the following major EDA standardsorganizations:Accellera,a not

163、-for-profit formal standards organization that drives language-based standards forsystems,semiconductor,and design tool companies;the interoperability committee of the EDA Consortium,which helps promote quality andinteroperability among EDA products from different vendors;the Institute of Electrical

164、 and Electronics Engineers(IEEE),a non-profit,technical professionalassociation and a leading developer of global industry standards;the Virtual Socket Interface Alliance(VSIA),an industry group that promotes standards thatfacilitate the integration and reuse of functional blocks of intellectual pro

165、perty;and the Open SystemC Initiative(OSCI),a non-profit organization that manages SystemC,alanguage developed by Synopsys and donated to OSCI,with representation from the systems,semiconductor,IP,embedded software and EDA industries.Synopsys TAP-inSM program provides interface standards to all comp

166、anies through an open sourcelicensing model.Synopsys manages changes and enhancements that come from the community oflicensees.Synopsys,other EDA companies and EDA customers use these standards to facilitateinteroperability of their tools.The standards offered through our TAP-in program include our

167、Libertyformat for library modeling,SDC for design constraints,SAIF for switching activity,our OpenVeralanguage for hardware verification,and Open MAST for electromechanical design modeling.Synopsyscommon database,Milkyway,is available for tool integration by EDA vendors through our MAP-inSMprogram.1

168、0Synopsys products are written mainly in the C and C+languages and utilize industry standardsfor graphical user interfaces.Our software runs under UNIX operating systems,such as Solaris andHP-UX,and under the RedHat Linux operating system.Synopsys products run on the most widelyused hardware platfor

169、ms,including those from Sun Microsystems,Hewlett-Packard,IBM and PCs thatare based upon Intel and AMD microprocessors.Sales,Distribution and BacklogWe market our products and services primarily through direct sales in the United States andprincipal foreign markets.We typically distribute our product

170、s and documentation to customerselectronically,but provide physical media(i.e.CD-ROMs)when requested by the customer.We employhighly skilled engineers and technically proficient sales persons in order to understand our customersneeds and explain and demonstrate the value of our products.We have sale

171、s/support centers throughout the United States,in addition to our Mountain View,California headquarters.Outside the United States,we have sales/support offices in Canada,Denmark,Finland,France,Germany,Hong Kong,India,Israel,Italy,Japan,the Netherlands,the PeoplesRepublic of China,Singapore,South Kor

172、ea,Sweden,Taiwan and the United Kingdom.Our foreignheadquarters is located in Dublin,Ireland.Our offices are further described under Part I,Item 2.Properties.In limited circumstances,we have used distributors to assist us in the sale of certain products inspecified markets.See Note 12 of our Notes t

173、o Consolidated Financial Statements in Part II,Item 8.Financial Statements and Supplementary Data for additional information about one of our formerdistributors.In fiscal 2004,2003 and 2002,foreign revenues represented 45%,43%and 35%,respectively,ofSynopsys total revenue.Additional information relat

174、ing to domestic and foreign operations iscontained in Note 10 of our Notes to Consolidated Financial Statements in Part II,Item 8.FinancialStatements and Supplementary Data.Information relating to risks associated with foreign operations aredescribed in Part II,Item 7.Managements Discussion and Anal

175、ysis of Financial Condition and Results ofOperationsFactors That May Affect Future ResultsStagnation of foreign economies,foreign exchangerate fluctuations or other international issues could adversely affect our performance.Historically,our orders and revenue have been lowest in our first quarter a

176、nd highest in our fourthquarter,with a material decline between the fourth quarter of one fiscal year and the first quarter ofthe next fiscal year,although the timing of major license renewals can alter this typical trend.However,as a result of the shift in our license model,as more fully described

177、in Part II,Item 7.ManagementsDiscussion and Analysis of Financial Condition and Results of OperationsResults of OperationsOrdersand Revenue Seasonality,we expect less revenue seasonality beginning in fiscal year 2005.Synopsys aggregate non-cancelable backlog was approximately$1.48 billion on October

178、 31,2004,representing an approximately 8%decrease from the end of fiscal 2003.Aggregate non-cancelablebacklog includes deferred revenue,operational backlog and financial backlog and excludes all itemsrelating to consulting services.Deferred revenue represents that portion of orders for softwareprodu

179、cts,license maintenance and other services which has been delivered and billed to the customerbut on which the revenue has not yet been earned.Operational backlog consists of orders for softwareproducts sold under perpetual or term licenses and TSLs with customer-requested ship dates withinthree mon

180、ths that have not been shipped.Financial backlog consists of future installments undertime-based licenses and maintenance which are not yet currently due and payable.Our aggregatebacklog at the end of fiscal 2004 including consulting was approximately$1.53 billion,approximately9%lower than at the en

181、d of fiscal 2003.We have not historically experienced material order cancellations.11See Item 13.Certain Relationships and Related Transactions for information concerning customersaccounting for more than 10%of our revenue during fiscal 2004.Research and DevelopmentOur future performance depends in

182、large part on our ability to further integrate our design andverification platforms,maintain and enhance our current products,develop new products,and meet anexpanding range of customer requirements.Research and development on existing and new products isprimarily conducted within each product group

183、.In addition,an Advanced Technology Group withinSynopsys Silicon Engineering Group explores new technologies and maintains strong researchrelationships outside Synopsys with both industry and academia.During fiscal 2004,2003 and 2002,research and development expenses,net of capitalized softwaredevel

184、opment costs,were$285.3 million,$285.9 million and$225.5 million,respectively.Synopsyscapitalized software development costs were approximately$2.7 million,$2.6 million and$1.6 million infiscal 2004,2003 and 2002,respectively.We expect sales and marketing expense to increase slightly infiscal 2005 a

185、s a result of increased headcount from acquisitions during fiscal 2004 and higher targetedincentive compensation.CompetitionThe EDA industry is highly competitive.We compete against other EDA vendors and against ourcustomers own design tools and internal design capabilities.In general,we compete pri

186、ncipally ontechnology leadership,product quality and features(including ease-of-use),time-to-results,post-salesupport,interoperability with our own and other vendors products,price and payment terms.Our competitors include companies that offer a broad range of products and services,such asCadence De

187、sign Systems,Inc.and Mentor Graphics Corporation,and companies that offer productsfocused on one or more discrete phases of the IC design process,such as Magma DesignAutomation,Inc.Since the recent semiconductor downturn,we have increasingly competed on the basisof payment terms and price.In certain

188、 situations,in order to win business we must offer substantialdiscounts on our products due to competitive factors.In other situations,we may lose potentialbusiness to a vendor offering a lower price.Product Sales and Licensing AgreementsWe typically license our software to customers under non-exclu

189、sive license agreements that transfertitle to the media only and restrict use of our software to specified purposes within specifiedgeographical areas.The majority of our licenses are network licenses that allow a number of individualusers to access the software on a defined network,including,in som

190、e cases,regional or globalnetworks.License fees depend on the type of license,product mix and number of copies of eachproduct licensed.Under certain circumstances,we provide our customers the right to exchange a portion of thesoftware they initially license for other specified Synopsys products.For

191、example,a customer may useour front-end design products for a portion of the license term and then exchange such products forback-end placement software for the remainder of the term in order to complete the customers ICdesign.This practice helps assure the customers access to the complete design fl

192、ow needed to designits product.The customers exchange of product for other existing products,when so provided underthe customer agreement,does not alter the timing of recognition of the license fees paid by thecustomer,which is governed by our revenue recognition policies.The ability to offer this r

193、ight tocustomers often gives us an advantage over competitors who offer a narrower range of products,because customers can obtain more of their design flow from a single vendor and because customersthen have an opportunity to try additional Synopsys tools before licensing them separately.At the same

194、12time,because in such cases the customer need not obtain a new license and pay an additional licensefee for the use of the additional products,the use of these arrangements could result in reducedrevenue compared to licensing the individual products separately without exchange rights.We currently o

195、ffer our software products under two license types:renewable TSLs and perpetuallicenses.For a full discussion of these licenses,see Part II,Item 7.Managements Discussion andAnalysis of Financial Condition and Results of OperationsCritical Accounting Policies and Results ofOperationsRevenue Backgroun

196、d.With respect to our DesignWare Core intellectual property products,we typically license thoseproducts to our customers under nonexclusive license agreements that provide usage rights for specificapplications.Fees under these licenses are typically charged on a per design basis plus,in some cases,r

197、oyalties.Finally,our professional services teams typically operate under consulting agreements with ourcustomers with statements of work specific to each project.Proprietary RightsSynopsys primarily relies upon a combination of copyright,patent,trademark and trade secret lawsand license and nondiscl

198、osure agreements to establish and protect its proprietary rights.Our sourcecode is protected both as a trade secret and as an unpublished copyrighted work.However,thirdparties may develop similar technology independently.In addition,effective copyright and trade secretprotection may be unavailable o

199、r limited in certain foreign countries.We currently hold United Statesand foreign patents on some of the technologies included in our products and will continue to pursueadditional patents in the future.Under our customer agreements and other license agreements,in many cases we offer toindemnify our

200、 customer if the licensed products infringe on a third partys intellectual property rights.As a result,we are from time to time subject to claims that our products infringe on these third partyrights.For example,we are currently defending some of our customers against claims that their use ofone of

201、our products infringes a patent held by a Japanese electronics company.We believe this claim iswithout merit and will continue to vigorously pursue this defense.EmployeesAs of October 31,2004,Synopsys had 4,378 full-time employees,with 2,940 based in NorthAmerica and 1,438 based outside of North Ame

202、rica.Our future financial results depend in part uponthe continued service of our key technical and senior management personnel and our continuing abilityto attract and retain highly qualified technical and managerial personnel.We participate in a dynamicindustry,with significant start-up activity,a

203、nd our headquarters is located in Silicon Valley,wherecompetition for the most highly skilled technical,sales and management employees is intense.Item 2.PropertiesUnited States FacilitiesSynopsys principal offices are located in four adjacent buildings in Mountain View,California,which together prov

204、ide approximately 400,000 square feet of available space.This space is leasedthrough February 2015.Within one half mile of these buildings,in Sunnyvale,California,Synopsysoccupies approximately 200,000 square feet of space in two adjacent buildings under lease throughApril 2007,and approximately 72,

205、000 square feet of space in a third building under lease throughApril 2007.We use these buildings for administrative,marketing,research and development,sales andsupport activities.13We own two buildings totaling approximately 230,000 square feet on approximately 43 acres ofland in Hillsboro,Oregon.O

206、nly one of these buildings is occupied,and is used for administrative,marketing,research and development and support activities.In addition,we lease approximately 80,000square feet of space in Marlboro,Massachusetts for sales and support,research and development andcustomer education activities.This

207、 facility is leased through January 2009.Synopsys owns a third building in Sunnyvale,California with approximately 120,000 square feet,which is leased to a third party through February 2009.Synopsys also owns 34 acres of undevelopedland in San Jose,California and 13 acres of undeveloped land in Marl

208、boro,Massachusetts.Synopsys currently leases 32 other offices throughout the United States,primarily for sales andsupport.International FacilitiesSynopsys leases approximately 45,000 square feet in Dublin,Ireland for its foreign headquartersand for research and development purposes.This space is lea

209、sed through April 2026.In addition,Synopsys leases foreign sales and service offices in Canada,Denmark,Finland,France,Germany,HongKong,India,Israel,Italy,Japan,the Netherlands,the Peoples Republic of China,Singapore,SouthKorea,Sweden,Taiwan and the United Kingdom.We also lease research and developme

210、nt facilities inArmenia,Canada,France,Germany,India,the Netherlands,the Peoples Republic of China,SouthKorea,Taiwan and the United Kingdom.As a result of acquisitions,we have assumed leases in a number of foreign and domestic locations.Following each acquisition,where feasible,we consolidate the acq

211、uired companys employees andoperations into our existing local sites.In such cases,we generally seek to sublease the assumed spaceor negotiate with the landlord to terminate the underlying lease.We believe our properties are adequately maintained and suitable for their intended use and thatour facil

212、ities have adequate capacity for our current needs.Item 3.Legal ProceedingsOn August 25,2004,a class action complaint entitled Kanekal v.Synopsys,Inc.,et al.,No.C-04-3580,was filed in federal district court for the Northern District of California againstSynopsys and certain of our officers alleging

213、violations of the Exchange Act.The complaint purports tobe a class action lawsuit brought on behalf of persons who acquired Synopsys stock during the periodof December 3,2003 through August 18,2004.The complaint alleges that the individual defendantscaused Synopsys to make false and misleading state

214、ments about Synopsys business,forecasts,andfinancial performance,and that certain Synopsys officers or employees sold portions of their stockholdings while in the possession of adverse,non-public information.The complaint does not specify theamount of damages sought.In November 2004,the Court appoin

215、ted a lead plaintiff in the case.As aresult,Synopsys expects the plaintiff to file an amended complaint in January 2005.Discovery has notcommenced in the case and no trial date has been established.While management intends to defendagainst these federal securities claims vigorously,and Synopsys does

216、 not believe that this lawsuit willhave a material effect on Synopsys financial position,results of operations or cash flows,there can beno assurance as to the ultimate disposition of this lawsuit.After the end of fiscal 2004,and in connection with our December 1,2004 announcement that wehave signed

217、 agreements to acquire Nassda Corporation(Nassda)and to settle all outstanding litigationbetween the two companies,a class action complaint entitled Robert Israel v.Nassda Corporation,et.al.,No.4705695,was filed in the Court of Chancery of the State of Delaware naming Nassda,itsdirectors and Synopsy

218、s as defendants.The complaint purports to be a class action lawsuit brought onbehalf of shareholders of Nassda,other than the defendant directors and their affiliates,who allegedly14would be injured or threatened with injury if the proposed acquisition of Nassda by Synopsysproceeded forward on the t

219、erms announced.The purported class action seeks to enjoin the transaction,or alternatively,damages.The complaint does not specify the amount of damages sought.Synopsysbelieves the claims in this purported class action are without merit,and intends to defend against themvigorously.Item 4.Submission o

220、f Matters to a Vote of Security HoldersNo matters were submitted for a vote of security holders during the fourth quarter of fiscal 2004.Executive Officers of the RegistrantThe executive officers of Synopsys and their ages as of December 31,2004,were:NameAgePositionAart J.de Geus50Chief Executive Of

221、ficer and Chairman of the Board ofDirectorsChi-Foon Chan55President and Chief Operating OfficerSteven K.Shevick48Senior Vice President,Finance and Chief Financial OfficerVicki L.Andrews49Senior Vice President,Worldwide SalesRaul Camposano49Senior Vice President,Chief Technology Officer andGeneral Ma

222、nager,Silicon Engineering GroupJohn Chilton47Senior Vice President and General Manager,SolutionsGroupJanet S.Collinson48Senior Vice President,Human Resources and FacilitiesAntun Domic53Senior Vice President and General Manager,Implementation GroupManoj Gandhi44Senior Vice President and General Manag

223、er,VerificationGroupJay N.Greenberg57Senior Vice President,MarketingDeirdre Hanford42Senior Vice President,Worldwide Application ServicesRex S.Jackson44Vice President,General Counsel and Corporate SecretaryDr.Aart J.de Geus co-founded Synopsys and currently serves as Chairman of the Board ofDirector

224、s and Chief Executive Officer.Since the inception of Synopsys in December 1986,he has helda variety of positions,including Senior Vice President of Engineering and Senior Vice President ofMarketing.From 1986 to 1992,Dr.de Geus served as Chairman of the Board.He served as Presidentfrom 1992 to 1998.D

225、r.de Geus has served as Chief Executive Officer since January 1994 and has heldthe additional title of Chairman of the Board since February 1998.He has served as a Director since1986.From 1982 to 1986 Dr.de Geus was employed by General Electric Corporation,where he wasthe Manager of the Advanced Com

226、puter-Aided Engineering Group.Dr.de Geus holds an M.S.E.E.from the Swiss Federal Institute of Technology in Lausanne,Switzerland and a Ph.D.in electricalengineering from Southern Methodist University.Dr.Chi-Foon Chan joined Synopsys as Vice President of Application Engineering&Services inMay 1990.Si

227、nce April 1997 he has served as Chief Operating Officer and since February 1998 he has15held the additional title of President.Dr.Chan also became a Director of Synopsys in February 1998.From September 1996 to February 1998 he served as Executive Vice President,Office of the President.From February

228、1994 until April 1997 he served as Senior Vice President,Design Tools Group,andfrom October 1996 until April 1997 as Acting Senior Vice President,Design Re-Use Group.Inaddition,he has held the titles of Vice President,Engineering and General Manager,DesignWareOperations and Senior Vice President,Wor

229、ldwide Field Organization.From March 1987 to May 1990,Dr.Chan was employed by NEC Electronics,where his last position was General Manager,Microprocessor Division.From 1977 to 1987,Dr.Chan held a number of senior engineering positionsat Intel Corporation.Dr.Chan holds an M.S.and a Ph.D.in computer en

230、gineering from Case WesternReserve University.Steven K.Shevick joined Synopsys in July 1995 and currently serves as Senior Vice President,Finance and Chief Financial Officer.Mr.Shevick was appointed Senior Vice President and ChiefFinancial Officer in January 2003.From October 1999 to January 2003,he

231、 was Vice President,InvestorRelations and Legal,General Counsel and Corporate Secretary.From March 1998 to October 1999,hewas Vice President,Legal,General Counsel and Assistant Corporate Secretary.From July 1995 toMarch 1998 he served as Deputy General Counsel and Assistant Corporate Secretary.Mr.Sh

232、evickholds an A.B.from Harvard College and a J.D.from Georgetown University Law Center.Vicki L.Andrews joined Synopsys in May 1993 and currently serves as Senior Vice President,Worldwide Sales.Before holding that position,she served in a number of senior sales roles at Synopsys,including Vice Presid

233、ent,Global and Strategic Sales,Vice President,North America Sales and Director,Western United States Sales.She has more than 18 years of experience in the EDA industry.Ms.Andrews holds a B.S.in biology and chemistry from the University of Miami.Dr.Raul Camposano has served as Senior Vice President,C

234、hief Technology Officer and GeneralManager,Silicon Engineering Group since July 2004.Prior to that time,he was Senior Vice Presidentand Chief Technology Officer from September 2000 to July 2004,and Senior Vice President,GeneralManager of the Design Tools Group from 1997 through September 2000.Prior

235、to joining Synopsys in1994,he directed the Design Technology Institute at the German National Research Center forComputer Science(GMD)and was a professor in the Department of Computer Science at theUniversity of Paderborn,Germany.Between 1986 and 1991,Dr.Camposano worked at the IBM T.J.Watson Resear

236、ch Center.He was also a member of the research staff at the Computer ScienceResearch Laboratory at the University of Karlsruhe.Dr.Camposano received a B.S.E.E.degree in 1977and a diploma in electrical engineering in 1978 from the University of Chile and a Ph.D.in computerscience from the University

237、of Karlsruhe in 1981.John Chilton has served as Senior Vice President and General Manager of the Solutions Group ofSynopsys since August 2003.Prior to that time,he was Senior Vice President and General Manager ofthe IP and Design Services Business Unit from 2001 to August 2003.From 1997 to 2001,Mr.C

238、hiltonserved as Vice President and General Manager of the Design Reuse Business Unit.Mr.Chiltonreceived an M.S.E.E.from the University of Southern California and a B.S.E.E.from University ofCalifornia at Los Angeles.Janet S.Collinson has served as Senior Vice President,Human Resources and Facilities

239、 sinceAugust 2003.From September 1999 to August 2003 she was Vice President,Real Estate and Facilities.Prior to that time she served as Director of Facilities from January 1997 to September 1999.Ms.Collinson received a B.S.in Human Resources from California State University,Fresno.Dr.Antun Domic has

240、 served as Senior Vice President and General Manager of the ImplementationGroup since August 2003.Prior to that,Dr.Domic was Vice President and General Manager of theNanometer Analysis and Test Group from 1999 to August 2003.Dr.Domic joined Synopsys inApril 1997,having previously worked at Cadence D

241、esign Systems and Digital Equipment Corporation.16Dr.Domic has a B.S.in Mathematics and Electrical Engineering from the University of Chile inSantiago,Chile,and a Ph.D.in Mathematics from the Massachusetts Institute of Technology.Manoj Gandhi has served as Senior Vice President and General Manager,V

242、erification Group sinceAugust 2000.Prior to that he was Vice President and General Manager of the Verification Tools Groupfrom July 1999 to August 2000.Prior to that time,he was Vice President of Engineering fromDecember 1997 until July 1999.He holds a B.S.in Computer Science and Engineering from th

243、e IndianInstitute of Technology,Kharagpur and an M.S.in Computer Science from the University ofMassachusetts,Amherst.Jay N.Greenberg joined Synopsys in November 2004 as Senior Vice President,Marketing.FromMarch 2003 until joining Synopsys,Mr.Greenberg was President of Green Mountain Solutions,aconsu

244、lting firm that he also founded.From March 1999 to March 2003 Mr.Greenberg was employedby Taiwan Semiconductor Manufacturing Company,Ltd.(TSMC),where he held the positions of VicePresident of Business Development and Vice President of Strategic Marketing.Mr.Greenberg servedas Vice President and Seni

245、or Partner at Thomas Group,Inc.,a consulting firm,from 1987 through1998.Mr.Greenberg has also held executive,management and technical positions at Memorex,Amdahl and EDS.Mr.Greenberg holds a B.A.from the University of the Pacific in Stockton,California.Deirdre Hanford has served as Senior Vice Presi

246、dent of Worldwide Applications Services sinceDecember 2002.Prior to that time,she was Senior Vice President,Business and Market Developmentof Synopsys from September 1999 to December 2002.From October 1998 until September 1999,sheserved as Vice President,Sales for Professional Services and prior to

247、that as Vice President,CorporateApplications Engineering from April 1996 to September 1999.Ms.Hanford received a B.S.E.E.fromBrown University and an M.S.E.E.from University of California at Berkeley.Ms.Hanford sits on theAmerican Electronics Associations national board of directors.Rex S.Jackson joi

248、ned Synopsys in February 2003 as Vice President,General Counsel andCorporate Secretary.Prior to joining Synopsys,Mr.Jackson was an investment director with RedleafGroup,Inc.,an early stage venture capital firm,from April 2000 through December 2001,andPresident and CEO of Atlantes Services,Inc.,a Red

249、leaf portfolio company,from December 2001through January 2003.Prior to joining Redleaf,from August 1998 to April 2000,Mr.Jackson was VicePresident and General Counsel of AdForce,Inc.,a provider of ad management and delivery services onthe Internet.Prior to joining AdForce,Mr.Jackson served as Vice P

250、resident,Business Developmentand General Counsel of Read-Rite Corporation,a manufacturer of thin film recording heads for thedisk and tape drive industries from 1996 to 1998,and as Vice President and General Counsel from1992 to 1996.Mr.Jackson holds an A.B.degree from Duke University and a J.D.degre

251、e from StanfordUniversity.There are no family relationships among any Synopsys executive officers or directors.17PART IIItem 5.Market for Registrants Common Equity,Related Stockholder Matters and Issuer Purchases of EquitySecuritiesThe table below sets forth information regarding repurchases of Syno

252、psys common stock bySynopsys during the fiscal quarter ended October 31,2004.Maximum Dollar Value OfTotal Number Of SharesShares RemainingTotal Number OfPurchased As Part OfPurchasable Under TheSharesAverage PricePublicly AnnouncedPrograms As Of End OfPeriodPurchasedPaid Per ShareProgramsPeriodMonth

253、#1August 1,2004 throughSeptember 4,2004.3,727,345$15.40213,727,345$154,253,651Month#2September 5,2004through October 2,20043,215,00016.33663,215,000101,731,402Month#3October 3,2004 throughOctober 31,2004.1,554,81216.10251,554,81276,695,086Total.8,497,157$15.88388,497,157$76,695,086All shares were pu

254、rchased pursuant to a$500 million stock repurchase program originallyapproved by Synopsys Board of Directors in July 2001 and renewed in December 2002 andDecember 2003.Funds are available until expended or until the program is suspended by the ChiefFinancial Officer or the Board of Directors.Effecti

255、ve and announced on December 1,2004 the Boardof Directors renewed the stock repurchase program,authorizing up to$500 million in additional sharerepurchases,not including amounts expended prior to such date.The remaining information required by Item 5 is set forth in Note 14 of our Notes to Consolida

256、tedFinancial Statements in Part II,Item 8.Financial Statements and Supplementary Data,incorporated byreference here.Item 6.Selected Financial DataFinancial SummaryFiscal Year Ended October 31,(1)20042003200220012000(in thousands,except per share data)Revenue.$1,092,104$1,176,983$906,534$680,350$783,

257、778Income(loss)before income taxes andextraordinary items(2).91,592218,989(288,940)83,533145,938Provision(benefit)for income taxes.17,25569,265(88,947)26,73148,160Net income(loss).74,337149,724(199,993)56,80297,778Earnings(loss)per share(3):Basic.0.480.99(1.50)0.470.71Diluted.0.460.95(1.50)0.440.69W

258、orking capital.171,878434,247151,946254,962331,857Total assets.2,092,1872,307,3531,978,7141,128,9071,050,993Long-term debt.7,4437,2196,54773564Stockholders equity.1,265,0491,433,4101,113,481485,656682,829(1)Synopsys has a fiscal year that ends on the Saturday nearest October 31.Fiscal 2004,2003,2002

259、,and 2000were 52-week years while fiscal 2001 was a 53-week year.For presentation purposes,the consolidated financialstatements refer to the calendar month end.(2)Includes charges of$1.6 million,$19.8 million,$87.7 million,and$1.7 million for fiscal 2004,2003,2002,and2000,respectively,for in-process

260、 research and development.Fiscal 2002 includes merger-related and othercosts of$33.5 million and insurance premium costs of$335.8 million related to the Avant!merger.(3)Per share data for all periods presented have been adjusted to reflect Synopsys two-for-one stock splitcompleted on September 23,20

261、03.18Item 7.Managements Discussion and Analysis of Financial Condition and Results of OperationsOverviewThe following summary of our financial condition and results of operations is qualified in its entirety bythe more complete discussion contained in this Item 7 and by the risk factors set forth be

262、low under thecaption entitled Factors That May Affect Future Results.Synopsys is a world leader in EDA software for semiconductor design.We deliver technology-leading semiconductor design and verification software platforms and IC manufacturing softwareproducts to the global electronics market,enabl

263、ing the development and production of complex SoCs.We also provide IP and design services to simplify the design process and accelerate time-to-market forour customers.Fiscal 2004 Business EnvironmentWe generate substantially all of our revenue from the semiconductor and electronics industries.Our c

264、ustomers typically fund purchases of our software and services out of their research anddevelopment(R&D)budgets.As a result,our business is heavily influenced by our customers businessoutlook and willingness to invest in new,and increasingly complex,chip designs.Beginning in late calendar 2000,the s

265、emiconductor industry experienced its steepest and longestdownturn of the past 20 years.Semiconductor industry sales dropped approximately 46%from late2000 to early 2002 and then recovered slowly into 2003.Throughout this period,our customers tookmany steps to reduce their expenses,including constra

266、ining R&D expenditures,reducing the number ofdesign engineers they employed,cutting back on their design starts,purchasing from fewer suppliers,and requiring more favorable pricing,payment and license terms from those suppliers,as well aspursuing consolidation within their own industry.Further,durin

267、g this downturn,many semiconductordesign companies failed or were acquired and the pace of investment in new companies declined.The Semiconductor Industry Association reported semiconductor industry growth of approximately18%in 2003 and estimates growth in 2004 of approximately 29%.Historically,grow

268、th in semiconductorsales has been followed by growth in semiconductor R&D spending,which in turn has led to growth inEDA expenditures.This relationship is not precise,however,and in the past there has been a lag ofseveral quarters between an upturn in semiconductor industry sales and growth in EDA s

269、pending.Atthe beginning of fiscal 2004,we based our forecast for the year in part on our expectations that theforecasted continued recovery in semiconductor revenue and improving conditions in the U.S.economywould lead to significantly increased spending on EDA products by our customers.However,by t

270、heend of our third fiscal quarter,it became clear that EDA spending growth was not tracking the upturnin the semiconductor industry.We believe EDA spending has not tracked the industrys recovery for a number of reasons.First,in light of the severity of the 2000-2002 downturn,we believe customers int

271、ense focus on expensereduction persists,and that they now generally approach spending more conservatively.In addition,thesemiconductor industrys recovery has been driven primarily by the consumer electronics market,whereproduct price is a primary competitive factor,further increasing pressure on our

272、 customers to controlcosts,including by limiting their EDA spending.In addition to these broader trends,we believe our customers turned more cautious about theirown business outlook in mid-calendar 2004 due to a number of factors,including lack of visibility intotheir own future results,unexpected i

273、nventory buildup in the semiconductor supply chain and concernsabout the industrys growth prospects in 2005.As a result,we believe our customers became morereluctant to extend or increase their existing commitments to us and to agree to upfront payment termsfor multi-year licenses.These developments

274、 materially and adversely affected both our bookings andrevenue for fiscal year 2004.In particular,lower than expected upfront license bookings adversely19impacted our third quarter of fiscal 2004 results,since we recognize all revenue from upfront licensesin the quarter they are shipped.Lower than

275、expected time-based license bookings also adverselyaffected our results for the year and will adversely affect our future results,as a less-than-expectedamount was added to our backlog to be recognized in future periods.Following the third quarter of fiscal 2004,we re-evaluated customer demand for u

276、pfront licenses,which require customers to pay at least 75%of the license fee in the first year.Our customersincreased preference for conserving cash by paying for licenses over time has made upfront paymentterms a significantly more difficult negotiating issue.Accordingly,effective in the fourth qu

277、arter offiscal 2004,we shifted our target license mix to consist almost entirely of time-based licenses.For thefourth quarter of fiscal year 2004,upfront licenses constituted approximately 7%of license orders,compared to an average of approximately 24%since our original introduction of time-based li

278、censes inAugust 2000.This shift negatively impacted revenue,earnings and cash flow from operations for thequarter as many orders which previously would have generated revenue,and in many cases cash,upfront instead were booked as TBLs,contributing primarily to backlog for future quarters.Our results

279、in the third quarter and the license mix shift in the fourth quarter resulted in lowerrevenue,earnings and cash flow from operations in fiscal 2004 compared to fiscal 2003.In addition,due to our further license mix transition we expect revenue,earnings and cash flow from operations forthe first thre

280、e quarters of fiscal 2005 under the new model to be below the comparable quarters underthe old,higher upfront model in fiscal 2004.However,we believe making this transition meets ourcustomers needs while enabling us to better preserve the value of our technology and enhance thepredictability of our

281、business.We continue to believe that,over the long-term,any growth in EDA spending will continue todepend on growth in semiconductor R&D spending and on continued growth in the overallsemiconductor market.The Semiconductor Industry Association has forecasted semiconductor revenuesto be flat in 2005

282、and to grow modestly in 2006.Accordingly,and with our continuing license modelshift and our expectation of a relatively low level of major customer license renewals in fiscal 2005based on scheduled renewal dates,we expect our revenue,earnings and cash flow from operations forfiscal 2005 to be below

283、fiscal 2004.Synopsys is under no obligation(and expressly disclaims any such obligation)to update or alterany of the information contained in this Overview,whether as a result of new information,futureevents or otherwise.Fiscal 2004 Product DevelopmentsDuring fiscal 2004,we announced or introduced a

284、 number of enhancements to our products,including:Delivery of our Galaxy 2004 platform,a major enhancement to our original Galaxy DesignPlatform,offering substantial improvements in speed,capacity,quality of results and processtechnology support,and representing two years of work integrating product

285、s acquired in ouracquisition of Avant!Corporation with Synopsys core products.Release of our Discovery AMS solution,a subset of our verification technologies optimized forverification of analog and mixed-signal designs.Enhancements to our PrimeTime timing analysis product,increasing speed and capaci

286、ty by up tothree times compared to the prior version.Delivery of our Galaxy Power solution,offering designers the ability to improve the powerefficiency of their ICs.20 Enhancements to our HSPICE circuit simulator,providing up to 20 times better performanceand supporting high-frequency and RF IC des

287、igns.Improvements to our Proteus OPC product,providing near linear scalability when usingindustry-leading processors.Availability of DesignWare PCI Express physical layer IP core,enabling lower cost IP.Fiscal 2004 Financial Performance Summary Orders were$956 million versus$1,368 million in fiscal 2

288、003,reflecting the trends anddevelopments discussed above in Fiscal 2004 Business Environment and the timing of a majorcontract renewal which was expected to be completed in fiscal 2004,but was not completed untilthe first quarter of fiscal 2005.Our book-to-bill ratio in fiscal 2004 and fiscal 2003

289、wasapproximately 0.9 and 1.2,respectively.Revenue was$1,092 million,down 7%from fiscal 2003,due primarily to a lower level of ordersthan expected in the first three quarters of fiscal 2004,the shift in license mix during the fourthquarter to an almost completely ratable model and a decrease in maint

290、enance revenue.Time-based revenue increased 7%from fiscal 2003 to$663 million,primarily reflectingrecognition of revenue on increased time-based orders in fiscal 2003.Upfront license revenuedeclined 28%from$298 million to$216 million,due primarily to a lower-than-expected level ofupfront license ord

291、ers in the third quarter and to the license model shift effective in the fourthquarter.For the year,we derived approximately 25%of our software revenue from upfront licenses and75%from time-based licenses,versus approximately 33%and 67%,respectively,during fiscal2003.The percentage of software reven

292、ue from upfront licenses was 29%in the first half of thefiscal year and 20%in the second half of the fiscal year,reflecting lower-than-expected upfrontlicense bookings in the third quarter and the shift from upfront licenses to time-based licenses inthe fourth quarter,each of which translated into a

293、 reduction in the revenue from upfront licenseorders.Reflecting this shift,during the fourth quarter,approximately 90%of our revenue wasderived from backlog attributable to prior period time-based license bookings.Maintenance revenue declined by 23%from$220 million in fiscal 2003 to$170 million,prim

294、arilyreflecting the lower-than-expected level of upfront license orders,which led to a lower level ofnew maintenance orders,the shift of some upfront licenses to TSLs(under which maintenance isincluded with the license fee and therefore is not reported separately),and non-renewal ofmaintenance by ce

295、rtain customers compared to fiscal 2003.Professional service and other revenue,at$43 million,increased slightly from$41 million forfiscal 2003,primarily as a result of customers continued use of outside consultants to augmenttheir internal staff and to assist in implementing their advanced IC design

296、s.Net income was$74 million compared to$150 million in the fiscal 2003,primarily due to lowerrevenue and other income,an increase in cost of services revenues due to increased fieldsupport headcount and higher amortization of intangible assets from acquisitions.Cash provided by operations for fiscal

297、 2004 was$264 million compared to$392 million for fiscal2003,driven primarily by lower orders and reported revenues compared to fiscal 2003,cashdisbursements for foreign income taxes,higher general and administrative expenses andworkforce realignment expenses.We repurchased 16.9 million shares of ou

298、r common stock in fiscal 2004 for approximately$423 million.In December 2004,after the end of the fiscal year,our Board renewed the stock21buyback program,restoring the authorization to repurchase up to$500 million of our commonstock.Fiscal 2004 AcquisitionsIn fiscal 2004,we acquired(i)Accelerant Ne

299、tworks,Inc.(Accelerant)to enhance our standards-based IP solutions;(ii)Cascade Semiconductors,Inc.(Cascade),to augment our IP portfolio of PCIExpress products;and(iii)the technology assets of Analog Design Automation,Inc.(ADA)to expandour analog and mixed-signal offerings.In addition,in fiscal 2004

300、we completed one additionalacquisition and two additional asset acquisition transactions we do not consider material for financialstatement purposes.After the fiscal year end,we completed the acquisition of ISE Integrated SystemsEngineering AG(ISE),broadening our TCAD product line and announced the

301、proposed acquisition ofNassda Corporation,which would settle our outstanding litigation and enhance our circuit simulationofferings.Critical Accounting PoliciesWe base the discussion and analysis of our financial condition and results of operations upon ouraudited consolidated financial statements,w

302、hich we prepare in accordance with accounting principlesgenerally accepted in the United States of America.In preparing these financial statements,we mustmake estimates and judgments that affect the reported amounts of assets,liabilities,revenues andexpenses and related disclosure of contingent asse

303、ts and liabilities.On an on-going basis,we evaluateour estimates based on historical experience and various other assumptions we believe are reasonableunder the circumstances.Our actual results may differ from these estimates.The accounting policies that most frequently require us to make estimates

304、and judgments,andtherefore are critical to understanding our results of operations,are:Revenue recognition;Valuation of intangible assets and goodwill;Income taxes;and Allowance for doubtful accounts.Revenue Recognition.We have designed and implemented revenue recognition policies inaccordance with

305、Statement of Position(SOP)97-2,Software Revenue Recognition,as amended by SOP98-9,Modification of SOP 97-2,Software Revenue Recognition,With Respect to Certain Transactions.With respect to software sales,during fiscal 2004,we utilized three license types:Technology Subscription Licenses(TSLs)are for

306、 a finite term,on average approximately threeyears,and generally provide the customer limited rights to receive,or to exchange certainquantities of licensed software for,unspecified future technology.Maintenance is bundled forthe term of the license and not purchased separately.Term Licenses are als

307、o for a finite term,usually three years,but do not provide the customer anyrights to receive,or to exchange licensed software for,unspecified future technology.Customerspurchase maintenance separately for the first year and may renew annually for the balance ofthe term.The annual maintenance fee is

308、typically calculated as a percentage of the net licensefee.Perpetual Licenses,which continue as long as the customer renews maintenance,plus anadditional 20 years.Perpetual licenses do not provide the customer any rights to receive,or toexchange licensed software for,unspecified future technology.Cu

309、stomers purchase maintenanceseparately for the first year and may renew annually.The annual maintenance fee for purchases22under$2 million is typically calculated as a percentage of the list price of the licensed software.For purchases over$2 million,the annual maintenance fee is typically calculate

310、d as a percentageof the net license fee.We sometimes refer to TSLs and term licenses,either individually or collectively,as renewablelicenses because the customer must purchase an extension or a new license in order to continue usingthe software after the specified term of the contract expires.In a

311、renewal transaction,we may eitherreplace the pre-existing arrangement with an entirely new arrangement or maintain two agreements.Where we replace the existing agreement,we often supersede the original arrangement and thereafterdeliver software and recognize revenue based upon the type of license re

312、flected in the new agreement.Where we maintain two agreements,we recognize revenue on the new incremental agreement basedupon the new license type purchased.If we grant extended payment terms(as discussed below),werecognize license revenue as payments become due and payable.Customers occasionally co

313、nvert their existing TSLs to perpetual licenses,paying an incremental feewhich we recognize upon contract signing in accordance with AICPA Technical Practice Aid(TPA)5100.73,assuming all other revenue recognition criteria have been met.In some situations,the contractconverting the TSL to a perpetual

314、 license is modified to such an extent that a new arrangement exists.The changes to the contract may include increases or decreases in the total technology under license,changes in payment terms,changes in license terms and other pertinent factors.In these situations,weaccount for all of the arrange

315、ment fee as a new sale and recognize revenue when all other revenuerecognition criteria have been met.We report revenue in three categories:upfront license,time-based license and service.Upfront license revenue includes:Perpetual licenses.We recognize the perpetual license fee in full if,upon shipme

316、nt of thesoftware,payment terms require the customer to pay at least 75%of the perpetual license feewithin one year from shipment and all other revenue recognition criteria are met.For perpetuallicenses in which less than 75%of the license fee is payable within one year from shipment,werecognize the

317、 revenue as customer installments become due and payable.Upfront term licenses.We recognize term license fees in full if,upon shipment of the software,payment terms require the customer to pay at least 75%of the term license fee within one yearfrom shipment and all other revenue recognition criteria

318、 are met.Time-Based License(TBL)revenue includes:Technology Subscription Licenses.We typically recognize revenue from TSL license fees(whichinclude bundled maintenance)ratably over the term of the license period.However,where weoffer extended payment terms(i.e.,where less than 75%of the TSL license

319、fees are due withinone year from shipment),we recognize revenue from TSLs in an amount equal to the lesser ofthe ratable portion of the entire fee or customer installments as they become due and payable.Term Licenses with Extended Payment Terms.For term licenses where less than 75%of the termlicense

320、 fee is due within one year from shipment,we recognize revenue as customer installmentsbecome due and payable.Service revenue includes:Maintenance Fees Associated with Perpetual and Term Licenses.We generally recognize revenuefrom maintenance associated with perpetual and term licenses ratably over

321、the maintenanceterm.Professional Service Fees.We generally recognize revenue from consulting and training servicesas services are performed and accepted.23We allocate revenue on software transactions(referred to as arrangements)involving multipleelements to each element based on the respective fair

322、values of the elements.Our determination of fairvalue of each element is based on vendor-specific objective evidence(VSOE).We limit our assessmentof VSOE for each element to the price charged when the same element is sold separately.We have analyzed all of the elements included in our multiple-eleme

323、nt arrangements anddetermined that we have sufficient VSOE to allocate revenue to the maintenance components of ourperpetual and term license products and to consulting.Accordingly,assuming all other revenuerecognition criteria are met,we recognize revenue from perpetual and term licenses upon deliv

324、eryusing the residual method in accordance with SOP 98-9,recognize revenue from maintenance ratablyover the maintenance term and recognize consulting revenues as the related services are performed.We make significant judgments related to revenue recognition.Specifically,in connection with eachtransa

325、ction involving our products,we must evaluate whether(i)persuasive evidence of an arrangementexists,(ii)delivery has occurred,(iii)our fee is fixed or determinable,and(iv)collectibility is probable.We apply these criteria as discussed below.Persuasive Evidence of an Arrangement Exists.Our customary

326、practice is to have a writtencontract,signed by both the customer and us,or a purchase order from those customers thathave previously negotiated a standard end-user license arrangement or volume purchaseagreement with us prior to recognizing revenue on an arrangement.Delivery Has Occurred.We deliver

327、 software to our customers physically or electronically.Forphysical deliveries,our standard transfer terms are typically FOB shipping point.For electronicdeliveries,delivery occurs when we provide the customer access codes or keys that allow thecustomer to take immediate possession of software.The F

328、ee is Fixed or Determinable.Our determination that an arrangement fee is fixed ordeterminable depends principally on the arrangements payment terms.Our standard paymentterms require 75%or more of the arrangement fee to be paid within one year.Where theseterms apply,we regard the fee as fixed or dete

329、rminable,and we recognize revenue upon delivery(assuming all other revenue recognition criteria are met).If the payment terms do not meet thisstandard,which we refer to as extended payment terms,we do not consider the fee to be fixedor determinable and generally recognize revenue when customer insta

330、llments are due andpayable.In the case of a TSL,we recognize revenue ratably even if the fee is fixed ordeterminable,due to application of other revenue accounting guidelines relating to maintenanceservices and arrangements that include rights to unspecified future technology.Collectibility is Proba

331、ble.To recognize revenue,we must judge collectibility of the arrangementfees,which we do on a customer-by-customer basis pursuant to our credit review policy.Wetypically sell to customers with whom we have a history of successful collection.For a newcustomer,we evaluate the customers financial posit

332、ion and ability to pay and typically assign acredit limit based on that review.We increase the credit limit only after we have established asuccessful collection history with the customer.If we determine at any time that collectibility isnot probable based upon our credit review process or the custo

333、mers payment history,werecognize revenue on a cash-collected basis.Valuation of Intangible Assets and Goodwill.We evaluate our intangible assets for indications ofimpairment whenever events or changes in circumstances indicate that the carrying value may not berecoverable.Intangible assets consist of purchased technology,contract rights intangibles,customer-installed base/relationships,trademarks