Session 35Implantable and Wearable Biomedical Devices.pdf

1、Session 35 Overview:Implantable and Wearable Biomedical Devices IMAGERS,MEDICAL,AND DISPLAYS SUBCOMMITTEEBiomedical devices for implantable and wearable applications integrate various functionalities,including wireless power and data transfer,recording and stimulation,security,and imaging.The papers

2、 in this session continue to explore different modalities for wireless power and data transfer(e.g.,inductive,ultrasound,magnetoelectric),neural stimulation(e.g.,electrical,ultrasound),and biomedical imaging(e.g.,photoacoustic,bioimpedance spectroscopy).The first half of the session focuses on ASICs

3、 designed for security,ultrasound stimulation and imaging,and bioimpedance spectroscopy,while the second half highlights ASICs with wireless power/data capabilities.Session Chair:Mehdi Kiani Pennsylvania State University University Park,PA Session Co-Chair:Bo Zhao Zhejiang University Hangzhou,China

4、566 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARABLE BIOMEDICAL DEVICES/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE1:55 PM 35.2 A Spatial-Domain Compressive-Sensing Photoacoustic Imager with Matrix-Multiplying SAR ADC Huan-Cheng Liao,Rice Univer

5、sity,Houston,TX In Paper 35.2,Rice University introduces a low-power photoacoustic receiver for wearable imagers that employs a multichannel analog spatial-domain compressive sensing.The ASIC provides 4 reduction in output data rate and number of ADCs.2:20 PM 35.3 A 30MHz Wideband 92.7dB SNR 99.6%Ac

6、curacy Bioimpedance Spectroscopy IC Using Time-to-Digital Demodulation with Co-Prime Delay Locked Sampling Jiayang Li,University College London,London,United Kingdom In Paper 35.3,University College London presents a 30MHz wideband bioimpedance spectroscopy IC with time-to-digital demodulation.The I

7、C achieves an equivalent sampling rate of 21.6GHz with a 240MHz clock utilizing a co-prime delay-locked sampling method.At 30MHz,the IC has an overall 92.7dB SNR,99.6%accuracy with 0.39%magnitude error and 0.57 phase error,and 3.18mW power consumption.1:30 PM 35.1 A Single-Inductor-Based High-Voltag

8、e Transmit Beamformer for Wearable Ultrasound Devices Achieving 88%fCV2 Power Reduction Peng Guo,Delft University of Technology,Delft,The Netherlands In Paper 35.1,Delft University of Technology presents an efficient high-voltage transmit beamformer ASIC for wearable ultrasound stimulation.It drives

9、 a 32-element array with 36V phase-delayed pulses using a single inductor that resonates with the capacitance of the transducer elements,reducing the energy loss by 88.2%.ISSCC 2025/February 19,2025/1:30 PM567 DIGEST OF TECHNICAL PAPERS 353:35 PM 35.5 A Wireless Adiabatic Stimulator System with Curr

10、ent-Mode Power Reception and Stimulus Current Regulation Achieving Precise Charge Delivery and Electrode Scalability for Miniaturized Electroceuticals Yechan Park,KAIST,Daejeon,Korea In Paper 35.5,Korea Advanced Institute of Science&Technology shows a wireless adiabatic neural stimulation system emp

11、loying current-mode power reception through inductive coupling.The ASIC achieves precise charge delivery,a power conversion efficiency of 72.5%,and a stimulation efficiency factor of 6.02.4:00 PM 35.6 An Enhanced-Frequency-Splitting-Based Wireless Power and Data Transfer System Achieving 60.2%End-to

12、-End Efficiency and 1Mb/s Data Rate with a Sub-cm RX Coil for Miniaturized Implants Yechan Park,KAIST,Daejeon,Korea In Paper 35.6,Korea Advanced Institute of Science&Technology presents an enhanced-frequency-splitting-based wireless power and data transfer system for small implants employing link-lo

13、ad isolation.The wireless system achieves an end-to-end power efficiency of 60.2%and a downlink data rate of 1Mb/s using a sub-cm receiver coil.4:25 PM 35.7 A Programming-Free Three-Dimensional Resonant Current-Mode Wireless Receiver with Real-Time Link-Adaptivity and a 0.904cm3 Receiver Coil for Im

14、plantable Systems Jong-Hun Kim,Pohang University of Science and Technology,Pohang,Korea In Paper 35.7,Pohang University of Science and Technology presents an automated resonant current-mode ASIC for wireless power transfer with a three-dimensional receiver coil.The power-management ASIC achieves up

15、to 75.1%power conversion efficiency,while the three-dimensional receiver coil provides robustness against misalignments.4:50 PM 35.8 DustNet:A Network of Time-Division Multiplexed Ultrasonic Implants with 16-Level ASK Backscatter Modulation Changuk Lee,University of California,Berkeley,CA In Paper 3

16、5.8,University of California at Berkeley describes DustNet,an ultrasound-based transceiver capable of supporting up to 8 implants through time-division multiplexing with 16-level amplitude-shift-keying backscatter modulation.The wireless system operates at 90mm depth with a maximum data rate of 400k

17、b/s at 2MHz carrier frequency(50kb/s uplink per implant).2:45 PM 35.4 A Miniature Biomedical Implant Secured by Two-Factor Authentication with Emergency Access Wei Wang,Rice University,Houston,TX In Paper 35.4,Rice University introduces a mechanical-input-based two-factor authentication(2FA)protocol

18、 in a miniature implant powered wirelessly by a magnetoelectric transducer.It achieves a 2FA success rate of 98.27%and demonstrates continuous uplink with on-off keying modulation at up to 110kb/s.568 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARAB

19、LE BIOMEDICAL DEVICES/35.1979-8-3315-4101-9/25/$31.00 2025 IEEE35.1 A Single-Inductor-Based High-Voltage Transmit Beamformer for Wearable Ultrasound Devices Achieving 88%fCV2 Power Reduction Peng Guo,Zu-Yao Chang,Michiel A.P.Pertijs,Tiago L.Costa Delft University of Technology,Delft,The Netherlands

20、Compared to its implant-based electrical counterpart,ultrasonic vagus nerve stimulation alters neuronal activity through mechanical ultrasound waves,emerging as a promising non-invasive therapy for managing drug-resistant epilepsy 1.To enable immediate intervention following seizure detection,a low-

21、power,compact wearable device is sought to send continuous low-or medium-intensity focused ultrasound waves to targeted areas,such as the cervical vagus nerve(Fig.35.1.1).The integration of transducer arrays and ASICs supporting high-voltage(HV)pulsing enables on-chip electrical transmit(TX)beamform

22、ing with sufficient acoustic pressure at the focal spot and allows for the miniaturization of such devices,but it also poses challenges in power consumption.A conventional class-D pulser(Fig.35.1.1)exhibits excessive fCV2 power loss due to the charging and discharging of the transducers capacitance.

23、A resonant pulser,in contrast,uses an inductor to recycle the associated energy,ideally reducing fCV2 loss to 0.However,previous works 2,3 would require multiple off-chip inductors to implement TX beamforming,making them unsuitable for our application.Moreover,the use of body-diode conduction for en

24、ergy recycling significantly reduces power efficiency 2.This paper presents a resonant TX beamformer architecture that employs a single inductor to pulse groups of transducer elements at different phases,thus enabling the required efficient continuous-wave TX beamforming.To reduce hardware overhead,

25、continuous-wave TX beamforming often employs a Fresnel delay profile(Fig.35.1.1)combined with phase delay quantization,i.e.,wrapping the quantized phase delay between 0 and 2 4.A 32-element transducer array is divided into 8 phase delay groups(PD1-8)based on the distance of the elements to the desir

26、ed focal spot,each corresponding to one of 8 quantized phase delays(Fig.35.1.2).To generate the rising and falling transitions,the inductor(L0)is cyclically connected to the phase delay groups and their antiphase group(e.g.,PD1,5,PD2,6,etc.)when the inductor current drops to zero(L18).Between the tr

27、ansitions,the transducers are connected to ground or to the supply(S18),both to replenish the energy lost during the resonating period and to provide the energy for ultrasound transmission.To prevent overvoltage,a non-uniform quantization scheme is employed so that each group contains an equal numbe

28、r of elements and thus a roughly identical capacitance(Fig.35.1.3).Compared to the 8-phase uniform quantization in 4,which would result in unequal group sizes,this scheme only slightly degrades the focal spot pressure,making it well-suited for our application.This architecture allows energy to reson

29、ate between the transducers capacitance and the inductor,eliminating the need for body-diode conduction and thus improving both power efficiency and immunity to latch-up.A clock frequency of 8 the transducer center frequency(f0)is employed.The durations of the transitions(L18)need to be precisely tu

30、ned to achieve zero-current switching,thereby maximizing power efficiency and compensating for PVT variations.This is accomplished via a PWM-based resonating time control loop,incorporating a fully differential slope-based zero-current detector(ZCD)followed by eight 6b up/down counters and a DLL-bas

31、ed PWM generator(Fig.35.1.3).To detect the slope of the differential voltage(VL0)across the inductor,the slope-based ZCD employs a pair of capacitors(CDP/N),which are connected to ground via switches(SP/N)during each rising/falling period(e.g.,L1).After this period,the switches are turned off for a

32、short interval(),during which a voltage(VCP)proportional to the slope of the differential voltage across the inductor(VL0)is built at the input of a comparator,followed by a polarity decision.The decision results,corresponding to 8 rising and falling durations,are cyclically fed to 8 dedicated up/do

33、wn counters,allowing for separate tuning of each duration.The outputs of these 8 counters are concatenated and input to an edge combiner,which accordingly selects two edges out of 128 phases generated from a DLL and combines them into a PWM signal(PWMSYS)in a center-aligned fashion,i.e.,the center o

34、f the PWM signal is always aligned with the falling edge of the clock signal(CKSYS).This scheme aims to align all rising/falling transitions approximately at their mid-transition points(Fig.35.1.2),thus reducing delay errors resulting from PVT variations.The PWM signal and clock signal are XOR-encod

35、ed into a single signal(CKPWM),similar to Manchester encoding,and then distributed across the entire chip via a global distribution network before being decoded locally(e.g.,PWMCHn,CKCHn),thereby minimizing skew and phase delay errors between different pulser channels.This feedback loop continuously

36、 adjusts the resonating period towards its optimized value(Fig.35.1.3),which can be further read out and preloaded as the initial value of the counters,facilitating quick loop settling.Back-to-back isolating high-voltage(HV)switches are used to switch the inductor among the 32 transducer elements(Fi

37、g.35.1.3).As these switches experience steep voltage changes due to the rapid switching across a wide voltage range,a robust bootstrap gate driver is implemented to ensure safe operation(Fig.35.1.4),employing a bootstrap capacitor(CBST)to generate a floating supply of approximately 5V,a latch-based

38、level shifter,and a modified C-element 5.CBST provides the charge to turn on the back-to-back switches,while being replenished to 5V via MRP when the transducer is discharged to ground.The floating supplies(VBST,VMID)can vary rapidly,while the latch cannot immediately charge and discharge two level-

39、shifting capacitors(CLSP/N)in response,causing the latch outputs to bear either both low or both high states.In contrast with a conventional SR latch 6,the modified C-element retains its output during these states,thereby ensuring reliable switching.The ASIC is fabricated in a 180nm BCD process,inco

40、rporating 32 pulser channels and the feedback control(Fig.35.1.7).Figure 35.1.4 shows measured steady-state outputs of the ASIC,equipped with a 1.1H off-chip inductor,operating at 2MHz and a 36V HV supply.All pulser channels are loaded with 120pF capacitors.The deviation from the ideal phase delays

41、is 2mm)than pure optical approchesOptical Wave ExcitationReveals optical contrasts based on chemical compositionsExcite different molecules with selected optical wavelengthsHardware Requirements-Wireless communication-Limited data rate-Low power&low noiseRef:6Ref:89+.AFEAFEADCADC.Fs=FNyquistMVM SAR

42、ADC4xAFE16xSpatial Domain CompressionOutput N channels(N FNyquistFIFODigital BFRef:7?High output data rateHigh output channel countAccess to raw data of full arrayAx=BA:Sensing Matrixx:Input ArrayB:ADC OutputNxMMx1Nx1Power-and area-consuming MACMultiple channels share one ADCSupport general sensing

43、matrix?+?PRBSInputADCFs FNyquistPower-consuming mixer&integratorOne or more ADC per input channelSupport general sensing matrix+?InputCS SAR ADC.LNA+?Fully passive MACOne ADC per input channelRestricted choice of sensing matrixRef:11Ref:12PRBSInputADCLNARef:13?PRBSFigure 35.2.3:MVM SAR ADC schematic

44、.Figure 35.2.4:Measured AFE and ADC performance.105Frequency(Hz)106107HD3 HD5Fs=20.41MHzFin=1.7MHzSFDR=67.96dBSNDR=57.51dB213 FFT Points-100-80-60-40-200Magnitude(dBFS)ADC Spectrum-60-50-40-30-20-1000102030405060SNR/SNDR(dB)SNDRSNRDR=61.2dB-0.4-0.20565860Input Amplitude(dBFS)ADC Dynamic RangeIRN(nVr

45、ms/Hz)1234567 833.544.55Frequency(MHz)AFE Input-Referred NoiseFrequency(Hz)30354045AFE Gain(dB)105106107PGA Gain Setting18dB12dB8.52dB6dBAFE AC ResponseAnalog Domain Matrix-Vector MultiplicationSampling phaseConversion phase?sCLKC.SAR Logic10bVrefpVrefnVcmADC OutputVcmCDACV116,pVrefpVrefnVcmVcmCLKC?

46、sV116,nXA=1 or 0 or-1.AAAAAAAA.Control 1st ADC2nd ADC3rd ADC4th ADCVLPF,1.VLPF,2VLPF,15VLPF,16AAAAAAAADifferential outputs from LPFsComparatorVcm64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64CVcmVrefpVcmVrefnCC2C8C16C32C64C128C256C512C4CMultiplication(ADC sampling phase)SAR Logic ControlAAAAAAAAAAA

47、AAAAAVLPF,1VLPF,2VLPF,3VLPF,4VLPF,5VLPF,6VLPF,7VLPF,8VLPF,9VLPF,10VLPF,11VLPF,12VLPF,13VLPF,14VLPF,15VLPF,16Accumulation(ADC conversion phase)Figure 35.2.5:Linearity measurement results for the MVM SAR ADC;PA imaging setup and reconstructed image using uncompressed data.Figure 35.2.6:Reconstructed i

48、mages with different compression ratios using FISTA and INR-based method;reconstructed image using software emulated compressed data;comparison with the state-of-the-art ultrasound/PA RX chip.*Includes LDO*SNR instead of SNDR*Includes ultrasound TXThis WorkISSCC17 7VLSI19 6ISSCC22 9JSSC24 8JSSC21 17

49、Technology65nm28nm180nm180nm BCD180nm BCD180nmImaging ModalityPhotoacousticPhotoacousticUltrasoundUltrasoundUltrasoundUltrasoundTransducerPZTCMUTPZTPZTPZTPMUTTransducer Array Size4x44x44x48x916x166x6Center Frequency3.5MHz5MHz5MHz6MHz9MHz5MHzNyquist Sampling Rate20.41M20MHz30MHz24MHz40MHz20MHzInput-R

50、eferred Noise3.5nV/?HzN/AN/AN/A0.7pA/?Hz19.3nV/?HzPeak SNDR57.51dB58.9dB49.8dB52.3dB*54dB59.4dBRX Area/CH0.118 mm2*0.065 mm20.023 mm20.0265 mm20.048 mm20.0625 mm2*RX Power/CH5.83mW22.7mW1.54mW0.98mW1.83mW0.95mWOutput Data Reduction TechniqueCompressive SensingDigital BeamformingNoAnalog BeamformingA

51、nalog BeamformingNox(mm)16/3x compression w/FISTA4x compression16/3x compressionFISTAINR-based51015222630340240 2 4y(mm)z(mm)y(mm)x(mm)51015222630340240 2 4y(mm)x(mm)z(mm)y(mm)51015222630340240 2 4y(mm)x(mm)z(mm)y(mm)51015222630340240 2 4y(mm)z(mm)y(mm)4x compression w/FISTA8x compression51015222630

52、340240 2 4y(mm)x(mm)z(mm)y(mm)Software Emulated Compression 51015222630340240 2 4y(mm)x(mm)z(mm)y(mm)51015222630340240 2 4y(mm)x(mm)z(mm)y(mm)51015222630340240 2 4y(mm)x(mm)z(mm)y(mm)PhantomhairagarosePCBASICTransducer ArrayWater TankWaterLaserPlastic wrapPhantomLaserChip&TransducerPhantomPower supp

53、lyLight PathExample of single channel waveformAmplitude(mV)94m0-94m051015202530Time(?s)Laser start1st2nd3rd&4th5th3D View20 02405101522263034x(mm)z(mm)024y(mm)y(mm)Top viewSide view10Reconstructed Image from Uncompressed DataReceived Photoacoustic WaveformPhotoacoustic Imaging Testing SetupFixed?Wi

54、and Sweep InputNormalized ADC Output-1-0.500.512468Input Amplitude(mVpp)Mean R2=0.99998Minimum R2=0.9999333?Wi-0.319-0.3164MinMax+SD-SDMeanFixed Input and Sweep?Wi-16-80816?Wi-1-0.500.51Normalized ADC OutputOutput=?(Wi x Ij)=I x?Wi-14-0.682-0.68-0.678-0.676MaxMinMean+SD-SD8mVpp,R2=0.9999964mVpp,R2=0

55、.9999972mVpp,R2=0.9999981mVpp,R2=0.999991ConnectorHandler&Moving stageTransducer ArrayzxyxyzISSCC 2025/February 19,2025/1:55 PM571 DIGEST OF TECHNICAL PAPERS 35 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFi

56、gure 35.2.7:PA RX chip micrograph.8-ch AFEController2 ADCTest structure2 ADC8 LNA2 LDO8 PGA8 LPF2940?m1090?mRe f e re nce s:1 H.Hu,et al.,“A wearable cardiac ultrasound imager,”Nature,vol.613,no.7945,pp.667-675,Jan.2023.2 V.C.Protopappas,et al.,“An ultrasound wearable system for the monitoring and a

57、cceleration of fracture healing in long bones,”IEEE Trans.Biome d.Engine e ring,vol.52,no.9,pp.1597-1608,Sept.2005.3 D.Ryu,et al.,“Comprehensive pregnancy monitoring with a network of wireless,soft,and flexible sensors in high-and low-resource health settings,”Proc.Natl.Acad.Sci.U.S.A.,vol.118,no.20

58、,p.e2100466118,May 2021.4 L.V.Wang and S.Hu,“Photoacoustic Tomography:In Vivo Imaging from Organelles to Organs,”Scie nce,vol.335,no.6075,pp.1458-1462,Mar.2012.5 M.Xu and L.V.Wang,“Photoacoustic imaging in biomedicine,”Re vie w of Scie ntific Ins trume nts,vol.77,no.4,p.041101,Apr.2006.6 J.Li,et al.

59、,“A 1.54mW/Element 150m-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes,”Sy mp.VLSI Circuits,pp.C220-C221,June 2019.7 M.-C.Chen,et al.,“A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-

60、Sigma Beamformer in 28-nm UTBB FD-SOI,”IEEE JSSC,vol.52,no.11,pp.2843-2856,Nov.2017.8 P.Guo,et al.,“A 125 m-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D Transfontanelle Ultrasonography,”IEEE JSSC,vol.59,no.8,pp.2604-2617,Aug.2024.9 Y.Hopf,et al.,“A Pitc

61、h-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-Frame-Rate 3D Ultrasound Probes,”ISSCC,pp.494-495,Feb.2022.10 M.Soozande,et al.,“Imaging Scheme for 3-D High-Frame-Rate Intracardiac Echography:A Simulation Study,”IEEE Trans.Ultras onics,Fe rroe le ctric

62、s,and Fre que ncy Control,vol.69,no.10,pp.2862-2874,Oct.2022.11 J.Yoo,et al.,“A 100MHz-2GHz 12.5x sub-Nyquist rate receiver in 90nm CMOS,”IEEE RFIC,pp.31-34,June 2012.12 W.Guo,et al.,“A Fully Passive Compressive Sensing SAR ADC for Low-Power Wireless Sensors,”IEEE JSSC,vol.52,no.8,pp.2154-2167,Aug.2

63、017.13 M.Shoaran,et al.,“Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition,”IEEE TBioCAS,vol.8,no.6,pp.857-870,Apr.2014.14 A.Beck and M.Teboulle,“A Fast Iterative Shrinkage-Thresholding Algorithm for Linear Inverse Problems,”SIAM J.Imaging Sci.,vol.2,no.

64、1,pp.183-202,Jan.2009.15 V.Sitzmann,et al.,“Implicit Neural Representations with Periodic Activation Functions,”Advance s in Ne ural Inf ormation Proce s s ing Sy s te ms,pp.7462-7473,2020.16 S.M.Farrell,et al.,“CoIR:Compressive Implicit Radar,”IEEE Trans.Patte rn Analy s is and Machine Inte llige n

65、ce,2023.17 J.Lee,et al.,“A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System,”IEEE JSSC,vol.56,no.6,pp.1910-1923,June 2021.572 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARABLE BIOMEDICAL DEVICES/35.3979-

66、8-3315-4101-9/25/$31.00 2025 IEEE35.3 A 30MHz Wideband 92.7dB SNR 99.6%Accuracy Bioimpedance Spectroscopy IC Using Time-to-Digital Demodulation with Co-Prime Delay Locked Sampling Jiayang Li,Dai Jiang,Yu Wu,Andreas Demosthenous University College London,London,United Kingdom The permittivity and con

67、ductivity of bioimpedance in tissues are governed by,and dispersions,with biological features detectable in the tens of MHz range.Wideband spectroscopyis required in many applications including body fluid volume assessment 1,cancer diagnosis 2,anatomical characterization 3,and plant content estimati

68、on 4.However,state-of-the-art bioimpedance ICs are limited to frequencies up to 10MHz,which hampers biological research.For example,estimating starch content in cassavas requires wideband spectroscopy with frequencies up to 30MHz 4.In a wideband system using analog I-Q demodulation,accuracy is limit

69、ed by the large distortion from its multiplication process;a phase error of 4.32 at 10MHz was reported in 2.In a wideband system using digital I-Q demodulation,a phase error of 0.15%at 10MHz was reported in 5 but at the expense of a large power consumption(12.2mW for the amplifier and ADC alone)and

70、a mediocre SNR of 65dB.This paper presents a wideband(30MHz)bioimpedance spectroscopy IC achieving both high SNR(92.7dB)and high accuracy(99.6%)with low power consumption(3.18mW).The IC employs time-to-digital(T-D)demodulation and features:1)a co-prime delay-locked(CDL)sampling approach achieving an

71、 equivalent sampling rate of 21.6GHz with a 240MHz sampling clock;2)a delay-locked loop(DLL)architecture utilizing a compact phase comparator for high accuracy delay generation;3)optimized wideband design for the current generator and readout front end to further reduce power consumption.The IC has

72、0.39%magnitude error and 0.57 phase error at 30MHz bioimpedance spectroscopy measurements.Figure 35.3.1 shows the block diagram of the IC.It consists of(1)a sinusoidal current generator,(2)a readout front end,(3)a clock generator and(4)digital modules.By injecting a current into the bioimpedance loa

73、d,the induced voltage,Vm,can be measured.A resistor is connected in series with one of the recording electrodes for calibration.Based on the T-D demodulation principle in 6,dynamic comparators controlled by a known clock CLKcomp detect the crossing point between Vm and the known differential dc refe

74、rence voltages Vdc.The magnitude|Vm|and phase of the measured sinusoidal voltage is extracted by counting 3 periods of pulses,N0-2.Then the bioimpedance is calculated using the two equations shown in Fig.35.3.1.In all T-D demodulation methods,the ICs bandwidth and sensitivity depend heavily on the f

75、requency of the CLKcomp;tens of GHz are required for 30MHz bioimpedance spectroscopy.A normal GHz clock would significantly increase power consumption and design complexity.To overcome this,a CDL sampling approach is proposed,featuring a programmable pico-second-precision delay-locked clock generato

76、r for the dynamic comparators.As shown in Fig.35.3.2,the clock generator consists of two cascaded blocks,a 9-phase phase-locked loop(PLL)and a 10-phase DLL.The PLL generates a 9-phase 240MHz clock with a step delay of T/9 where T(4.167ns)is the period of the clock,and each phase is further delayed b

77、y the DLL at a step of T/10.Since 9 and 10 are co-prime numbers,the least significant delay(LSD)step is T/90(46.3ps or 21.6GHz).The total delay at the DLL output is ,where p 9 and q 10.The CDL sampling takes two steps as shown in the 30MHz example in Fig.35.3.2.First,for coarse comparison a 240MHz C

78、LKcomp is used,dividing the signal into coarse slots(8 slots for a 30MHz signal)where two slots contain the cross points.Second,for fine cross point detection CDL sampling in the two slots is used.By controlling p and q,the CDL CLKcomp delay changes each cycle by one LSD until it covers the entire s

79、lot with a 46.3ps temporal resolution,taking 3s(90 cycles).The total delay of the DLL is first initialized to T(4.167ns)in closed-loop operation before measurement,and then the DLL works as an open loop delay generator.To overcome the current mismatch in the charge pump(CP)and the dead zone of the p

80、hase-frequency-detector(PFD)in conventional DLLs,a DLL architecture is proposed for generating an accurate 4.167ns delay with 10 phases,as shown in Fig.35.3.2 and Fig.35.3.3.It has a phase comparator and a 10b resistive DAC(R-DAC)for defining the control voltage,Vctrl,for a voltage-controlled delay

81、chain(VCDC).The VCDC is a 20-cell delay chain,from which 10 phases are selected by a dynamic element matching(DEM)module to randomize accumulated phase errors from single delay cells.Dummy delay cells are also used to isolate input and output offset from phase comparison.The measured VCDC delay vers

82、us Vctrl is shown in Fig.35.3.3.A slope of 6.5ps/mV was measured around the target delay time,where a 10b R-DAC with 1.2V supply provides sufficient resolution.During closed-loop initialization,two pulses clipped from a 120MHz clock(there are 20 delay cells),divided from a PLL output,are used as the

83、 input of the VCDC.The delay is defined by the time difference between the first rising edge of CLKre f(input of delay cell 1)and CLKde lay(output of delay cell 20).The phase comparator has 3 D flip-flops(DFFs)and a few logic gates.After Re s e t,DFF1 is triggered by the first rising edge of CLKre f

84、 to release the reset pins of DFF2 and DFF3.The first arriving rising edge between CLKre f and CLKde lay sets output Q of either DFF2 or DFF3 to logic 1,which in turn resets the other DFF.The difference between Out1 and Out2 determines whether the input of the R-DAC decreases or increases by one LSB

85、.This procedure repeats until the rising edges CLKre f and CLKde lay align,indicating an 8.333ns delay(1/120MHz)is achieved and the initialization is completed.The dead zone or resolution of the phase comparator is determined by the transmission delay difference between the complementary outputs of

86、the DFF,Q andQ(a few ps),rather than the time required to switch on/off the CP in a conventional FPD(hundreds of ps).Within the dead zone,Out1 and Out2 are both either 0 or 1,depending on which one in Q andQ has a shorter transmission delay,as shown in Fig.35.3.3.The simulated dead zone was less tha

87、n 5ps,far smaller than 46.3ps temporal resolution.A long enough time is allocated to the initialization process and the averaged value determines the final value of the R-DAC in the last 32 comparisons for noise integration.An 8.337ns delay was measured after initialization,as shown in Fig.35.3.3,wi

88、th only 4ps offset compared with the target 8.333ns delay.The measurement was repeated 50 times to remove the impact of clock jitter.After initialization,the DLL operates in open-loop.The 240MHz clock,CLKDLL,is injected into one of the delay cells through the multiplexer(MUX)and the required delay i

89、s selected by another MUX,according to the values of p and q.The block diagram of the current generator and readout front end are shown in Fig.35.3.4.An optimized lookup table(LUT)with 24 oversampling rates and 77 unit steps is used for high efficacy and linear sinewave generation 7.The 720MHz clock

90、 is multiplied from the 9-phase 240MHz PLL to further reduce power.The trans-impedance(TI)filter after the current DAC exhibits high current efficiency and linearity since the transfer function only depends on passive components.A current feedback current driver is used due to its high efficiency an

91、d linearity 8.The current generator can deliver a current from 15.6 to 500A,with a frequency from 10kHz to 30MHz.It achieves a measured THD of 0.39%at 3MHz and 0.82%at 10MHz.An instrumentation amplifier(IA)and a programmable gain amplifier(PGA)are used to amplify the voltage,providing a gain from 30

92、V/V to 150V/V in 4 steps.Two dummy comparators with a complementary clock are used to compensate the kickback noise and reduce the value of load capacitors,which reduces power in the PGA.Resistors are connected in series before Vm and Vdc to balance the output impedance of the PGA and buffers for ac

93、curate measurements.The IC was fabricated in a 65nm CMOS process.High-frequency resistors from 10 to 1k were measured at 30MHz with pre-set current excitation level,Vdc voltage and PGA gain.A 3ms measurement window was allocated to single impedance data for sufficient DEM and noise integration.The m

94、easured resistance at dc are considered to be the theoretical values and were used in error calculations.An overall magnitude error of 0.39%and phase error of 0.57 was achieved after calibration,as shown in Fig.35.3.5.The accuracy decreases with increasing load resistance due to parasitic capacitanc

95、es.The SNR was calculated from the mean values and standard deviation in continuously measured 3s dataset(1000 data).Rrms is the corresponding standard deviation.An overall SNR of 92.7dB was obtained and the Rrms varies from 0.24 to 23.3m with different loads.A spectroscopy measurement with various

96、concentrations of cassava flour solutions is shown in Fig.35.3.5,showing high accuracy bioimpedance data.A comparison with prior work is presented in Fig.35.3.6.The chip micrograph is shown in Fig.35.3.7.It occupies an area of 1.6mm2.Figure 35.3.1:Simplified block diagram of the proposed wideband bi

97、oimpedance readout IC and principle of the T-D method.Figure 35.3.2:Principle of the proposed co-prime delay-locked sampling and the DLL architecture.Figure 35.3.3:Working principle of the DLL and phase comparator,and measured results of the delay versus Vctrl and the generated delay after calibrati

98、on.Figure 35.3.4:Detailed diagram of the current generator,readout front end and TI filter.Figure 35.3.5:Measured magnitude error,phase error,SNR and Rrms with different loads at 30MHz and impedance of various cassava flour concentration solutions at different frequencies.Figure 35.3.6:Comparison wi

99、th prior work.ISSCC 2025/February 19,2025/2:20 PM573 DIGEST OF TECHNICAL PAPERS 35 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 35.3.7:Chip micrograph and die size.Re f e re nce s:1 M.Y.Jaffrin and H.M

100、orel,“Body fluid volumes measurements by impedance:A review of bioimpedance spectroscopy(BIS)and bioimpedance analysis(BIA)methods,”Me dical Engine e ring&Phy s ics,vol.30,no.10,pp.1257-1269,Dec.2008.2 J.Lee,et al.,“A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate P

101、hase Compensation for Early Breast Cancer Detection,”IEEE JSSC,vol.56,no.3,pp.887-898,Mar.2021.3 A.Adler and A.Boyle,“Electrical Impedance Tomography:Tissue Properties to Image Measures,”IEEE Trans.Biome d.Engine e ring,vol.64,no.11,pp.2494-2504,Nov.2017.4 T.Odedeyi,et al.,“Estimation of starch cont

102、ent in cassava based on coefficient of reflection measurement,”Frontie rs in Food Scie nce and Te chnology,vol.2,Sep.2022.5 M.Takhti and K.Odame,“A Power Adaptive,1.22-pW/Hz,10-MHz Read-Out Front-End for Bio-Impedance Measurement,”IEEE TBioCAS vol.13,no.4,pp.725-734,Aug.2019.6 J.Li,et al.,“A 1.76 mW

103、,355-fps,Electrical Impedance Tomography System with a Simple Time-to-Digital Impedance Readout for Fast Neonatal Lung Imaging,”IEEE JSSC early access.7 S.-I.Cheon,et al.,“Optimal Parameter Design of DAC-Based Sinusoidal Signal Generators for Electrical Impedance Spectroscopy,”IEEE Trans.Ins trume n

104、tation and Me as ure me nt,vol.72,2023,Article no.2000711.8 J.Li,et al.,“An 89.3%Current Efficiency,Sub 0.1%THD Current Driver for Electrical Impedance Tomography,”IEEE TCAS-II,vol.70,no.10,pp.3742-3746,Oct.2023.9 S.Hong,et al.,“A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lu

105、ng Ventilation Monitoring System,”IEEE JSSC,vol.50,no.11,pp.2501-2512,Nov.2015.10 C.S.Park,et al.,“A 145.2dB-DR Baseline-Tracking Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring,”ISSCC,pp.346-347,Feb.2022.11 S.-I.Cheon,et al.,“A Two-Electrode Bio-Impedance

106、Readout IC with Complex-Domain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation,”ISSCC,pp.556-557,Feb.2024.574 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARABLE BIOMEDICAL DEVICES/35.4979-8-3315-4101-9/25/$31.00 2025 IEEE35.4

107、 A Miniature Biomedical Implant Secured by Two-Factor Authentication with Emergency Access Wei Wang*,Yumin Su*,Huan-Cheng Liao,Yiwei Zou,Tian Qiu,Kaiyuan Yang Rice University,Houston,TX *Equally Credited Authors(ECAs)The advancement of miniature implantable medical devices(IMDs)has made remarkable p

108、rogress toward creating minimally invasive and broadly accessible therapeutic and monitoring solutions for various complex health conditions 1,2.However,a critical challenge associated with this trend is ensuring the security of IMDs,which handle highly private data and life-critical therapies.This

109、challenge is greatly amplified by the increasing need for Internet connectivity to remotely access IMDs by patients and doctors.While the adoption of standard cryptography with pre-shared keys(PSKs)3 addresses many issues in the wireless channel,two major challenges specific to IMDs remain:1)in emer

110、gencies,the responders may not have access to the server storing the PSK and thus cannot program the implant;2)if the doctors account is compromised,e.g.,through phishing 4,and the attacker can therefore bypass all protections and hijack the implant using the doctors credentials.Recent studies have

111、explored solutions to these challenges(Fig.35.4.1).In 5,the programmer and the IMD authenticate each other using signatures extracted from the patients ECG in real-time.The prox imity assumption,that only a legitimate doctor can make physical contact with the patient to obtain ECG,enables PSK-less a

112、uthentication in emergencies.But this approach requires strong assumptions on the uniqueness and specificity of the chosen bio-signal across time and subjects,and can be broken by non-contact sensing of bio-signals(like ECG 6).In 7,a touch sensor is added to an IMD to achieve two-factor authenticati

113、on(2FA),a well-known technique for preventing password leaks.However,a touch sensor is too bulky for miniature implants.To tackle these challenges,we present utilizing intentional wireless power transfer(WPT)misalignment as a secure physical channel to achieve 2FA for an implant without extra sensor

114、s,and to grant emergency responders direct access without the server,under the proximity assumption.The custom mechanical design of the wearable hub ensures the external transceiver(TRX)coil and PCB laterally move to different locations as the user dials 0 and 1 on the disk,leading to distinguishabl

115、e rectifier voltage(Vrect)changes at the implant.Our prototype mm-scale implant system with a 180nm SoC features:1)an all-in-one magnetoelectric(ME)transducer for WPT with angular offset tolerance,bidirectional communication,and 2FA;2)a low-cost misalignment-based 2nd factor detection method,achievi

116、ng a 98.27%success rate among 10 volunteers;3)mechanical-input-enabled emergency mode(EMGC mode),allowing responders to access the implant without server;4)a fully integrated lightweight security engine based on DTLS-PSK protocol 8 over ME link(ME-DTLS).Here is the attacker model we consider in this

117、 work.First,we assume the IMD is trustworthy,and the only access is via the wireless channel.We also assume the PSK stored on the server cannot be compromised.The wearable hub is secure and trustworthy,as it executes a fixed routine with hardcoded logic.An attacker cannot operate the wearable hub wi

118、thout user approval but can set up a separate device to transmit or receive arbitrary data with full knowledge of the communication protocol.The attacker may be present at any communication link(Fig.35.4.1)and can eavesdrop,forge,or drop any data packet.Additionally,the attacker may steal the doctor

119、s password.The attackers goal is to secretly reprogram the implant or access private data without alerting the user or doctor.Thus,denial-of-service and battery drainage attacks through jamming the wireless channel are outside the scope of this work.To defend the described attacker,we developed the

120、ME-DTLS protocol(Fig.35.4.2).In standard mode,the implant first establishes a secure and authenticated channel with the server under a lightweight DTLS-PSK protocol.Since the wearable hub and the users phone serve solely as relays in standard mode,this secure channel inherently prevents attacks at t

121、hese links.After establishing the channel,the implant generates a random 8b pattern as the 2FA passcode,which is sent to the server to notify the user.This pattern does not need to remain secret because the attacker cannot operate the hub due to the proximity assumption.Once the users consent is ver

122、ified through the input pattern,the requested remote access is granted.In EMGC mode,a distance-bounded uplink is employed to compensate for the absence of PSK.The uplink is set to the lowest power level to transmit the unlock pattern in plaintext,ensuring only the trusted hub within 6cm of the impla

123、nt can receive it.The unlock pattern is designed to take over 10s to complete,preventing skimming attempts where an attacker gains brief proximity(e.g.,pretending to bump into the user)to complete the EMGC authentication.This scheme also protects against attackers exploiting EMGC mode when no emerge

124、ncy exists since an attacker-controlled hub cannot receive the uplink signal with sufficient SNR beyond the 6cm range.Once the implant verifies the pattern,application data can be exchanged through a secure and authenticated channel,as in standard mode.ME-DTLS messages are transmitted over the ME ph

125、ysical layer as shown in Fig.35.4.2.To reliably transmit ME-DTLS messages exceeding 500b,each message is divided into fragments and packaged in 128b ME frames.When one party receives a valid fragment with the correct message sequence number,fragment number,and CRC bits,it replies with an acknowledge

126、(ACK)frame.This process repeats until the entire message is sent.The ME-DTLS engine retrieves or dispatches frames using the communication module.It adopts a compact and highly stable PUF 9 based on 2T structures 10 to harvest process variations as the PSK,and a fully synthesizable TRNG 11 based on

127、edge-chasing ring oscillators 12 to produce true random numbers from transient noise.Both modules have been validated to function across the typical IMD temperature and voltage range while passing relevant NIST tests 13.We also implemented an ultra-compact 8b-datapath AES128 accelerator 14 that can

128、be reconfigured for encryption and decryption 15 and a basic SHA256 module.These primitives support the PSK-WITH-AES128-CBC-SHA256 cipher suite.The pattern detection module analyzes Vrect changes as the user moves the coil using the external hub.Once all 8 pattern bits are determined,the ME-DTLS eng

129、ine checks if this pattern matches the generated one.If not,a new pattern is generated,and the user can retry until a timeout occurs.After completing 2FA,application data for implant programming and sensor readout can proceed(such as stimulation programming and temperature sensing 16 in our prototyp

130、e).We use an inverter-based ring oscillator ADC working at 1 to 2.4V to digitize Vrect as the user moves the coil(Fig.35.4.3).To enhance detection accuracy across different users,we adopt a Vrect-slope-based method to reliably locate when the coil reaches the expected displacement for 0 or 1 input a

131、nd then sample the Vrect voltage at this point to decide 0 and 1.Therefore,the goal becomes locating the proper zero-crossing points of dVrect/dt.In the scenario where the implant travels away from the peak of the coils EM field,each pattern bit contains only one zero-crossing point,which the algori

132、thm can easily detect.In the second scenario,when the implant travels toward the peak field due to lateral or angular misalignment in the initial state,Vrect sees a peak on the moving path,resulting in three zero-crossing points on the dVrect/dt waveform.To differentiate slopes,we set a slope thresh

133、old and design the mechanical structure to slow down return motion with a directional damper,ensuring only the first slope exceeds the threshold and triggers detection in each pattern bit.Moreover,the moving distance of the coil is designed to be 2 the implants maximum lateral offset(1cm)to prevent

134、a monotonic Vrect increase during movement.Our system requires a robust ME data uplink.Prior works have employed the same frequency for power and communication 17,which is limited by the trade-off between Q-factor and bandwidth,resulting in a low data rate.Another approach leverages MEs higher-frequ

135、ency width mode resonance by sending two consecutive pulses with opposite phases to transmit OOK data at a higher data rate but with a worse BER 18.In this work,we also utilize width mode resonance but apply continuous OOK modulation to achieve a high data rate and low BER,effectively reducing authe

136、ntication latency.The output strength is adjustable by modifying carrier duty cycles and changing the number of active units in the output PA,ensuring reliable but distance-bounded communication.Our prototype implant(10.93.22.3mm3)integrates a 180nm CMOS ASIC.Figure 35.4.4 shows waveforms of 1st and

137、 2nd factor authentication and application data exchange in standard mode.ME-DTLS is enabled after a downlink command,transmitting 128b of uplink data at 55kb/s.Successful decoding of the input pattern in the 2nd factor authentication phase is verified,covering the 2 scenarios in Fig.35.4.3.Finally,

138、bidirectional application data exchange after 2FA is demonstrated with stimulation pattern programming and temperature sensor readout.Measurement of the pattern detection module confirms Vrect corresponding to 0 and 1 inputs is consistently distinguishable under various conditions(distance between T

139、X and implant:2,3,4cm,lateral offset:0,1cm,and angular rotation:0,45 degrees),proving the reliability of pattern detection(Fig.35.4.5).A total of 405 patterns were collected from 10 volunteers,covering a broad age range.Each volunteer entered various 8b 2FA patterns at different distances and offset

140、s.Our pattern detection achieves a 95%success rate in all cases,with an average 98.27%success rate.We observe that it takes 10 to 20s to input all 8b of the pattern.Overall,the 1st factor authentication consumes 21.5J and takes 0.36s to finish.Uplink BER was tested with various PA power and data rat

141、es at different distances.BER remains low at short distances but increases rapidly at longer ranges,which supports the distance-bound assumption for security.Figure 35.4.6 provides comparisons with state-of-the-art security 5,7,19 and wireless power and communication 17,18,20,21 schemes for IMDs.Fig

142、ure 35.4.7 illustrates the chip micrograph,the assembled ME implant,the in-vitro testing setup,and the prototype of the wearable hub.Ack nowle dge me nt:This work is supported by the National Science Foundation(NSF)CAREER award(#2146476).The authors want to thank Weili Fan for contributing to the AE

143、S module.Figure 35.4.1:Security challenges in existing biomedical implant devices;principle of the misalignment-based 2FA with mechanical input for the secure implant;and illustration of mechanical structure implementation.Figure 35.4.2:Authentication protocol of standard mode and emergency mode;sys

144、tem diagrams include an implant SoC and a compact external hub with the moving structure;and implementation of message structure.VrectSHA256RectifierPMUSuper capStimulatorTemp sensorSuppliesME-DTLS EngineAES128TRNGPUF keyTdatapatternActive driving TXDownlink decodeBasebandCommunication FSM&config re

145、gfileConfig bits to each moduleData_inData_outVrect ADC1st factor Auth.ME filmExternal hubME power&downlinkME power TXME uplinkME uplink RXMovingPattern detectionStandard Mode ProtocolServerTRX,phone(Relay)ImplantClientHello:256bServerHello:256b .ClientHelloRequest ClientFinished:ServerFinished:.Unl

146、ockPattern:8b randomUser pattern inputPatternResult:Sends to userApplicationData(bi-directional)Emergency Mode ProtocolTRXImplantEMClientHelloRequestEMUnlockPattern:8b randomUser(responder)input .EMPatternResult:EMKeySeed:ApplicationData(bi-directional)sends message ,containing Xsends ,with AES128 a

147、nd SHA256sends distance bounded messageSHA256 hash.DTLS 8 defined master secret and pseudorandom functionMSG:X MSG .MSG.ME comm.schemeHeaderME framePayloadCRCFrame#0ACKME-DTLS fragmentsFrag.#0Frag.#1Frag.#nME-DTLS messageFrame#1ACKBLE moduleCLK recovery&FLLCLKController2nd factor Auth.?1st factor:se

148、cure channel w/ME-DTLS(PSK)2nd factor:user authentication w/patternPattern only emergencyresponder authorizationCLKElectrodeExternal TRXImplantWPT&DownlinkUplinkThis Work:A Miniature Bio-Implant Secured by Two-Factor Authentication(2FA)with Emergency AccessBiosignal authentication5Implant chip w/DTL

149、S engineTouch SensorBio-application chipInternetBLEImplantBLEMechanical input structure for 2ndfactor authenticationTRX(relay)Phone(relay)ServerTRXResponderUplink&downlinkWPT transducerRectifierVrectPattern detectorImplantDetected pattern?ImplantCryptographic authentication bypass due to password le

150、ak An all-in-one ME transducer for all proposes:WPT,bidirectional communication,2FALow-cost misalignment-based&high accurate 2ndfactor detectionMechanical-input-pattern-enabled emergency modeFully integrated lightweight ME-DTLS engineDoctors passwordIMD(inside)recoded bio-signal PatientDoctorProgram

151、mer(outside)measured bio-signal=?User input 2FAAdditional touch sensor neededBulky packageNo protocol for emergency mode?Directional damperTRX coil+PCBDStandard mode:For remote access,e.g.,telemedicine applicationEmergency mode:Responder needs to access the implant w/o server access2cm offset:Data 1

152、2.5cm offset:Data 001020Lateral offset(mm)13Measured Vrect(V)230Data 1Data 001020Lateral offset(mm)13Measured Vrect(V)230Data 1Data 0?Bio signal as keyMeasurement variabilityHigh energy consumptionNo guarantee of uniquenessDirect access w/o server connection in emergenciesTouch-based 2FA 7?Existing

153、SolutionsSecurity Challenges:AttackerUplink&downlinkPowerPowerFigure 35.4.3:Circuit diagrams and operational principle of 2nd factor authentication pattern detection and ME uplink using width mode active driving.Figure 35.4.4:Measured waveforms in one standard authentication process,including commun

154、ication procedure for one fragment,operating waveform of pattern detection under different implant poses,and application data.CLK from FLLTXImplantVrectLevel shifterFoutCounterDoutMechanical-Input-Based Pattern Detection for 2nd Factor Authentication IDS?Vrect2(in sat.region)Fout=1/Tclk?IDS/(C*Vrect

155、)Fout?Vrect(1st order approx.)RO-Based ADC for Vrect SensingDifferentiatorSampler&data bufferData classifier 8-bit detected pattern Peak location detectionTXImplantTXmoving10VrectDetection indicator12820V18FieldFieldDuty cycle ctrlME filmMulti-modaldivider8MHz from FLLP2S128-bit data from ME-DTLS en

156、gineMMD ConfigCarrier:870kHzIF:DataRectifierME OOK active uplink1357911131004007001000 x105(Hz)ME Impedance(Ohm)ME length mode resonanceME width mode resonanceVDD=VrectHigh Q-Good for powerLow Q-High BW&dataratePattern DetectionADC outputPALength mode Width mode Directional DamperNot dampedDampedDet

157、ection threshold54043Data classifier threshold:(43+5)/2=24Max MinDetected pattern01120VDetection thresholdADC output787456Scenario1:Vrect monotonically drops during forward movementScenario2:Vrect reaches a maxima before dropping during forward movement-9.07V/s-1.25V/sVrectME Uplink Using Width Mode

158、 Active DrivingDetecting zero-crossing after crossing threshold dVrectdtdVrectdtdVrectdtdVrectdtDetecting zero-crossing after crossing threshold Detection indicatorData classifier threshold:(78+56)/2=67Max MinDetected pattern110TXmoving10Figure 35.4.5:Linearity of Vrect ADC;ADC output distributions

159、of pattern detection under different cases;energy breakdown for authentication and voltage scaling of ME-DTLS engine;the detection accuracy across volunteers.Figure 35.4.6:Measured uplink BER across different distances;the comparison tables with the state-of-the-art authentication and wireless link

160、schemes for biomedical applications.Comparison with State-of-the-Art Authentication Schemes for Medical DevicesComparison with State-of-the-Art Wireless Power and Communication Schemes for Medical ApplicationsBER Testing for ME Uplink6.17nJ/bit5.03nJ/bit2.65nJ/bit55kbps110kbps*Estimated from figure1

161、23456External TRX-Implant Distance(cm)10-710-610-510-410-310-210-1BERLimited by recording timeDistance boundThis WorkS.MajiCICC 20 7S.MaityJSSC 21 19M.RostamiCCS 13 5IMDIMDWearable devicesIMD1806565MCUME-DTLSDTLS-PSKBody channelTLSTRX movement patternUser tapNoneECGNoneTouch sensorNoneECG sensorYesN

162、oNoYesEavesdroppingYesYesYesYesReplayYesYesYesYesPassword leakageYesYesNoYes1.1mm x 1.4mm(ME-DTLS engine)315um20.17mm2N/A10.9x3.2x2.325x20 x12+sensor(20 x20 x0.5)*N/AN/A2nd factorImplant package volume(mm3)TechnologySecure channelEmergency modeAreaAttack resistanceSensor overheadApplicationThis Work

163、Z.YuISSCC24 17S.HosurTbioCAS23 18M.RoschelleJSSC24 20L.ZhaoTbioCAS24 21Core temp sensing,stimulationStimulation,recordingN/AIn vivo imagingECG,PPG,Tsensor180180N/A180180Transducer(frequency)ME(320k)ME(331k)ME(330k)Ultrasound(920k)Inductive(13.56M)Efficiency0.3%(2cm)0.37%(2cm)0.04%(2cm)3.3%(5cm)N/AMo

164、dulationTime domainTime domainTime domainPPM-OOKData rate(kbps)Average:20Average:12.56Average:0.14350ModulationContinuous OOKPWM backscatterPulse OOKASK backscatterIF-LSK backscatterCarrier frequency(kHz)87033170992013560Data rate(kbps)11017.731013192Data rate/carrier freq0.1260.0540.0140.0140.014BE

165、R3.3E-63cm55kbps1.5E-42cm110kbps2E-43cm1e-33cm1e-65cmN/ADatadownlinkN/AData uplinkWPTTechnology(nm)Biomedical functionISSCC 2025/February 19,2025/2:45 PM575 DIGEST OF TECHNICAL PAPERS 35 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-41

166、01-9/25/$31.00 2025 IEEEFigure 35.4.7:Chip micrographs of the secure implant SoC;the SoC specification summary;pictures of the assembled ME implant prototype,the in-vitro testing setup,and the prototype of the external wearable hub.Re f e re nce s:1 W.Wang,et al.,“Omnidirectional Wireless Power Tran

167、sfer for Millimetric Magnetoelectric Biomedical Implants,”IEEE JSSC,vol.59,no.11,pp.3599-4611,Nov.2024.2 J.C.Chen,et al.,“A wireless millimetric magnetoelectric implant for the endovascular stimulation of peripheral nerves,”Nat.Biome d.Eng.,vol.6,no.6,pp.706-716,June 2022.3 Y.Jeon,et al.,“Secure and

168、 Stable Wireless Communication for an Ingestible Device,”IEEE EMBC,July 2023.4 S.Zhuo,et al.,“SoK:Human-centered Phishing Susceptibility,”ACM Trans.Priv.Se cur.,vol.26,no.3,pp.1-27,Article 24,Apr.2023.5 M.Rostami,et al.,“Heart-to-heart(H2H):authentication for implanted medical devices,”ACM SIGSAC Co

169、nf.Compute r&Communications Se curity,pp.1099-1112,Nov.2013.6 J.Chen,et al.,“Contactless Electrocardiogram Monitoring With Millimeter Wave Radar,”IEEE Trans.Mob.Comput.,vol.23,no.1,pp.270-285,Jan.2024.7 S.Maji,et al.,“A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices,”IEEE C

170、ICC,Mar.2020.8 E.Rescorla and T.Dierks,“The Transport Layer Security(TLS)Protocol Version 1.2,”Inte rne t Engine e ring Tas k Force,Re que s t f or Comme nts RFC 5246,Aug.2008.9 D.Li and K.Yang,“A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabiliza

171、tion,”IEEE JSSC,vol.55,no.1,pp.98-107,Jan.2020.10 K.Yang,et al.,“A 553F2 2-transistor amplifier-based Physically Unclonable Function(PUF)with 1.67%native instability,”ISSCC,pp.146-147,Feb.2017.11 Y.He and K.Yang,“A Fully Synthesizable 100Mbps Edge-Chasing True Random Number Generator,”IEEE Sy mp.VLS

172、I Te chnology and Circuits,June 2023.12 K.Yang,et al.,“An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations,”IEEE JSSC,vol.51,no.4,pp.1022-1031,April 2016.13 A.Rukhin,et al.,“A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic App

173、lications,”National Ins titute of Standards and Te chnology,NIST Spe cial Publication(SP)800-22 Re v.1,Apr.2010.14 Y.Zhang,et al.,“A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm,”IEEE Sy mp.VLSI Te chnology and Circuits,June 2016.15 S.Mathew et al.,“340 mV1.1 V,289 Gbps/W,2090-G

174、ate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4)2 Polynomials in 22 nm Tri-Gate CMOS,”IEEE JSSC,vol.50,no.4,pp.1048-1058,April 2015.16 W.Wang,et al.,“A 36nW CMOS Temperature Sensor with VO).Since the energy is transferred from the high-voltage output to the low-voltage RX

175、 link,this discharging operation is named the reverse-buck operation.The SEF is significantly improved by energy replenishment and controlled VDS,MIN,allowing CSs to consume minimum energy and operate in the saturation region.PCE is also improved owing to the simple circuit structure,enabling a smal

176、l RX form factor.During STIM2B,anodic ISTIM is supplied from VOP instead of VON,maintaining regulated VO through the boost operation.For efficient energy delivery,the CTRL adjusts the falling and rising edges of the clock(CLK)to control the starting and ending points,respectively,of both charging an

177、d discharging operations(Fig.35.5.3).The CLK falls at the rising edge of CLKF and rises at the rising edge of CLKR.The AC voltage at the RX LC tank(VAC)is divided and level-shifted by a signal level shifter 7 and then fed to a clock recovery circuit to generate the operating clock(CLKOP).In the char

178、ging phase,the CLK is controlled through peak/zero current detection.After settling,the waveforms show that IAC is at the peak when charging starts and zero when it ends.The discharging phase should be initiated when the IAC direction changes to become opposite to the charging phase and properly con

179、trolled to keep the NMOS body diode off.Three delay cells are used in the loop,adjusting the falling edge of the CLK,and the last cell is utilized only in the discharging phase for the phase shift of 90.The loop tracks the negative peak of VAC,where IAC is zero.The delay difference among delay cells

180、 has little effect on the overall operation as feedback loops track the key operation timings.In the ASTIM,the upper CSs are controlled by negative feedback with an amplifier that equalizes the common-mode voltage of the electrodes(VCM)to the VSS of the RX chip 4(Fig.35.5.4).The lower CSs are contro

181、lled by a 4b current DAC,allowing the sensing ratio to be adaptively changed based on ISTIM so that the entire operating point of the current sensor remains constant.The stimulation is completed by comparing ETI voltages and conducting passive charge balancing.In the I-REG,replica CSs replicate the

182、VGS and VDS of the lower CSs in the ASTIM to sense ISTIM.Since the operating point is constant,the sensed voltage remains nearly consistent across different ISTIM levels.In both ASTIM and I-REG blocks,VT,LL,the node for ISTIM sensing,is lower than VON in STIM2A,and thus,adaptive body switching(BS)is

183、 utilized.The measurement of the proposed RCM WPT and adiabatic stimulation was performed for an inductive link with a 32.5mm TX coil and an 8mm RX coil over a 15mm distance.Figure 35.5.5 shows that VOP and VON track VT,RR and VT,LL,respectively,with VDS,MIN of 80mV,and ISTIM is well regulated in al

184、l stimulation phases,unlike prior arts.During STIM2A,as VO drops below VT,energy replenishment from the ETI to the RX LC tank occurs.When the phase changes from STIM1 to STIM2,the RCM WPT operation seamlessly changes from boost to reverse-buck mode.Because adiabatic supplies are created with a simpl

185、e single-stage implementation,despite low charge delivery,the maximum RX PCE reaches 72.5%for ISTIM of 160A(Fig.35.5.6).The system achieves SEF up to 6.02 through the energy-efficient CCS that maintains VDS,MIN across CSs.Moreover,the RX coil size is reduced,and the operating distance is extended by

186、 minimizing the RX power consumption,resulting in the highest normalized distance(improved by 2 compared to previous works).The ICs were fabricated in a 180nm BCD process(Fig.35.5.7).A 15mm porcine tissue was used to mimic the condition of the actual application.Ack nowle dge me nt:This work was sup

187、ported by the Ministry of Science and ICT,Korea,under Grant 2022M3E5E9018349.The chip fabrication was supported by the IC Design Education Center(IDEC),Korea.Figure 35.5.1:Electroceuticals and challenges in miniaturizing wireless neural stimulator system;comparison among conventional and proposed su

188、pply voltage modulation methods.Figure 35.5.2:Overall architecture and operational waveforms of the proposed wireless adiabatic stimulator system;operation principles and waveforms illustrating the generation of bipolar supply voltages.Figure 35.5.3:RX controller adjusting the edges of the switching

189、 clock(CLK)for the power stage by using two delay-based tracking loops;operation principles and waveforms of the boost and reverse-buck operations.Figure 35.5.4:Simplified schematics of the differential adiabatic stimulator circuit;current sensing and regulating circuits and measured sensed voltages

190、 across ISTIM,demonstrating consistent sensor accuracy.Figure 35.5.5:Measured transient waveforms:Bipolar supply voltages with ETI voltages and ISTIM verifying the operation of the differential adiabatic stimulation;RCM WPT performing boost and reverse-buck operations.Figure 35.5.6:Measured PCE and

191、normalized distance compared with previous wireless stimulator and RCM WPT systems;performance summary and comparison with prior arts.ISSCC 2025/February 19,2025/3:35 PM577 DIGEST OF TECHNICAL PAPERS 35 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFEREN

192、CES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 35.5.7:Chip micrographs and coil parameters;measurement setup for through-air and ex vivo tests.Re f e re nce s:1 S.C.Payne,et al.,“Bioelectric neuromodulation for gastrointestinal disorders:Effectiveness and mechanism,”Nat.Re v.Gas troe nte rol He pato

193、l.,vol.16,pp.89-105,Feb.2019.2 H.-M.Lee,et al.,“A power-efficient wireless system with adaptive supply control for deep brain stimulation,”IEEE JSSC,vol.48,no.9,pp.2203-2216,Sept.2013.3 C.-H.Cheng,et al.,“A fully integrated 16-channel closed-loop neural-prosthetic CMOS SoC with wireless power and bi

194、directional data telemetry for real-time efficient human epileptic seizure control,”IEEE JSSC,vol.53,no.11,pp.3314-3326,Nov.2018.4 S.Ha,et al.,“A fully integrated RF-powered energy-replenishing current-controlled stimulator,”IEEE TBioCAS,vol.13,no.1,pp.191-202,Feb.2019.5 S.Agarwal,et al.,“A current-

195、source-free constant-current wireless adiabatic neural stimulator achieving a 5.5-27.7x improved RF-to-electrode stimulation efficiency factor,”IEEE Sy mp.VLSI Circuits,June 2024.6 M.Choi,et al.,“A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems,”ISS

196、CC,pp.372-373,Feb.2016.7 S.-W.Hong,“A 13.56MHz current-mode wireless power and data receiver with efficient power extracting controller and energy-shift keying technique for loosely coupled implantable devices,”ISSCC,pp.486-487,Feb.2020.8 W.Biederman,et al.,“A 4.78 mm2 fully-integrated neuromodulati

197、on SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation,”IEEE JSSC,vol.50,no.4,pp.1038-1047,Apr.2015.9 D.Ahn and M.Ghovanloo,“Wireless power transmission with self-regulated output voltage for biomedical implant,”IEEE TIE,vol.61,no.5,pp.2225-2235,May 2014.

198、10 J.Lim,et al.,“Optimal design of resonance-based voltage boosting rectifier for wireless power transmission,”IEEE TIE,vol.65,no.2,pp.1645-4654,Feb.2018.11 H.-S.Lee,et al.,“A power-efficient resonant current mode receiver with wide input range over breakdown voltages using automated maximum efficie

199、ncy control,”IEEE TPE,vol.37,no.7,pp.8738-8750,July 2022.578 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARABLE BIOMEDICAL DEVICES/35.6979-8-3315-4101-9/25/$31.00 2025 IEEE35.6 An Enhanced-Frequency-Splitting-Based Wireless Power and Data Transfer S

200、ystem Achieving 60.2%End-to-End Efficiency and 1Mb/s Data Rate with a Sub-cm RX Coil for Miniaturized Implants Yechan Park1,Phan Dang Hung2,Donghyun Youn1,Daehyeon Kwon1,Chul Kim1,Minkyu Je1 1KAIST,Daejeon,Korea 2Samsung Electronics,Hwaseong,Korea Implantable medical devices have been scaled down to

201、 minimize the invasiveness and complexity of the device-deployment process.In such miniaturization,the main bottleneck is wireless power and data transfer(WPDT),particularly the volume of the receiver(RX)coil.Conventionally,on-off keying(OOK)has been widely used for WPDT over a single inductive link

202、 due to its simplicity.However,the OOK scheme restricts the power delivered to the load(PDL)as the data rate(DR)increases.To address the trade-off between PDL and DR,frequency-shift keying(FSK)and phase-shift keying(PSK)have been utilized.In these WPDT systems,there is an inherent trade-off between

203、the power transfer efficiency(PTE)and DR,driven by the quality factors(Qs)of coils.Recently,to alleviate these trade-offs,a frequency-splitting-based WPDT(FS-WPDT)system that employs a flat-region FSK(FR-FSK)scheme operating at two frequencies(fH,fL)in the flat region of the link gain has been prese

204、nted 1.However,the FS-WPDT system still suffers from significant coil size to achieve a coupling coefficient(k)larger than the critical value(kC)for frequency splitting(FS).This work presents an enhanced-frequency-splitting-based WPDT (EFS-WPDT)system breaking this limitation through the FS enhancem

205、ent(FSE)enabled by the dynamically controlled LC tank in RX(Fig.35.6.1).Since kC is inversely proportional to the loaded QRX,it is proportional to the load resistance(RL)in the series-series topology.The link-load isolation(LLI)allows the link to see switch on-resistance(RSW)rather than RL,thus lowe

206、ring kC regardless of RL,resulting in FSE even with fairly small coils.The effect of dynamic LLI on FS is simulated,confirming the feasibility of the EFS-WPDT system.The proposed EFS-WPDT system relieves the trade-offs among PDL,PTE,and DR while improving the form factor of the RX coil by 10.Figure

207、35.6.2 shows the overall system architecture.The data(DATAIN)is fed to the transmitter(TX)controller to generate a frequency-modulated(FM)signal and modulate the carrier frequency(fC)of a class-D power amplifier.In the RX,the FM carrier is converted to driving clocks of power switches,which control

208、the capacitor interleaving for LLI and the operation of a quasi-resonant boost converter(QRBC)2.The RX controller includes a clock recovery circuit(CRC),a pulse-frequency modulation(PFM)controller based on a multi-modulus divider(MMD)3,which is named MPC,a body-tuned peak detector(BTPD),a QRBC duty

209、generator(QDG),and a zero current detector(ZCD).The signals from the RX controller appropriately control the power switches through bootstrapped bipolar gate drivers(BSBP-GDs).Additionally,the FM carrier is demodulated for data delivery by an FSK demodulator(DEMOD).The EFS-WPDT system utilizes two c

210、apacitors for time-interleaved resonance,operating in two phases.Each phase consists of resonance and charging stages.The RX LC tank always resonates with TX,continuously receiving power and downlink data.Through time-interleaved operation,one of the capacitors forms a resonating LC tank,while the o

211、ther capacitor forms a QRBC with an inductor LQRBC,performing output voltage boosting and regulation.The system operates at fH and fL,which have similar link gain for frequency modulation.The flow chart and waveforms of the CRC and MPC are also shown in Fig.35.6.2.The MPC uses the clock(CLK)recovere

212、d by the CRC to generate the clock for PFM(CLKPFM).With conventional QRBC regulation methods,energy remains in the RX LC tank during capacitor interleaving,causing significant voltage fluctuations.To address this,the QRBC is designed to deliver all the energy to the load,while regulation is achieved

213、 by adjusting the number of resonance cycles(N).Unlike typical PFM controllers,where the frequency varies by a factor of 2 and thus N varies significantly along with load variation,the MPC in our design changes the frequency as an integer multiple using the MMD.The load receives the maximum power fr

214、om the QRBC when N=3,and N doesnt go lower than 3.When N8,power delivery in the QRBC is controlled in a bang-bang(BB)manner,improving light-load efficiency,range,and transient response.For time-interleaved operation,we need to detect the resonant voltage(VAC)peak,the moment when all the resonance en

215、ergy is stored at the resonant capacitor(C1,2).Conventional diode-mode peak detection 2 causes considerable loss due to the diode operation of power switches.Even if the peak detector finds the peak points correctly,delays from a gate driver and control circuits ruin detection accuracy.To tackle the

216、se issues,the BTPD,which includes self-clocked dynamic comparators,body-tuned background offset calibration circuits(OS-CAL)with charge sharing 4,and an optimum comparison time checker(OCTC)is proposed(Fig.35.6.3).Self-clocked comparators compare the voltage across interleaving switches(S1,2)to dete

217、ct the moment when the voltage sign changes as VAC peaks and the current direction turns opposite.These comparators use their outputs as a clock,and two comparators operate alternately to detect zero voltage instances across each interleaving switch to improve peak detection accuracy.Furthermore,as

218、the capacitors are interleaved,resonance continuity causes the following VC(VC2 for 1)to increase or decrease depending on peak detection delay.Therefore,VC2,1 sampled at the peak detection instance,for example,is compared with VC2,2 at the slightly delayed moment after the phase changes from 1 to 2

219、.Note that VC2,1 is close to 0V as all energy is delivered to the load.Then,the body voltage of input MOSFETs of comparators(CMP1,2)is adjusted according to this result to improve comparison accuracy.Even with these schemes,the comparators may consume large power for accurate comparison between extr

220、emely small inputs.The OCTC is adopted to optimally reduce the operating time of these comparators,thereby reducing power consumption.To drive power switches at the high impedance nodes of the RX link(VAC and VC1,2),the gate drivers output swing must reach higher than VAC,MAX by VTH and low enough t

221、o block VAC,MIN.Conventional gate driving circuits 2 only work for the link with a fairly small voltage swing due to the voltage drop of diodes used in envelope holders.Therefore,the BSBP-GD is proposed by applying the bootstrap technique 5 to achieve sufficient PDL.Figure 35.6.3 shows its operation

222、.Each bootstrap capacitance(CBS)is designed to be larger than the gate parasitic capacitance(CG)of each switch and is carefully adjusted not to exceed the breakdown voltage of all transistors used.When C1 or C2,to which all received energy in each phase is transferred,is connected to the QRBC,an app

223、ropriate duty ratio(D)is required to ensure that all of this energy is delivered to the load(Fig.35.6.4).The QDG monitors VC and adjusts D(or t1)in such a way that VC becomes zero at the end of the QRBC operation.This optimal end point is found by the ZCD.Since the input voltage of the QRBC(VC)depen

224、ds on N,the conventional delay-based tracking loop is unsuitable.To achieve accurate zero current detection against varying input voltages,the proposed ZCD with a voltage-based tracking loop adjusts the comparison speed by applying an offset(VCP2)to the comparators negative input(INN).The delay of t

225、he ZCD is compensated by comparing the voltages at both ends of the swtich S6(VL and VX)at the end of the ZCD operation to detect precise timing for zero current with low power consumption.Since these controls for D and offset may conflict with each other,D is adjusted only once every four times.Fig

226、ure 35.6.4 also shows the circuits for downlink data delivery.The CLK recovered from VAC at the CRC is fed to a pulse generator that produces pulses with a constant width(CLKDEMOD)even when the pulse width of the CLK changes due to the varying VAC magnitude and resultant CRC delay.A frequency-to-amp

227、litude converter(FAC)implemented using an injection-locked ring oscillator(ILRO)converts the frequency difference of FM pulses to amplitude difference 1.Since the FR-FSK in this work has a narrower bandwidth than 1 due to its miniaturized low-k link,the amplitude difference at the ILRO output(VILRO)

228、is insufficient for reliable demodulation.Thus,an envelope amplifier(ENV-AMP)with a shifted limiter 6 is employed to amplify the envelope difference of VILRO,improving the sensitivity of the FAC by 4.12.The demodulated data(ASKDOUT)is generated by comparing the envelope signal(VENV)and the averaged

229、VENV(VAVG)after the envelope detection of the ENV-AMP output(VEA).A single-loop reference-less clock and data recovery(CDR)circuit is adopted to recover the clock and data 7,8.The EFS-WPDT system was measured over an enhanced-frequency-split link with a 12.5mm TX coil and a 9.5mm RX coil at a 5mm di

230、stance.The capacitor interleaving and QRBC operation are verified in Fig.35.6.5.A 1Mb/s PRBS-7 signal is applied to the TX as DATAIN and transmitted to the RX over the single link along with power.Although the link bandwidth and frequency difference for the FR-FSK is reduced compared to 1,a larger d

231、ifference in VENV is achieved owing to the proposed FAC circuit.The minimum difference between VENV values measured at fL(=6.8MHz)and fH(=7.2MHz)is about 700mV.The BTPD performance is also verified.When the background OS-CAL is turned off,peak detection is delayed by several ns or more,degrading bot

232、h PTE and DR.When the OS-CAL is on,peak detection accuracy is improved to 99%.Figure 35.6.6 shows system performance compared to prior arts.Even with the small RX coil,the maximum PTE is 60.2%when the PDL reaches 43.4mW.The presented EFS-WPDT system shows FoM1 similar to prior arts using cm-scale li

233、nks.Moreover,2.5 better FoM2 than the conventional WPDT system is achieved even with a sub-cm RX coil.The ICs were fabricated in a 180nm BCD process(Fig.35.6.7).Coil parameters,along with photos of the RX module and measurement setup,are presented.A porcine head was used to replicate the condition o

234、f the actual application.Ack nowle dge me nt:This work was supported by the Ministry of Science and ICT,Korea,under Grant 2022M3E5E9018349.The chip fabrication was supported by the IC Design Education Center(IDEC),Korea.Figure 35.6.1:Motivation and comparison of the proposed data modulation method w

235、ith prior methods;frequency-splitting enhancement caused by dynamically controlled LC tank in RX.Figure 35.6.2:Overall architecture of the proposed EFS-WPDT system;flow chart and waveforms of the clock recovery circuit(CRC)and multi-modululs-divider-based PFM controller(MPC).Figure 35.6.3:Simplified

236、 block diagram and waveforms of the body-tuned peak detector(BTPD)including background offset calibration circuits(OS-CAL);necessity and operation of the bootstrapped bipolar gate drivers(BSBP-GDs).Figure 35.6.4:Simplified block diagram and operation principle of the QRBC duty generator(QDG)and zero

237、 current detector(ZCD);circuit implementation and sensitivity of the proposed data demodulator.Figure 35.6.5:Measured operational waveforms demonstrating the performance of the EFS-WPDT system;measured operation of the peak detection with and without background offset calibration.Figure 35.6.6:Measu

238、red PTE and PDL performances,and FoM1 and FoM2 plotted for the downlink WPDT systems;performance summary and comparison with prior arts operating with a single link.ISSCC 2025/February 19,2025/4:00 PM579 DIGEST OF TECHNICAL PAPERS 35 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025

239、PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 35.6.7:Chip micrographs and coil parameters;RX module with a miniaturized RX coil and measurement setup for through-air and ex vivo tests.Re f e re nce s:1 Y.Park,et al.,“A frequency-splitting-based wireless power and data

240、 transfer IC for neural prostheses with simultaneous 115mW power and 2.5Mb/s forward data delivery,”ISSCC,pp.472-473,Feb.2021.2 S.-U.Shin,et al.,“A time-interleaved resonant voltage mode wireless power receiver with delay-based tracking loops for implantable medical devices,”IEEE JSSC,vol.55,no.5,pp

241、.1374-1385,May 2020.3 C.S.Vaucher,et al.,“A family of low-power truly modular programmable dividers in standard 0.35-m CMOS technology,”IEEE JSSC,vol.35,no.7,pp.1039-1045,July 2000.4 L.Kull,et al.,“A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed

242、 in 32 nm digital SOI CMOS,”IEEE JSSC,vol.48,no.12,pp.3049-3058,Dec.2013.5 J.H.Lou and J.B.Kuo,“A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI,”IEEE JSSC,vol.32,no.1,pp.119-121,Jan.1997.6 Y.Wang,et al.,“A 13.56MHz wireless power and data

243、transfer receiver achieving 75.4%effective-power-conversion efficiency with 0.1%ASK modulation depth and 9.2mW output power,”ISSCC,pp.142-143,Feb.2018.7 C.H.Son and S.Byun,“On frequency detection capability of full-rate linear and binary phase detectors,”IEEE TCASII,vol.64,no.7,pp.757-761,July 2017.

244、8 Y.Park,et al.,“A wireless power and data transfer IC for neural prostheses using a single inductive link with frequency-splitting characteristic,”IEEE TBioCAS,vol.15,no.6,pp.1306-1319,Dec.2021.9 M.L.Navaii,et al.,“Efficient ASK data and power transmission by the class-E with a switchable tuned net

245、work,”IEEE TCASI,vol.65,no.10,pp.3255-3266,Oct.2018.10 A.Trigui,et al.,“Generic wireless power transfer and data communication system based on a novel modulation technique,”IEEE TCASI,vol.67,no.11,pp.3978-3990,Nov.2020.11 H.-S.Lee and H.-M.Lee,“A power-efficient envelope-detector-less amplitude-shif

246、t-keying forward telemetry for wirelessly powered biomedical devices,”IEEE TBioCAS,2024 Early access.12 R.Muller,et al.,“A minimally invasive 64-channel wireless ECoG implant,”IEEE JSSC,vol.50,no.1,pp.344-359,Jan.2015.13 C.Kim,et al.,“A 3 mm 3mm fully integrated wireless power receiver and neural in

247、terface system-on-chip,”IEEE TBioCAS,vol.13,no.6,pp.1736-1746,Dec.2019.14 S.-W.Hong,“A resonant current-mode wireless power and data receiver for loosely-coupled implantable devices,”IEEE JSSC,vol.55,no.12,pp.3200-3209,Dec.2020.15 Y.-P.Lin and K.-T.Tang,“An inductive power and data telemetry subsyst

248、em with fast transient low dropout regulator for biomedical implants,”IEEE TBioCAS,vol.10,no.2,pp.435-444,Apr.2016.16 M.Kiani and M.Ghovanloo,“A figure-of-merit for designing high-performance inductive power transmission links,”IEEE TIE,vol.60,no.11,pp.5292-5305,Nov.2013.17 D.Ahn and M.Ghovanloo,“Wi

249、reless power transmission with self-regulated output voltage for biomedical implant,”IEEE TIE,vol.61,no.5,pp.2225-2235,May 2014.580 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARABLE BIOMEDICAL DEVICES/35.7979-8-3315-4101-9/25/$31.00 2025 IEEE35.7 A

250、 Programming-Free Three-Dimensional Resonant Current-Mode Wireless Receiver with Real-Time Link-Adaptivity and a 0.904cm3 Receiver Coil for Implantable Systems Jong-Hun Kim,Seung-Ju Lee,Yeon-Woo Jeong,Mun-Jung Cho,Min-Sik Kim,Myeong-Ho Kim,Se-Un Shin Pohang University of Science and Technology,Pohan

251、g,Korea Implantable medical devices(IMDs)are used in the human body for the treatment of diseases affecting the nervous,circulatory,and endocrine systems 1-3,5.Charging the battery embedded in IMDs using conductors poses the risks of infection and aversion to surgery,leading to the development of wi

252、reless power transfer(WPT)technology.However,challenges related to body tissue heating and electromagnetic field exposure regulations must be managed,while maintaining small system sizes to enhance patient preference.To address these challenges,a resonant current-mode(RCM)WPT with low power receptio

253、n capability has been reported 1.The concept of RCM WPT with two operational phases is presented along with an overview of previous works(Fig.35.7.1,top)1-3.Here,an LC-tank resonates multiple times to accumulate energy(RESO).Once all the energy is stored in the inductor,it directly charges the batte

254、ry as current(ICHG)during the charging phase(CHG).Extending RESO increases resonances(NRESO),resulting in a higher charging current but reducing the number of charging operations(NCHG).Previous works 1,2 require complex processes to detect the most power-extraction optimized NRESO(NOPT),involving ci

255、rcuit parameters and received power(PRx)measurements to generate a look-up table(LUT).Environmental changes necessitated reprogramming,adding further complexity.Another work 3 introduces a method to detect NOPT by sensing accumulated and lost energy.However,the formula-based method struggled to acco

256、unt for parasitic losses,and NOPT was not used in the actual charging.Meanwhile,efforts have been made to strengthen coil links depending on the orientation and location using multiple coils 4-6.While aligning the transmitter(Tx)coil outside the body is straightforward,optimizing the implanted Rx co

257、ils position remains challenging.Furthermore,since each Rx coil in voltage-mode(VM)receivers functions equivalently as a voltage source,connecting them in parallel significantly diminishes the effectiveness of multidimensional coils 6.To address these issues,an RCM three-dimensional wireless power r

258、eceiver(RCM 3D-Rx)is proposed(Fig.35.7.1,bottom).This implementation of a multidimensional RCM WPT receiver is capable of fully automated NOPT detection.Due to the RCM WPT characteristic,where the LC-tank functions as a dependent current source,ICHG,n(ICHG,1,ICHG,2,ICHG,3)from each Rx(Rx1,Rx2,Rx3)ca

259、n be combined into a summed battery current(IBAT)with different charging periods.Additionally,each NOPT(NOPT,1,NOPT,2,NOPT,3)is individually selected for each receiver,enabling link-adaptive charging based on each PRx.In contrast to previous works,where users manually measured the received power,cal

260、culated NOPT based on circuit parameters,and inputted the values themselves,the proposed RCM 3D-Rx automates the entire process,significantly improving the usability.The requirements to self-detect NOPT are illustrated in Fig.35.7.2(top).Given the sampling time,the RCM 3D-Rx determines NOPT by selec

261、ting NRESO that maximizes the total energy transferred to the battery,EBAT.To achieve this,the controller should:1)autonomously adjust NRESO using VLV,the DC voltage compared to the resonating capacitor voltage VRx;2)generate a fixed sampling time(TSP);and 3)accurately sample EBAT.During TSP,energy-

262、measurement capacitors are connected to the power stage instead of the battery,capturing EBAT as the sampled voltages(VSP:VA,VB,VC,VD).Figure 35.7.2(bottom)shows the conceptual waveforms of the RCM 3D-Rx to determine NOPT.During the initial sampling time tENV,the three LC tanks resonate simultaneous

263、ly and continuously,capturing the maximum voltages that can be received under the present link conditions,stored as envelope voltages VENV,n(VENV,1,VENV,2,VENV,3).Each VENV is connected to its own resistor ladder,which outputs five DC voltages with the same division ratio.VLV is adjusted by this res

264、istor ladder at each sampling phase,which causes a change in NRESO of the power stage.The actual EBAT is sampled on battery-modeled capacitors,and NOPT is determined by ranking these sampled values.First,VLV for tA is set to the highest value(0.83VENV),which results in the largest NRESO and storing

265、EBAT as the voltage VA.Similarly,during tB,VLV is set to 0.17VENV,leading to the smallest NRESO and the other sampled voltage VB.The same process during tC is repeated with 50%of VENV as VLV,capturing VC.Finally,VLV during tD is shifted to either 66%or 33%of VENV,depending on which direction yields

266、better energy extraction.After tD,the most energy-optimized VLV is determined by ranking the sampled voltages VSP.At this point,all VLV,n(VLV,1,VLV,2,VLV,3)for each Rx unit are individually fixed based on each coils alignment,and NOPT,n remain constant to continue charging during steady-state operat

267、ion.The three NOPTs are later re-evaluated,allowing optimized charging as the link status changes over time.The top structure of the RCM 3D-Rx is shown in Fig.35.7.3(top left).The revised series LC-tank resolves the breakdown voltage issue in 1,3 caused by VRx,enabling a wider range of input power 2

268、.A single die integrates a common controller,including a Global RST and reference block,with three receivers.Each receiver unit is composed of two MOSFETs(S1,S2),and a controller,which contains RCM phase changer(RCM-PC)and optimum VLV generator(OVG).First,RCM-PC manages the transition between RESO a

269、nd CHG,performing the fundamental operation of RCM WPT(Fig.35.7.3,top right).It consists of two comparators:CP1,which detects if sufficient energy has accumulated in the LC-tank,and CP2,which triggers TRC to switch from RESO to CHG.The LC-tank in this work differs from that in 1 by allowing ICHG to

270、flow back to both CRx and the battery,which results in residual energy in the LC-tank.Through a non-residual VRx feedback loop(NRFL),the timing of TRC is adjusted with a resolution of 500ps to ensure that the capacitor voltage reaches zero at the end of charging,thereby reducing the energy loss.On t

271、he other hand,due to the ultra-short CHG duration(10 ns),a passive diode-based zero-current detector(ZCD)was used to sense the voltage at VX with a digital buffer,instead of using a high-power comparator for switching from CHG to RESO(TCR).Second,the OVG,composed of a sampling phase generator(SPG)an

272、d an EBAT-delivery sampler(EBAT-DS),generates VLV(Fig.35.7.3,bottom).The SPG outputs five sampling phases,tENV,tA,tB,tC,and tD,and generates the EN signal that triggers EBAT-DS.From tA to tD,sampling capacitors CA,CB,CC,and CD are sequentially connected to the power stage,storing EBAT while varying

273、VLV.During tD,VLV is adjusted to either the 0.66VENV or 0.33VENV based on the comparison data CPAB(Fig.35.7.3,bottom right).After the sampling phase ends,the most energy-optimized VLV(i.e.,NOPT)is selected by comparing all the sampled voltages(VSP),after which OVG is disabled to reduce power consump

274、tion.Subsequently,OVG is reactivated by the RST signal from the Global RST block.Figure 35.7.4 presents the measurement results of the RCM 3D-Rx.The sampling phases from tENV to tD,during which NRESO changes and ultimately leads to the selection of NOPT,are shown(Fig.35.7.4,top left).From tA to tD,N

275、RESO is 6,2,4,and 3,respectively.NOPT is selected as 2,demonstrating that VB is the maximum among VSP.Figure 35.7.4(top right)shows zoomed-in waveforms illustrating how NRESO varies with changes in VLV.At the end of TSP,NOPT is selected as 5 for this link status.Additionally,at the end of each CHG,t

276、he convergence of VRx to zero confirms that residue-less battery charging occurs in conjunction with NRFL.Figure 35.7.4(bottom)shows the measurement results obtained while varying the angle of the interfacing Tx/Rx coils,with all three Rx units simultaneously detecting their respective NOPT,n.As mis

277、orientation increases,VENV decreases or is not captured at all.When x equals y,the same NOPT is detected.This demonstrates that for Rx coils positioned at the same distance and orientation,optimal charging occurs when the same NOPT is selected.Figure 35.7.5(top left)presents a power analysis of the

278、RCM 3D-Rx,handling 293W to 23.7mW.When 8.559mW is received,maximum power conversion efficiency(PCE)of 75.1%is achieved.NRFL achieved an output power improvement from 12.1%to 38.0%under the same transmitted power PTx from a Class-D power amplifier operating at the same DC link voltage.Figure 35.7.5(t

279、op right)illustrates the changes in VRx and VX as the coupling strength increases over time,demonstrating that re-evaluating NOPT maintains optimal charging despite external changes.Figure 35.7.5(bottom)presents the calculated coupling coefficient k as a function of distance d and angle z for both t

280、he 2D-Rx and 3D-Rx when y is fixed at 45 degrees 7.Unlike the 2D coil,which loses coupling as it rotates in the z direction relative to the Tx coil on the x-y plane,the 3D coil strengthens coupling through the Rx coil on the y-z plane,achieving up to a 696%improvement in the coupling in the dead zon

281、e.Therefore,the two link-adaptivity techniques enable the battery to maintain optimal charging regardless of changes in time,angle,or position.Figure 35.7.6 summarizes and compares the RCM 3D-Rx with prior works.The proposed work presents an implementation of multidimensional coils in RCM WPT.The Rx

282、 coil was constructed using 0.07mm/125 Litz wire with four turns on a 3D-printed structure,making it suitable for implantation.Thanks to the low-power design techniques and the revised LC-tank,the ratio of maximum to minimum input power is 80.9,the highest among previous works.This work also introdu

283、ces a self-NOPT detecting RCM WPT system that requires no external programming.The combination of multiple Rx coils and the real-time link-adaptivity scheme ensures optimal battery charging that is independent of position,angle,or time.Figure 35.7.7 shows the fabricated RCM 3D-Rx chip,3D-Rx coil,and

284、 the experimental setup.Ack nowle dge me nt:This work was supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(2022-0-01170),the Technology Innovation Program(RS-2022-00154983)funded By the Ministry of Trade,industry&Ener

285、gy(MI,Korea),and IC Design Education Center(IDEC),Korea.Figure 35.7.1:Previous RCM WPT works and the proposed RCM 3D wireless receiver.Figure 35.7.2:Controller requirements for self-NOPT detection and conceptual waveforms.Figure 35.7.3:Top structure of the proposed RCM 3D-Rx,RCM Phase Changer,and Op

286、timum VLV Generator.Figure 35.7.4:Measured results of the RCM 3D wireless power receiver.Figure 35.7.5:Power analysis,two link-adaptivity techniques,and calculated results of the normalized coupling coefficient k(d,z)(=0,y=45).Figure 35.7.6:Performance comparison with previous works.ISSCC 2025/Febru

287、ary 19,2025/4:25 PM581 DIGEST OF TECHNICAL PAPERS 35 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 35.7.7:Die micrograph,3D-Rx coil specification,and experimental setup.Re f e re nce s:1 M.Choi,et al.,“

288、A Resonant Current-Mode Wireless Power Receiver and Battery Charger With 32 dBm Sensitivity for Implantable Systems,”IEEE JSSC,vol.51,no.12,pp.2880-2892,Dec.2016.2 H.-S.Lee,et al.,“A Power-Efficient Resonant Current Mode Receiver With Wide Input Range Over Breakdown Voltages Using Automated Maximum

289、Efficiency Control,”IEEE Trans.Powe r Ele ctronics,vol.37,no.7,pp.8738-8750,July 2022.3 M.Taghadosi and H.Kassiri,“A Calibration-Free Energy-Efficient IC for Link-Adaptive Real-Time Energy Storage Optimization of CM Inductive Power Receivers,”IEEE JSSC,vol.57,no.3,pp.793-802,Mar.2022.4 F.Huang,et al

290、.,“3D Wireless Power Transfer with Noise Cancellation Technique for 62dB Noise Suppression and 90.1%Efficiency,”ISSCC,pp.452-453 Feb.2023.5 W.Wang,et al.,“Omnidirectional Magnetoelectric Power Transfer for Miniaturized Biomedical Implants via Active Echo,”ISSCC,pp.314-315,Feb.2024.6 S.Wu,et al.,“Com

291、pact and Free-Positioning Omnidirectional Wireless Power Transfer System for Unmanned Aerial Vehicle Charging Applications,”IEEE Trans.Powe r Ele ctronics,vol.37,no.8,pp.8790-8794,Aug.2022.7 F.Liu,et al.,“Modeling and Optimization of Magnetically Coupled Resonant Wireless Power Transfer System With

292、Varying Spatial Scales,”IEEE Trans.Powe r Ele ctronics,vol.32,no.4,pp.3240-3250,April 2017.582 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 35/IMPLANTABLE AND WEARABLE BIOMEDICAL DEVICES/35.8979-8-3315-4101-9/25/$31.00 2025 IEEE35.8 DustNet:A Network of Time-Division Mul

293、tiplexed Ultrasonic Implants with 16-Level ASK Backscatter Modulation Changuk Lee*,Jade Pinkenburg*,Mohammad Meraj Ghanbari*,Cem Yalcin,Miguel Montalban,Rikky Muller University of California,Berkeley,CA *Equally Credited Authors(ECAs)A network of distributed neural implants can give insight into the

294、 operation of neurological circuits and provides opportunities to restore function in patients with nerve damage.Real-time activity data from specific,spatially distributed efferent nerves provide motor signals that enhance intuitive control of prostheses 1,2.To enable long-term recording with minim

295、al risk of infection,wirelessly networked and powered implants,each with an uplink data rate of 50kb/s,are required to measure a wide range of neural signals,including LFP,AP,and EMG signals.Therefore,multi-implant networks of 4 to 8 implants require total data rates of 200 to 400kb/s.Recent studies

296、 have demonstrated multi-implant networks using RF,optical(NIR),or magnetoelectric communication schemes 3-5,but they suffer from limited depth(10mm)or low total data rates(2 chip-based implants using a single US link.DustNet implements a custom TDMA protocol to enable multi-implant bidirectional co

297、mmunication and wireless power transmission while only requiring a single external transducer.Compared to code division(CDMA)9,TDMA is robust to inter-implant interference due to vertical misalignment and does not limit the number of implants for a given depth.Compared to frequency division(FDMA),TD

298、MA enables a scalable fabrication process,since FDMA would require a unique piezo sizing for each implant.Fig.35.8.1(bottom)shows the conceptual diagram of the proposed TDMA protocol for a two-implant system,which can be extended to N implants without loss of generality.To enable link configuration

299、and high-speed operation,the protocol has two modes of operation:Config Mode and Uplink Mode.Config Mode pulses consist of two segments allocated for downlink and uplink communication.In the downlink segment,an external interrogator modulates the US pulse envelope to set configuration bits for a tar

300、get implant ID that is hard-coded externally for each implant.When an implant receives its own ID,it acknowledges the transmission by backscattering its ID during the uplink segment.By sweeping all possible IDs,the interrogator can discover and configure all implants without prior knowledge of the i

301、mplant IDs.After configuring each implant,the channel transitions to Uplink Mode,which is designed for high-speed data transmission;the implants continuously record neural activity and backscatter data using 16-level ASK modulation.The interrogator transmits short US pulses that are each modulated b

302、y a single implant;uplink slots cycle sequentially between implants.Since only one implant backscatters modulated data during each uplink slot,the reflections from other implants are unmodulated and considered as background signals that can be removed at the receiver.The order of implants is set in

303、Config Mode;implants monitor channel control by counting the Uplink Mode pulses,which eliminates the need to send a target ID in Uplink Mode.The overall system architecture and IC block diagram are shown in Fig.35.8.2.Each implant comprises a 0.43mm2 IC,a 0.34mm3 PZT,and an off-chip capacitor(CSTORE

304、=10nF)that is required for maintaining chip functionality between US pulses.The piezo converts US pulses from the interrogator into electrical AC signals(VPZ)that are rectified to DC(VRECT1.2V)by an active rectifier.Power-management blocks generate stable supplies for analog blocks(1V)and the digita

305、l backend(0.8 to 1.1V).A POR signal initializes the digital backend when the LDO supplies are settled.An envelope detector decodes AM downlink data(DLDATA)in Config Mode.DLDATA is sampled using a downlink sampling clock(CLKDL)that is derived from the extracted ultrasound clock(CLKUS)and is time alig

306、ned with the downlink symbols.To evaluate the bit error rate(BER),pseudorandom binary sequence(PRBS)data DPRBS is generated on-chip by a linear feedback shift register(LFSR).A local clock(CLKLO=7kHz)is generated by a relaxation oscillator to control the PRBS sampling rate while allowing for variatio

307、n in the US frequency.Since one implant transmits data at any given time,data is stored in a FIFO memory between uplink slots.A TDMA scheduler counts the ultrasound pulses using the extracted USON signal to determine whether the implant controls the channel.If it does,the uplink interface concatenat

308、es the FIFO data to form transmission packets and the uplink modulator performs 16-level ASK modulation of the US backscatter.The backscattered pulse is received by the external interrogator and the signal is amplified,filtered,and demodulated by the RX channel.The length of each uplink US pulse tra

309、nsmitted by the external interrogator is controlled to be 2ToF based on the implant depth to avoid TX/RX interference.Accordingly,to account for implant depth variation,the number of symbols transmitted during each uplink pulse is adjustable(set in Config Mode).The TDMA protocol requires each implan

310、t to transmit the stored data within a short pulse duration(2ToF),necessitating a spectrally efficient modulation scheme.Digital 16-level ASK modulation is used to boost the data rate and improve robustness to carrier noise relative to conventional OOK 6,8 or analog AM schemes 9.Since the backscatte

311、r amplitude requires 8 US cycles to settle,16 ASK levels are used to achieve a total data rate of 400kb/s at 2MHz carrier frequency.The amplitude modulation of the backscattered echo is achieved by modulating the reflection coefficient()of the piezo,as shown in Fig.35.8.3.Multi-level AM backscatter

312、can be achieved using a resistive DAC(RE)in series with the piezo resistance RP.However,because is a nonlinear function of RE,a simple linear RDAC would create overlap between echo distributions,resulting in an impractically large BER.Alternatively,by exploiting the linear relationship between and V

313、P 9,10,linearly spaced echo levels can be achieved by modulating the envelope of VP(=VS-VPZ)using a current DAC.The uplink modulator is implemented using a pair of 4b iDACs incorporated into the active rectifier,as shown in Fig.35.8.3(right).Each iDAC has 15 unit-current sources(IM)to create 16 line

314、arly spaced VP amplitudes,which enable linearly spaced echo levels(Vecho).Since the piezo resistance(RP)is higher at parallel resonance than at series resonance,the system operates at the parallel resonant frequency to maximize the ASK modulation depth(IMRP).The unit current IM is reconfigurable fro

315、m 4 to 40A(using ULFS set in Config Mode)to ensure sufficient modulation depth and headroom on the current sources in the presence of RP(typically 15k)variations across piezos.In each half cycle of VPZ,one of the piezo terminals is tied to ground by a cross-coupled NMOS pair(M1,2)while the other ter

316、minal draws current IDAC,creating a linear voltage drop across the piezo that modulates the backscattered echo.To protect the stored charge on CSTORE from dropping due to the large IDAC modulation,the PMOS pass transistors(M3,4)are turned off to disconnect VPZ from VRECT.The functionality of the ent

317、ire DustNet system is validated through in vitro experiments using an US carrier frequency of 2MHz with an implant depth of 90mm in oil.Figure 35.8.4 shows the measured waveforms of the implant piezo voltage VPZ and the corresponding backscattered echo VRX received at the external transducer.The mod

318、ulated VPZ(2-level ASK)is received by the external transducer after 1ToF and shows that the implant successfully backscatters its ID.The envelope of the backscattered echo VRX has a modulation amplitude of 5mV,which is sufficient for demodulation.Figure 35.8.4(bottom)shows the backscattered echo rec

319、eived from one implant with the system configured to support 6 total implants;the implant backscatters its data once every 6 packets.Transmitted data is reconstructed by extracting the envelope of the received backscatter at the transducer.Figure 35.8.5 shows an eye diagram of 827 overlapped packet

320、envelopes and corresponding histogram of the ASK voltages with clearly separable levels.The reconstructed PRBS data is also compared against a ground-truth reference and no errors are made over 6616 samples,yielding a BER of at most 1.89E-5.Finally,multi-implant functionality is demonstrated in Fig.

321、35.8.6,which shows the modulated VPZ waveforms and backscattered echo received from 4 implants with the system configured to support 8 implants.The backscattered pulse envelopes are demodulated and the 16 ASK levels are again clearly separable for all 4 implants.Each implant transmits 24-symbols(96b

322、)per 8-pulse period(1.9ms)which corresponds to an achievable data rate of 50kb/s per implant.With 8 possible implants,this confirms a total data rate of 400kb/s.The 0.43mm2 DustNet IC was fabricated in a 28nm CMOS process and dissipates 6W.Figure 35.8.7 shows the die photo,performance summary and co

323、mparison with chip-based implants with wireless power and communication that utilize multiple-access networking.DustNet operates at a high implant depth of 90mm,which is 15 deeper than RF or optically powered implants 3,4.The TDMA protocol and 16-level ASK modulation allow DustNet to support up to 8

324、 implants with a total data rate of 400kb/s when using a 2MHz carrier frequency.This corresponds to a spectral efficiency of 200kb/s/MHz,which is 5 higher than state-of-the-art multi-implant systems 3-5,9.Ack nowle dge me nt:The authors thank the sponsors of BWRC and TSMC for chip fabrication.The au

325、thors also thank Weill Neurohub Postdoctoral Fellowship and NSF Graduate Research Fellowship Program.Figure 35.8.1:Conceptual diagram of the DustNet system and implant mock-up(top).Timing diagram of the proposed TDMA protocol(bottom).Figure 35.8.2:Simplified block diagram of the overall DustNet syst

326、em,including the external ultrasound interrogator circuitry and implant IC.Figure 35.8.3:Proposed 16-level ASK modulation mechanism for US backscatter(left)and implemented uplink modulator circuitry(right).Figure 35.8.4:In vitro measured waveforms from a single implant in Config Mode and Uplink Mode

327、 with N=6 total implants.VPZ is the voltage across the implant piezo and VRX is the backscattered voltage received at the interrogator.Figure 35.8.5:In vitro measured performance of the 16-level ASK modulation scheme.ASK levels are clearly separable and no errors are made when reconstructing PRBS da

328、ta.Figure 35.8.6:In vitro verification of a network of 4 implants:Measured VPZ of 4 implants and VRX which shows the functionality of the TDMA protocol(left).Demodulated and overlapped envelope waveform of each 4 implants(right).ISSCC 2025/February 19,2025/4:50 PM583 DIGEST OF TECHNICAL PAPERS 35 20

329、25 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 35.8.7:Chip micrograph and power breakdown.Performance summary and comparison to state-of-the-art chip-based wireless implants with multiple-access networking

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331、6 microelectrodes implanted in the median and ulnar nerves,”J.Ne ural Engine e ring,vol.13,no.3,p.036001,Mar.2016.3 J.Lee,et al.,“Neural recording and stimulation using wireless networks of microimplants,”Nature Ele ctronics,vol.4,pp.604-614,Aug.2021.4 G.Atzeni,et al.,“A 260274 m2 572 nW Neural Reco

332、rding Micromote Using Near-Infrared Power Transfer and an RF Data Uplink,”IEEE Sy mp.VLSI Circuits,pp.64-65,June 2022.5 Z.Yu,et al.,“Wireless Network of 8.8-mm3 Bio-Implants Featuring Adaptive Magnetoelectric Power and Multi-Access Bidirectional Telemetry,”IEEE RFIC,pp.47-50,June 2022.6 T.C.Chang,et

333、 al.,“A 30.5mm3 Fully Packaged Implantable Device with Duplex Ultrasonic Data and Power Links Achieving 95kb/s with 10-4 BER at 8.5cm Depth,”ISSCC,pp.460-461,Feb.2017.7 S.Alamouti,et al.,“High Throughput Ultrasonic Multi-implant Readout Using a Machine-Learning Assisted CDMA Receiver,”IEEE EMBC,pp.3289-3292,July 2020.8 S.Sonmezoglu,et al.,“A 4.5mm3 Deep-Tissue Ultrasonic Implantable Luminescence O