1、1Multi-Modality and Multi-AI Agents for Hardware DesignChia-Tung(Mark)Ho,Senior Research Scientist|GTC 20252AgendaMotivationLLM Agents for Hardware DesignConclusion&Future Work3NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Hardware Design Challenges Hardware design becomes more and more challenging as techn

2、ology advancing Increasing number of design rules Complex inter-layer design rules Strict patterning rule Growing number of transistors and more complex designs lead to long TAT.Opportunity:Leverage intelligent AI Agent to improve productivity and shorten TAT Timing analysis agent(days/weeks to mins

3、)Design rule checking code generation(days to mins)Verilog coding and debugging Source:IMEC Future Summits,May,2022Source:Nvidia4NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Autonomous Agent for Hardware Design Problems?How to acquire domain capability and improve deployment efficiency What problems to sol

4、ve with agent?Design generation,debug,review/analysis,optimization Low to medium intellectual effort,lots of tedious works Increase productivity,make designers life easier Extensive domain capability required to build useful agents for chip design Diverse design knowledge:Logic design,physical desig

5、n,verification,analog design,etc.Diverse set of tool commands and file format:PrimeTime,ICC2,Innovus,reports,LEF/DEF,etc Capability acquisition methods By model:foundation and fine-tuned models By prompt:prompt engineering By tools:RAG/customized tools/APIs By decomposition:task flow,multi-AIs conve

6、rsation By learning:trial-and-error,experience accumulation Many knowledge comes from the designers insights Need a framework that is easy to develop by designer experts Low-code development Library of Agents and ToolsHardware Design Problems&Challenges for Agent DeploymentLLM Skill&Capability for S

7、olving Hardware DesignCould we leverage LLM-based Agent in the real-world design flow?5NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Multi-Modality&Multi-AI Agents for Hardware Design Dynamic/Static Configurable Graph-Based Task Solving:Flexibly integrated with hardware design knowledge Single-AI/Multi-AI S

8、olving for Subtask:Leverage autogen for multi-AI collaboration configures Skill&Capability for Hardware Design:Customized tools,memory,knowledge DB development(a)Task Flow Level(b)SubTask Level:Multi-AI Config(c)Agent Skill/Capability ConfigAutogen:Wu,Qingyun,Gagan Bansal,Jieyu Zhang,Yiran Wu,Shaoku

9、n Zhang,Erkang Zhu,Beibin Li,Li Jiang,Xiaoyun Zhang,and Chi Wang.Autogen:Enabling next-gen llm applications via multi-agent conversation framework.arXiv preprint arXiv:2308.08155(2023).6AgendaMotivationLLM Agents for Hardware DesignConclusion&Future Work7NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Overvie

10、w of Our Agent Research for Hardware DesignLLM for Standard Cell Design Optimization NTECH 2024,LAD24 Best PaperReAct+Netlist Tools ReasoningSept,2023April,2024July,2024MCMM Timing AnalysisNTECH 2024Multi-AIs+Dynamic Task Graph+Human InteractiveVerilogCoder AAAI 2025Multi-Ais+Dynamic Task Graph+Cust

11、omized Debug Toolsiverilog simulatorSyntax Checker123DRC-Coder NTECH 2024,ISPD 2025Multi-Modality&Multi-AIs+Tools+CodingTiming Path DebugNTECH 2024Static Task Graph+Multi-AIs+Agentic RetrievalSPICE Verification Agent ChipVQA Agent ERC Check Agent Formal Verification Agent AgentsRTLFixer DAC24ReAct+C

12、ompiler+RAGMore Agent for Hardware Design 60 SpeedupsReduce hours to mins8NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Overview of Our Agent Research for Chip DesignAgent WorksTask CategoryConfiguration of Marco FrameworkTask GraphSub-Task Agent Config.Customized ToolsRTLFixer Code Syntax FixingN/ASingle-A

13、IRTL Syntax Error RAG DatabaseStandard Cell Layout Opt.OptimizationN/ASingle-AICluster Evaluator,Netlist Traverse ToolMCMM Timing Analysis(Partition/Block-Level)Summary&Anomaly IdentificationDynamicMulti-AITiming Distribution Calculator,Timing Metric Comparator DRC Coder Code GenerationN/AMulti-Moda

14、lity&Multi-AIFoundry Rule Analysis,Layout DRV Analysis,DRC Code EvaluationTiming Path Debug(Path-Level)Summary&Anomaly IdentificationStatic(Fig.1(a)Right)Hierarchical Multi-AIAgentic Timing Report RetrievalVerilogCoder Code GenerationDynamicMulti-AITCRG Retrieval Tool,AST-Based Waveform Tracing Tool

15、9NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Autonomous Agent for Verilog&DRC Coding TaskVerilogCoder(Mark Ho,Mark Ren)Multi-Ais+Dynamic Task Graph+Customized Debug ToolsDRC-Coder(Chen-Chia Chang,Mark Ho,Mark Ren,ATG)Industrial 3nm technology node design rulesMulti-Modality+Multi-AIs+Tools+Coding10Verilog

16、Coder11NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.VerilogCoder:Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree(AST)-based Waveform Tracing Tool VerilogEval Benchmark 94.2%pass Better than SOTA over 33.9%Dynamic Task Graph Planning Task-Driven Circuit Knowledge Graph(TC

17、RG)Retrieval Code Completion&Debugging Task-Flow Driven Multi-Agent AST-guided waveform debugging tool VerilogCoder+MCTS:98.1%Agentic(VerilogCoder+MCTS)Agentic(VerilogCoder)Non-agenticAgentic(VerilogCoder)Non-agenticLlama3GPT4-TurboToken Count:Non-agentic vs Agentic Approx.13X more token count on av

18、erage 12NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Preliminary StudyPlannerWaveform Debugging13NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Framework OverviewDynamic Task Graph Solving+Multi-AI Collaboration+Customized Tool14NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Experiment Results15NVIDIA CONFIDENTIAL.DO NOT DI

19、STRIBUTE.VerilogCoder:Automatically Fixing Functional Error16DRC-Coder17NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.DRC-Coder:Automated Design Rule Checking Code Generation Task:Write DRC code for DRC rule checker.Input:Foundry document image,Post-processed grid based DRV image from commercial tool.Output

20、:DRC code that can detect the DRC error correctly.Chen-Chia Chang,Chia-Tung Ho,Yaguang Li,Yiran Chen,Haoxing Ren,“DRC-Coder:Automated DRC Checker Code Generation Using LLM Autonomous Agent”,To appear in ISPD 202518NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.DRC Agent Flow Planner:Summarize the design rule

21、 condition Foundry Rule Analysis Tool(VLM)Layout DRV Analysis Tool(VLM)Programmer:Base on the design rule condition to write code DRC Code Evaluation Tool19NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Multi-Modal CapabilityFoundry Rule Analysis(VLM Reasoning)Layout DRV Analysis(VLM Reasoning)20NVIDIA CONFI

22、DENTIAL.DO NOT DISTRIBUTE.Experimental ResultsView DRC checking as a classification problem;Metrics:Precision(P),Recall(R),Accuracy(A),and F1 score(F)Proposed method achieves perfect score(1.00)across Precision,Recall,and F1 scoreProposed method Achieves 37%higher F1 score than standard prompting21N

23、VIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.DRC-Coder:Automatically Generate Design Rule Checking Code22LLM for Standard Cell Layout Design Optimization23NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.PPA AND LAYOUT-AWARE DEVICE CLUSTRING High quality device clustering consider:Diffusion break/sharing,Transistor pi

24、n access,Routing metal DRCs Prior work:Novel transformer model-based clustering methodology ISPD24 Best Paper Reduce complexity Narrow down searching space Assist finding routable+optimal layouts fasterDiffusion Break/SharingTransistor Pin AccessRouting Metal DRCsActive TransistorGateMDM0 Challengin

25、g to select a good set of LVS/DRC clean layouts for training:Routability+PPA Routability Cell Area PPA /Compact Cell Layout Routability Limited amount of LVS/DRC clean layouts available in the early development stage of new technology node.24NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Expert Designer Agen

26、t for Standard Cell Layout Optimization Goal:Adjust and fine-tune device clustering constraints incrementally to optimize PPA and routability together Input:SPICE Netlist,Clustering constraints,Cell Layouts,Routability Reports,etc.Output:Adjusted and fine-tuned device clustering constraints Contribu

27、tions:First to explore LLM for EDA optimization on an industrial-level benchmark.Holistic assessments and studies on the capabilities and domain knowledge of existing LLM on transistor level designs.Achieve up to 19.4%smaller cell area/generate 23.5%more LVS/DRC clean cell layouts than previous work

28、.25NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Expert Designer Agent:LLM for Standard Cell Design Layout Optimization ReACT+Domain Knowledge Knowledge Extraction Netlist topology,Physical layout,Routability Netlist Tools cluster_evaluator:Evaluate the quality of the cluster using simple cluster score.=(2+

29、2+min(,)get_MOSFETs_from_net:Traverse the circuit netlist to search and explore potential good clusters.save_potential_cluster:Save potential clusters and Fix the duplicated devices in multiple clusters by considering the shared nodes of the devices in each cluster.get_best_cluster:Get the cluster t

30、hat has the highest simple cluster score so far.Flow overview of LLM for standard cell layout design optimizationPotential Diffusion Sharable Nets in LayoutPotential Common Gate in Layout26NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Experimental ResultCell Name#DevsTransformer Cluster ISPD 2024Transformer

31、 Cluster ISPD 2024SASAProposed MethodProposed Method(a)2nm weak(b)5nmOpt.Opt.(a)(a)Opt.Opt.(b)(b)Opt.Opt.(a)(a)Opt.Opt.(b)(b)ImprImpr.(%).(%)Over(a)Over(b)Seq1402631X3125253.8519.35Seq260X41XX3939V4.88Seq34033262726272618.180.00Seq4382725X2525257.410.00Seq5362322262222224.350.00Seq6362225222222220.0

32、012.00Seq7342020202020200.000.00Seq8382525252524254.000.00Seq9321919191919190.000.00Seq10342021202020200.004.76Seq11402626252825253.853.85Seq12382427262824240.0011.11Seq1356XXXX4140VVSeq1444X36XX3434V5.56Seq1542X32XX3131V3.13Seq16564240X40353516.6712.50Seq17422525252525250.000.00Success Rate(%)76.50

33、94.10 58.8076.50100100-Fix RoutabilityOpt.Area Successfully27Timing Path Debug28NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Timing Path Debug Agent Task:multi-corner multi-mode(MCMM)timing path debugging Challenges:Multiple Timing Reports that provide various timing information(i.e.,Max,Xtalk,etc)440k lin

34、es in a report,8k timing paths with relations between timing paths29NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Hierarchical Plan Solving+Multi-Agent Collaboration MCMM:Hierarchical Plan Solving Report Dependency:Distilled Timing Debug Relation Graph Database Retrieval:Agentic Retrieval30NVIDIA CONFIDENTI

35、AL.DO NOT DISTRIBUTE.MCMM Report Debugging Task Multi-report benchmark from real-world design Pass rates:Evaluated by experienced human engineers.Set1:No in formation about reports and relationsSet2:Limited node description onlySet3:Limited edge description onlySet4:Limited node and edge description

36、sSet5:Detailed node and limited edge descriptionsSet6:Detailed edge limited node descriptionsSet7:Proposed31AgendaMotivationLLM Agents for Hardware DesignConclusion&Future Work32NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Conclusion What problems to solve with agent?Design generation,debug,review/analysis

37、,optimization Low to medium intellectual effort,lots of tedious works Increase productivity,make designers life easier Extensive domain capability required to build useful agents for chip design Diverse design knowledge:Logic design,physical design,verification,analog design,etc.Diverse set of tool

38、commands and file format:PrimeTime,ICC2,Innovus,reports,LEF/DEF,etc.Agent capability comes from the designers insights Potential to achieve significant design and verification productivity improvement33NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.Future Works Training LLMs with high-quality hardware design

39、 data Improving LLM-based agents ability for hardware signal and waveform debugging Incorporating PPA metrics into the agentic design flow Developing more efficient self-learning techniques and memory systems for LLM agents for solving more complex hardware tasks34NVIDIA CONFIDENTIAL.DO NOT DISTRIBU

40、TE.Thank you NVIDIA Design Automation Research Group for the Latest News.For those interested in the technologies highlighted in the post,heres a list of relevant papers:RTLFixer:Automatically Fixing RTL Syntax Errors with Large Language Models/NVlabs/RTLFixer GitHub repo VerilogCoder:Autonomous Ver

41、ilog Coding Agents with Graph-based Planning and Abstract Syntax Tree(AST)-based Waveform Tracing Tool/NVlabs/VerilogCoder GitHub repo DRC-Coder:Automated DRC Checker Code Generation using LLM Autonomous Agent Large Language Model(LLM)for Standard Cell Layout Design Optimization NTECH,Santa Clara,20

42、24(Agents in Production)LLM for Standard Cell Layout Design Optimization DRC-Agent:LLM-Agent-based Automated Design Rule Checking Timing Agent:A Multi-LLM Agent for Timing QoR Summary Generation NanoTime Agent Automating multi-report analysis with distilled timing debug relation graphs and agentic r

43、etrieval MAGIC:Multi-Agent Generative Intelligence for Charting Powered by Large Language Models Formal Verification Assertion Generation via a Multi-Agent LLM Framework35NVIDIA CONFIDENTIAL.DO NOT DISTRIBUTE.ACKNOWLEDGEMENTMany thanks to production teams and internal collaborators on this workDAR t

44、eam member:Yunsheng Bai,Chenhui Deng,Yi-Chen Liu,Danny Liu,Rongjian Liang,Haoyu Yang,Mingjie Liu,Mark RenDAR Intern:Chen-Chia Chang,Xufeng Yao,Yun-Da TsaiProduction team member:Jing Gong,Jatin Nainani,Abhishek Akkur,Ghaith Bany Hamad,Scott Fields,Yaguang Li,Tsunghsun Hsieh,Minsoo Kim,Alvin Ho,Anirudh Dhurka,Rakshit Tikoo,Ghasem Pasandi,Ravikishore Gandikota,Garvit Goel3637Taxonomy Study3738Taxonomy Study