9.RISCV-Summit-China-2023.pdf

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1、BRIDGING THE DIVIDE Unifying RISC-V through Binary TranslationDr.Philipp Tomsich Chief Technologist&Founder,VRULL GmbHRISC-V BUILDS MOMENTUMRISC-V offers the freedom for every implementer to add to,remove from,or customise the ISA as needed for their specific application or use-case.SCALES TO EVERY

2、APPLICATIONThe RISC-V ecosystem shares a common software foundation,and support the continuous innovation through custom,vendor-defined extension.INNOVATION ON A GLOBAL SCALEThe Technical Groups at RISC-V are continuously evolving the capabilities of the instruction set through new standards develop

3、ment.RAPIDLY EVOLVING CAPABILITIES2SLIDE2021State-of-the-art scalable vector extension supporting applications including ADAS,AI/ML and video processingRISC-V Vector extensionWorkloads change.RISC-V evolves.3CONTINUOUS EVOLUTIONSLIDERISC-V evolves rapidly driven by market and application requirement

4、s.RISC-V bitmanipulation extensionsInstructions that improve code-density and optimise a wide variety of workloads in general purpose computing and signal processing RISC-V scalar cryptography extensionCryptographic instructions targeting embedded workloads and microcontrollersRISC-V Hypervisor exte

5、nsionArchitectural prerequisites for virtualisation202320224SLIDESupport higher code-density with a wider range of compressed 16-bit instructionsRISC-V code-size reduction extensionsRISC-V Vector Cryptographic extensionCryptographic instructions built on the SIMD resources for high-throughput crypto

6、graphic processing in application processors and serversRISC-V Additional FP instructionsAdditional floating-point instructions motivated by real-world software workloads in image processing and scientific computingRISC-V Conditional Execution extensionInstructions to build up branchless sequences u

7、sing a RISC-friendly design suitable for high-performance microarchitecturesWorkloads change.RISC-V evolves.ARCHITECTURAL EVOLUTIONSOFTWARE MIGRATIONAddressing the adoption challengeENGINEERING UBIQUITY FOR RISC-V5SLIDESignRun binaries from legacy architectures on RISC-V unmodified and avoid porting

8、 overheads.Embrace differentiation and avoid fragmentation through transparent retranslation.SMART CAMERASDATACENTERCLIENT COMPUTING6SLIDEINDUSTRIAL7SLIDEAnnouncing theOpen Binary Translation Alliance7“An open and multi-ISA Binary Translation framework will be an unprecedented gamechanger for the ra

9、pidly evolving RISC-V landscape:it accelerates adoption,solves the question of legacy software,and empowers rapid innovation of the ISA without sacrificing compatibility.“www.binary-translation-alliance.orgOPEN-SOURCECOMMUNITY-OWNEDMULTI-ISASLIDE8OPEN COLLABORATION POOLED RESOURCESBinary translation

10、 has a prosperous and long future in RISC-V:we need to pool resources and build a single,maintained and well-optimised solution.LEARN FROM THE MISTAKES OF THE PASTVendor lock-in and“temporary solutions”would be a disadvantage for the entire RISC-V ecosystem while competing against legacy architectur

11、es.EDUCATEDEVELOPEMPOWER9SLIDEADVANCING BINARY TRANSLATIONWe engage with the research community.Our academic outreach helps to educate the next generation of researchers and engineers.Develop and maintain the key components for integrating production-ready binary-translation into a wide range of pro

12、ductsEncourage the development of a downstream ecosystem of service providers,consultants and integrators that assist in the commercial adoptionEARLY ACCESS TO INNOVATIONGain a head start by being a part of the communitys open-source development.BUILDING TRUST AND RELIABILITYBe at the forefront of b

13、uilding a trusted and reliable standard solutionAMPLIFY YOUR IMPACTBe a driving force in the community shaping decisions in line with your product strategy,SHARED RISKMaximize efficiency&share risk through collaboration.FLEXIBILITY&TRANSPARENCYEmbrace open-source freedom.Avoid vendor lock-in.ACCELER

14、ATE COMMERCIALIZATIONEstablish Binary Translation as an Open-Source Technology and speed up RISC-V adoption.10SLIDE11PROPOSED DEVELOPMENT TIMELINESLIDEEnsure readiness before the first Android devices ship.Open Binary Translation Alliance launched and proof-of-concept implementation available.Member

15、ship drive to secure all funding agreements necessary for the development.First developer previewTODAYLATE 2024LATE 2023First customer shipMID 2025ptomsichfedora-riscv$uname-a Linux fedora-riscv 6.1.22#2 SMP Thu May 4 19:24:40 CST 2023 riscv64 GNU/Linux ptomsichfedora-riscv$file/coremark.exe/home/pt

16、omsich/coremark.exe:ELF 64-bit LSB executable,ARM aarch64,version 1(GNU/Linux),statically linked,BuildIDsha1=23bd08adbe542b95ce0c227ccb315660ccd9e83b,for GNU/Linux 3.7.0,not stripped,too many notes(256)ptomsichfedora-riscv$/coremark.exe-bash:/home/ptomsich/coremark.exe:cannot execute binary file:Exe

17、c format error ptomsichfedora-riscv dbt-xlate$./build/xlate/coremark.exe 0 x0 0 x0 0 x66 100000 2K performance run parameters for coremark.CoreMark Size :666 Total ticks :17744 Total time(secs):17.744000 Iterations/Sec :5635.707845 Iterations :100000 Compiler version:GCC12.2.1 20221121(Red Hat 12.2.

18、1-4)Compiler flags :-O2-O3-static-DPERFORMANCE_RUN=1 -lrt Memory location :Please put data memory location here (e.g.code in flash,data on heap etc)seedcrc :0 xe9f5 0crclist :0 xe714 0crcmatrix :0 x1fd7 0crcstate :0 x8e3a 0crcfinal :0 xd340 Correct operation validated.See README.md for run and repor

19、ting rules.CoreMark 1.0:5635.707845/GCC12.2.1 20221121(Red Hat 12.2.1-4)-O2-O3-static-DPERFORMANCE_RUN=1 -lrt/Heap 12SLIDEARM Neoverse-N1 binary executing on a Sophia Milk-VJoin the Alliance!BRING THE SPIRIT OF OPEN COLLABORATION TO BINARY TRANSLATIONwww.binary-translation-alliance.orgPROMOTERCOPY WRITER13SLIDE