1、PROCEEDINGS OF SPIESPIEDigitalLibrary.org/conference-proceedings-of-spieNanoimprint lithography:today andtomorrowHirotoshi Torii,Mitsuru Hiura,Yukio Takabayashi,AtsushiKimura,Yoshio Suzaki,et al.Hirotoshi Torii,Mitsuru Hiura,Yukio Takabayashi,Atsushi Kimura,YoshioSuzaki,Toshiki Ito,Kiyohito Yamamoto

2、,Byung Jin Choi,Teresa Estrada,Nanoimprint lithography:today and tomorrow,Proc.SPIE 12054,NovelPatterning Technologies 2022,1205403(25 May 2022);doi:10.1117/12.2615740Event:SPIE Advanced Lithography+Patterning,2022,San Jose,California,United StatesDownloaded From:https:/www.spiedigitallibrary.org/co

3、nference-proceedings-of-spie on 11 Oct 2022 Terms of Use:https:/www.spiedigitallibrary.org/terms-of-useNanoimprint Lithography:Today and Tomorrow Hirotoshi Torii1,Mitsuru Hiura1,Yukio Takabayashi1,Atsushi Kimura1,Yoshio Suzaki1,Toshiki Ito1,Kiyohito Yamamoto1,Jin Choi2,Teresa Estrada2 1Canon Inc.,20

4、-2,Kiyohara-Kogyodanchi,Utsunomiya-shi,Tochigi 321-3292 Japan 2Canon Nanotechnologies,Inc.,1807 West Braker Lane,Austin,TX,78641 USA Abstract Imprint lithography is an effective and well-known technique for replication of nano-scale features.Nanoimprint lithography(NIL)manufacturing equipment utiliz

5、es a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate.The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action.Following th

6、is filling step,the resist is crosslinked under UV radiation,and then the mask is removed,leaving a patterned resist on the substrate.The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment.Additionally,as

7、 this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment,NIL equipment achieves a simpler,more compact design,allowing for multiple units to be clustered together for increased productivity.Previous studies h

8、ave demonstrated NIL resolution better than 10nm,making the technology suitable for the printing of several generations of critical memory levels with a single mask.In addition,resist is applied only where necessary,thereby eliminating material waste.Given that there are no complicated optics in the

9、 imprint system,the reduction in the cost of the tool,when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications.In this review paper,we touch on the markets that can be addressed with NIL and also describe the

10、 efforts to further improve NIL performance.In addition,we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error.As a final topic,we describe Canons efforts in developing a sustainable future and touch on how new methods can be applied to redu

11、ce waste and enable environmentally friendly solutions.Keywords:nanoimprint lithography,NIL,overlay,edge placement error,memory,logic,MOE,sustainability 1.Introduction Imprint lithography is an effective and well-known technique for replication of nano-scale features.1,2 Nanoimprint lithography(NIL)

12、manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate.3-9 The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mas

13、k by capillary action.Following this filling step,the resist is crosslinked under UV radiation,and then the mask is removed,leaving a patterned resist on the substrate.The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolit

14、hography equipment.Additionally,as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment,NIL equipment achieves a simpler,more compact design,allowing for multiple units to be clustered together for increas

15、ed productivity.Previous studies have demonstrated NIL resolution better than 10nm,making the technology suitable for the printing of several generations of critical memory levels with a single mask.In addition,resist is applied only where necessary,thereby eliminating material waste.Given that ther

16、e are no complicated optics in the imprint system,the reduction in the cost of the tool,when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications.Invited PaperNovel Patterning Technologies 2022,edited by Eric

17、M.Panning,J.Alexander Liddle,Proc.of SPIE Vol.12054,1205403 2022 SPIE 0277-786X doi:10.1117/12.2615740Proc.of SPIE Vol.12054 1205403-1Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-useAny new lith

18、ographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage.Key technical attributes include alignment,overlay and throughput.In previous papers,overlay and throughput results have been reported on test wafers.In 2018,Hiura et al.reported a

19、 mix and match overlay(MMO)of 3.4 nm and a single machine overlay(SMO)across the wafer was 2.5nm using an FPA-1200 NZ2C four station cluster tool.10 These results were achieved by combining a magnification actuator system with a High Order Distortion Correction(HODC)system,thereby enabling correctio

20、n of high order distortion terms up to K30.In this review paper,we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance.In addition,we describe recent efforts to develop pattern transfer processes that can be used to address edge placem

21、ent error.As a final topic,we describe Canons efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.2.NIL Applications and Markets Unlike other patterning methods for semiconductor devices,NIL has the pote

22、ntial to impact additional markets,as illustrated in Figure 1.Beyond,memory and logic,the device space covered includes CMOS image sensors,diffractive optical elements and meta optical elements(MOEs).In this paper we discuss DRAM,logic and MOEs.Also included in this section of the paper is an update

23、 on how defectivity is addressed and how machine learning is driving NIL performance.Figure 1.Potential application space for NIL.a.DRAM Recent efforts have focused on the development of NIL for advanced memory applications such as DRAM and storage class memory.DRAM memory is challenging,because the

24、 roadmap for DRAM calls for continued scaling,eventually reaching half pitches of 14nm and beyond.For DRAM,overlay on some critical layers is much tighter than NAND Flash,with an error budget of 15-20%of the minimum half pitch.For 14nm,this means 2.1-2.8nm.A device roadmap,which includes DRAM overla

25、y requirements is shown in Figure 2.DRAM device design is also challenging,and layouts are not always conducive to pitch dividing methods such as SADP and SAQP.This makes a direct printing process,such as NIL an attractive solution.Proc.of SPIE Vol.12054 1205403-2Downloaded From:https:/www.spiedigit

26、allibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use In recenhighly yielderror(EPE)line in a deverrors result to EPE has rfor a single immersion aproximity coof contributoand process For NIL OPC Ove LCD GCnt years,devicing devices,ani

27、s the differencvice which muin misalignmerisen significanline and via isand an EUV exorrection(OPCors.As an examcontrol.a FigurL,using a singlC term:No OPerlay accuracyDU:Good locaCDU:Strict GCFigure 2.Ne manufacturend several yeace between theust be placed went,which in tuntly because ofs shown in

28、Figxposure are reqC),overlay accumple,LCDU in re 3.a)EPE sce exposure stepPC required:The applicatial CDU is drivCDU is requiredNIL Roadmap fers have needears ago the cone intended andwith precision urn impacts devf the need for cgure 3a.Mulkequired(Figure 3uracy,GCDU ncludes source chematic for a p

29、,the terms beon of single paen by imprint md for both intrafor advanced seed to consider ncept of edge d the printed feso that a contvice yield.Whicomplex multiens et al.prese3b).11,12 The EPand LCDU.We and mask opt b line and via13 become more simatterning offersmask CDU anda and inter wafeemicondu

30、ctor dmore than jusplacement erratures of circutact can correcile simple conciple patterning ented the EPE PE budget wasWith the excepttimization,scab)EPE budgetmplified as folls more budget d reduced linewfer CD devices st overlay errorror was introduuit layout.As actly land on thceptually,the nsch

31、emes.A sibudget for thes broken into fotion of OPC,eanner optics antary breakdownlows:for NIL overlawidth roughnesrs in order to uced.Edge plaan example,cohat line.Devianumber of contimple examplee case where bour categories:each term has ad dynamics,ann ay ss produce acement onsider a ations or tri

32、butors e of EPE both ArF Optical a variety nd resist Proc.of SPIE Vol.12054 1205403-3Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use Based ocan be expreTo addrroughness an To addrquite differed

33、one by manHigh Order D One And The HODC order to drivinclude:Dro Imp Imp Ref Wa Details on thtuning knobsFigure 4.Toon this model,tessed as:ress EPE,NILnd optimize criress overlay in nt than what isnipulating bothDistortion Corre is using Magd second is Hemethod has beve cross matchop Pattern Compri

34、nt Force print tip/tilt confined mask afer zone chuckhese corrections used for NILo address overthe total NIL EL must reduceitical dimensioa Nanoimprins required for ph lens and stagerection(HODCnification actuat input,whicheen presented hed machine ovmpensation ntrol k pneumatics n methods can.rlay

35、 there are mbroken dowEPE,for the cas overlay erroron uniformity.nt system,therephotolithogrape during the exC)for NIL canuators,which aph is supplied byin the past,anverlay(XMMOn be found in rmany factors thwn into two catse of DRAM ars and develope are many fachic tools.In anxposure processn be en

36、abled bypply force usiny a DMD to cond recently addO)to an ArF imreferences 14-at need to be ctegories:Alignctive layer(AAp pattern transtors that need n optical lithogs.A different ay combining twng an array of porrect distortionditional correcmmersion scan-16.Figure 4considered.Gennment and DistA)

37、to the storag sfer methods tto be considergraphy,High Oapproach is reqwo techniques.piezo actuatorsn on a field-byctions methodsnner down to 2schematically nerally speakintortion.ge node contacto minimize lired,some of wOrder Compensquired for nanos.-field basis.s have been ap2nm.Additionillustrates

38、 the ng,the process ct(SNC)inewidth which are sation is oimprint.pplied in al terms various can be(1)Proc.of SPIE Vol.12054 1205403-4Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use In Figure 5,

39、we present the most recent XMMO results.NIL was matched to an ArF immersion scanner,and the reported results show the measurements for all fields,322 locations per field.Full field XMMO was on the order of the 2nm mean plus three sigma.Full fields and partial fields results were slightly higher,with

40、 x and y values of 2.30nm and 2.21nm,respectively.Recent improvements focus on partial field,including methods designed to improve overlay convergence times,as shown in Figure 6.In this example,the control point for alignment,or point of Figure 5.Full field and partial field NIL cross matched machin

41、e overlay.interest is placed relative to the center of the TTM marks,thereby accelerating alignment convergence and reducing overlay errors in the partial fields.In this example,the alignment error was reduced in y from 2.20nm to 1.79nm,3.Other methods being developed include a new final imprint for

42、ce and tilt control system that can control force and tilt more precisely.Figure 6.Effect of the control point for alignment(POI)The pattern transfer process for NIL involves three individual etch steps,starting with a resist descum(residual layer etch)and followed by the etching of a SiARC and spin

43、 on carbon film(Figure 7).In an initial study with TEL,a Quasi-atomic layer etch process developed by TEL was applied to the SiARC layer.17 A description of the q-ALE process is shown to the right.Layer by layer etch is realized by adsorbing fluorocarbon and bombarding in Ar ion alternatively.Proc.o

44、f SPIE Vol.12054 1205403-5Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-useFigurun The resu Figure 8.A For NILpossible to afrom field todimensions aexamples arethe order of ore 7.Pattern tranifor

45、mity specifults of the first three step etchL,it is possibleadjust the finalo field can beafter etch as ile shown in Figone to three naansfer technolofications.NIL,etch study areh process has beqe to adjust CD l CD after etche controlled wllustrated in Figure 9b.Note tanometers can bogy is critical,

46、a,like other adve shown for boteen used to patquasi-ALD appafter etch by ch.This can be aith picoliter prigure 9a.The athe change in be made.and an integratvanced lithograth 19nm and 32 ttern transfer 1roach developehanging the reaccomplished recision.In geamount of corrslope as the ettion scheme is

47、 aphic methods,2nm half pitch9nm and 32nmed by TEL.esidual layer thsince the volumeneral,thinnerrection is a funtch condition isneeded to meeuses a trilevel lines and spacm half pitch linhickness(RLT)me of resist jer RLT will resnction of the es varied.As a et critical dime resist stack.ces(Figure 8

48、).nes.The proces)across the watted within a fsult in smalleretch process,anresult,adjustm nsion ss uses a afer,it is field and r critical nd three ments on Proc.of SPIE Vol.12054 1205403-6Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:http

49、s:/www.spiedigitallibrary.org/terms-of-use Thelinewidth roLWR was minto the 19nmelectron micLWR are shoafter pattern other LWR sto a small dare referred tin this Proce b.Log A seconEnhanced inIndustrial Teother key sematter is theverification and Technol a Figuree pattern transfoughness(LWRmeasured

50、after m half pitch fecroscope.Featown in Figure transfer.Thisstudies.18 Finaldegree by the Nto the paper oneedings.19 gic nd market of infrastructures fechnology Devemiconductor me extension of of nanofabricalogy(AIST).AFig e 9.a)Impact fer process canR).An exampNIL exposureeatures using a ture imag

51、es an10.Note the re type of reduclly,we note thaNIL exposure n edge placemeinterest is logifor Post-5G Invelopment Orgmanufacturing logic-based deated wafers usiA schematic illugure 11.Schem of RLT on CDn also be usedple is shown ie and after pattHitachi CG63nd the resultineduction in LWction has be

52、en at CD can alsodose.Interesteent error by Ogic,and in 202nformation anganization(NEequipment coevices after theing a shared piustration of thematic of the NE D.b)SOC CD a d to manage in Figure 9.tern transfer 00 scanning ng unbiased WR to 2.6nm observed in o be adjusted ed readers gusu et al.1 Can

53、on applind CommunicaEDO)on extenompanies in Jae 2nm node.Inilot line at thee NEDO projecEDO manufactuF bas a function oied to“Researation Systems”nded miniaturiapan.The progncluded in theNational Instict organization uring developmFigure 10.LWf etch conditiorch and Develo”solicited by ization for lo

54、ggram was appre program is thitute of Advanis shown in Fiment program WR before and an.opment Projecthe New Enegic devices aloroved,and thehe implementatced Industrial igure 11.after pattern tra ct of the ergy and ong with e subject tion and Science ansfer Proc.of SPIE Vol.12054 1205403-7Downloaded

55、From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use Development work will target nanosheet devices as shown in the figure below.In this program,Canon will develop NIL technology for BEOL at 12nm half pitches

56、and below.Figure 12.Development target of nanosheet devices.c.Meta Optical Elements(MOEs)Meta optical elements or MOEs are a type of patterned metasurface.20,21 A potential use for these devices is optical elements that are used in cameras,mobile phones and other devices that typically rely on shape

57、d lenses that focus light to form an image.With the introduction metasurfaces,it becomes possible to shrink lenses and remove constraints of the past.Metasurfaces typically refer to the two-dimensional counterparts of metamaterials.Metasurfaces can be either structured or unstructured with subwavele

58、ngth-scaled patterns in the horizontal dimensions.Because metalenses are flat(planar)and ultra-thin,they do not produce chromatic aberrationsthey are“achromatic”because all wavelengths of light pass through virtually simultaneously.Their advantages also include tunable dispersionthe ability to manip

59、ulate how colors of light are dispersedas opposed to glass or other tradition materials that have fixed dispersions.Wavelengths of interest cover both infrared and the UV/Vis spectrum.In the examples shown in the figure to the right,note the changes in feature size and direction of the elements.Earl

60、y work on MOEs mainly relied on electron beam writing,which is appealing for prototyping,but not for production.NIL is an appealing choice for the production patterning of MOEs because of the few patterning constraints associated with the technology.Figure 13.Examples of meta optical elements.MOE pa

61、tterns can be configured to operate either in the infrared or UV/Vis spectrum.Proc.of SPIE Vol.12054 1205403-8Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-used.Def A commmanagementdictates strat

62、sources.Lowhereas DRmore as an ais not nearly Several NIL defect particle cleadetection(Wblank wafersSP3 tool as to avoid acquse.e.Art Finally,productivity“Lithographymachine leardrop pattern where Liplus Figure 15.fect Managememon theme tot.Each devicetegies and pragic devices hRAM tends to averagi

63、ng devias tight as the papers have besources.22,23 Maning and paWPC)system hs and was confshown in Figuquiring any repificial IntelligeCanon is appand enable my Plus”or Liprning models can quickly bes can be applieLiplus enablesalgorithms arent o all devices e type has its actices for manhave the mo

64、stbe relaxed relice and the levmost advanceeen published oMore recent warticle detectias sensitivity ofirmed by comure 14.The tooeater defects o ence and Machlying machinemore autonomoplus.An examare developed e fine tuned aned include aligns quick optimizre used to detecis defectivity own requiremn

65、aging the vart stringent relative to logic.vel of defectivid semiconducton methods forork has lookeion.The wafon the order ofmparison to a Kol will be used on the replica mhine Learning fe learning and ous control fomple for how tto examine pnd fed back to tnment optimizazation of the Nct drop recip

66、e d and defect ents,which rious defect quirements,.MOEs act ity required tor circuits.r mitigating ed at in-situ fer particle f 200nm for KLA-Tencor as a means mask during for NIL AI technologyor fast system this is appliedotential defectthe tool log,reation,resist jet NIL process anddefects and the

67、 y to further enhramp up.Thed to NIL is sht sites from thesulting in mortting and vibratd performance.en quickly geneFigure 14system senhance system e system softwhown n Figuree automated dre efficient droption mitigation.In this examperate optimized.Wafer Particlnsitivity performance,ware is referr

68、ee 15.In this edrop recipe so p patterns.Othn.ple,machine lead recipes.le Detection(Wincrease ed to as example,that the her areas arning WPC)Proc.of SPIE Vol.12054 1205403-9Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigi

69、tallibrary.org/terms-of-use 3.Sustainable Development Goals As a final topic,we discuss how Canons efforts in developing sustainability and addressing worldwide issues to the betterment of humanity.This has led to a“list of goals as shown in Figure 16.24 Captured in the list are such topics as affor

70、dable and clean energy,responsible consumption and production and innovation and infrastructure in industry.Figure 16.Sustainable development goals.These guiding principles apply to NIL technology as shown in Figure 17.The NIL tool has been developed to minimize power consumption and resist waste.Re

71、sist usage is minimized by jetting the resist directly on the stepper field on a wafer with volumes commensurate with what is necessary to fill the relief images on the imprint mask,along with a thin residual underlayer directly beneath the formed resist patterns.Figure 17.The NIL tool and process i

72、s designed to be more environmentally friendly,with the ability to address a more diverse application space.With respect to power consumption,NIL takes advantage of a simple single step patterning process combined with lower power exposure sources to reduce power consumption,regardless of the device

73、 node as shown in Figures 18a and 18b.Proc.of SPIE Vol.12054 1205403-10Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use Figure 18.Power consumption comparison for a)BEOL manufacturing and b)tota

74、l chip manufacturing.As a final example,we consider the resist fill process,after jetting,which requires the removal of any gas present in order to complete the drop coalescence and feature filling steps.Helium has always been used because it easily diffuses into the fused silica mask.However,the wo

75、rld currently is faced with a helium gas shortage.As an example,Figure 19 shows the United States production and storage over the last seventy years and the recent trend for both is apparent.25 Figure 19.Helium production and storage in the United States 1940-2014 To combat this trend,we have recent

76、ly examined alternative gases such as nitrogen and helium.Gas permeability is essentially the product of the solubility coefficient and the diffusion coefficient.In the presence of the right materials,it is possible to more efficiently remove the CO2.This is shown in Figure 20,where resist fill time

77、 has been simulated as a function of the thickness of an underlying spin on carbon(SOC)film.A minimal thickness of SOC is needed to achieve faster filling.Further experimental studies are required to understand the mechanism,but a roadmap is now in place to minimize or eliminate the use of helium ga

78、s.Proc.of SPIE Vol.12054 1205403-11Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use Figure 20.Simulation of resist fill time as a function of spin on carbon thickness for three different gases:h

79、elium,nitrogen and carbon dioxide.In the presence of a thin carbon layer,CO2 is observed to outperform the helium baseline process.4.Conclusions Imprint lithography is an effective and well-known technique for replication of nano-scale features.Nanoimprint lithography(NIL)manufacturing equipment uti

80、lizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate.Previous studies have demonstrated NIL resolution better than 10nm,making the technology suitable for the printing of several generation

81、s of critical memory levels with a single mask.In addition,resist is applied only where necessary,thereby eliminating material waste.Given that there are no complicated optics in the imprint system,the reduction in the cost of the tool,when combined with simple single level processing and zero waste

82、 leads to a cost model that is very compelling for semiconductor memory applications.In this review paper,we have touched on the markets that can be addressed with NIL,including advanced memory,logic and meta optical elements.We also described the efforts to further improve NIL performance,covering

83、both defect mitigation and machine learning algorithms.In addition,we reported on recent efforts to develop pattern transfer processes that can be used to address edge placement error by adjusting critical dimensions across a wafer and reducing line edge roughness As a final topic,we discussed Canon

84、s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.Acknowledgments The authors gratefully acknowledge the pattern transfer work done by Hideki Kunugi,Shuhei Tamura,Ryuichi Asano,Keisuke Tanaka and Tom

85、ohito Yamaji from Tokyo Electron Limited.References Proc.of SPIE Vol.12054 1205403-12Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use1.S.Y.Chou,P.R.Kraus,P.J.Renstrom,“Nanoimprint Lithography”,J

86、.Vac.Sci.Technol.B 1996,14(6),4129-4133.2.T.K.Widden,D.K.Ferry,M.N.Kozicki,E.Kim,A.Kumar,J.Wilbur,G.M.Whitesides,Nanotechnology,1996,7,447-451.3.M.Colburn,S.Johnson,M.Stewart,S.Damle,T.Bailey,B.Choi,M.Wedlake,T.Michaelson,S.V.Sreenivasan,J.Ekerdt,and C.G.Willson,Proc.SPIE,Emerging Lithographic Techn

87、ologies III,379(1999).4.M.Colburn,T.Bailey,B.J.Choi,J.G.Ekerdt,S.V.Sreenivasan,Solid State Technology,67,June 2001.5.T.C.Bailey,D.J.Resnick,D.Mancini,K.J.Nordquist,W.J.Dauksher,E.Ainley,A.Talin,K.Gehoski,J.H.Baker,B.J.Choi,S.Johnson,M.Colburn,S.V.Sreenivasan,J.G.Ekerdt,and C.G.Willson,Microelectroni

88、c Engineering 61-62(2002)461-467.6.S.V.Sreenivasan,P.Schumaker,B.Mokaberi-Nezhad,J.Choi,J.Perez,V.Truskett,F.Xu,X,Lu,presented at the SPIE Advanced Lithography Symposium,Conference 7271,2009.7.K.Selenidis,J.Maltabes,I.McMackin,J.Perez,W.Martin,D.J.Resnick,S.V.Sreenivasan,Proc.SPIE Vol.6730,67300F-1,

89、2007.8.I.McMackin,J.Choi,P.Schumaker,V.Nguyen,F.Xu,E.Thompson,D.Babbs,S.V.Sreenivasan,M.Watts,and N.Schumaker,Proc.SPIE 5374,222(2004).9.K.S.Selinidis,C.B.Brooks,G.F.Doyle,L.Brown,C.Jones,J.Imhof,D.L.LaBrake,D.J.Resnick,S.V.Sreenivasan,Proc.SPIE 7970(2011).10.M.Hiura,T.Hayashi,A.Kimura,Y.Suzaki,Proc

90、.SPIE.10584,Novel Patterning Technologies 2018.11.J.Mulkens et al.,Proc.of SPIE Vol.10145,1014505(2017).12.J.Mulkens et al.,Proc.of SPIE Vol.10585,105851L(2018).13.https:/www.semiconductor- et al.,SPIE Proceedings Volume 11610,Novel Patterning Technologies 2021;1161005(2021).15.N.Roy et al.,Proceedi

91、ngs Volume 11610,Novel Patterning Technologies 2021;1161005(2021).16.A.Kimura et al.,Proceedings Volume 11324,Novel Patterning Technologies for Semiconductors,MEMS/NEMS and MOEMS 2020;113240B(2020)17.S.Aihara et al.,Proceedings Volume 11610,Novel Patterning Technologies 2021;1161007(2021).18.M.Chand

92、hok et al.,Journal of Vacuum Science&Technology B:Microelectronics and Nanometer Structures Processing,Measurement,and Phenomena 26,2265(2008).19.M.Ogusu et al.,Nanoimprint Edge Placement Error Elements and Control,presented at the SPIE Advanced Lithography Symposium,2022.20.U.Quaade et al.,Proceedi

93、ngs Volume PC12010,Photonic and Phononic Properties of Engineered Nanostructures XII;PC1201012(2022).21.H.Giessen,Proceedings Volume PC12005,Smart Photonic and Optoelectronic Integrated Circuits 2022;PC120050J(2022).22.K.Emoto et al.,Proceedings Volume 9777,Alternative Lithographic Technologies VIII

94、;97770C(2016).23.T.Nakayama et al.,Proceedings Volume 10144,Emerging Patterning Technologies;1014407(2017).24.https:/global.canon/en/csr/report/pdf/canon-sus-2021-e.pdf 25.https:/commons.wikimedia.org/wiki/File:US_Helium_Production_and_Storage_1940-2014.png Proc.of SPIE Vol.12054 1205403-13Downloaded From:https:/www.spiedigitallibrary.org/conference-proceedings-of-spie on 11 Oct 2022Terms of Use:https:/www.spiedigitallibrary.org/terms-of-use