6432 - Green FPGA - The Role of FPGA in Waveform Agnostics Radio Unit for 5G and 6G Applications.pdf

1、Munir AhmadDr.Hossam FattahGreen FPGA:The Role of FPGA in Waveform Agnostics Radio Unit(RU)for 5G and 6G ApplicationsMunir AhmadDr.Hossam FattahGreen FPGA:The Role of FPGA in Waveform Agnostics Radio Unit(RU)for 5G and 6G ApplicationsSPECIAL FOCUS:OPENRANIt is the goal of ORAN to support waveform ag

2、nostics Shall supports 4G(LTE),5G NR,and 6GModularity,adaptability,scalability,interoperability,and customizationEnable mixed-generation network deploymentAllocate bandwidth based on demand and network conditionsSupport Cloud and Virtualized ServicesCope with the rapid changes and performance tuning

3、 required by 3GPP protocol stackWaveform Agnostics Radio UnitPeak data rate:Maximum achievable data rate under ideal conditions per device.The research target of peak data rate would be 50,100,200 Gbit/s.Latency:Latency over the air interface target(over the air interface)could be 0.1 1 mSecurity an

4、d resilience:Preservation of confidentiality,integrity,and availability of information,such as user data and signaling,and protection of networks,devices and systems against cyberattacks Sustainability(low power consumption):Refers to the ability of both the network and devices to minimize greenhous

5、e gas emissions and other environmental impacts throughout their life cycleInteroperability(waveform Agnostics):Refers to the radio interface being based on member-inclusivity and transparency,to enable functionalities between different entities of the system.6G Goals and ObjectivesSource:https:/ar5

6、iv.labs.arxiv.org/html/2305.138875G NR numerology:A slot has 14 OFDM symbols;each symbol has a normal Cyclic Prefix(CP).5G NR supports multiple different types of Sub-carrier Spacing(SCS).Each numerology is labeled as a parameter().The numerology(=0)represents 15 kHz.Slot length has different durati

7、ons depending on numerology.5G includes several low and mid-frequency bands in the sub-7 GHz range,defined as FR1,as well as higher frequency bands above 24 GHz,defined as FR2(mm Wave).5G frequency includes all previous cellular spectrum and additional spectrum 5G System ModelNUMEROLOGYSUBCARRIER SP

8、ACING =.15 kHzRESOURCE BLOCK BANDWIDTH.12OFDM SYMBOL DURATION(us)015180 kHz66.67130360 kHz33.33260720 kHz16.6731201440 kHz8.63342402880 kHz4.1754805760 kHz2.23696011520 kHz1.125G SpectrumSource:https:/moniem- GHz3 GHz6 GHz24 GHz39 GHz100 GHzLow-bandMid-bandHigh-band(e.g.,mmWaveFR1FR2JESD204 Protocol

9、JESD204 is a high-speed serial interface used between.With converter sampling rates and data throughput increasing,the JESD204 interface offers advantages in terms of size,cost,and speed.JESD204B key component is the ability to provide deterministic latency.It supports data rate up to 12.5 Gbps per

10、lane and up to 12 lanes per link.JESD204C supports up to 32Gbps per lane and up to 32 lanes.The JESD204B provides a mechanism to ensure that,from power-up cycle and across link re-synchronization events,the latency is repeatable and deterministic.JESD204B/C SERDES LANE RATEENCODING#OF AxC AT RF BAND

11、WIDTH=100 MHz AND Fs IS 122.88 MHz2.4576 G8 B/10 B0.54.9152 G8 B/10 B19.8304 G8 B/10 B219.6608 G8 B/10 B48.11008 G64 B/66 B216.22016 G64 B/66 B424.33024 G64 B/66 B6FPGA SERDES:supports 8 SERDES channels;each up to 10.3125 Gbps while the Lattice Avant-X FPGA supports 28 SERDES channels;each up to 25

12、Gbps.Both FPGAs are suitable for supporting JESD204B and JESD204C with up to 8 lanes and 28 lanes respectivelySingle RF bandwidth of 100 MHz component carrier for each AxC thus having eight component carriers for eight antennas.Two RF bandwidth of 100 MHz component carriers occupying a total 200 MHz

13、 in the same band for each AxC thus having four pairs of component carriers across four antennas.Two 100 MHz component carriers deployed in separate bands;each for each AxC thus having four pairs of component carriers across four antennas.FPGA Serializer and De-serializer Hardware feature support in

14、cluding key generation and storage and disabling physical interfacesSoftware support including hardened operating system and network protocol stack,standards defined authentication processes,interface input validation and protocol securityOperational security including supply chain,secure firmware u

15、pdates,mutual-authentication,and certificate management and monitoring.FPGA SecurityFPGA SECURITY FEATUREDESCRIPTIONRoot of TrustA unique hardware identity for each device,an immutable first stage boot loader,and secure storage for root cryptographic keys and certificates.Cryptographic accelerators

16、and trusted platform modulesSpeeding up cryptographic operations,provide key generation and storage so that keys are never visible to software.Secure processing featuresTrusted execution environments isolate sensitive code.NX 9no execute)mapping prevents execution of code hiding in data.Hardware sta

17、ck protection and pointer authentication counter some of the most prevalent software attacks.5G Small Cell Bridge Block Diagram(4Tx4Rx)5G layers (L3/L2/L1)are mostly performed by the BB and host CPUs,which generates the radio signal,samples it,and sends the resulting data to the FPGA.FPGA performs m

18、ultiple functions such as FIR(Finite Impulse Response),MIMO multiplexing and processing,RFFE preprocessing,arithmetic and logic(ALU),bridging(such as converting from/to SERDES to/from JESD204B/C)RFFE usually has a JESD204B interface while ASIC baseband can have PCIe,Ethernet,or SERDES interfaces.Imp

19、ortant function of FPGA is to translate,bridge,and process the digital samples from the BB and to convert it into the required 5G/6G waveform and then to the RFFE5G NR Traffic Digitization and Sampling In DL/UL,FPGA receives(I/Q)samples from the BB,performs DSP processing(e.g.FIR,MIMO,arithmetic&log

20、ic operations)and bridges the I/Q samples from SERDES interface over JESD204B/C interface to RFFEIn the case of an RF channel bandwidth of 100 MHz,a 30 kHz SCS,NFFT is 4096.The sampling frequency,Fs,is set to 32 x 3.84=122.88 MHz.Sampling and quantization of a single AxC requires an I/Q data bit rat

21、e of BAxC=2M x Fs bit/s,expanded by a factor of 10B/8B for the JESD204B or a factor of 66B/64B for JESD204C.Accordingly,a 100 MHz bandwidth requires 2 x 16 x 122.88 x 10/8=4.9152 Gbps.If JESD204C interface is used,it requires a 2 x 16 x 122.88 x 66/64=4.055 Gbps.5G NR Data Rate Dimensioning Guidelin

22、eBANDWIDTH(B)SUBCARRIER SPACING(SCS)5 MHz10 MHz20 MHz30 MHz50 MHz60 MHz80 MHz90 MHz100 MHzNumber of Subcarriers15 KHz300624127219203240NANANANA30 KHz1322886129361596194426042940327660 KHzNA132288456780948128414521620Number of PRB(Nprb)15 KHz2552106160270NANANANA30 KHz1124517813316221724527360 KHzNA1

23、124386579107121135FFT Size(Nfft)15 KHz5121024204830724096NANANANA30 KHz256512102415362048307240964096409660 KHzNA25651276810241536204820482048Sampling Freq(MHz)15 KHz7.6815.3630.7246.0861.44NANANANA30 KHz7.6815.3630.7246.0861.4492.16122.88122.88122.8860 KHzNA15.3630.7246.0861.4492.16122.88122.88122.

24、88Fs=SCS X Nfft15 KHz2 x 3.84 MHz4 x 3.84 MHz8 x 3.84 MHz12 x 3.84 MHz16 x 3.84 MHz24 x 3.84 MHz32 x 3.84 MHz32 x 3.84 MHz32 x 3.84 MHz30 KHz60 KHzOFDM Symbol Duration(Ts)(us)15 KHz66.6730 KHz33.3360 KHz16.67Cyclic Prefix Duration(Tcp)(us)15 KHz4.730 KHz2.360 KHz1.2Modulation Constellation64QAM6256Q

25、AM8No.of Bits for I and Q32I/Q Data Rate(Gbps)0.245760.491520.983041.474561.966082.949123.932163.932163.93216JESD204B per Lane Rate0.30720.61441.22881.84322.45763.68644.91524.91524.9152L1 Throughput(Gbps)(64QAM)15 KHz0.02522070.0524590.10693570.16141240.272383430 KHz0.02222850.04849850.10305920.1576

26、20.26876230.32736460.43850690.49508840.551669960 KHz0.04432010.09669840.15310580.26189140.31829880.43111360.4875210.5439284L1 Throughput(Gbps)(256QAM)15 KHz0.03362760.06994540.14258090.21521650.363177830 KHz0.02963790.06466460.13741230.210160.35834970.43648610.58467580.66011790.735559960 KHz0.059093

27、50.12893120.2041410.34918860.42439840.57481810.6500280.7252378BB ASIC has a limited configuration of SERDES(e.g.PCIe or Ethernet)that are not compatible with the RFFE interface and thus requires bridging functionality so that the BB and RFFE can communicate to each other.FPGA hosts other functionali

28、ties such as bit-format conversion(ones complement or twos complement conversion),FIR for signal filtering and shaping,MIMO multiplexing,demultiplexing,or proprietary DSP algorithms to enhance the 5G RF waveform.Baseband,FPGA,and RFFE Functional SplitFUNCTIONS OF BBFUNCTIONS OF FPGAFUNCTIONS OF RFFE

29、DOWNLINKUPLINKDOWNLINKUPLINKDOWNLINKUPLINKRadio base station control&managementChannel FilteringBackhaul transportSERDES to JESD204B/CJESD204B/C to SERDESD/A conversionA/D conversionMAC layerLip conversionDown conversionChannel coding,interleaving,modulationChannel decoding,deinterleaving,demodulati

30、onFinite Impulse Response(FIRs)On/off control of each carrierAutomatic Gain ControlIFFTFFTBit-format conversion and representation(ones or twos complement conversion)Power amplification and limitingLow Noise AmplificationAdd CP(optional)Remove CPMIMO Multiplexing and ProcessingDigital Pre-Distortion

31、(DPD)Signal aggregation from signal processing unitsProprietary DSP algorithmsDigital Pre-Distortion(DPD)Transmit Power Control of each physical channelSignal distribution to signal processing unitsRF filteringFrame and slot signal generation(including clock stabilization)Transmit Power Control&Feed

32、back Information detectionTDD switching in case of TDD modeMeasurementsMeasurementsHardware reference architecture:host TCP/IP,L3/L2(RRC,PDCP,RLC),L1(MAC/PHY),and a configuration of 4Tx4Rx antennas.MIMO unit can be used to process SU-MIM,MU-MIMO,and FIR Used for TDD or FDD modes and can be used with

33、 a single-sector or multiple-sector eNodeB.If a multiple-sector scenario is used,the baseband CPU communicates with multiple FPGAs/RFFEs where each single unit of FPGA/RFFE is used for each sectorFPGA interfaces with BB through SERDES.SERDES supports up to 8 or 28 embedded channels and each channel

34、can run at a maximum speed of 10.3125 Gbps or 25 Gbps FPGA interfaces with the RFFE through JESD204B/C.The FPGA JESD204B/C supports up to x8 lanes(or x24 lanes).5G Hardware Reference ArchitectureBB can host the L2/L1(MAC and PHY)layers.It has multiple cores,floating arithmetic unit,DDR4 interface,PC

35、Ie Gen3/4 interface,10G/25G Ethernet interfacesFPGA can host other L1 functionalities to offload BB for custom L1 functionalities.It has SERDES interface,DDR4/DDR5,Flash,and embedded memory interfaces,DSP slices,LUTs,10/25G Ethernet interfaces,secure booting,and SPI/I2C interfacesRFFE is responsible

36、 for on-air 5G waveform analog functionalities.It contains ADCs/DACs,JESD204B/C interfaces,decimation and programmable FIRs,automatic gain control(AGC),PLLs,tunning and interpolation engines,power control,synthesizers,and SPI interface.5G Hardware Reference ArchitectureAn RF bandwidth of 100 MHz and

37、 a 4Tx4Rx antenna system are used.BB runs 5G L1 and has an OFDM modulator and demodulator.OFDM modulator generates 64QAM modulated symbols,performs IFFT,and transfers the 16-bits I and Q samples to the FPGA over four SERDES channels.The FPGA process and transmits the I/Q samples to RFFE over JESD204

38、B four lanes.For 4Tx4Rx system,the SERDES has four channels and JESD24B has four lanes,and each lane runs at 4.9125 GbpsRFFE uses a carrier frequency of 1 GHz5G Hardware Reference ArchitectureBB generates rf_start in RED which is synced to 1PPS.rf_start is now synced to RF_out in BLUETx_Enable_trigg

39、er is triggered 850 ns in advance from rf_start,as is evident from the snip belowTx_Enable_trigger(the signal captured here is the debug signal from FPGA)is triggered 850 ns in advance from rf_start5G Hardware Reference Architecture(Tx Delay Characterization)Rx_En_Trigger is raised at rf_start to ch

40、aracterize the Rx path delay.Signal being sent from VSG(TM3.3 100M 30K option8 waveform)Captured waveform at BB(I samples are zoomed in but they experience a 1200 ns delay like the Q samples).Waveform is not starting from 0 and has some inherent delay,Rx path delay is around 152 samples i.e.1200 ns5

41、G Hardware Reference Architecture(Rx Delay Characterization)3GPP TM 1.1100 MHz and 30KHzEVM is less than 1%5G Hardware Reference ArchitectureWe are delighted to see that OCP have a special session for community efforts around Open RAN which will drive the wide-spread adoptionWe propose that OCP crea

42、tes a dedicated OCP working group focused on developing solutions for ORAN networks that prioritize security,including future-proofing with Post-Quantum Cryptography(PQC)We also propose that OCP promote green telecom initiatives through low-power FPGA designLattice has been playing a leadership role

43、 in providing low power,secure and high-performance solutions for ORAN with its ORAN solution stack Lattice will continue to work with OCP and we are requesting other OCP members to work together for a green and secured ORAN solutionAdditional informationg8 9 9 v F 4 g8 9 v v 9 v Call to ActionThank You!