11.High Performance RISC-V Chiplets for Cloud and Edge Computing - final.pdf

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1、High Performance RISC-V Chiplets for Cloud and Edge ComputingJeff Maguire,Director of Product ManagementAugust 24,2023THE RISC-V PERFORMANCE LEADER2Chiplets Are Key To Extend Moores LawSource:Synopsys,https:/ may prove to be more economical to build large systems out of smaller functions,which are s

2、eparately packaged and interconnected1.”-Gordon E.Moore1:“Cramming more components onto integrated circuits”,Electronics,Volume 38,Number 8,April 19,1965Ventana with DSAChiplet Solutions3CPU cluster/chipletCPU cluster/chipletCPU cluster/chipletD2D linkDiscrete CPUDevice Attach:brings devices in-pack

3、age as chiplets,connected over D2D with device protocols(CXL)Die Disaggregation Unlocks Innovation CHI-based CoherentOn-chip InterconnectPCIe/CXLComputeDeviceTraditional PCIe/CXL Attached AcceleratorDomain SpecificAccelerator Programmable AcceleratorD2D PHYCHI-based CoherentOn-chip InterconnectPCIe/

4、CXLCPU Cluster Proxy(Controller)Accelerator VentanasChiplet ArchitectureProxies represent the chiplets,unpacking D2D transport streams into protocol transactions on the SoC block interfaceDie Disaggregation:breaks a monolithic SoC into chiplets,which can then be composed into systems using SoC proto

5、cols over D2D(CHI,AXI)Ventana chiplets are CPU cluster interfaced over a D2D link with AMBA CHI protocolIntegrated PackageAccelerators typically interface with AXI or ACE-LiteVentanas Chiplet Architecture enables Chiplet vs IP integration to be interchangable4Pioneering Efficient Chiplet Interconnec

6、t ControllerRequirements Low D2D latency Predictable memory performance Standard SoC buses and networks must map easily to D2D transport CHI,AXI,HW memory coherency for efficient support of acceleratorsUCIe or BoW D2D Physical LayerVentana ControllerUCIe or BoW D2D Physical LayerChiplet AChiplet B 7

7、ns latencylatencyvs 100ns+for PCIeVentana has developed a low latency controller IP which transports standard SoC buses over D2D linksCHI/AXICHI/AXIUCIe or BoW D2D Physical LayerVentana Controller5Standard chiplets composable into desired solution with short lead timeSwitch between desired configura

8、tion of CPUs,Memory,and AcceleratorsOption of Standard IO Hub or Custom IO Hub with integrated featuresIO Hub and Custom Accelerators can be designed in N-1/N-2 process node for cost efficiencyDevelopment Time:1 yearDevelopment Cost:$25MChiplets Enable Composability and Late Binding AI AcceleratorsS

9、cale Out ServerAI ServerVeyron V1 CPU Compute ChipletsCHI-based CoherentOn-chip InterconnectD2D InterfacesD2D InterfacesAIAIOMMUHBMHBM ChipletCHI-based CoherentOn-chip InterconnectD2D InterfacesD2D InterfacesAIAIOMMUVeyron V1 CPU Compute Chiplets6AutomotiveClient5G Edge&AITarget MarketsData Center7S

10、calable Architecture for Server-class ComputeEntry level serverHigh end serverMid level server8-12 chiplets(128-192 cores)4 chiplets(64 cores)2 chiplets(32 cores)CHI-based CoherentOn-chip InterconnectD2D InterfacesD2D InterfacesCHI-based CoherentOn-chip InterconnectD2D InterfacesD2D InterfacesCHI-ba

11、sed CoherentOn-chip InterconnectD2D InterfacesD2D InterfacesAIAIOMMUAIAIOMMUAIAIOMMU8DPU and Edge AI ComputeDPU AcceleratedNetworking,Storage,Security AcceleratorVentana Veyron V116-Core ComputeEdge AI ComputeFPGA AcceleratorVentana Veyron V116-Core ComputeIO HubIO HubIO HubCHI-based CoherentOn-chip

12、 InterconnectD2D InterfacesEthernetPCIe/CXLCHI-based CoherentOn-chip InterconnectD2D InterfacesCHI-based CoherentOn-chip InterconnectD2D InterfacesEthernetPCIe/CXLEthernetPCIe/CXLVentana Veyron V116-Core ComputeAI/ML AcceleratorDPU+FPGA95G Open RAN SolutionsOpen RAN 5G RU5G RU AcceleratorVentana Vey

13、ron V14-Core ComputeOpen RAN 5G DUOpen RAN 5G CU5G DU AcceleratorVentana Veyron V116-Core ComputeVentana Veyron V164-Core ComputeIO HubIO HubIO HubCHI-based CoherentOn-chip InterconnectD2D InterfacesJESD PCIe eCPRICHI-based CoherentOn-chip InterconnectD2D InterfacesCHI-based CoherentOn-chip Intercon

14、nectD2D InterfaceseCPRIPCIe EthernetEthernet PCIe/CXL10 Cost tends to drive domain specific SoC hub integrations Chiplets can then be used to provide a high degree of scalability across product tiers Client and Automotive ProcessorsPCIe,USB,UFSD2D InterfacesVentana ComputeChipletGPUConnectivityISPAI

15、VideoDisplaySecurityAudio5GBTWiFiIOMMUPCIe,USB,Enet,CSI,2,CAN,LIN,FlexrayD2D InterfacesVentana ComputeChipletsAI/ML AccelerationISPIOMMU VideoDisplay/Video/AudioHSMGPGPUSafety IslandClientAutomotive ComputeAutomotive Grade UCIe D2D links ISO26262 Safety and ISO21434 Cybersecurity certified solutionH

16、ighly scalable compute and AI/ML acceleration11Veyron:Putting It Together With Chiplets UCIe or BoW D2D Physical LayerVentana ControllerUCIe or BoW D2D Physical LayerChiplet AChiplet BCHI/AXICHI/AXIUCIe or BoW D2D Physical LayerVentana ControllerAIAIOMMUVeyron Chiplet SolutionVentana compute chiplet

17、sIO HubDomain SpecificAccelerationVeyron compute chipletsoIn latest process node technologyoScalable CPU performance/countIO HuboImplemented in process node of choiceoCustomized for application requirementsCustom Domain Specific AccelerationoLow-cost process nodeSolving the D2D Latency ProblemVentana has developed low-latency controller IP which maps standard SoC buses such as CHI&AXI to D2D PHY Ventana system IP 7ns latencyThank YouTHE RISC-V PERFORMANCE LEADER