Overview of the White paper, the Agenda and the Workstream.pdf

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1、OCP Global Summit October 18,2023|San Jose,CADr.Michael Bortz,Open Compute ProjectPhotonics for Computer Interconnects:FTI WorkshopFuture-looking Photonics InitiativeDeployment 3-5 years outShort-reach(0.1-10m),in-server interconnect applications of photonicsScale-up not scale-outDifferent use cases

2、Server Disaggregation/ComposabilityxPU-xPU&Cache Coherent InterconnectsxPU-Memory Interconnects/Disaggregation CXL/PCIE and NVMe/PCIE over PhotonicsFuture Technology Initiative WorkshopApplication and Technology TalksWhite Paper(Q4 2023)OCP FTI Workstream(Q1-Q3 2024)Like an informal OCP projectInter

3、ception points vs use caseFormal OCP ProjectLaunch at 2024 Global SummitPlenty of time for strategic alignmentWhy are we here?Workshop Technical ContentIntention/Plan to OCP ProjectExamples:Use Cases 1 With first-generation chips now available,the early hype around CXL is giving way to realistic per

4、formance expectations.At the same time,software support for memory tiering is advancing,building on prior work around NUMA and persistent memory.Finally,operators have deployed RDMA to enable storage disaggregation and high-performance workloads.Thanks to these advancements,main-memory disaggregatio

5、n is now within reach.Enfabrica sponsored the creation of this white paper,but the opinions and analysis are those of the author.Tiering Addresses the MemTiering Addresses the Memory Crunchory Crunch Memory tiering is undergoing major advancements with the recent AMD and Intel server-processor intro

6、ductions.Both AMDs new Epyc(codenamed Genoa)and Intels new Xeon Scalable(codenamed Sapphire Rapids)introduce Compute Express Link(CXL),marking the beginning of new memory-interconnect architectures.The first generation of CXL-enabled processors handle Revision 1.1 of the specification,however,wherea

7、s the CXL Consortium released Revision 3.0 in August 2022.When CXL launched,hyperbolic statements about main-memory disaggregation appeared,ignoring the realities of access and time-of-flight latencies.With first-generation CXL chips now shipping,customers are left to address requirements for softwa

8、re to become tier-aware.Operators or vendors must also develop orchestration software to manage pooled and shared memory.In parallel with software,the CXL-hardware ecosystem will take years to fully develop,particularly CXL 3.x com-ponents including CPUs,GPUs,switches,and memory expanders.Eventually

9、,CXL promises to mature into a true fabric that can connect CPUs and GPUs to shared memories,but network-attached memory still has a role.As Figure 1 shows,the memory hierarchy is becoming more granular,trading access latency against capacity and flexibility.The top of the pyramid serves the perform

10、ance tier,where hot pages must be stored for maximum performance.Cold pages may be demoted to the capacity tier,which storage devices traditionally served.In recent years,however,developers have optimized software to improve performance when pages reside in different NUMA domains in multi-socket ser

11、vers as well as in persistent(non-volatile)memories such as Intels Optane.Although Intel discontinued Optane development,its large software investment still applies to CXL-attached memories.FIGURE 1.FIGURE 1.MEMORY HIERARCHYMEMORY HIERARCHY (Data source:University of Michigan and Meta Inc.)2-Socket

12、Block Diagram-many interconnectsMemory HierarchyRam Huggahalli and Nathan Tracy started to touch on these topics this morningPlatformsSiPH,VCSEL,LED,WDM/Comb lasers,Optical PCB2 Gbps/lane to 200 Gbps/laneArchitecturesPluggables/LPO/NPO/CPORetimed,un-retimed,DSP,no DSPOptical transparency/switchingRe

13、quirementsReach/BER/FEC/Latency/Power/ReliabilityCost?Technology and Architecture OptionsWe have asked some questions of the presenters(1)DescriptionArchitectural ParameterIdentify if your assessment is an application requirement for photonics to be useful or if it is a technical capability of your

14、technologyApplication requirement or technical capabilityIdentify the use case for your application/technology.If multiple use cases exist with significantly different parameters please describe as appropriateUse caseDefine/identify the number of links per host ASIC or host moduleLinks/HostDefine th

15、e electrical interface to the host and electrical interface power requirements(pJ/bit)Host interface(power)Define if the solution is retimed or un-retimed and include CDR function if retimedUn-retimed/retimed?Define is FEC needed to support optical transmission and FEC typeFEC requirementsPlease inc

16、lude a block diagram in your presentation,to support the architecture described and the parameters listed belowBlock DiagramFor Applications/Use Cases,Outline RequirementsWe have asked some questions of the presenters(2)CommentsMaxMinUnitsParameterSelf-explanatoryGbpsData rate per laneSelf-explanato

17、ry#lanes/linkSelf-explanatoryGbpsAggregate BW/linkState assumptionsGbps/mmLinear BW densityState assumptions Gbps/mm2Areal BW densityInclude EO and OE functions for 1 optical modules(1 TX and 1 RX)exclude the external light source.Include CDR/DSP function for retimed interfacespJ/bitEnergy efficienc

18、y single direction linkTake above energy efficiency and add in external light source.State assumptions about light source utilization and cooling and other factorspJ/bitEnergy efficiency with external light sourceInclude EO and OE functions,CDR/DSP functions,external laser,and host interface for tot

19、al single ended powerpJ/bitTotal Energy EfficiencySelf-explanatorymetersReachlatency with no FEC for the optical link.Host to host may have FECnanosecLatency(no FEC)Native BER of optical link with no FEC,add comments on error modelsBER(no FEC)latency with FEC for the optical link.Host to host may al

20、so have FECnanosecLatency(post FEC)For Technology Talks,Outline CapabilitiesAgenda2023 OCP Global SummitTrack NamePhotonics for Computer Interconnect WorkshopDate:Oct.1812:30-Room:TBDStartEndDurationActivitySpeaker(s)NameCompanyTitle of Session12:30 PM12:45 PM15OverviewMichael BortzOCPOverview of th

21、e White paper,the Agenda and tha Workstream12:45 PM1:00 PM15PresentationDavid PiehlerDellNIC PhotoNICs1:00 PM1:15 PM15PresentationDrew AlduinoMetaOpportunities for Optical Computer Interconnects:A Meta Platforms Perspective1:15 PM1:30 PM15PresentationGeorgios MichelogiannakisLBL/StanfordPhotonics-Ba

22、sed Resource Disaggregation for HPC1:30 PM1:45 PM15PresentationHuaiyu MengLightelligenceOptical CXL Interconnect for Large Scale Memory Pooling1:45 PM2:00 PM15PresentationMatthew WilliamsRockport NetworksOptical Interconnect:Pathways to an Open Infrastructure for AI2:00 PM2:15 PM15PresentationBob Wh

23、eelerLightcountingThe Long Road to Rackscale Disaggregation2:15 PM2:30 PM15Break2:30 PM2:45 PM15PresentationJeff HutchinsRanovusEnergy Efficient Optical Links for PCIE2:45 PM3:00 PM15PresentationLK BhupathiAyar LabsScalable Optical I/O Solutions for Disaggregated Infrastructure3:00 PM3:15 PM15Presen

24、tationKaren LiuNubisHigh Density Optical Interconnect for the ML Array Edge3:15 PM3:30 PM15PresentationBrian KochQuintessentMulti-wavelength Technology for Scalable and Reliable Optical Compute Interconnects3:30 PM3:45 PM15PresentationVipul BhattCoherentVCSELs in co-packaged optics for SR applicatio

25、ns3:45 PM4:00 PM15PresentationChris PfistnerAvicenaHigh Density Low Power Micro-LED based Optical Interconnects for Chip-to-Chip Communications4:00 PM4:15 PM15PresentationRadha NagarajanMarvellHeterogeneous Integration and Linear Optical Engines4:15 PM4:30 PM15Break4:30 PM5:00 PM30Panel/QAMichael Bo

26、rtz ModeratorOCPPanel/Open SessionRon Swartzentruber12:30-5:00I suggest we bump the Panel Q/A to before the break(move Panel to 4:15-4:30)Then people can go to the party sooner and get a drinkIdentify topics that the White Paper and FTI Workstream should addressFor Q4 2023 and Q1-Q3 2024PresentersEach offer up 1 or more important topics they want addressedAudienceTell us what you want to see,so that the work output is more useful to the communityPanel QA:Very Informal