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1、ISSCC 2025SESSION 5Front-End Circuits for High-Performance Transceivers5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference1 of 37A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB
2、 Back-Off Efficiency over 1.35 to 7.6GHzGuansheng Lv1,Wenhua Chen1,Xiaofan Chen1,Fei Huang2,Zhenghe Feng11Tsinghua University,Beijing,China2Gaxtrem Technology,Beijing,China5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE Internationa
3、l Solid-State Circuits Conference2 of 37Outline Introduction SLCG-Doherty-Continuum Power Amplifier Prototype Implementation Measurement Results Conclusion5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Cir
4、cuits Conference3 of 37Outline Introduction SLCG-Doherty-Continuum Power Amplifier Prototype Implementation Measurement Results Conclusion5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference4
5、 of 37Introduction Complex modulation High peak-to-average ratio(PAPR)Power amplifiers(PAs)must operate in power back-off(PBO)Back-off-efficient(BE)PA are used for high average efficiency78.5%78.5%BE PAClass-B PAPoutEff.5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Effic
6、iency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference5 of 37Introduction2G/3G：1 Ch.4G：4+Ch.5G：32+Ch.0.9 GHz2 GHz3 GHz4 GHz4G 28 GHz39 GHz5G B5G/6G：256+Ch.Freq.2G/3G Wideband B5G/6G m-MIMO systems Wideband compact PAs5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achievi
7、ng 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference6 of 37Classical Back-off-Efficient PAsMain PA:Vd,IdRopt/2Aux.PA:Vd,Id/4Z0=Ropt Doherty PA Envelope Tracking OutphasingLimited RF bandwidthLarge signal bandwidthSimple structure Large RF bandwidt
8、hLimited signal bandwidthComplex structure Limited RF bandwidthLimited signal bandwidthComplex structure 5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference7 of 37Broadband Back-off-Efficien
9、t PAs Load modulated balanced amplifier(LMBA)D.J.Shepphard et al.2016 MWCLNo bandwidth limitation theoreticallyNarrowband lossy on-chip coupler limited on-chip bandwidth5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International S
10、olid-State Circuits Conference8 of 37Broadband Back-off-Efficient PAs Distributed efficient power amplifier(DEPA)P.Saad et al.2018 TMTTPMN50 MainZd,0InputSplitterRLRFinRMZd,1Zd,2Zd,N-1TL0TL1TL2TLN-1Aux1Aux2AuxNIMN_MZg,1Zg,2Zg,N-1Zg,NRLgIMN_ARLgDistributed Input Matching Network RLMainRMZd,0Zd,1Zd,2Z
11、d,N-1RMIA,1IA,iIA,NIMRA,iZd,1Zd,0Zd,i-1Zd,iZd,N-1Zd,N=RLRLgRLgCin1Cin2CinN50 RgNRg2Rg1IMN_AZg,1Zg,2Zg,N-1Zg,NG.Lv et al.2021 TMTTUltra-widebandLarge circuit size Chip area hungry Complex multi-way architecture Difficulty of design5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back
12、-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference9 of 37Broadband Back-off-Efficient PAs Switchless class-G(SLCG)power amplifierSLCG PAX.Chen et al.2022 IMSClassical class-G PAUltra-widebandSimple two-way architectureBulky choke inductors Large chip area,lim
13、ited signal bandwidthF.H.Raab 1986 TCEParasitics degrade high-frequency performance5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference10 of 37Design Goals How to satisfy the following requir
14、ements simultaneously?Large RF bandwidthLarge signal bandwidthCompact circuit sizeSimple two-way structureNo reconfigurationLow design complexityOutput NetworkInput NetworkLoadRF IN5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE Int
15、ernational Solid-State Circuits Conference11 of 37Outline Introduction SLCG-Doherty-Continuum Power Amplifier Prototype Implementation Measurement Results Conclusion5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid
16、-State Circuits Conference12 of 37SLCG-Doherty-Continuum PAFreq.Doherty ModeSLCG ModeDoherty Modef0fHfL-90o0o+90oMain PA:Vd,Id-2IdRoptAux.PA:2Vd,2IdZ0,Frequency-Adaptive TLMain PA:Vd,IdRopt/2Aux.PA:Vd,Id/4Z0=RoptMain PA:Vd,IdVdRoptLchokeCblock2VdLchokeAux.PA:2Vd,2IdCblockDoherty PASLCG PASLCG-Dohert
17、y-Continuum PA(SDCPA)Combine merits of Doherty and SLCG PANarrow RF BWCompact SizeLarge signal BWParasitics absorp.Large RF BWBulky choke ind.Limited signal BWNo parasitics absorp.Large RF BWCompact SizeLarge signal BWParasitics absorp.5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6d
18、B Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference13 of 37SLCG-Doherty-Continuum PAModeZ0Main Sat.CurrentAux.Sat.CurrentSat.PowerBack-off PowerPBO0oSLCGRopt02Id2VdIdVdId/26dB90DohertyCase IRopt2IdId2VdIdVdId/26dBCase II2RoptId3Id/22VdIdVdId/812dBCase II
19、I1.5Ropt4Id/34Id/32VdId2VdId/99.5dB1.01.21.41.61.82.00.00.51.01.52.0 Main Aux.Z0/RoptNormalized Sat.Current1.01.21.41.61.82.06789101112Z0/RoptPBO(dB)Sat.Current vs Z0in Doherty modePBO vs Z0in Doherty modePBO in SLCG mode is 6dBPBO in Doherty mode is controlled by Z0(6-12dB)Low Z0,large main transis
20、tor sizeHigh Z0,small main transistor sizeMedium Z0,medium main transistor size(Chosen)5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference14 of 37SLCG-Doherty-Continuum PA-90-60-3003060900.0
21、0.51.01.52.02.5Red Line:Z0=RoptDohertyBlue Line:Z0=1.5RoptDohertyGreen Line:Z0=2RoptDoherty(degree)Normalized Aux.Sat.Current-90-60-3003060900.00.51.01.52.02.5 Red Line:Z0=RoptDohertyBlue Line:Z0=1.5RoptDohertyGreen Line:Z0=2RoptDoherty(degree)Z0/Ropt Assumption for theoretical analysis:Z0can be fix
22、ed(dash line)or frequency-adaptive(solid line)Aux.sat.current decreases linearly with the increase of|Main transistor shows no reverse drain currentConstant saturation output powerAux.Sat.Current vs Z0vs 5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35
23、to 7.6GHz 2025 IEEE International Solid-State Circuits Conference15 of 37SLCG-Doherty-Continuum PA-90-60-300306090468101214Red Line:Z0=RoptDohertyBlue Line:Z0=1.5RoptDohertyGreen Line:Z0=2RoptDoherty(degree)PBO(dB)-90-60-3003060900.00.51.01.52.02.5Red Line:Z0=RoptDohertyBlue Line:Z0=1.5RoptDohertyGr
24、een Line:Z0=2RoptDoherty(degree)Normalized Main Sat.CurrentMain Sat.Current vs PBO(dB)vs 5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference16 of 37SLCG-Doherty-Continuum PASat.Drain Efficie
25、ncy(DE)vs Back-off DE vs-90-60-300306090606468727680Red Line:Z0=RoptDohertyBlue Line:Z0=1.5RoptDohertyGreen Line:Z0=2RoptDoherty(degree)Back-off DE(%)-90-60-300306090606468727680Red Line:Z0=RoptDohertyBlue Line:Z0=1.5RoptDohertyGreen Line:Z0=2RoptDoherty(degree)Sat.DE(%)Variation of sat.and back-off
26、 DE for Z0=1.5Roptis smaller than 10%5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference17 of 37SLCG-Doherty-Continuum PALsCsCpLpCpLpZ0,B.Liu et al.2021 TCASIWidebandSupply pathDC blockNarro
27、w bandwidthOutput TL is realized by LCcircuits for miniaturization and parasitics absorptionFrequency-adaptive Z0Fixed Z0-type networkCoupled Resonator(CR)5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Cir
28、cuits Conference18 of 37SLCG-Doherty-Continuum PA0.00.51.01.52.02.53.03.501234 Z0/Ropt Cs/Cp=2 Z0/Ropt Cs/Cp=3 Z0/Ropt Cs/Cp=4Normalized FrequencyNormalized Impedance0.00.51.01.52.02.53.03.5-180-90090180 Cs/Cp=2 Cs/Cp=3 Cs/Cp=4Normalized FrequencyPhase Shift(deg.)-180-9009018001234 96o 1.5 Z0/Ropt C
29、s/Cp=2 Z0/Ropt Cs/Cp=3 Z0/Ropt Cs/Cp=4(deg.)Normalized ImpedanceZ0vs frequency vs frequencyZ0vs Bandwidth is controlled by Cs/Cp,larger Cs/Cpleads to larger bandwidthZ0=1.5Ropt=96o,close to the theoretical requirement(Z0=1.5Ropt=90o)5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB B
30、ack-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference19 of 37Outline Introduction SLCG-Doherty-Continuum Power Amplifier Prototype Implementation Measurement Results Conclusion5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficien
31、cy over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference20 of 37Circuit Schematic 0.25um GaN-HEMT process,15/30V supply for main/aux.PA 3.2-GHz center frequency,cover most of sub-8GHz bands25 pF30 3.73 nH0.68 pFVgm0.96 nHQm26 6 pF25 pF30 1.5 nH0.85 pFVga0.89 nHQa30 8 pF0.12 pFV
32、dm6.18 nH1.2 pF2.06 nH6.18 nH10 pFRFoutVda1.64 pF1.45 nH1.64 pF1.45 nH0.64 pF3.74 nH0.9 nHRFin2 pF2 pF5.8 nH0.37 pF0.9 nH59 6.3 nH6.3 nH1.2 pF1.2 pFPower SplitterPhase CompensationMain PAAux.PAQm:4X150 mQa:2X4X150 mVdm:15 VVda:30 V5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Bac
33、k-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference21 of 37Power CellsMain transistorAux.transistorMain PAAux.PATransistor Size4*150um2*4*150umSupply Voltage15V30VLoad-pull Ropt4040Cout0.28pF0.4pFChosen Ropt5050Sat.Power33dBm39dBm Chosen Ropt(50)is larger tha
34、n load-pull Ropt(40)leave margin for current capability5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference22 of 37Coupled Resonator2.06 nH1.2 pFCout_M6.18nH0.12 pF6.18nHCout_ACout_ACout_MCou
35、t_M=0.28 pF Cout_A=0.4 pF Cs/Cp=312345678050100150200 Z0 Extracted from Schematic Z0 Extracted from LayoutFreq(GHz)Z0()-180-90090180 Extracted from Schematic Extracted from Layout(deg.)123456780.00.51.01.52.0 Loss Extracted from Schematic Loss Extracted from LayoutFreq(GHz)Insertion Loss(dB)12345678
36、-50050100150Imag.Part Real Part Back-off Load Impedance Real Part,Shematic Imag.Part,Schematic Real Part,Layout Imag.Part,LayoutFreq(GHz)Impedance()Z0&Insertion LossBack-off Load Impedance Cs/Cp=3 Cover most of sub-8GHz bands Low loss:0.38dB7.6GHz,1dB1.7GHzEM simulations in ADS Momentum5.1:A GaN SLC
37、G-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference23 of 37Power Splitter and Phase CompensationLumped Wilkinson divider0.9 nHRFin2 pF2 pF5.8 nH0.37 pF0.9 nH59 6.3 nH6.3 nH1.2 pF1.2 pF1.64 pF1.45 nH1.64
38、pF1.45 nH0.64 pF3.74 nH12345678-30-25-20-15-10-50 S32 S21 S31 S11 S22 S33Freq(GHz)S-parameters(dB)12345678-50-40-30-20-10010 S21 S11Freq(GHz)S-parameters(dB)12345678-150-100-50050100150200Freq(GHz)Phase Shift(degree)Band-pass phase compensation circuit5.1:A GaN SLCG-Doherty-Continuum Power Amplifier
39、 Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference24 of 37Chip Photo5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference25 of 37
40、Outline Introduction SLCG-Doherty-Continuum Power Amplifier Prototype Implementation Measurement Results Conclusion5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference26 of 37Small-signal Per
41、formance12345678-30-20-1001020 S11_Sim.S22_Sim.S21_Sim.S11_Mea.S22_Mea.S21_Mea.Freq(GHz)S-parameters(dB)Measured S-parameters agree well with the simulated ones S1110dB in 1.5-7GHz5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE Inte
42、rnational Solid-State Circuits Conference27 of 37Measurement Setup Measurement setup for large-signal and modulated-signal test Large-signal test:pulsed CW,50us pulse width,10%duty cycle Modulated-signal test:100MHz LTE signal,PAPR 7.5dBTriggerRef.10MHzPCLANLANR&S FSW43Spectrum AnalyzerDriver Amplif
43、ierChipR&S SMW200ASignal Generator30-dB AttentuatorIsolator5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference28 of 37Large-signal Performance Freq.:1.35-3.8GHz Psat:36.6-38dBm DE6dB:40%-51%
44、Freq.:4.4-7.6GHz Psat:37.6-38.6dBm DE6dB:38%-56%21232527293133353739471013161922 2.6 GHz 3.2 GHz 3.8 GHz 1.35 GHz 1.7 GHz 2.0 GHzPOUT(dBm)Gain(dB)5152535455565 DE(%)21232527293133353739471013161922 6.8 GHz 7.6 GHz 4.4 GHz 5.0 GHz 5.6 GHz 6.2 GHzPOUT(dBm)Gain(dB)5152535455565 DE(%)5.1:A GaN SLCG-Dohe
45、rty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference29 of 37Large-signal Performance Summary1.21.62.02.42.83.23.64.04.44.85.25.66.06.46.87.27.68182838485868 DESAT DE6dB DE7.5dBFreq(GHz)DE(%)34363840424446 PSATP
46、OUT(dBm)Saturated performance:36.6-38.6dBm Psat,31.5%-63.5%DEsat Back-off performance:38%-56%DE6dB,37%-54%DE7dB5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference30 of 37Modulated Performanc
47、e Freq.:1.6GHz DEAVG:43%29.8dBm ACPR w DPD:-48.2dBc-200-150-100-50050100150200-60-50-40-30-20-10010100 MHz LTEPAPR=7.5 dBfC=1.6 GHzPAVG=29.8 dBmDEAVG=43%ACPR w DPD:-48.4/-48.2dBcPSD(dBm/Hz)Frequency Offset(MHz)ACPR w/o DPD:-38.4/-37.3dBc-200-150-100-50050100150200-60-50-40-30-20-10010100 MHz LTEPAPR
48、=7.5 dBfC=3.6 GHzPAVG=30.5 dBmDEAVG=45.2%ACPR w DPD:-51.4/-51.5dBcPSD(dBm/Hz)Frequency Offset(MHz)ACPR w/o DPD:-27.5/-26.5dBc Freq.:3.6GHz DEAVG:45.2%30.5dBm ACPR w DPD:-51.4dBc5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE Interna
49、tional Solid-State Circuits Conference31 of 37Modulated Performance Freq.:5GHz DEAVG:39.8%30.9dBm ACPR w DPD:-55dBc Freq.:6.8GHz DEAVG:49.2%30.9dBm ACPR w DPD:-52.5dBc-200-150-100-50050100150200-60-50-40-30-20-10010100 MHz LTEPAPR=7.5 dBfC=5.0 GHzPAVG=30.9 dBmDEAVG=39.8%ACPR w DPD:-55.0/-55.5dBcPSD(
50、dBm/Hz)Frequency Offset(MHz)ACPR w/o DPD:-30.1/-27.8dBc-200-150-100-50050100150200-60-50-40-30-20-10010100 MHz LTEPAPR=7.5 dBfC=6.8 GHzPAVG=30.9 dBmDEAVG=49.2%ACPR w DPD:-52.6/-52.5dBcPSD(dBm/Hz)Frequency Offset(MHz)ACPR w/o DPD:-29.2/-33.4dBc5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achievin
51、g 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference32 of 37Modulated Performance 100MHz 64QAM signal,PAPR 7.9dB,w/o DPD1.6GHz:EVM=-33.5dB3.6GHz:EVM=-28.3dB5.0GHz:EVM=-29.4dB6.8GHz:EVM=-33.7dB5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achievi
52、ng 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference33 of 37Modulated Performance Summary 29.1-31dBm PAVG,35%-49.2%DEAVG ACPR w/o DPD -25.3dBc,ACPR w DPD 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits C
53、onference34 of 37ComparisonThis WorkChenIMS22LvTMTT21LvTCASI24GustafssonTMTT14PangJSSC22XiongISSCC19HuangISSCC21ZhuISSCC24Technology250nmGaNGaN250nmGaN250nmGaN250nmGaN250nmGaN40nmCMOS45nmSOI CMOS65nmCMOSArchitectureSLCG-Doherty ContinuumSLCGaDEPADEPAbDohertyDohertyPolar Digital DohertyRole-ExchangeD
54、ohertyLMBASupply(V)15/3016/28282812.5/28281.11/21Freq.(GHz)1.35-7.60.7-2.83.2-5.21.8-5.45.8-8.84.1-5.61.3-3.5d26-6027.8-38.7FBW(%)14012047.61004230.991.77932.9PSAT(dBm)36.6-38.643.1-4540.4-41.741.5-4335-3638.4-39.520.4-21.419.5-22.726.2-27.2DESAT(%)31.5-63.556-70.346-5644.3-5626-45c51.7-60.824.5-31.
55、3c19.4-41.9c25.4-28.8cPBO(dB)6/7.56/7.588966/1266/9DEPBO(%)38-56/37-5445-57.5/40-5335-5038-46.831-39c38.5-46.527.7/16.6c10.2-33.8c19.7-23.2/14-16.3cGain(dB)7.8-138-128.5-11.510-12.58.5-98.3-11.2NA10-17.516.1-17Modulation100MHz LTE40MHzLTE100MHzLTE100MHzLTE20MHz 256QAM100MHz64QAM20MHz LTE800MHz64QAM7
56、50MHz64QAMCarrier Freq.(GHz)1.4-7.60.7-2.83.2-5.21.8-5.45.8-8.84.4/5.21.526-6028/38PAPR(dB)7.57.77.88.58.56.666NAPAVG(dBm)29.1-3136.3-37.833.3-34.133-34.427-27.832.515.211.3-15.817.3/19.2DEAVG(%)35-49.247.8-5035.7-4735-4332-41c42.3/38.625.3c8.5-23.8c13.9/18.2cACPR w/o DPD(dBc)-25.3NA-26.1-24.5-36.6-
57、30.3NA-25.3-32.7/-31.1ACPR w DPD(dBc)-46-47-46-47-46.638%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference35 of 37Outline Introduction SLCG-Doherty-Continuum Power Amplifier Prototype Implementation Measurement Results Conclusion5.1:A GaN SLCG-Dohert
58、y-Continuum Power Amplifier Achieving 38%6dB Back-Off Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference36 of 37Conclusion Simple two-way back-off-efficient PAs with large RF and signal bandwidth are pursued Propose SLCG-Doherty-Continuum PA,combining the merits o
59、f switchless class-G(SLCG)PA and Doherty PA 1.35-7.6GHz demonstration in a 0.25um GaN process38%6dB back-off DECompact chip size of 3.36mm2 Largest fractional bandwidth(140%)among all reported integrated back-off-efficient PAs5.1:A GaN SLCG-Doherty-Continuum Power Amplifier Achieving 38%6dB Back-Off
60、 Efficiency over 1.35 to 7.6GHz 2025 IEEE International Solid-State Circuits Conference37 of 37AcknowledgementThis work was supported in part by the National Science Fund forDistinguished Young Scholars under Grant 62225111 and in part byNational Natural Science Foundation of China(NSFC)under Grant6
61、2071273The authors would like to thank Gaxtrem Technology for chipfabrication and measurement supportThank You5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference1 of 72Spatia
62、l-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased ArrayYutian Zhao1,Yiyang Song1,Weiyan Gu1,Shiyuan Yu1,Zhehao Yu2,Yuxiang Han1,Xinen Zhu3,Xuyang Lu11Shanghai Jiao Tong University,Shanghai,China2University of Pennsylvania,Philadelphia,PA3SGR Se
63、miconductors,Shanghai,China5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference2 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power
64、 Back-offHarmonic Suppression via Switching EngineeringSpatial-Temporal Beamforming Circuit Implementation Measurement Results Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circu
65、its Conference3 of 72Introduction Wireless communication technology is transitioning from coverage and capacity to efficiency dominated.2G3G4G5G6GCapacity Dominated Efficiency DominatedCoverage DominatedNew ModulationSpatial DomainDigital CellularTime200020102020CapacityExpected Energy Consumption5.
66、2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference4 of 72Power Back-off for Advanced ModulationSupplyPeakAveragePowerTransmitted SignalHigh PAPRDissipatedTimePAEBack-offPeakAv
67、erageAverage PowerPeak PowerHigh PAPRClass AB PA efficiency decreases when transmitting high PAPR signals.Back-off efficiency characterizes the efficiency degradation.5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE I
68、nternational Solid-State Circuits Conference5 of 72Power Back-off for Advanced ModulationSupplyPeakAveragePowerTransmitted SignalHigh PAPRDissipatedTimePAEBack-offPeakEnhancedAverageHigh Back-off Efficiency PAAverage PowerClass ABPeak Power PA efficiency decreases when transmitting high PAPR signals
69、.Back-off efficiency characterizes the efficiency degradation.5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference6 of 72Classical Back-off Enhancement TechniquesDohertyOutpha
70、singRFinCouplerMainAuxiliaryZCZT ZPZLRFinPA1PA2ZLSignal Component Separator(SCS)PAEPeakMainAuxiliaryClass ABBack-offIQVmVmIQ()()()()5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits C
71、onference7 of 72Classical Back-off Enhancement TechniquesDissipated as HeatTransmittedSupply VoltageSubharmonic SwitchingPAPAPA3/f0Aoyang Zhang,ISSCC 21ZLEnvelope TrackingLOPADynamic SupplyBasebandEnvelope DetectionZLThese methods continue to improve but are fundamentally limited by the performance
72、of the analog circuits and passives.tPAEPBO(dB)-9.5f0/3f05f0/35.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference8 of 72 Beamforming enhances efficiency by directing signals
73、to specific locations instead of broadcasting them.Spatial Efficiency Improvement via BeamformingBase StationMulti-userBase StationTraditional Base Station AntennaBeamformingAntenna Array5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phas
74、ed Array 2025 IEEE International Solid-State Circuits Conference9 of 72Classical Beamforming ArchitecturesRF BeamformingLOIFPhase ShifterPAPAIFLOPhase ShifterPAPAProposed BeamformingIF BeamformingLimited bandwidthLow complexityLow RF lossWide bandwidthHigh complexityHigh RF lossAgile implementationT
75、unable bandwidthBalanced EfficiencySWRFSWPAPA5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference10 of 72Moores Law Drives Digital ApproachesDigital methods can benefit power
76、back-off and beamforming.fmaxClock SpeedDigitalEnergyChannelLengthTransistorcount“lin”Log197110,000 nm200565 nm201222 nm2024“3 nm”2037“0.5 nm”B.Nauta,“1.2 Racing Down the Slopes of Moores Law,”2024 ISSCC5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency
77、 in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference11 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power Back-offHarmonic Suppression via Switching EngineeringSpatial-Temporal Beamforming Circuit Implementation Measurement Resu
78、lts Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference12 of 72Time Modulation Power Back-off=tttUSWURFUTM5.2:Spatial-Temporal Direct-Digital Beamforming Power Ampl
79、ifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference13 of 72Time Modulation Power Back-off=MagMagMagFreqFreqFreqtttUSWURFUTMfSWfRFfRF+fSW5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficienc
80、y in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference14 of 72Time Modulation Power Back-off=MagMagMagFreqFreqFreqtttUSWURFUTMfSWfRFfRF+fSWReduced5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025
81、IEEE International Solid-State Circuits Conference15 of 72Time Modulation Power Back-off=New Degree of Back-off Back-off can be controlled by duty cycle modulation.MagMagMagFreqFreqFreqtttUSWURFUTMfSWfRFfRF+fSWReduced5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-
82、Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference16 of 72Time Modulation Power Back-off=Unwanted HarmonicsUnwanted harmonics degrade efficiency and pollute the spectrum.MagMagMagFreqFreqFreqtttUSWURFUTMfSWfRFfRF+fSWReduced5.2:Spatial-Temporal Direct-Digit
83、al Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference17 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power Back-offHarmonic Suppression via Switching EngineeringSpat
84、ial-Temporal Beamforming Circuit Implementation Measurement Results Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference18 of 72Harmonic Suppression via Switching En
85、gineeringfRF180 270900 RFinDriver AmplifierVCCTime-modulated PA Array5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference19 of 72Harmonic Suppression via Switching Engineering
86、fRF180 270900 RFinDriver AmplifierVCCTime-modulated PA Array5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference20 of 72Harmonic Suppression via Switching Engineering Modulate
87、d waveforms from all paths are combined to create a quasi-single-frequency signal.fRF180 270900 RFinDriver AmplifierVCCTime-modulated PA ArrayfRF+fSW5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid
88、-State Circuits Conference21 of 72180 270900 RFinDriver AmplifierVCCTime-modulated PA ArrayHarmonic Suppression via Switching EngineeringfRFfRF+fSW Modulated waveforms from all paths are combined to create a quasi-single-frequency signal.5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifie
89、r with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference22 of 72Step 1:Even Harmonic Suppression=CH1tttUSWURFUTMTSW5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025
90、 IEEE International Solid-State Circuits Conference23 of 72Step 1:Even Harmonic Suppression=CH1USWMagtfRF+fSWRFFreq5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference24 of 72
91、=Step 1:Even Harmonic Suppression=CH1=/19%HarmonicEfficiency Harmonic efficiency can be calculated by power spectrum.tfRF+fSWRFFreqUSWMag5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circu
92、its Conference25 of 72=Step 1:Even Harmonic SuppressionCH1CH2=ttFreqfRF+fSWfRF+fSWRF-RFFreqUSWMagUSWMag=/19%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Confere
93、nce26 of 72Step 1:Even Harmonic SuppressionCH1=CH2t1t2=/=ttFreqfRF+fSWfRF+fSWRFFreqUSWMagUSWMag=/19%HarmonicEfficiency-RF5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference27
94、 of 72Step 1:Even Harmonic SuppressionCH1=CH2t1t2=/180=ttFreqfRF+fSWfRF+fSWRFFreqUSWMagUSWMag=/19%HarmonicEfficiency-RF5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference28 o
95、f 72Step 1:Even Harmonic SuppressionCH1CH2t1t2=/180=Two differential channels eliminate all even harmonics.MagttFreqFreqfRF+fSWfRF+fSWfRF+fSWRFFreqUSWMagUSWMag=/45%HarmonicEfficiency-RF19%5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Pha
96、sed Array 2025 IEEE International Solid-State Circuits Conference29 of 72Step 1:Even Harmonic SuppressionCH1CH2S1MagttFreqfRF+fSWRFUSWUSWStep1=/45%HarmonicEfficiency-RF5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE
97、International Solid-State Circuits Conference30 of 72=Step 2:(4k-1)thHarmonic Suppressiont1t2CH1CH2tfRF+fSWS1FreqUSWMag=/45%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State
98、Circuits Conference31 of 72=Step 2:(4k-1)thHarmonic SuppressionCH1CH2CH3CH4t1t2t3t4=ttFreqfRF+fSWfRF+fSWS1FreqUSWMagUSWMag=/45%HarmonicEfficiencyS1905.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid
99、-State Circuits Conference32 of 72=Step 2:(4k-1)thHarmonic SuppressionCH1CH2CH3CH4=/t1t2t3t4=ttFreqfRF+fSWfRF+fSWS1FreqUSWMagUSWMag=/45%HarmonicEfficiencyS1905.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE Internatio
100、nal Solid-State Circuits Conference33 of 72=Step 2:(4k-1)thHarmonic SuppressionCH1CH2CH3CH4=/t1t2t3t4180=ttFreqfRF+fSWfRF+fSWS1FreqUSWMagUSWMag=/45%HarmonicEfficiencyS1905.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEE
101、E International Solid-State Circuits Conference34 of 7245%=Step 2:(4k-1)thHarmonic SuppressionCH1CH2CH3CH4=/t1t2t3t4180=4 orthogonal channels further eliminate(4k-1)thharmonics.MagttFreqFreqfRF+fSWfRF+fSWfRF+fSWS1FreqUSWMagUSWMag=/90%HarmonicEfficiencyS1905.2:Spatial-Temporal Direct-Digital Beamform
102、ing Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference35 of 72Step 2:(4k-1)thHarmonic SuppressionCH1CH2CH3CH4t1t2t3t4S2MagttFreqfRF+fSWS1USWUSW=/90%HarmonicEfficiencyS190Step25.2:Spatial-Temporal Direct-Digital Beamformin
103、g Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference36 of 72=Step 3:-3rdHarmonic Suppressiont1t2t3t4tfRF+fSWS2FreqUSWMag=/90%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced
104、Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference37 of 72=t5t6t7t8Step 3:-3rdHarmonic Suppression=t1t2t3t4ttFreqfRF+fSWfRF+fSWS2-S2FreqUSWMagUSWMag=/90%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Ba
105、ck-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference38 of 72=t5t6t7t8Step 3:-3rdHarmonic Suppression=t1t2t3t4=/ttFreqfRF+fSWfRF+fSWS2FreqUSWMagUSWMag=/90%HarmonicEfficiency-S25.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Ba
106、ck-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference39 of 72=t5t6t7t8Step 3:-3rdHarmonic Suppression=t1t2t3t4=/180ttFreqfRF+fSWfRF+fSWS2FreqUSWMagUSWMag=/90%HarmonicEfficiency-S25.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced
107、 Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference40 of 7290%=t5t6t7t8Step 3:-3rdHarmonic Suppressiont1t2t3t4=/180More harmonics can be eliminated by replicating the channels.MagttFreqFreqfRF+fSWfRF+fSWfRF+fSWS2FreqUSWMagUSWMag=/100%HarmonicEfficienc
108、y-S25.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference41 of 72Digitally Controlled Back-off Waveform High harmonic efficiency back-off modulation waveform can be engineered
109、using 8 channels.ChannelstSW1SW4SW2SW3SW5SW6SW7SW1Tx1Tx2=/19%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference42 of 72Digitally Controlled Back-off Wavefo
110、rm High harmonic efficiency back-off modulation waveform can be engineered using 8 channels.Step1EvenChannelstSW1SW4SW2SW3SW5SW6SW7SW1Tx1Tx2=/45%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE Inter
111、national Solid-State Circuits Conference43 of 72Digitally Controlled Back-off Waveform High harmonic efficiency back-off modulation waveform can be engineered using 8 channels.Step1EvenStep2(4k-1)thChannelstSW1SW4SW2SW3SW5SW6SW7SW1Tx1Tx2=/90%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beam
112、forming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference44 of 72Digitally Controlled Back-off Waveform High harmonic efficiency back-off modulation waveform can be engineered using 8 channels.Step1EvenStep2(4k-1)thStep3
113、-3rdChannelstSW1SW4SW2SW3SW5SW6SW7SW1Tx1Tx2=/100%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference45 of 72Digitally Controlled Back-off WaveformThe harmon
114、ic efficiency remains almost constant until high-order harmonics occupy a significant portion of the total energy.Step1EvenStep2(4k-1)thStep3-3rdChannelstSW1SW4SW2SW3SW5SW6SW7SW1Tx1Tx2=/100%HarmonicEfficiency5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Effic
115、iency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference46 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power Back-offHarmonic Suppression via Switching EngineeringSpatial-Temporal Beamforming Circuit Implementation Measurement
116、 Results Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference47 of 72=Time Modulation Phase Shiftingt1t2t3t4tfRF+fSWA1Freq=/90%HarmonicEfficiencyUSWMag This method a
117、lso enables beamforming by engineering spatial-temporal switching patterns.5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference48 of 72=t5t6t7t8Time Modulation Phase Shifting=
118、t1t2t3t4USWUSWMagttFreqfRF+fSWfRF+fSWA1A1FreqMag5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference49 of 72=t5t6t7t8Time Modulation Phase Shifting=t1t2t3t4=/90High-frequency
119、phase shift can be precisely digitally controlled.ttFreqfRF+fSWfRF+fSWA1A2FreqUSWUSWMagMag5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference50 of 721/fswfRF+fswChannel Group
120、 ntMagFreq1/fswfRF+fswChannel Group 1tMagFreqUSWSpatial-Temporal Beamforming=()Tx1Tx2Tx3Txn(n-1)2Tx1Tx2TxnTx3 Digitally controlled beamforming can be realized by channel expansion similar to a phased array.5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficie
121、ncy in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference51 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power Back-offHarmonic Suppression via Switching EngineeringSpatial-Temporal Beamforming Circuit Implementation Measurement R
122、esults Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference52 of 72Circuit Technique to Enhance Modulation DepthTraditional serial switches introduce insertion loss
123、and leakage.RFinVCCPA5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference53 of 72Circuit Technique to Enhance Modulation Depth Proposed out-of-path switches can reduce inserti
124、on loss.RFinVCCPASwitch Out of Path5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference54 of 72Circuit Technique to Enhance Modulation Depth Off-state cascade mismatch improve
125、s modulation depth.RFinVCCPAPAVCC5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference55 of 72Switching PA UnitThe size ratio between the upper amplifying and lower switching t
126、ransistors can be optimized to reach the best switching power ratio.2468Switching/Amplifying Transistor Size Ratio7.588.59Switching Power RatioSPRmax:8.7Zhehao Yu,TAP 2022RFinVCCPAVCCSW5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased
127、 Array 2025 IEEE International Solid-State Circuits Conference56 of 72Switching Power ModellingPower Loss Model of Switching PA,=,=/()Switching characteristics are modelled to predict efficiency.C1C1Csw IleakVx=VCC“OFF”StageVCCkRFoutkC1C1Csw Vx=0“ON”StageVCCkRFoutkRFin+-RFin+-RswCharged to VCCDischa
128、rged to GND5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference57 of 72STB-PA ChainTwo-stage neutralized PAs with current source switches are used in each channel.Each chip co
129、nsists of four quadrature channels with digitally programmable switching waveforms.RFinRFoutPower Stage 1Power Stage 2VCCVCCVbiasVbiasSWSWx45.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Ci
130、rcuits Conference58 of 72STB-PA Driving Network The driver and 1-to-4 passives provide 6.2(12.2-6)dB gain.RFinVbiasDriver stageQuadrature HybridQuadrature HybridVbVCCRF-RF-RF+RF+5050090180270TlineTline5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency i
131、n a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference59 of 72Chip Photo&PackagingPA 2PA 1DALogicPTATBalanced Quadrature HybridRFinRFout x4SW DataSW Data2.15 mm1.85mmPCB Matching Structure5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off E
132、fficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference60 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power Back-offHarmonic Suppression via Switching EngineeringSpatial-Temporal Beamforming Circuit Implementation Measure
133、ment Results Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference61 of 72Small Signal Performance Connectorized measurement shows 4 orthogonal channels with a 41 dB
134、small signal gain.2022242628Frequency(GHz)-1000100200300Channel Phase(deg)Measured CH1 referred to CH1Measured CH2 referred to CH1Measured CH3 referred to CH1Measured CH4 referred to CH12022242628Frequency(GHz)51015202530354045Small Signal Gain(dB)Simulated S21Measured S21Simulated S31Measured S31Si
135、mulated S41Measured S41Simulated S51Measured S51Connectorized Measurement5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference62 of 72Saturation Performance The measured Psatis
136、 21(15+6)dBm,and the maximum saturated drain efficiency is 25.3%.-5051015Pout(dBm)051015202530Drain Efficiency(%)MeasuredSimulated-5051015Pout(dBm)1520253035Gain(dB)MeasuredSimulated5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Ar
137、ray 2025 IEEE International Solid-State Circuits Conference63 of 72Modulation Waveform Chip 1 and Chip 2 demonstrate a 23.6 dB on-off ratio and the time delays between switching waveforms for each channel.050100150200250300Time(ns)Switched WaveformCH1CH2CH3CH4050100150200250300Time(ns)Switched Wavef
138、ormCH5CH6CH7CH8Chip Tx1Chip Tx21/3 duty cycle23.6 dB On-off Ratio5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference64 of 72Harmonic SuppressionMulti-channel switching demons
139、trates 17 to 43 dB suppression.With 8 paths,the-3rd harmonic can be further eliminated.23.9723.9823.992424.0124.0224.03Frequency(GHz)-30-25-20-15-10-50Normalized Power(dB)UnsuppressedSuppressed23.9723.9823.992424.0124.0224.03Frequency(GHz)-30-25-20-15-10-50Normalized Power(dB)UnsuppressedSuppressed-
140、3rd1st-3rd1st4 paths modulated at 4.167 MHz8 paths modulated at 4.167 MHz5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference65 of 72Harmonic&Total Efficiency The harmonic eff
141、iciency and total efficiency remain near 90%and 20%,respectively,across a wide back-off range.00.20.40.60.8PBO Duty Ratio60708090100Harmonic Efficiency(%)0510152025Total Efficiency(%)8 paths modulated at 4.167 MHzUnsuppressedSuppressed00.20.40.60.8PBO Duty Ratio30405060708090100Harmonic Efficiency(%
142、)0510152025Total Efficiency(%)4 paths modulated at 4.167 MHzUnsuppressedSuppressed6 dB PBO3 dB PBO6 dB PBO3 dB PBO5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference66 of 72I
143、mprovement of Power Back-off Efficiency A peak efficiency improvement of up to 23%is achieved over the-15 dB power back-off range.-16-14-12-10-8-6-4-2Power Back-off(dB)0510152025Total Efficiency(%)4 paths 8.333 MHz8 paths 8.333 MHz4 paths 4.167 MHz8 paths 4.167 MHzUnmodulated(Class AB)23%PBO Efficie
144、ncy Peak5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference67 of 72Measurement SetupBeamforming with harmonic suppression was measured by a spectrum analyzer in an anechoic c
145、hamber.Antenna BoardDC SupplyRF Power SourceSpectrum AnalyzerChip Setup Covered Antenna Board5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference68 of 729060300-30-60-90-92.87
146、-85-70-55-40Power Level(dBm)Angle(Deg)23.987 GHz24.000 GHz24.004 GHz24.008 GHz24.021 GHz9060300-30-60-90-93.70-80-60-40Power Level(dBm)Angle(Deg)23.987 GHz24.000 GHz24.004 GHz24.008 GHz24.021 GHz9060300-30-60-90-92.25-80-60-40Power Level(dBm)Angle(Deg)23.987 GHz24.000 GHz24.004 GHz24.008 GHz24.021 G
147、HzTwo-element Array Beamformingt51tTp/2SW5t11tTp/2SW1Tx1Tx2t51tTp/2SW5t11tTp/2SW1Tx1Tx2t51tTp/2SW5t11tTp/2SW1Tx1Tx2=Targeted at 0Targeted at 30Targeted at-301stHarmonic SuppressionH-planeH-planeH-plane5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency i
148、n a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference69 of 72Communication PerformanceThe system demonstrates 16QAM at 2.5 MSym/s and 32/64QAM at 2 MSym/s.The symbol rate is limited by the USRP measurement setup.6.36%EVM4.25%EVM3.76%EVM5.2:Spatial-Temporal Direct-Digital Bea
149、mforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference70 of 72Comparison TableA temporal domain modulation method for back-off efficiency enhancement with comparable performance.A digitally assisted modulation approa
150、ch can evolve with Moores Law.This work2018 JSSC 1 2017 RFIC 3 2019 JSSC 4 2020 JSSC 5 2019 ISSCC 6 2019 RFIC 7 2022 RFIC 82021 ISSCC 92021 RFIC 10Frequency(GHz)18.9 to 24.430 to 5529 to 5726 to 4427.557601.22.427Process0.18m SiGe0.13m SiGe28nm CMOS0.13m SiGe0.13m SiGe45nm CMOSSOI45nm CMOSSOI45nm CM
151、OSSOI40nm CMOS28nm CMOSArchitectureST-BPAMultibanddohertyBroadbandseries powercombinerMultibanddohertySingle-InputLinear Chireix(SILC)3-way on-antennaDohertyCoupler-basedDohertyHybrid modedigitialDohertyQuadratureSFCPA withhybrid Dohertyand impedanceboostingParallel-seriescombinedDohertyPsat(dBm)212
152、3.716.617.11921.220.121.830.318.8Max (%)2328.53525.13421.82633.841.336 3dB-PBO(%)202433192717.52029.737.531.6 6dB-PBO(%)1617.530172319.516.820.336.127.1 9dB-PBO(%)11122610.8161814.912.830.919.5Supply(V)3.3/1.84.0/1.60.91.54.3221.1/2.21.2/2.41.8Area (mm2)3.98(4 channels)1.760.161.760.563.610.765.092.
153、20.4155.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference71 of 72Outline Introduction Spatial-Temporal Direct-Digital Beamforming PA Time Modulation Power Back-offHarmonic Su
154、ppression via Switching EngineeringSpatial-Temporal Beamforming Circuit Implementation Measurement Results Conclusion5.2:Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array 2025 IEEE International Solid-State Circuits Conference72 of
155、72Conclusion This work demonstrates a new degree of freedom for high-efficiency back-off using digital switching and can be integrated with conventional methods at mmWave and THz frequencies.This approach eliminates the need for complex RF-band phase shifters using a flexible modulation frequency ne
156、ar IF and facilitates straightforward expansion for beamforming.2025 IEEE International Solid-State Circuits Conference1 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMO
157、SA 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSDeshan Tang,Bingzheng Yang,Aoran Han,and Xun LuoBEAM X-LAB,UESTC,China 2025 IEEE International Solid-State Circuits Conference2
158、of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architec
159、ture of 4-Way Sub-PA PA Implementation Measurement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference3 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in
160、40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architecture of 4-Way Sub-PA PA Implementation Measurement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference4 of 525.3:A 56-to-64GHz Linear Po
161、wer Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSIntroductionPower Amplifier(PA)is a critical building block in any wireless transmitterPersistent PA challenges:High output power&high efficiencyV-band
162、CMOS mm-wave PAs:30.1dBm Psat(CMOS_SOI),25dBm Psat(CMOS_bulk)Goal:Watt-level V-band PA with high efficiency in bulk CMOS505560657075805101520253035Frequency(GHz)Psat(dBm)CMOS_BulkCMOS_SOITrend of CMOS_bulkhttps:/ideas.ethz.ch/research/surveys/pa-survey.html 2025 IEEE International Solid-State Circui
163、ts Conference5 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSSingle Power Combining TechniquesVoltage-Mode Power CombiningCompact layout in implementationUltra low in
164、put impedance with the increasing number of sub-PAInherent imbalance with deteriorated power and efficiencyPA-CoreSub-PA mZSub-PAPA-CoreSub-PA 2ZSub-PARLPA-CoreSub-PA 1ZSub-PAPA-CoreSub-PA nZSub-PAPA-CoreSub-PA 2ZSub-PAPA-CoreSub-PA 1ZSub-PARLCurrent-Mode Power CombiningSymmetric layout with low imb
165、alanceUltra high input impedance with the increasing number of sub-PAAdditional routing for combining 2025 IEEE International Solid-State Circuits Conference6 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining w
166、ith EM-Loss Reduction in 40nm Bulk CMOSSub-PA 1RLSub-PA 2Sub-PA 2n-1Sub-PA 2nStage 1Stage nStage 1Single Power Combining TechniquesBinary Wilkinson Power CombiningConveniently configured input impedanceLarge routing loss due to the multi-stage transmission lines.Large circuit size due to the quarter
167、-wavelength transmission lines.DAT Power CombiningArea-efficient layout with sharing dc supplyInherent load mismatch due to inter-winding capacitorInherent phase mismatch due to the comparable DAT size to wavelengthRLPA-Core 2PA-Core 3PA-Core 1PA-Core 4 2025 IEEE International Solid-State Circuits C
168、onference7 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSHybrid Power Combining TechniquesAntenna&Current-Mode Power Combining(16-way)Direct antenna-based combining a
169、nd impedance transformingNarrow operation bandwidthUltra large size for on-chip antenna Asymmetric DAT&Binary Wilkinson Power Combining(48-way)Reduced imbalance and improved efficiency by asymmetric DAT Complex design equations with limited impedance transforming abilityLarge size of combinerRL1 T.C
170、hi,ISSCC172 H.T.Nguyen,ISSCC19 2025 IEEE International Solid-State Circuits Conference8 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Ma
171、tched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architecture of 4-Way Sub-PA PA Implementation Measurement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference9 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpea
172、kUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS12V/mRL(V,I)m12m12m1212nVsIsEM-loss-reduced impedance inverter(1:b)12aVi IiVcv IcvPA-CorePA-Core1:nXFMR1:nXFMRVcIcSub-PASub-PAEM-loss-reduced XFMRVp IpScalable Matched-Zone-Expanding Architecturem-w
173、ay voltage-mode power combining using EM-loss-reduced XFMRn-way current-mode power combining to impedance inverterEM-loss-reduced impedance inverter for flexibly-configuring matched zonea-way current-mode power combining to load 2025 IEEE International Solid-State Circuits Conference10 of 525.3:A 56
174、-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS12V/mRL(V,I)m12m12m1212nVsIsEM-loss-reduced impedance inverter(1:b)12aVi IiVcv IcvPA-CorePA-Core1:nXFMR1:nXFMRVcIcSub-PASub-PAEM-loss
175、-reduced XFMRVp IpScalable Matched-Zone-Expanding ArchitectureLarge Pout=mnaPsub-PAZsub-PA=Vs/Is=(n/m)(a/b)RLZPA-Core=Vp/Ip=(n/m)(a/b)RL/nXFMR2 2025 IEEE International Solid-State Circuits Conference11 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matc
176、hed-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS Pout versus ZPA-corePoutZPA-coreRL0 Psub-PAm(or n)Psub-PAMatched ZoneMismatched ZoneCurrent-Mode Power CombiningVoltage-Mode Power Combining PoutZPA-coreRL0 Psub-PAmnPsub-PAHybrid Power Combiningm=1,n=1,2,3.m=2,n=2,3,
177、4.n=2,m=2,3,4.n=1,m=1,2,3.Matched ZoneMismatched ZonePoutZPA-coreRL0 Psub-PAmnaPsub-PAProposed CombiningMatched Zonem=1,n=1,2,3.m=2,n=2,3,4.n=2,m=2,3,4.n=1,m=1,2,3.Impedance transforming ability of XFMRImpedance transforming ability of n to 1 inverter(a/b)Larger Power with More Matched-Zone Selectio
178、nn=1,2,3.m=1,2,3.Scalable Matched-Zone-Expanding Architecture Comparison of voltage-mode,current-mode,hybrid voltage-and current-mode power combining schemes with proposed architecture 2025 IEEE International Solid-State Circuits Conference12 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dB
179、m Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS12V/mRL(V,I)m12m12m1212nVsIsEM-loss-reduced impedance inverter(1:b)12aVi IiVcv IcvPA-CorePA-Core1:nXFMR1:nXFMRVcIcSub-PASub-PAEM-loss-reduced XFMRVp IpScalable Matched-Zone-Expa
180、nding ArchitectureLarge Pout=mnaPsub-PAZsub-PA=Vs/Is=(n/m)(a/b)RLZPA-Core=Vp/Ip=(n/m)(a/b)RL/nXFMR2Scalable large power combining with flexibly-configuring ZPA-Corefor different Zopt 2025 IEEE International Solid-State Circuits Conference13 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm
181、Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSScalable Floorplan of Proposed Architecture12V/mRL(V,I)m12m12m1212nVsIsEM-loss-reduced impedance inverter(1:b)12aVi IiVcv IcvRLCurrent flow1m1m1m12n1m3PA-CorePA-CoreaRL1:nXFMR1:nX
182、FMRVcIcSub-PASub-PAEM-loss-reduced XFMRVp IpSub-Power-Combining CellTotal-Power-Combining SchemeCircular distribution for conveniently increasing m,n,and a without affecting the balance of the circuit.2025 IEEE International Solid-State Circuits Conference14 of 525.3:A 56-to-64GHz Linear Power Ampli
183、fier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architecture of 4-Way Sub-PA PA Implementation Me
184、asurement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference15 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS m=2a=2b=4Design Example o
185、f 32 to 1 Power Combiner m=2,n=4,a=2,b=44-to-1 impedance inverter combiner4-to-1 voltage-mode combiner 2025 IEEE International Solid-State Circuits Conference16 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining
186、 with EM-Loss Reduction in 40nm Bulk CMOSDesign of 4-to-1 voltage-mode combiner Conventional octagonal configuration with inverse current coupling(I.C.C)VDDVDDin+inin+inout+outCurrent directionM7M8VDDVDDin+inin+inout+outCurrent direction3 L.Zhang,TMTT23 2025 IEEE International Solid-State Circuits C
187、onference17 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSDesign of 4-to-1 voltage-mode combiner Conventional octagonal configuration with inverse current coupling(I.
188、C.C)Current directionQI.C.C_L1,L2=(1-kp1,p2)QL1,L2+PAPA+PAPA+PAPAkp1kp2kp1kp2kp1L1L2kp1,p2QI.C.C_L1,L2 2025 IEEE International Solid-State Circuits Conference18 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining
189、 with EM-Loss Reduction in 40nm Bulk CMOS4050607080657075808590Outer Passive efficiency(%)Frequency(GHz)with inverse-current-coupling(I.C.C)w/o inverse-current-coupling(I.C.C)5%improvementwith inverse-current-coupling(I.C.C)Design Example of 32 to 1 Power Combiner Passive efficiency comparison4-to-1
190、 voltage-mode combinerTotal combiner4-to-1 impedance inverter combiner 2025 IEEE International Solid-State Circuits Conference19 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm
191、Bulk CMOSDesign of 4-to-1 voltage-mode combiner Proposed straight configuration without inverse current coupling(I.C.C)PAPAPAPACurrent direction 2025 IEEE International Solid-State Circuits Conference20 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Mat
192、ched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSDesign Example of 32 to 1 Power Combiner Passive efficiency comparison4-to-1 voltage-mode combinerTotal combiner4-to-1 impedance inverter combiner4050607080657075808590Outer Passive efficiency(%)Frequency(GHz)with inv
193、erse-current-coupling(I.C.C)w/o inverse-current-coupling(I.C.C)5%improvement+2025 IEEE International Solid-State Circuits Conference21 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in
194、 40nm Bulk CMOS4050607080-160-80080160Impedance()(1)Re(Zin)Im(Zin)Frequency(GHz)Con.Re(Zin)Im(Zin)ZInv,1Zpath=Zin_sourcein1in2in3in4outDesign of 4-to-1 impedance inverter combiner Conventional quarter-wavelength inverterZinv=(Zin_sourceZRFout)1/2,1=90with single frequency impedance transformation4 K
195、.Datta,JSSC17 2025 IEEE International Solid-State Circuits Conference22 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS4050607080-160-80080160Con.Pro.Re(Zin)Im(Zin)Re(
196、Zin)Im(Zin)Frequency(GHz)Impedance()Design of 4-to-1 impedance inverter combiner Proposed resonator-loaded inverterZInv,1+outin1in2in3in4CZpathZr,rZinv(Zin_sourceZRFout)1/2,ZpathZin_source,180%13%improvement(1.2)w/o L.R&with I.C.Cwith L.R&w/o I.C.C4050607080657075808590Inner Passive efficiency(%)Fre
197、quency(GHz)w/o loaded-resonator(L.R.)with loaded-resonator(L.R.)10%improvement4050607080657075808590Outer Passive efficiency(%)Frequency(GHz)with inverse-current-coupling(I.C.C)w/o inverse-current-coupling(I.C.C)5%improvement+=2025 IEEE International Solid-State Circuits Conference29 of 525.3:A 56-t
198、o-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architecture of 4-Way S
199、ub-PA PA Implementation Measurement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference30 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS
200、Architecture of 4-Way Sub-PA 2025 IEEE International Solid-State Circuits Conference31 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSHybrid Efficiency-Boosting Networ
201、k in PA Stage50556065702025303540Frequency(GHz)Load-pull PAE(%)W/o inductorSeries onlyParallel onlyHybridOut+OutIn+InSeriesSeriesParallel240/40n80f80fThe hybrid series and parallel inductors achieves better impedance matching between CS and CG stage compared to separate series and parallel inductors
202、 2025 IEEE International Solid-State Circuits Conference32 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSCoupled-Resonator-Based Matching NetworkCoupled-resonator-mod
203、el includes all parasitic parameters in the layout:Corresponding,Q,k to schematic and bandwidth decompression Ideal Ideal Separated L&C Frequency Layout extracted:mismatch due to parasitic S11 of singly loaded resonator Frequency Layout extracted:parasitic included in resonator 1,2 0 90901,2(90)1,2(
204、90)Q1,2=1,2/(1,2(90)1,2(90)Layout modeled by separated LC:bandwidth compressionLayout modeled by coupled resonator:bandwidth decompressionorTraditional LC-separate-model ignores multiple parasitic parameters in the layout:L,C,k mismatch to schematic and bandwidth compression 2025 IEEE International
205、Solid-State Circuits Conference33 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSPort1Port2VDDVDDPort3kr1,Q12,Q2krM7M6Coupled-Resonator-Based Matching Network505560657
206、0-14-46Layout modeled by coupled-resonator Layout modeled by separated LCIdeal schematicFrequency(GHz)Power Gain(dB)Compressed bandwidth Decompressed bandwidth Ideal bandwidth Interstage matching network between driver stage 1 and 2 2025 IEEE International Solid-State Circuits Conference34 of 525.3:
207、A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSPort2Port1M7M6M82,Q21,Q1kr5055606570-14-12-10-8-6-4-20Layout modeled by coupled-resonator Layout modeled by separated LCIdeal sch
208、ematicFrequency(GHz)|S21|(dB)Compressed bandwidth Ideal bandwidth Decompressed bandwidth Coupled-Resonator-Based Matching Network Interstage matching network between driver stage 1 and power divider 2025 IEEE International Solid-State Circuits Conference35 of 525.3:A 56-to-64GHz Linear Power Amplifi
209、er with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architecture of 4-Way Sub-PA PA Implementation Meas
210、urement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference36 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSTop-level Schematic of PA Pr
211、ototypeRFinZtrans2,trans2Ztrans3,trans3Ztrans1,trans1Z/4_1,/4_1=90 Z/4_1,/4_1=90 Ztrans1,trans1Z/4_2,/4_2=90 Ztrans2,trans2Ztrans3,trans34-waysub-PA4-waysub-PA4-waysub-PA4-waysub-PA4-waysub-PA4-waysub-PA4-waysub-PA32-to-1 power combiner with EM-loss reduction4-waysub-PA 2025 IEEE International Solid
212、-State Circuits Conference37 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSPrototype Implementation2.6mm2.1mm2.3mm1.8mm32-to-1 Scalable Radial Power Combiner with EM-
213、Loss ReductionInputCoupled-Resonator-Modeled Interstage Matching Network4-Way Sub-PA OutputResonator-Loaded InverterConventional 40nm bulk CMOS processSupply:2.4/1.2V4.1mm2core area5.5mm2die area 2025 IEEE International Solid-State Circuits Conference38 of 525.3:A 56-to-64GHz Linear Power Amplifier
214、with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Combiner with EM-Loss-Reduction Architecture of 4-Way Sub-PA PA Implementation Measure
215、ment and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference39 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSPower MeterSi gnal G ener atorO
216、n/Off789456123.0-AttenuatorDUTGSGGSGSignal GeneratorMultiplierTunableAttenuator4AttenuatorDUTGSGGSGSignal GeneratorSpectrum AnalyzerHarmonic MixerAmplifierMixerArbitrary Waveform GeneratorIFLORFSignal GeneratorLO/6RFIFLarge-signal continuous-wave measurement setupLarge-signal modulation measurement
217、setupMeasurement Setup 2025 IEEE International Solid-State Circuits Conference40 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSVector Network AnalyzerMicrograph of DU
218、TSupplyS-Parameter SetupDUTMeasurement Setup 2025 IEEE International Solid-State Circuits Conference41 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSModulation SetupS
219、upplyArbitrary Waveform GeneratorMultiplierMixerAmpliferAttenuatorSignal GeneratorSpectrum AnalyzerSignal GeneratorDUTMeasurement Setup 2025 IEEE International Solid-State Circuits Conference42 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone
220、-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSSmall-Signal and Large-Signal CW Results5355575961636567-50-40-30-20-1001020305052545658606264665101520253035Frequency(GHz)S-parameter(dB)|S21|S11|S22|S12|BW3dB:56 to 64GHzPsat(dBm)&PAEpeak(%)Frequency(GHz)PAEpeakPsatBW1dB:55
221、to 63GHzPeak small-signal gain:23.5dB3dB bandwidth:56 to 64GHzPeak Psat:30.2dBmPeak PAE:23.5%2025 IEEE International Solid-State Circuits Conference43 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-L
222、oss Reduction in 40nm Bulk CMOSPeak Psat:30.0dBm,OP1dB:27.7dBmPeak PAE:23.5%,PAEOP1dB:16.0%10121416182022242628303205101520251012141618202224262830320510152025Output Power(dBm)Power Gain(dB)&PAE(%)PAEPGainf=58GHzPsat=30.0dBmOP1dB=27.7dBmPAEpeak=23.5%PAEOP1dB=16.0%Output Power(dBm)Power Gain(dB)&PAE(
223、%)PGainPAEf=60GHzPsat=30.2dBmOP1dB=28.9dBmPAEpeak=23.1%PAEOP1dB=20.4%Large-Signal CW ResultsPeak Psat:30.2dBm,OP1dB:28.9dBmPeak PAE:23.1%,PAEOP1dB:20.4%2025 IEEE International Solid-State Circuits Conference44 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scala
224、ble Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSModulation ResultsSingle-carrier 4Gb/s 256QAMf=60GHz Baud Rate=500MSym/s Roll-off factor=0.35 Pavg=21.4dBmEVM=28.1dBSingle-carrier 3Gb/s 64QAMEVM=26.2dBf=60GHz Baud Rate=500MSym/s Roll-off factor=0.35 Pavg=23.5
225、dBm 2025 IEEE International Solid-State Circuits Conference45 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSModulation ResultsEVM=29.0dBEVM=28.9dBEVM=27.2dBEVM=25.8dB
226、Carrier1f=58.8GHz Pavg=13.0dBmCarrier2f=59.6GHz Pavg=13.6dBmCarrier3f=60.4GHz Pavg=16.8dBmCarrier4f=61.2GHz Pavg=16.5dBmCarrier1Carrier2Carrier3Carrier44-carrier 42.4Gb/s 64QAM Baud Rate=4400MSym/s 2025 IEEE International Solid-State Circuits Conference46 of 525.3:A 56-to-64GHz Linear Power Amplifie
227、r with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSComparison 2025 IEEE International Solid-State Circuits Conference47 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable M
228、atched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSComparison50556065707580510152025303551015202530350510152025303540Frequency(GHz)Psat(dBm)PAE(%)Psat(dBm)CMOS_BulkCMOS_SOICMOS_BulkCMOS_SOITrend of CMOS_bulkThis workThis workTrend of CMOS_bulk 2025 IEEE Internationa
229、l Solid-State Circuits Conference48 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSOutline Introduction Scalable Matched-Zone-Expanding Architecture 32 to 1 Power Comb
230、iner with EM-Loss-Reduction Architecture of 4-Way Sub-PA PA Implementation Measurement and Comparison Conclusion 2025 IEEE International Solid-State Circuits Conference49 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power
231、 Combining with EM-Loss Reduction in 40nm Bulk CMOSConclusion Scalable matched-zone-expanding radial power combinerwith EM-loss-reduction for Watt-level and efficient PA implemented in 40nm bulk CMOS Hybrid efficiency-boosting network in cascode PA core Coupled-resonator-based interstage matching ne
232、twork to avoid bandwidth compression between schematic and layout 2025 IEEE International Solid-State Circuits Conference50 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk
233、CMOSReferences1 T.Chi et al.,“A 60GHz on-chip linear radiator with single-element 27.9dBm Psat and 33.1dBm peak EIRP using multifeed antenna for direct on-antenna power combining,”inIEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2017,pp.296297.2 H.T.Nguyen,D.Jung,and H.Wang,“A 60GHz C
234、MOS power amplifier with cascaded asymmetric distributed-active-transformer achieving watt-level peak output power with20.8%PAE and supporting 2Gsym/s 64-QAM modulation,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2019,pp.9091.3 L.Zhang,K.Ma,and H.Fu,“A 60-GHz 32-way hybrid powe
235、r combination power amplifier in 55-nm Bulk CMOS,”IEEE Trans.Microw.Theory Techn.,vol.71,no.2,pp.613627,Feb.2023.4 K.Datta and H.Hashemi,“Watt-level mm-wave power amplification with dynamic load modulation in a SiGe HBT digital power amplifier,”IEEE J.Solid-State Circuits,vol.52,no.2,pp.371388,Feb.2
236、017.5 U.R.Pfeiffer and D.Goren,“A 23-dBm 60-GHz distributed active transformer in a silicon process technology,”IEEE Trans.Microw.Theory Techn.,vol.55,no.5,pp.857865,May 2007.6 T.S.D.Cheung and J.R.Long,“Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated c
237、ircuits,”IEEE J.Solid-State Circuits,vol.41,no.5,pp.11831200,May 2006.7 J.Li et al.,“A transformer-based quadrature doherty digital power amplifier with 4.1 W peak power in 28 nm bulk CMOS,”IEEE J.Solid-State Circuits,vol.58,no.12,pp.32963307,Dec.2023.8 A.Sarkar,F.Aryanfar,and B.A.Floyd,“A 28-GHz Si
238、Ge BiCMOS PA with 32%efficiency and 23-dBm output power,”IEEE J.Solid-State Circuits,vol.52,no.6,pp.16801686,Jun.2017.9 K.Kim et al.,“Analysis and design of multi-stacked FET power amplifier with phase-compensation inductors in millimeter-wave band,”IEEE Trans.Microw.Theory Techn.,vol.71,no.5,pp.187
239、71889,May 2023.10 Y.Chang,Y.Wang,C.-N.Chen,Y.-C.Wu,and H.Wang,“A V-band power amplifier with 23.7-dBm output power,22.1%PAE,and 29.7-dB gain in 65-nm CMOS technology,”IEEE Trans.Microw.Theory Techn.,vol.67,no.11,pp.44184426,Nov.2019.11 M.Pashaeifar,A.Kumar Kumaran,L.C.N.de Vreede,and M.S.Alavi,“A ch
240、ain-weaver balanced power amplifier with an embedded impedance/power sensor,”IEEE J.Solid-State Circuits,vol.59,no.12,pp.39383951,Dec.2024.12 X.Zhang,H.Guo,and T.Chi,“A millimeter-wave four-way doherty power amplifier with over-GHz modulation bandwidth,”IEEE J.Solid-State Circuits,vol.59,no.12,pp.38
241、983914,Dec.2024.13 X.Zhang,S.Li,D.Huang,and T.Chi,“A millimeter-wave three-way Doherty power amplifier for 5G NR OFDM,”IEEE J.Solid-State Circuits,vol.58,no.5,pp.12561270,May 2023.2025 IEEE International Solid-State Circuits Conference51 of 525.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psa
242、tand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSAcknowledgmentThe authors thank the support of Shenzhen Science andTechnology Program under Grant JCYJ20210324120004013.2025 IEEE International Solid-State Circuits Conference52 of 5
243、25.3:A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psatand 23.5%PAEpeakUsing Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOSThank you for your attention!5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-base
244、d Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference1 of 17A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 ApplicationsJooseok Lee,Hansik Oh,Seun
245、gjae Baek,Seungwon Park,Dongsoo Lee,Sehyug Jeon,Taewan Kim,Joonho Jung,and Sung-gi YangSamsung Electronics5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Ci
246、rcuits Conference2 of 17Outline Motivation Circuit Configuration Implementation and measurementS-parameter&Large signalReliability testModulation(5G NR FR2 64-QAM)Performance comparison Conclusions5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias S
247、cheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference3 of 17Motivation:High EIRP 70 dBmArray SizeArray Gain(dB)PA POUTafter SW(dBm)GANT(dBi)Loss(dB)PVT margin(dB)Dual pol.Total EIRP(dBm)RFIC 2019256489413No57 JSSC 2022384529413Yes(+3 dB)64 ISSCC
248、 20243845212413Yes(+3 dB)67 This Work3845215413Yes(+3 dB)70 High EIRP wide coverage For EIRP 70 dBm Higher POUTPA is requiredOur previous works for 5G FR2 base-station5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgf
249、or 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference4 of 17Previous Work DBPO Doherty PA(2-stack)Excellent PAEAVG(17.1%)PAVG(12 dBm)needs to be higher!Ultra compact size(0.14 mm2)RFoutPVDD,DRFinCbypDohertyoutputnetworkDriverCarrierPeakingPhase OffsetTF1TF2TF3Higher PAVG!H.O
250、h,ISSCC 2024Differential-Breaking Phase Offset5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference5 of 17 Maintaining ROPT(50),3-stack PA(vs.
251、2-stack)Obtain 1.5 VOUT SwingCan use 1.5 W/L(1.5 IOUT)Achieve1.52POUT(+3.5 dB)3-stack PAVINVG1VS1VDD=2.4 VVOUTW/LW/LVINVG1VG2VS1VS2VDD=3.6 VVOUT1.5W/L1.5W/L1.5W/L ChallengingComplex bias pointLarger parasitic capacitance Bandwidth limitation PAE 5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty
252、Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference6 of 173-stack PA with OPA-based bias schemeVDSconsistently stays at 1.2 V(=VMain/3)0.7 dB boost in PSATBetter reliability 5.4:A 22-nm FD-SOI C
253、MOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference7 of 17Circuit SchematicDBPOSingle-TF DohertyWide inter-stageSeries inductorsH.Oh,ISSCC 2024H.Park,JSCC 20225
254、.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference8 of 17ImplementationGNDVDrv1.2 VVAna1.8 VGNDVMain3.6 VVMain3.6 VGNDGNDVDrv1.2 VVDrv1.2 VG
255、NDVMain3.6 VVMain3.6 VGNDGNDGNDINOUTGNDGNDCarrier cellPeaking cellTF1LDBPOTF2TF3LQLQTF4Lser1Lser2Lser1Lser2Lser1Lser2Lser1Lser2Driver cell280 m540 m GF 22nm FDSOI Core size:0.151 mm25.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving
256、 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference9 of 17Measurement Setup5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Sol
257、id-State Circuits Conference10 of 17Measurements:S-parameter&Large Signal CW5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference11 of 17Measu
258、rements:Reliability TestDie temperature:105 C/VDrv=1.32 V(+10%)/VMain=4.4 V(+20%).PIN=15 dBm,POUT=PSAT,f0=27 GHzPSATIMainIDrv During 1000 HrsPSAT:-0.5 dBIMain:-4%IDrv:-5%5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pa
259、vgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference12 of 17Measurements:Modulation(5G NR FR2 64-QAM)5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE Inte
260、rnational Solid-State Circuits Conference13 of 17Measurements:Summary CW PSAT:23.0 to 24.1 dBmPAEmax:22 to 25%1 CC(100 MHz)Pavg:16.5 to 17.1 dBmPAEavg:15.9 to 16.8%8 CC(100 MHz)Pavg:16.0 to 16.8 dBmPAEavg:14.7 to 15.8%5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Sta
261、cked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference14 of 17Measurements:Summary5G NR OFDM 1-CC w/EVM=-25 dB,f0=24 30 GHz+3.3 dB5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-base
262、d Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference15 of 17Comparison Table5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025
263、 IEEE International Solid-State Circuits Conference16 of 17Conclusion In this work,the output power was improved by applying a 3-stack structure to a compact Doherty PA A stacked OPA was proposed to provide optimal bias for the 3-stack PA The proposed PA is expected to become a crucial building bloc
264、k for expanding coverage in 5G FR2 NR applications5.4:A 22-nm FD-SOI CMOS-based Compact 3-Stack Doherty Power Amplifier with the Stacked OPA-based Bias Scheme Achieving 16.5 dBm Pavgfor 5G FR2 Applications 2025 IEEE International Solid-State Circuits Conference17 of 17References1 H.Oh et al.,A 24.25
265、-to-29.5GHz Extremely Compact Doherty Power Amplifier with Differential-Breaking Phase OffsetAchieving 23.7%PAEavgfor 5G Base-Station Transceivers,ISSCC,pp.522-524,Feb.2024.2 H.-C.Park et al.,Single Transformer-based Compact Doherty Power Amplifiers for 5G RF Phased-array ICs,IEEE JSSC,vol.57,no.5,p
266、p.1267-1279,May 2022.3 E.Liu et al.,An Ultra-Compact 28GHz Doherty Power Amplifier with an Asymmetrically-Coupled-Transformer OutputCombiner,ISSCC,pp.536-538,Feb.20244 J.Yun et al.,A 5G FR2 n260/n259 Phased-Array Transmitter Front-End IC in 28-nm CMOS FD-SOI with 3-Stack PowerAmplifier Employing OPA
267、-Based Bias Scheme and Cross-Tied Inductor Topology,IEEE RFIC,pp.267-270,Jun.20245 E.Garay et al.,A mm-Wave Power Amplifier for 5G Communication Using a Dual-Drive Topology Exhibiting a Maximum PAEof 50%and Maximum DE of 60%at 30GHz,ISSCC,pp.258-259,Feb.20216 H.-W.Choi et al.,Highly Linear Ka-Band C
268、MOS Linear Power Amplifier Using T-Shape Linearizer With pMOS,IEEE MWTL,vol.33,no.8,pp.1179-1182,Aug.2023.7 M.Pashaeifar et al.,A Millimeter-wave CMOS Series-Doherty Power Amplifier With Post-silicon Inter-stage PassiveValidation,IEEE JSSC,vol.57,no.10,pp.2999-3013,Oct.2022.5.5 An Ultra-Compact Wide
269、band Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference1 of 36An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Res
270、ilient Operations in Large-Scale Phased ArraysMohamed Eleraky1,Tzu-Yuan Huang1,2,Hua Wang11ETH Zrich,Zrich,Switzerland2ARGUS SPACE AG,Zrich,Switzerland5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased
271、 Arrays.2025 IEEE International Solid-State Circuits Conference2 of 36Outline Introduction Why S22 Matters Prototype Implementation Measurement Results Conclusion5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-S
272、cale Phased Arrays.2025 IEEE International Solid-State Circuits Conference3 of 36Introduction VSWR varies with:,Frequency,Position on the Array.EX:Active S11 for 44 Patch Array =0fminfmaxVSWR 2:1*fmax and fmin are within 5%of fcenter5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-N
273、eutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference4 of 36Introduction VSWR varies with:,Frequency,Position on the Array.This challenges PA design,impacting OP1dB,PG,and PAE.fminfmaxEX:Active S11 for 44 Pat
274、ch Array =605.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference5 of 36Introduction VSWR 4:1+j0.2-J2-j5+j2-j1-j0.5-j0.20+j1+j0.5+j5PG Deviat
275、ion-5-4-3-2-1 012 Simulated Common Source PA under 4:1 VSWR condition exhibits an 8 dB PG deviation.This complicates the phased array calibration.(dB)5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased
276、Arrays.2025 IEEE International Solid-State Circuits Conference6 of 36Introduction:State-of-the-Art SolutionsThese solutions trade off VSWR resilience,form factor,and efficiency.We propose a PA with good S22 output matching to mitigate VSWR without comprising large signal performance.Limited Efficien
277、cy ComplicatedLLLLOut Matching NWPACoreSlices/Bias Sensor LUT recover(OP1dB,.)Area/Matching LossJJKKReconfig.CoreVSWR Resilience I/V Sensing Balanced PA True VSWRresilience Wide BW isolation Matching Loss Coupler mismatchPAE/OP1dB Area/ComplicatedJJJJKKLLLLVoutCoupledThruIsolationPAPARjX VinPAPAVSWR
278、123 Ant./PAdecoupled True VSWRresilience JJJJ Bulky/Lossy PAE/OP1dB LLHigh Matching LossCirculatorLLReconfigurable PAIsolation5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE Interna
279、tional Solid-State Circuits Conference7 of 36Outline Introduction Why S22 Matters Prototype Implementation Measurement Results Conclusion5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 I
280、EEE International Solid-State Circuits Conference8 of 36Why S22 Matters?PinAntennaPA VSWRPinAntennaPA VSWRPinAntennaPA VSWRPinAntennaPA VSWRMutual Coupling1)Power delivered to the Antenna:antaantbantPinS21S12S11b1a1a2b2PAS22Antenna VSWRSignal Flow Chart2)Undesired varying phase added:Load Pull(S22 V
281、SWR Vulnerable PA Load Pull with(S22 VSWR ResilienceJJLL5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference9 of 36Why S22 Matters?anta222n2
282、t22S2antantS-12SSsin(+)|=tan|oc)s(+-1a2222221antintantnPS|S|(1|-|)=P|-|1PinAntennaPA VSWRPinAntennaPA VSWRPinAntennaPA VSWRPinAntennaPA VSWRMutual Coupling1)Power delivered to the Antenna:antaantbantPinS21S12S11b1a1a2b2PAS22Antenna VSWRSignal Flow Chart2)Undesired varying phase added:Load Pull(S22 V
283、SWR Vulnerable PA Load Pull with(S22 VSWR ResilienceJJLL5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference10 of 36PinAntennaPA VSWRPinAnte
284、nnaPA VSWRPinAntennaPA VSWRPinAntennaPA VSWRMutual Coupling1)Power delivered to the Antenna:antaantbantPinS21S12S11b1a1a2b2PAS22Antenna VSWRSignal Flow Chart2)Undesired varying phase added:Load Pull(S22 VSWR Vulnerable PA Load Pull with(S22 VSWR ResilienceJJLLanta222n2t22S2antant2S-1SSsin(+)|cos(+)|
285、=tan|-1|Why S22 Matters?a2222221antintantnPS|S|(1|-|)=P|-|15.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference11 of 36Outline Introduction
286、Why S22 Matters Prototype Implementation Measurement Results Conclusion5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference12 of 36Proposed
287、Complex Cascode LC NeutralizedM2LserCDSNLserM1Common SourceCommon GateVBG1VBG2CDSN5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference13 of
288、36Proposed Complex Cascode LC NeutralizedM2LserCDSNLserM1Common SourceCommon GateVBG1VBG2CDSNM2LserCDS2CDSN1:1CGS2CDS1Shunt-Shunt-ve FB Zout(Co,Ro)Better S22 Higher order Neut.NW5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Opera
289、tions in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference14 of 36Proposed Complex Cascode LC NeutralizedM2LserCDSNLserM1Common SourceCommon GateVBG1VBG2CDSN-5-4-3-2-1 012-j0.2+j0.5+j0.2VSWR 4:1-J2-j5+j2-j1-j0.50+j1+j5EM simulated PG Deviation The proposed PA exhibits
290、 3 dB PG deviation.(dB)PG Deviation 5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference15 of 36Prototype Implementation PADriverGSGZe,Zo,CL
291、Z0,TL Ze,Zo,CLZ0,TL VDDVDDGSG1.6V1.6VCm5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference16 of 36Prototype Implementation M2VBG1VBG264 fF6
292、4 fF4822m 20nm 29 pH29 pH4822m 20nm PADriverGSGZe,Zo,CLZ0,TL Ze,Zo,CLZ0,TL VDDVDDGSG1.6V1.6VZLCm31.5 fF192 m20 nmDRM1M3DrainSourceSourceGateVBG1VBG2VBG1VBG2DSGM1/2MBGTR improves PA core linearity for better AM/PM performance.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutraliz
293、ed Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference17 of 36Prototype Implementation 0.20.40.60.81.01.01.02.05.01050Complex-Cascode LC-Neutralized:CDSN=50fF&Lser=25pH0.20.40.60.81.01.01.02.05.01050Psat Contours 17:0
294、.5:20dBmPAE Contours 24:3:41%Standard Neutralization:CDSN=185fF&CGDN=80fFPsat Contours 17.5:0.5:20.5dBmPAE Contours 25:5:51%Much Larger Load Impedance Region for Similar Psat Contours 80 fF185 fF50 fF25 pH25 pH5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplif
295、ier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference18 of 36Output Matching:CL with BW Extension TLs Wideband Load-Pull Matching.M8M9M10M11PAOUTVDDCL BalunZe:2 Zo:1 2 CL:19 ZLFrequency(GHz)Impedance 50250-25-5065605550454035305.5
296、An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference19 of 36Output Matching:CL with BW Extension TLs Wideband Conjugated-Matched.Low Insertion l
297、oss.M8M9M10M11PAOUTVDDCL BalunZe:2 Zo:1 2 CL:19 ZL3040506020-25-20-15-10-30-5-1.4-1.2-1.0-0.8-1.6-0.6Frequency(GHz)S22(dB)Passive Efficincy(dB)BW Extensionusing TLs32 to 62GHz2:15.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Opera
298、tions in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference20 of 36Outline Introduction Why S22 Matters Prototype Implementation Measurement Results Conclusion5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Res
299、ilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference21 of 36Chip Micrograph Process:GF 22nm.Core Area:0.093mm2.Power Supply:0.8/1.6V.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient
300、Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference22 of 36Measurement SetupMaury Load TunerDC Power SuppliesArbitrary Wave GeneratorDUTLoad Tuner/AWG/PSG ControllerUXR-Infinium Real time Osc.70GHz Power Meter PNA-X Network Analyzer5.5 An Ultra-Compact Wid
301、eband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference23 of 36Small-Signal Measurement Results 3dB BW from 34 to 40.8GHz.Peak Power Gain of 22.7dB.10dB S22 from 32 to
302、 62GHz.S11S22S21S125.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference24 of 36 Large-Signal Measurement Results(1-2)CW 39GHzGain(dB)22.5PSa
303、t(dBm)15.7OP1dB(dBm)15.3PAEPsat(%)31.5PAEOP1dB(%)31AM-PM()1.455.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference25 of 36Large-Signal Measu
304、rement Results(1-2)CW 39GHzGain(dB)22.5PSat(dBm)15.7OP1dB(dBm)15.3PAEPsat(%)31.5PAEOP1dB(%)31AM-PM()1.455.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Cir
305、cuits Conference26 of 36Large-Signal Measurement Results(2-2)1.6V35 to 45GHzPsat(dBm)15.1 to 16.2OP1dB(dBm)15.1 to 16.1PAEPsat(%)25.1 to 34.2PAEOP1dB(%)25 to 34.2VDD 1.6VVDD 1.96V1.96V35 to 45GHzPsat(dBm)17 to 18OP1dB(dBm)14.5 to 17PAEPsat(%)25 to 37PAEOP1dB(%)25 to 37*Psat is defined as the maximum
306、 PAE.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference27 of 36VSWR(2:1 Circle)Measurement Results(1-3)Power Gain(PG)Deviation 1.2dB.OP1dB
307、 Deviation 2dB.PAEOP1dB-PAEOP1dB50 7%.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference28 of 36VSWR(3:1 Circle)Measurement Results(2-3)Po
308、wer Gain(PG)Deviation 1.5dB.OP1dB Deviation 2.5dB.PAEOP1dB-PAEOP1dB50 10%.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference29 of 36VSWR(4
309、:1 Circle)Measurement Results(3-3)Power Gain(PG)Deviation 1.5dB.OP1dB Deviation 3dB.PAEOP1dB-PAEOP1dB50 11%.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State
310、 Circuits Conference30 of 36Modulation Measurements(64-QAM)5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference31 of 36Modulation Measuremen
311、ts(64-QAM)5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference32 of 36Comparison Table for VSWR-Resillience PAs0102030401012141618202224PAEO
312、P1dB(%)OP1dB(dBm)Reported CMOS PAs(35 to 45GHz)ISSCC24RFIC24ISSCC20TMTT20 PA with VSWR ResiliencePA without VSWR Resilience Proposed PA(1.6V/1.96V)M.Pashaeifar ISSCC 2021N.M.Sasikanth ISSCC 2020G.Diverrez RFIC 2024M.Pashaeifar ISSCC 2024C.R.Chappidi TMTT 2020Technology40nm 45nm SOI28nm SOI40nm 65nmP
313、A ArchitectureTX with Balanced Doherty Reconfigurable Series/Parallel DohertyInductive DohertyChain Weaver 8-Way Balanced Reconfigurable Doherty Like Operation VDD(V)1.61.9612221.1Frequency(GHz)24 to 3038.5 to 4722 to 4234 to 4426 to 42Gain(dB)21.8(TX Gain)12.42229.915*S22(dB)-22.2-9-10-20N.R.Core A
314、rea(mm2)1.41.20.822.081.35OP1dB(dBm)16.317.32020.219.822.719.1Psat(dBm)16.417.62020.820.325.219.6PAEOP1dB(%)343729.8(D.E.)32.234*N.R.21.6Peak PAE(%)34.137.53133.334.416.224Power Density(W/mm2)0.470.580.070.100.130.160.07AM-PM OP1dB()N.R.N.R.N.R.1.90N.R.VSWR=3:13:13:1(No VSWR Angles Shown)(1.5:1)/(3:
315、1)4:1VSWR Freq.Range(GHz)27 to 283924 to 3037 to 4033Gain Deviation(dB)1.31N.R.0.72*OP1dB Deviation(dBm)0.41.72.10.82PAEOP1dB Deviation(%)N.R.1011N.R.N.R.VSWR=(3:1)/(4:1)VSWR=3:1VSWR=3:1505050Single Carrier 64-QAMSingle Carrier 64-QAM64-QAM 5G N.R.FR2OFDM 64-QAMOFDM 64-QAMFrequency(GHz)27/2839303937
316、Data Rate(MHz)10010010010020020002000EVMrms(dB)-251011.28.315.8010.00PAEavg(%)14.4 9 7 17 /9 13 N.R.9.612.33.310.2-24.6 *Estimated From reported figures N.R.Not Reported1.6/2.4/37/10/11Modulation SchemeSingle Carrier 64-QAM411.2/1.5/1.5This work22nm SOIComplex-Cascode LC-Neutralized34 to 40.822.7-10
317、(32 to 62GHz)0.0931.45 39GHz(2:1)/(3:1)/(4:1)37 to 435.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference33 of 36Comparison Table for VSWR-R
318、esillience PAs0102030401012141618202224PAEOP1dB(%)OP1dB(dBm)Reported CMOS PAs(35 to 45GHz)ISSCC24RFIC24ISSCC20TMTT20 PA with VSWR ResiliencePA without VSWR Resilience Proposed PA(1.6V/1.96V)M.Pashaeifar ISSCC 2021N.M.Sasikanth ISSCC 2020G.Diverrez RFIC 2024M.Pashaeifar ISSCC 2024C.R.Chappidi TMTT 20
319、20Technology40nm 45nm SOI28nm SOI40nm 65nmPA ArchitectureTX with Balanced Doherty Reconfigurable Series/Parallel DohertyInductive DohertyChain Weaver 8-Way Balanced Reconfigurable Doherty Like Operation VDD(V)1.61.9612221.1Frequency(GHz)24 to 3038.5 to 4722 to 4234 to 4426 to 42Gain(dB)21.8(TX Gain)
320、12.42229.915*S22(dB)-22.2-9-10-20N.R.Core Area(mm2)1.41.20.822.081.35OP1dB(dBm)16.317.32020.219.822.719.1Psat(dBm)16.417.62020.820.325.219.6PAEOP1dB(%)343729.8(D.E.)32.234*N.R.21.6Peak PAE(%)34.137.53133.334.416.224Power Density(W/mm2)0.470.580.070.100.130.160.07AM-PM OP1dB()N.R.N.R.N.R.1.90N.R.VSWR
321、=3:13:13:1(No VSWR Angles Shown)(1.5:1)/(3:1)4:1VSWR Freq.Range(GHz)27 to 283924 to 3037 to 4033Gain Deviation(dB)1.31N.R.0.72*OP1dB Deviation(dBm)0.41.72.10.82PAEOP1dB Deviation(%)N.R.1011N.R.N.R.VSWR=(3:1)/(4:1)VSWR=3:1VSWR=3:1505050Single Carrier 64-QAMSingle Carrier 64-QAM64-QAM 5G N.R.FR2OFDM 6
322、4-QAMOFDM 64-QAMFrequency(GHz)27/2839303937Data Rate(MHz)10010010010020020002000EVMrms(dB)-251011.28.315.8010.00PAEavg(%)14.4 9 7 17 /9 13 N.R.9.612.33.310.2-24.6 *Estimated From reported figures N.R.Not Reported1.6/2.4/37/10/11Modulation SchemeSingle Carrier 64-QAM411.2/1.5/1.5This work22nm SOIComp
323、lex-Cascode LC-Neutralized34 to 40.822.7-10(32 to 62GHz)0.0931.45 39GHz(2:1)/(3:1)/(4:1)37 to 435.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Co
324、nference34 of 36Outline Introduction Why S22 Matters Prototype Implementation Measurement Results Conclusion5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State
325、 Circuits Conference35 of 36Conclusion We propose a new concept to mitigate VSWR by improving the PAs S22.The LC complex cascode PA design achieves load-pull matching and enhances S22.It demonstrates resilience over 4:1 antenna VSWR with wide bandwidth.The design is ultra-compact,low-loss,and requir
326、es no reconfigurability or calibration,ideal for large-scale phased array systems.5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased Arrays.2025 IEEE International Solid-State Circuits Conference36 of
327、36Acknowledgement The authors would like to thank Globalfoundries for design kit and chip fabrication.The research is in part sponsored by the Swiss State Secretariat for Education,Research,and Innovation(SERI)under the SwissChips initiative,the HORIZON-JU-SNS-2023“6G-REFERENCE”project under grant a
328、greement 101139155,the EU Chips-JU“SHIFT”project under grant agreement 101096256,the Adrian Weiss Stiftung for the ETH Grant on“Electronic-Plasmonic Chip”project,Swiss National Science Foundation(SNSF)REquip TECHS Project(Grant number 213239),and ETH Scientific Equipment Funding for equipment fundin
329、g support.Thank you.5.6:A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM 2025 IEEE International Solid-State Circuits Conference1 of 47A Power-efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-based PA Supporting 256-QAMYuncheng Zhang,Zezhen
330、g Liu,Duo Li,Minzhe Tang,Yi Zhang,Hongye Huang,Dingxin Xu,Waleed Madany,Ashbir Aviat Fadila,Wenqian Wang,Yuang Xiong,Daxu Zhang,Garry Pranata Kusuma,Hiroyuki Sakai,Kazuaki Kunihiro,Atsushi Shirane,Kenichi OkadaInstitute of Science Tokyo(formerly Tokyo Institute of Technology)5.6:A Power-Efficient CO
331、RDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM 2025 IEEE International Solid-State Circuits Conference2 of 47Outline Motivation&Concept of This Work Prior artsDelta-Sigma Modulator(DSM)Digital Polar Transmitter Proposed ArchitectureGenerating AM&PM without CORDICCircuit
332、 Implementation Measurements Conclusion5.6:A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM 2025 IEEE International Solid-State Circuits Conference3 of 47Outline Motivation&Concept of This Work Prior artsDelta-Sigma Modulator(DSM)Digital Polar Transmit
333、ter Proposed ArchitectureGenerating AM&PM without CORDICCircuit Implementation Measurements Conclusion5.6:A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM 2025 IEEE International Solid-State Circuits Conference4 of 47 Wireless communication demand higher data throughput Wide bandwidth operation High-order QAM modulationStringent linearity requirement
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