SESSION 18 - High-Performance Optical Transceivers.pdf

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1、ISSCC 2024SESSION 18High-Performance Optical Transceivers18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference1 of 46A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit A

2、DC/DAC in 16nm CMOSGuansheng Li,Adesh Garg,Tim He,Ullas Singh,Jiawen Zhang,Lakshmi Rao,Chang Liu,Meisam Nazari,Yang Liu,Yong Liu,Heng Zhang,Tamer Ali,Hyo Gyuem Rhew,Jiayoon Ru,Delong Cui,Ali Nazemi,Bo Zhang,Afshin Momtaz,Jun CaoBroadcom,Irvine,CA18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver F

3、rontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference2 of 46Outline Introduction 600Gbps Coherent Optical TransceiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CM

4、OS 2024 IEEE International Solid-State Circuits Conference3 of 46Outline Introduction 600Gbps Coherent Optical TransceiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuit

5、s Conference4 of 46Introduction Optical Link is Striving for Data Rate 400Gbps/Complex Modulation Provides a Promising SolutionLimited bandwidth of electrical and optical channelsPowerful signal processing capacity on TRX siliconHigher Spectral EfficiencyModulationBits/SymbolNRZ1PAM42DP-QPSK4DP-QAM6

6、412CoherentIMDD18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference5 of 46ADC/DAC-Based Coherent Optical TRX Four Streams of Data Carried by a Single-LightDual-Polarization Quadrature-Amplitude

7、Modulation Four Synchronized ADC and DAC at E/O InterfaceFlexible modulation formats,data rates and rangesDACDACDACDACTX PLLTXDSPADCADCADCADCRX PLLRXDSPIQXIinXQinIQYIinYQinPolarizationBeam CombinerPolarizationBeam Splitter90o HybridXITIAXQYIYQTIA90o HybridTIATIAOptical LinkArbitrary PolarizationStat

8、e and PhaseScope ofThis Paper18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference6 of 46ADC/DAC for 600Gbps/Coherent TRX High Speed for 600Gbps/:105GSps&40GHz BW High SNDR for DP-QAM64:8bit Reso

9、lution Low Power for Optical Thermal RequirementsData:600Gb/sData:150GbpsFECUp to 4x210=840Gb/s70GBaud/s4x105GS/sXIXQYIYQDP-QAM6412 bits/symbolXIXQYIYQ1.5X Over SamplingDACADCDACDACDACADCADCADCClock Data RecoverySpectrum Shaping18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105

10、GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference7 of 46Outline Introduction 600Gbps Coherent Optical TransceiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE Inter

11、national Solid-State Circuits Conference8 of 46ADC Block Diagram Integrated Variable Gain Amplifier(VGA)192 Unit SARs Time-Interleaved by 2-Stage T/Hck12ck8ck4VGA 4SSFBUFSkew Cali.16CK_4Tfrom PLLSAR0,0SAR0,1SAR0,11Token&Clock Gen.SAR0,10.SAR0,011 Retimerckbckckbckck0,0ck0,1ck0,10ck0,11ck0SAR4,011 Re

12、timerSAR8,011 RetimerSAR12,011 RetimerClock and Global TokenSAR1/5/9/13,111SAR2/6/10/14,111SAR3/7/11/15,111ck1/5/9/13ck2/6/10/14ck3/7/11/1516Global Retimer4SAR0/4/8/12,11118.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International So

13、lid-State Circuits Conference9 of 46Variable Gain Amplifier VGA Integrated on ChipDrive large SAR arrayAdjust signal swingReject input CM ripple Large BandwidthTcoil for BW extension High LinearityDistortion cancellationIbiasVin+Vin-Vout+Vout-gm1gm2Rs2Rs1I01I0218.1:A 600Gbps DP-QAM64 Coherent Optica

14、l Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference10 of 46Variable Gain Amplifier:Linearization(1/2)High Linearity by Distortion Cancellation CircuitTwo differential pairs connected in opposite polarityCancel distortion without red

15、ucing gain significantlyI-V Relation of Differential Pair3=31 118.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference11 of 46Variable Gain Amplifier:Linearization(2/2)High Linearity by Distortion

16、Cancellation CircuitsCancellation Relies on Ratios of Devices and CurrentsInsensitive to Process,Temperature and Voltage VariationDevice Ratios for HD3 Cancellation Perfect HD3 Cancellation Slight Gain ReductionOnly Rely on Ratios18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x1

17、05GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference12 of 46Super Source Follower in T/H Super Source Follower Drives Sampling CapacitorFeedback loop extends BW and speeds up settlingConstant-Gm bias current reduces PVT variationVinVout XXXXXXRfbCLgmCPCbulk-gm/CL-

18、1/RfbCPRoot Locus when Rfb18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference13 of 46Capacitive Leakage in T/HVin(t)VTH(t)=Vin(t)CTHCSARt0t0+18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver

19、 Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference14 of 46Capacitive Leakage in T/HVin(t)VTH(t)=Vin(t0)CTHCSARt0t0+18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International So

20、lid-State Circuits Conference15 of 46Capacitive Leakage in T/H Capacitive Leakage Gets Serious in Wideband T/HDue to large switch transistor and small CTHVin(t)VTH(t)=Vin(t0)+Vin(t)-Vin(t0)CTHCSARt0t0+Cds=Cds+CTHCds18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC

21、/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference16 of 46Capacitive Leakage in T/H Capacitive Leakage Gets Serious in Wideband T/HDue to large switch transistor and small CTHVin(t)VTH(t)=Vin(t0)+Vin(t)-Vin(t0)CTHCSARt0t0+VSAR=Vin(t0)+Vin(t)-Vin(t0)Cds18.1:A 600Gbps DP-QAM64 C

22、oherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference17 of 46Capacitive Leakage in T/H Capacitive Leakage Gets Serious in Wideband T/HDue to large switch transistor and small CTHVin(t)VTH(t)=Vin(t0)+Vin(t)-Vin(t0)CTHCSAR

23、t0t0+VSAR=Vin(t0)+Vin(t0+)-Vin(t0)Cds18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference18 of 46Capacitive Leakage in T/H Capacitive Leakage Gets Serious in Wideband T/HDue to large switch tran

24、sistor and small CTHVin(t)VTH(t)=Vin(t0)+Vin(t)-Vin(t0)CTHCSARt0t0+VSAR=Vin(t0)+Vin(t0+)-Vin(t0)Cds=(1-)Vin(t)+Vin(t+)|t=t018.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference19 of 46Capacitive

25、Leakage in T/H Capacitive Leakage Gets Serious in Wideband T/HDue to large switch transistor and small CTHCauses ISI in time domain and ripples in frequency domain VSAR(t)=(1-)Vin(t)+Vin(t+)VSAR()=Vin()(1-)+ej2 VSAR()Vin()VSAR(t)Vin(t)18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend wit

26、h 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference20 of 46Capacitive Leakage in T/H Sampling Switches with Cds CancellationDifferential capacitive leakage can be cancelledckbckckbck18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps

27、 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference21 of 46Outline Introduction 600Gbps Coherent Optical TransceiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE Internat

28、ional Solid-State Circuits Conference22 of 46DAC Structure Half Rate vs.Quarter Rate?Quarter Rate Clock+Quarter Rate DataHalf Rate Clock+Half Rate DataLarge parasitic cap with 3/4 idle branches Small parasitic cap with 1/2 idle branches Internal signal with 1T pulses Internal signal with 2T pulsesAB

29、CKCKBI0ACBDCK_ICK_IBCK_QCK_QBI0CK_ICK_IBCK_QCK_QB18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference23 of 46Proposed I/Q DAC Structure(1/2)Quarter Rate Clock+Half Rate DataInternal clock/data w

30、ith 2T pulse high speed,low powerOnly 50%idle branches at output small cap,large BWMismatch between even and odd edges interleaving spurD D D D DD D DD D D D DD D DD D D D DD D DDDDDDDDDDDDDDDDDDABCDCK_ICK_IBCK_QCK_QBI02I02DAC_IDAC_QDAC_IDAC_QDACABCDCK_ICK_IBCK_QCK_QBDACDatriggered by clocktriggered

31、 by data2T18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference24 of 46Proposed I/Q DAC Structure(2/2)Quarter Rate Clock+Half Rate Data DAC_I+DAC_Q Average Out Edge MismatchAll output edges match

32、 systematicallyD D D D DD D DD D D D DD D DD D D D DD D DDDDDDDDDDDDDDDDDDABCDCK_ICK_IBCK_QCK_QBI02I02DAC_IDAC_QDAC_IDAC_QDACABCDCK_ICK_IBCK_QCK_QBDAC18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Co

33、nference25 of 46Clock/Data Skew Insensitive to Clock/Data Skew at DAC InputEven/odd bits still match systematicallyD D D D D D D DD D D D D D D DD D D D DD D DDDDDDDDDDDDDDDDDDDAC_IDAC_QDACABCDCK_ICK_IBCK_QCK_QBCK_I/IB/Q/QB skewed from the center of data A/B/C/DEven/odd mismatch averaged out in fina

34、l DAC output 18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference26 of 46I/Q Clock Skew I/Q Clock Skew Calibrated by On-Chip LoopOtherwise,lead to interleaving spurs at Fs/2 FoutD D D D D D D DD

35、 DD DD DD DD DD D D D D DDDDDDDDDDDDDDDDDDDAC_IDAC_QDACABCDCK_ICK_IBCK_QCK_QBCK_I/IB&Data B/D skewed from CK_Q/QB&Data A/C Even/odd mismatch NOT averaged out in final DAC output 18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE Internati

36、onal Solid-State Circuits Conference27 of 46Clock Duty Cycle Distortion Clock Duty Cycle Calibrated by On-Chip LoopOtherwise,lead to interleaving spurs at Fs/4 FoutCK_I/IB&Data B/D duty cycle distorted Bit width varies with period of 4T DDDDDDDDDDD DDDD DDDD DDDD DDDDDDDDDDDDDDDDDDDAC_IDAC_QDACABCDC

37、K_ICK_IBCK_QCK_QB18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference28 of 46DAC Block DiagramRegulated Power RailDAC_IDAC_QMMMMMABCD8:4MUXI/Q Data Encoder228128:8 MUXSkew Cali.CK_4T from PLLFFF

38、FFFFFFFFFFFFFFFFFFFFFFFFFFFFFLMCK_I/IB/Q/QBCK_128TCK_16TCK_8TLoad Ctrl4:2 MUX7 Thermometer Bits(3MSB)+5 Binary Bits(5LSB)18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference29 of 46Outline Intro

39、duction 600Gbps Coherent Optical TransceiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference30 of 46PLL Block Diagram Charge-Pump Based PLL ArchitectureTwo lo

40、w-noise LC VCOs cover wide frequency rangeDifferential CP and LPF for better noise immunityMUXPFD/CP2NLPFCK_RefCK_DivRST_CLKLB:3945GHz HB:4753GHz 156MHz3.3GHz18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Cir

41、cuits Conference31 of 46Global Clock Distribution Low-Skew and Low-Jitter Clock DistributionClock tree with two stages of large buffers Each buffer drives 1.2mm clock channelADCADCPLLADCADCCK_nearCK_farTransmission Line Effect Manifests 18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend w

42、ith 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference32 of 46Outline Introduction 600Gbps Coherent Optical TransceiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024

43、IEEE International Solid-State Circuits Conference33 of 46Integrated with DSP in 16nm CMOSPLLXQXIYQYI4.2mm1.3mmPLLXQXIYQYI1.0mm2.7mmReceiverTransmitter18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits C

44、onference34 of 46ADC Bandwidth-3dB Bandwidth 40GHzFrequency(GHz)Gain(dB)18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference35 of 46ADC ENOB ENOB 6bit up to 25GHzFrequency(GHz)ENOB_SNDR(bit)18.1

45、:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference36 of 46ADC Spectrum SFDR 50.7dB with Distortion Cancellation Circuit Interleaving Spur 35GHzFrequency(GHz)Gain(dB)18.1:A 600Gbps DP-QAM64 Coheren

46、t Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference39 of 46DAC THD THD 6bit up to 27GHzFrequency(GHz)ENOB_THD(bit)18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IE

47、EE International Solid-State Circuits Conference40 of 46DAC Spectrum SFDR=51.6dB1GHz and 41.5dB25GHzHD3HD318.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference41 of 46PLL RMS Jitter 10K-100MHz=51

48、.4fsCritical to SNDR of high-speed ADC/DACRMS Jitter 10kHz-100MHz18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference42 of 46Optical Loopback Constellations Flexible Modulation Formats and Data

49、RatesDP-QAM64 enabled by ADC/DAC with excellent SNDR400Gbps DP-QAM16600Gbps DP-QAM64200Gbps DP-QPSK18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference43 of 46State of the ArtBetter ADC SNDR50%h

50、igher data rate&spectral efficiencyBetter ADC SFDRBetter PLL JitterBetter DAC SNDR18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference44 of 46Outline Introduction 600Gbps Coherent Optical Transc

51、eiverADCDACPLL Measurement Conclusion18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conference45 of 46Conclusion 600Gbps/DP-QAM64 Coherent TRX based on 4x105GSps 8bit ADC/DAC in 16nm CMOSFlexible dat

52、a rate of 100/200/300/400/500/600GbpsFlexible format of DP-QPSK&DP-QAM16/32/64 Flexible range of long-haul/metro/ZR Has Been in Mass Deployment18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-State Circuits Conferenc

53、e46 of 46Acknowledgement The authors would like to thank the support of the Broadcom system,ASIC,and layout teams for this design,and the DVT team for the measurement.18.1:A 600Gbps DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GSps 8bit ADC/DAC in 16nm CMOS 2024 IEEE International Solid-

54、State Circuits Conference47 of 46Please Scan to Rate Please Scan to Rate This PaperThis Paper18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference1 of 27A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Termi

55、nated 4-Ch VCSEL-Based Optical TransmitterSusnata Mondal,Junyi Qiu,Sashank Krishnamurthy,Joe Kennedy,Soumya Bose,Tolga Acikalin,Shuhei Yamada,James Jaussi,Mozhgan MansuriIntel Labs,Hillsboro,Oregon,USA18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 20

56、24 IEEEInternational Solid-State Circuits Conference2 of 27Outline Motivation VCSEL-Based Co-Packaged Optical TX System Optical TX Circuit Architecture and InnovationsComplex-zero CTLE to equalize VCSELLow-power low-jitter resonant clocking Measurement Results464Gb/s NRZ optical TX80Gb/s NRZ optical

57、 driver(direct drive)Conclusion18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference3 of 27VCSEL-Based Optical Interconnects10cm1m10m100m1cmElectricalIntra-rackIntra-boardModule/packageInter-rackSingle-

58、mode optics Multi-mode optics(e.g.VCSEL)200Gb/s per lane200Gb/s per fiber ElectricalMulti-mode optics(e.g.VCSEL)Single-mode opticsVCSEL-Based Optical Interconnects10cm1m10m100m1cmElectricalIntra-rackIntra-boardModule/packageInter-rackSingle-mode optics Multi-mode optics(e.g.VCSEL)200Gb/s per lane200

59、Gb/s per fiber Module/PackageIntra-boardIntra-rackInter-rackElectrical vs Optical I/OVCSEL-based optics can overcome electrical reach limitation x Limited reach at higher data rates due to channel lossx High power consumptionHigh bandwidth connectivity Reach tens of metersEnergy efficientVCSEL Verti

60、cal-cavity surface-emitting laser18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference4 of 27Optical I/OOn pkg.electrical I/OengineOptical(fiber)VCSEL-based Co-packaged Optical InterconnectCo-packaging

61、requires only a short electrical I/O between XPU/SW*core and optical engine low channel loss high data rate/bandwidth density high energy efficiency low latencyCo-packaging can help with VCSELs thermal reliability(compared to heterogeneous integration)*XPU/SW Computing/switching system18.2:A 464Gb/s

62、 NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference5 of 27VCDRV ICTX ICPCBVCSEL-based Optical TX System PrototypeVCSEL,VCSEL Driver(VCDRV)&electrical TX integrated on packageOn-package fiber-terminated 4-ch prototy

63、pe using MOIMechanical Optical Interface(MOI)*D.Schoellner,et.al,Optical Interconnects XVII,2017(On-pkg interconnect)Fiber terminationCo-packaged and fiber terminated 4-channel VCSEL-based optical TX ElectricalTX IC12mm0.8mmVCSELDriver ICPackageWirebonded 14 VCSEL arrayVCDRV ICWirebonded 1x4 VCSEL a

64、rray18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference6 of 27Optical TX Architecture TX IC full-rate serialization&drives on-pkg electrical channel VCDRV IC performs equalization&drives VCSELOn-pkgVC

65、DRV CH#1VCDRV CH#1TX ICTX ICVCDRV ICVCDRV IC4:1 MUX+driverPattern gen.+16:4 MUXTX CH#1TX CH#1Quad gen.Input stageComplex-zero CTLEGain stageOutput stageTX CH#2TX CH#2VCDRV CH#2VCDRV CH#2TX CH#3TX CH#3VCDRV CH#3VCDRV CH#3TX CH#4TX CH#4VCDRV CH#4VCDRV CH#4Global clock dist./2Local clock1-UI data gen.1

66、8.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference7 of 27Outline Motivation VCSEL-Based Co-Packaged Optical TX System Optical TX Circuit Architecture and InnovationsComplex-zero CTLE to equalize VCSEL

67、Low-power low-jitter resonant clocking Measurement Results464Gb/s NRZ optical TX80Gb/s NRZ optical driver(direct drive)Conclusion18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference8 of 27VCSELs Optica

68、l Response Limits Complex-pole in VCSELs optical response limits performance Conventional CTLE:cant compensate in-band peaking&2nd-order roll-offFrequencyAmplitude responseVCSEL optical40 dB/decadeHVCSEL-O(s)R RC CConventional CTLE C CvlvlL LvlvlR RvlvlVCSEL modelVCSEL modelHHVCSELVCSEL-E E(s)(s)HHV

69、CSELVCSEL-OO(s)(s)Electrical OpticalCTLE Continuous time linear equalizerVCathodeVCSELGain stageOutput stageConv.CTLE18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference9 of 27Z ZL Lg gmmL LR RC CHHCTL

70、ECTLE(s)(s)New Complex-Zero CTLE New complex-zero CTLE performs complex pole-zero equalization gain and group delay flatness 2ndorder equalization extends BW1.5x higher baud rate-to-VCSEL BW ratio than two-path equalizer in 3FrequencyAmplitude responseVCSEL optical40 dB/decadeHVCSEL-O(s)Conventional

71、 CTLEHCTLE(s)Proposed CTLEHVCSEL-E(s)1/LvlCvls2+(Rvl/Lvl)s+1/LvlCvlgmZLs2+(R/L)s+1/LCs2+(R/L+gm/C)s+(1+gmR)/LC3 A.Sharif-Bakhtiar,et.al,IEEE CICC,2017 C CvlvlL LvlvlR RvlvlVCSEL modelVCSEL modelHHVCSELVCSEL-E E(s)(s)HHVCSELVCSEL-OO(s)(s)Electrical OpticalVCathodeVCSELGain stageOutput stageComplex-ze

72、ro CTLE18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference10 of 27Complex-Zero CTLE ReconfigurabilityC CR RL LReduce VCSEL Bias FrequencyAmplitude responseExample VCSEL optical responseReconfigurable

73、CTLE to support various biasing conditionsTuning inductor enables higher quality factor at lower freq.Tune L,C,and R based on peaking-freq.,damping factor and data-rate 18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State

74、 Circuits Conference11 of 27VB1VtermInput stageInput stageOutput stageOutput stageVCSEL biasVB2DCOCDCOCGain stageGain stageVCathodeComplexComplex-zero zero CTLECTLEComplete Circuit Architecture of VCDRV ChannelInput stage performs DC level conversionCherry-Hooper gain stage w/shunt-series peaking fo

75、r signal amplificationCherry-Hooper-based output stage w/shunt-series peakingPeaking inductors to overcome BW limitations from on-chip parasitics,package parasitics and VCSELs electrical responseVCDRV IC18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter

76、2024 IEEEInternational Solid-State Circuits Conference12 of 27gm1gm2R Rd dR Ro o 1/gm2I IPROPPROPComplete Circuit Architecture of VCDRV ChannelCherry-Hooper-based output stage improves VCSELs current modulation by a factor of(Rd-Ro)/Ro w.r.t an inverter-based voltage-mode driver in 22 M.Mansuri,et.a

77、l,IEEE JSSC,2022VCDRV ICgm1gm2Ro 1/gm2I ICONVCONVI IPROPPROPI ICONVCONV R Rd d-R Ro oR Ro oVB1VtermInput stageInput stageOutput stageOutput stageVCSEL biasVB2DCOCDCOCGain stageGain stageVCathodeComplexComplex-zero zero CTLECTLE18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Ba

78、sed Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference13 of 27Optical TX Architecture TX IC full-rate serialization&drives on-pkg electrical channelOn-pkgVCDRV CH#1VCDRV CH#1TX ICTX ICVCDRV ICVCDRV IC4:1 MUX+driverPattern gen.+16:4 MUXTX CH#1TX CH#1Quad gen.Input stageComplex

79、-zero CTLEGain stageOutput stageTX CH#2TX CH#2VCDRV CH#2VCDRV CH#2TX CH#3TX CH#3VCDRV CH#3VCDRV CH#3TX CH#4TX CH#4VCDRV CH#4VCDRV CH#4Global clock dist./2Local clock1-UI data gen.TX IC18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternatio

80、nal Solid-State Circuits Conference14 of 27CTLCTLresonatesCTL|CTL=2CTLCTLresonatesCTLClock Distribution(Resonant Transmission-Line)Resistive terminated TLResonant TL in 5Resonant TL in this work5 G.Li,et.al,IEEE ASSCC,20153rdharmonic filtering2L2LL High power No jitter filtering Area efficient Low d

81、istortion 4x better power efficiency than resistive TL(Q12)Performs input jitter filtering 2 inductors 2x each 3rd-harmonic distortion 4x better area than 5 Harmonic filter,low distortionWhen driven by full swing invertersTile Longer dist.can use multiple tiles w/single harmonic filter18.2:A 464Gb/s

82、 NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference15 of 27Quadrature Generation(quad-gen)Large area for differentialPoor energy efficiency (50 interface)Wide frequency rangeConv.quadrature hybrid*I+Q+I-Q-Driver 2x

83、 lower area:single coupled-resonator 3x power benefit:no 50 interface 5x tuning range w.r.t prior-art 6Tunable resistor at secondary coil to improve I-Q gain matching vs.freq.6 R.Singh,et.al,IEEE TMTT,2019Coupled-resonator quad-gen Dont need 2x input freq.as in divider-based 2quad-gen(better power&j

84、itter)2 M.Mansuri,et.al,IEEE JSSC,2022*D.Ozis,et.al,IEEE JSSC,2009I+Q+DriverI-Q-LCLCkPort#2Port#1=90 phase shift =1/LC)Z11Z211k(s2+2)sQ18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference16 of 27Resona

85、nt Local BufferLarge capacitive loading in the final driverResonant*local bufferImproves power efficiency Performs jitter filteringCoupled-resonator based quad-genResonant-TL-based global clock dist.Clock inputto TX serializerClkILocal resonant clockch#1ch#2ch#3ch#4ClkIbClkQClkQb*A.J.Drake,et.al,IEE

86、E JSSC,200418.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference17 of 27Overall Clock Architecture(Wide Frequency Tunability)Wide resonant path operation36Gb/s-to-64Gb/s in siliconInput clock jitter fil

87、tering30%for 64Gb/s in siliconCoupled-resonator based quad-genResonant-TL-based global clock dist.Clock inputto TX serializerClkILocal resonant clockch#1ch#2ch#3ch#4ClkIbClkQClkQb18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational S

88、olid-State Circuits Conference18 of 27TX 4:1 Serializer and Electrical Driver1-UI data gen+4:1 mux+driver(slice#1)slice#2slice#8CpadCesdLpeak1/4th rate4 phase clock1/4th rate dataBW extension1-UI Data GenerationN/N DriverClkIDatabClkQ4XClkIDataClkQ0.4 V0.85 V0.85 VCombination-logic 1-UI generator 7L

89、ow swing voltage-mode driver8-segments to tune drive strength4-UI pulses from all slices combined at output(50+series-peak inductor)7 J.Kim,et.al,IEEE JSSC,202218.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits

90、 Conference19 of 27Pulse-Width Correction in TX Serializer+DriverYtop-pYbot-n1-UI Data GenerationN/N DriverClkIDatabClkQ4XWeakClkIDataClkQStrong0.4 V0.85 V0.85 VWeakWeakStrongStrongYtop-pYbot-nw/o correctionasymmetricover correctionasymmetricw/correctionsymmetric eyeFinite slew at driver input:asymm

91、etric eyePulse widths of top and bottom NMOS inputs are tuned to achieve symmetric eye18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference20 of 27Outline Motivation VCSEL-Based Co-Packaged Optical TX S

92、ystem Optical TX Circuit Architecture and InnovationsComplex-zero CTLE to equalize VCSELLow-power low-jitter resonant clocking Measurement Results464Gb/s NRZ optical TX80Gb/s NRZ optical driver(direct drive)Conclusion18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optica

93、l Transmitter 2024 IEEEInternational Solid-State Circuits Conference21 of 27Co-Packaged Optical TX Prototype22nm FinFET CMOS processCo-packaged&fiber-terminatedLow-loss on-package channel3.2 dB at Nyquist frequency of 32GHz CH1CH1CH2CH2CH3CH3CH4CH4Electrical TX ICVCSEL driver ICCH1CH1CH2CH2CH3CH3CH4

94、CH4Global clk530um530um250um250um750um750um250um250um18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference22 of 274-Ch Optical TX(Electrical TX+VCSEL Driver+VCSEL)256Gb/s aggregate data rate BER=10-12:E

95、ye width0.5UI,Eye height(OMA)1.3mWppCHCH1 1CHCH2 2CHCH3 3CHCH4 4OMA Optical modulation amplitude1.3pJ/bit energy efficiency64 Gb/s/channel optical output eyeBiased at 9mA18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-Stat

96、e Circuits Conference23 of 27FrequencyAmplitude responseVCSEL optical responseProposed reconfigurable CTLEReduce VCSEL biasOptical TX across VCSEL Bias(at 64Gb/s)Improves energy eff.by 0.2pJ/b by reducing VCSEL bias to 5mAEqualizes severe peaking and BW limitation at lower bias Showcasing complex-ze

97、ro CTLE effectiveness and reconfigurability9 9mA biasmA bias7 7mA biasmA bias5 5mA biasmA biasEye height,width(BER=10-12)*1.3mWpp,0.5UI1.1mWpp,0.43UI0.9mWpp,0.3UIEnergy efficiency(EE)1.3pJ/b1.2pJ/b1.1pJ/b*Worst-case across 4 channels18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VC

98、SEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference24 of 27Standalone Optical Driver(VCSEL Driver+VCSEL)Complex-zero CTLE enables 1.54x Nyquist freq./VCSEL-BW ratio25x better energy eff.at 13%higher data-rate than state-of-the-art,implemented in BiCMOS 11 D.M.Kuchta,

99、et.al,IEEE Photonics Technology Letters,201564 64 Gb/sGb/s76 Gb/s76 Gb/s80 Gb/s80 Gb/sEye height,width(BER=10-12)2.0mWpp,0.57UI1.1mWpp,0.46UI0.75mW0.75mWpppp,0.30UI,0.30UIEnergy efficiency(EE)0.66pJ/b0.56pJ/b0.53pJ/b0.53pJ/bNyquist freq./VCSEL BW1.23x1.46x1.54x1.54xNative VCSEL:26GHzBW9mAVCSEL drive

100、r ICDriven at full rate18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference25 of 27Comparison to Prior-ArtOptical driver:25x better EE 13%higher baud-rate than 1Optical TX:1.4x EW,7.6x OMA,1.11x better

101、 EE 14%higher baud-rate than 2Co-packaged optical TX:6.4x baud-rate than prior art 4124 A.F.Benner,et.al,IEEE Optical Fiber Communication,201018.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference26 of 2

102、7Conclusion System integration and performanceCo-packaged&fiber-terminated multi-channel VCSEL-based optical TXBest reported data-rate and energy efficiency Circuit contributionsComplex-zero CTLE equalizes VCSELs responseTransmission-line-based resonant global clock dist.Wide-tuning-range resonant q

103、uadrature generationLow-power electrical TX w/pulse width correction Optical I/OOn pkg.electrical I/Oto opticalElectrical4 4-ch prototypech prototype18.2:A 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference

104、27 of 27AcknowledgementsNick Sanchez,James Tagumasi,Don Pawelski,Taehwan Kim,Enrique Calderon,and Jonathan Batres for layout/design helpKin Wai Lee,Ling Li Ong and Kai Yuen Cheah for package designDan Lake for PCB design and Trang Nguyen for lab supportThank you!18.2:A 464Gb/s NRZ 1.3pJ/b Co-Package

105、d and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter 2024 IEEEInternational Solid-State Circuits Conference28 of 27Please Scan to Rate Please Scan to Rate This PaperThis Paper18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800G

106、b/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference1 of 36An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm Fazil Ahmad,A.Mellati,A.Fernandez,A.Iyer,A.

107、Fan,B.Reyes,C.Abidin,C.Nani,D.Albano,F.Solis,G.Minoia,G.Hatcher,H.Carrer,K.Kota,L.Wang,M.Bachu,M.Garampazzi,M.Hassanpourghadi,N.Fan,P.Prabha,R.Nguyen,S.Ho,T.Dusatko,T.Wu,W.Elsharkasy,S.Jantzi,L.Tse18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calib

108、ration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference2 of 36Outline Coherent Optics&Tx Requirements Channel&TI Serializer Synchronization TI-DAC&Adaptive Filter based Calibration DAC&Driver Architecture Measurement Results Conclusion 18.3:An

109、8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference3 of 36Coherent Optical Communication Trend AI cloud data centers connected by coherent optics

110、Speed doubles in less than three years but not powerQSFP-DD 14W,QSFP 12W18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference4 of 36Transmi

111、tter for Coherent Optics Single PLL and 4 synchronous channelsThis workTXRX18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference5 of 36Desi

112、gn Challenges for Coherent Transmitter Baud rate 139GBdSampling frequency 60-160GSpsLarge bandwidth 60GHzRandom jitter 35%Lower capacitor at driver output better return lossOnly DAC based DAC with DriverSwing 650mV ppdiDAC=13mASwing 650mV ppdiDAC=3.25mA18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Inte

113、rleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference28 of 36DAC with Driver Architecture DAC current split into P&N sides Lower impedance to the DAC BW extension techniques Inductive pe

114、aking between DAC&Driver T-coil at bumpsT-coil at highly capacitive node18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference29 of 36Outlin

115、e Coherent Optics&Tx Requirements Channel&TI Serializer Synchronization TI-DAC&Adaptive Calibration DAC&Driver Architecture Measurement Results Conclusion 18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applic

116、ations in 5nm 2024 IEEE International Solid-State Circuits Conference30 of 36Measurement Results 5nm CMOS process 4 TX(HI,HQ,VI,VQ)with PLL area 3.8x0.86mm218.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Appli

117、cations in 5nm 2024 IEEE International Solid-State Circuits Conference31 of 36Calibration Measurement Results Spur reduced by 18dBFsig=976MHzENOB=5.07Main Tone=-6.37dBmFsig=976MHzENOB=7.07Main Tone=-6.82dBmBefore Calibration After Calibration 18dB Spec-A noiseSpec-A noise18.3:An 8-bit 160GS/s,57GHz

118、Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference32 of 36DAC Driver Bandwidth Measurement Large signal BW with PAM4 Package de-embedded Board de-embedded Magnitude

119、 response(dB)MeasuredPolynomial fitFrequency(Hz)f3dB=57GHzFFT(impulse response)18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference33 of 3

120、6PAM4 Eye Diagram PAM4 at 279.2Gbps Target baud rate 139GBd Swing=650mVppd Package de-embedded Board de-embedded650mV7.1ps18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE Internati

121、onal Solid-State Circuits Conference34 of 36Comparison Table ISSCC21 KimISSCC21 ChoiISSCC21 NguyenThis workTechnology10nm CMOS28nm CMOS7nm CMOS5nm CMOSTX Architecture7b TI-DACAnalog w/AFE8b TI-DAC8b TI-DACBandwidth(GHz)-3857Sampling frequency(Gsps)97160PAM Data Rate(Gbps)224200132279.2HF Sine SNDR d

122、B fin 30GHz-3234.8 fs=160GS/sLF Sine SNDR dB fin 1GHz-4638 fs=160GS/sTX Random Jitter(fs,rms)65-15065,with 3MHz CDR and including PLLTX Swing(Vppd)1.00.80.65TX Analog Power(pJ/b)1.74(w/o PLL)4.63(w/o PLL)-57GHz and PAM results at 279.2Gbps State of the art FOM=0.9pJ/b 18.3:An 8-bit 160GS/s,57GHz Ban

123、dwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference36 of 36AcknowledgementThe authors would like to thank the entire development team of this project,System,Digital,Ana

124、log,Layout,PD,DFT,and CAD for their dedication and valuable support.18.3:An 8-bit 160GS/s,57GHz Bandwidth Time-Interleaved DAC&Driver Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm 2024 IEEE International Solid-State Circuits Conference37 of 36Please Sca

125、n to Rate Please Scan to Rate This PaperThis Paper18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference1 of 24A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz A

126、FE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFETR.L.Nguyen1,A.Mellati1,A.Fernandez2,A.Iyer3,A.Fan1,B.Reyes2,C.Abidin1,C.Nani4,D.Albano4,F.Ahmad1,F.Solis2,G.Minoia4,G.Hatcher1,M.Bachu3,M.Garampazzi4,M.Hassanpourghadi1,N.Fan1,P.Prabha1,S.Fan3,S.Ho5,T.Dusat

127、ko5,T.Wu1,W.Elsharkasy1,Z.Sun6,S.Jantzi1,L.Tse31Marvell,Irvine,CA2Marvell,Cordoba,Argentina3Marvell,Santa Clara,CA4Marvell,Pavia,Italy5Marvell,Vancouver,Canada6Marvell,Singapore,Singapore18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coheren

128、t Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference2 of 24Outline Coherent motivation and challenges Receiver architecture Measurement results Conclusion18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Cohere

129、nt Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference3 of 24Coherent Optical CommunicationsAnalog NRZAnalog NRZ1XPAM PAM 4 4 DSPDSP2XEncodingDigital Coherent DSPDigital Coherent DSP2X,8x,for QPSK,16QAM,19801980-2018201820192019-PresentPresent(2 2 bits/symbol)bits/sy

130、mbol)(N bits/symbol,(N bits/symbol,dual polarization)dual polarization)Intensity Modulation Direct Detect(IMDD)Over copper or fibers Shorter reach Low costDigital Coherent Detection Over fibers only Longer reach&higher rates Complex DSP,higher costR.Nguyen et al.,ISSCC 2021 18.4:A 200GS/s 8-b 20fJ/c

131、-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference4 of 2410km500km100km2km60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET

132、2024 IEEE International Solid-State Circuits Conference5 of 24Coherent Receiver Challenges Ultra-high electrical performance requirementsLarge analog bandwidth(60GHz)Low clock jitter(60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE Inter

133、national Solid-State Circuits Conference6 of 24Anatomy of a Coherent ReceiverOptical Fiber80-5k kmRX PLLHIHQVIVQFramer/MapperRX CoreIngress Host InterfaceModulation/Channel/Distribution Matching DecoderRX DSPPolarization Beam SplitterBeam SplitterLO Light Source90 Optical HybridsADCADCADCADCTIATIATI

134、ATIAOptical RXOptical SignalElectrical SignalElectrical&Optical EqualizationTiming RecoverySkew CompensatorElectrical DevicesOptical DevicesFrom TX Source Oversampled system w/4 synchronous channels Dual polarization(HV)with IQ componentsDSPHQVQVIHI18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE

135、 Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference7 of 24RX Architecture Two-rank hierarchical samplingThree layers of signal buffering CTLE&high BW buffers16 TAHs256 SAHs inside 4 SAR arraysBackground

136、AVSAVSSAR ADC ARRAYRX InputCTLEBUF1BUF2TAH.RetimerDigital Detection&Post Correction011548633216.Retimer64.Retimer128.Retimer191127192255Matching NetworkAVSTrimmable18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm

137、 FinFET 2024 IEEE International Solid-State Circuits Conference8 of 24SAR ADC Strategy Asynchronous SARPre-Amp+latch Round trip delay set by Logic delay Comparator thermal noiseContinuous AVS Ensure constant delay Power savingADC Unit8b DACAsynchronous LogicCLK GenInputCKiCompararatorCKi+1OS DACCKCK

138、IPINIP/INOsp/OsnOspOsnSAR CKOPONREF.Digital CounterRing OSCCalibration06318.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference9 of 24RX ClockingCentral PL

139、L deliversEight fs/8 clock phases12.525GHz 50%DCDiv-2 to generate 16 TAH clocksFine DLL for skew compensationDiv-16 to generate SAR pulsesCK10:15.CK20 4Ts16Ts256TsCK2255.AVSSAR ADC ARRAYRX InputCTLEBUF1BUF2TAH.RetimerDigital Detection&Post Correction011548633216.Retimer64.Retimer128.Retimer191127192

140、255Matching NetworkAVSTrimmablefs/8 Clocks from PLL(12.5.25GHz)2 16160151CK10:15 CK20 18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference10 of 24RX Cali

141、bration Background calibrationAmplitudeOffsetSkewDigitally assisted Nonlinear digital correction Channel-to-channel alignmentAVSSAR ADC ARRAYRX InputCTLEBUF1BUF2TAH.RetimerDigital Detection&Post Correction011548633216.Retimer64.Retimer128.Retimer191127192255Matching NetworkAVSTrimmablefs/8 Clocks fr

142、om PLL(12.5.25GHz)2 16160151CK10:15 CK20 C2C AlignmentAnalog CalibrationAmplitude&OffsetAmplitude&Skew18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conferenc

143、e11 of 24Background Calibration Hierarchical groupingChild nodes working with parent nodes Redistributes cal ranges&maximizes yieldPost-correction relaxes analog rangesBefore calibration+x00+x0+x+x+x+x+x+x+x.00,0 01 02 03 00,1 00,14 00,15.00 000,0 01 02 03 00,1 00,14 00,15 BUF1BUF2ADCCalibrate to ch

144、ild nodes to statistical mean of parent nodeLocal grouping of child nodesfin=0.34GHzSNDR=41.5dBSNR=42dBHD2=-57.2dBHD3=-56.8dBTHD=51dBAfter calibration18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 I

145、EEE International Solid-State Circuits Conference12 of 24Increases peaking near NyquistTrades off S11&high freq.roll-off for better-3dB BWCompensates for secondary poles(e.g.sampling BW)Negative T-coil Matching NetworkIncreasing CLIncreasing CLRX InputCTLE.Matching Network.VipVp2RtermVn2VinMMCLCL18.

146、4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference13 of 24Impedance Splitting IllustrationSplitting Rterminto R1&R3improves Nyquist peakingTrades off DC g

147、ain&return loss for better BWRX InputCTLE.Matching Network.Increasing R1Increasing R1Vip-M-MR1R3VinCLVp2Vn218.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conf

148、erence14 of 24Impedance Splitting Illustration(2)Shunt Lsimproves mid-band return lossShunt Cstrades return loss&in-band droop for BW R2 partially recovers DC gain&DC return lossRX InputCTLE.Matching Network.Increasing CsVip-M-MCsLsR1R2R3VinCLVp2Vn2Varying R218.4:A 200GS/s 8-b 20fJ/c-s Receiver with

149、 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference15 of 24High Bandwidth Signal ConditioningPMOS CTLE with positive T-coilTrimmable Rs for gain tuningNeutralization capsVp3 Vn3Vp2Vn2.CpRpRLRLR

150、X InputCTLE.Matching Network.18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference16 of 24Active Inductive Signal PeakingClass AB buffers Nyquist peaking

151、active inductors with LchokeRX InputCTLE.Matching Network.Vn3CxVp4Vn4VbnVbpVp3LchokeLchokeLchokeLchoke18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conferenc

152、e17 of 24Fast Settling High Gain BufferingSuper-source follower with gm/gm gain boostingCapacitively coupled Zx/Cxfor fast settlingMOS resistors for gain calibrationRX InputCTLE.Matching Network.Vn4Vp4Vn5Vp5Vn4Vp4Vcal,1Vcal,2CxZxZxCc18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 2

153、56-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference18 of 24Sinusoidal PerformanceLow frequency performanceSNDR=41.5dB,ENOB=6.6bTHD50dBHigh frequency performance limited byClock jitterAFE high frequency nonlinearityfin=3

154、00MHzSNDR=41.5dBSNR=42dBHD2=-57dBHD3=-58dBTHD=51dBfin=21GHzSNDR=36dBSNR=38dBHD2=-48dBHD3=-42dBTHD=40dBfin=47.2GHzSNDR=26.5dBSNR=31.5dBHD2=-37dBHD3=-28dBTHD=27dB18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm Fin

155、FET 2024 IEEE International Solid-State Circuits Conference19 of 24Measured BandwidthPost embedding BW 60 GHzPeaking dependent on TIACompensate for channel loss18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm Fin

156、FET 2024 IEEE International Solid-State Circuits Conference20 of 24Comparison to Prior ArtsFOM includes complete RX power w/o PLL RX QUADRX1RX20.6mm0.55mmCategorySpecificationThis WorkNguyen 1Segal 2Yonar 3Kull 4Cao 5Kull 6CMOS Technology nm5754322014Resolution bits8868888Max Sampling Speed GS/s2001

157、00112561006972Sampling Speed Range GS/s25-20040-971125670-10055-6924-72SNR at LF b4244.5SFDR at LF b574458SNDR at LF dB41.541.141354039.3SNDR at HF dB*36.135.128.8535283434-3dB Bandwidth GHz604027201921Power mW400300315.2240845950235Complete RX PowerYesYesNoNoNoNoNoWaldon FOM DC fJ/c-s20344718618843

158、Waldon FOM HF fJ/c-s*386712493426377*80RX Area mm0.332.35*0.340.458*0.15*HF Input Freq20G20G10G20G20G16G20G*Full Quad Area with RX,TX,and PLLSpecsPerformanceEfficiencyNote18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications

159、 in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference21 of 24Walden FOM ChartSAR based RX highlightedAchieved complete RX FOMLF FOM=20fJ/c-sHF FOM=38fJ/c-sAdapted from B.Murmann,ADC Performance Survey 1997-2023,Online.Available:https:/ 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Ba

160、ndwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference22 of 24Conclusion First reported 200GS/s optical RX Full RX BW 60GHz Lowest reported total RX jitter of 70fs-rms(including PLL)Lowest FOM 20fJ/c-s(complet

161、e RX)above 100GS/s18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference23 of 24Acknowledgement The authors would like to thank the entire development team

162、 of this project,System,Digital,Analog,Layout,PD,DFT,and CAD for their dedication and valuable support18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conferenc

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166、Dig.Tech.Papers,pp.358360,Feb.2018.18.4:A 200GS/s 8-b 20fJ/c-s Receiver with 60GHz AFE Bandwidth and 256-way Interleaved SAR ADC for 800Gbps Coherent Communications in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference25 of 24Please Scan to Rate Please Scan to Rate This PaperThis Paper