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1、ISSCC 2025SESSION 6Imagers and Displays6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference1 of 24A 3-Stacked Hybrid-Shutter CM
2、OS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile ApplicationsHeesung Shim,Seung-Sik Kim,Min-Woong Seo,Sangsu Park,Hyukbin Kwon,Yongjun Kim,Sanggwon Lee,Sungbong Park,Daehee Bae,SiGyoung Koo,Masamichi Ito,Jae-hoon Jeon,Sol Yoo
3、n,Sung-Jae Byun,Sangyoon Kim,KwanSik Kim,Gihwan Cho,Joonho Lee,Tekyou Kim,Sungjae Jun,Jae-kyu Lee,Chang-Rok Moon,Jaihyuk Song Samsung Electronics Co.,Hwaseong,Korea6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shut
4、ter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference2 of 24Outline MotivationEfforts to enhance function of image sensorBenefits of global shutter for mobile application ApproachHybrid shutter CIS to maximize the benefits of GS and RS Proposed Hybrid Shutter CISP
5、ixel architectureOperational timing diagram ResultsMeasurement results,Images and Video Summary6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State
6、 Circuits Conference3 of 24Outline MotivationEfforts to enhance function of image sensorBenefits of global shutter for mobile application ApproachHybrid shutter CIS to maximize the benefits of GS and RS Proposed Hybrid Shutter CISPixel architectureOperational timing diagram ResultsMeasurement result
7、s,Images and Video Summary6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference4 of 24Development Trend of CMOS Image Sensors Pi
8、xel Scaling&Enhancing function of CIST.Ogita,et al.,IWJT 20230.5in 2024D.H.Kim,et al.,ISSCC 2024.GS IlluminationRS IlluminationexposurereadoutexposurereadoutTimeTime#of rows#of rowsPixel Scaling TechnologyExample of Function Enhancement GSilluminatorcamera:Eye Safety/Lower Illumination Power from GS
9、:Application for AR/VR,Robot,Drone,Industry Use:Simultaneous Exposure Benefits for MobileSimultaneous ExposureRolling ExposureEye Tracker6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applic
10、ations 2025 IEEE International Solid-State Circuits Conference5 of 24Benefits of Global Shutter for Mobile Application Pros of Global Shutter(1)Distortion FreeH.Sekine,et al.,Sensors 2017(3)Flash Band FreeRSGSH.Sekine,et al.,Sensors 2017Freq.of Light=60 HzBrightDarkFlicker Band of RS=Cons of Global
11、Shutter:Higher RN(Random Noise)due to kTC(2)Flicker Band FreeRSGS6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference6 of 24Out
12、line MotivationEfforts to enhance function of image sensorBenefits of global shutter for mobile application ApproachHybrid shutter CIS to maximize the benefits of GS and RS Proposed Hybrid Shutter CISPixel architectureOperational timing diagram ResultsMeasurement results,Images and Video Summary6.1:
13、A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference7 of 24Hybrid Shutter(HS)CIS(CMOS Image Sensor)Switchable RS and GS Modes for M
14、obile ApplicationsHS CIS50Mp12.5MpBenefitsRSMode Small Pixel Pitch Low RNGSMode Low Distortion Flicker Band Free Less Blur w/Short Exposure No Flash Banding*1Pixel1.2um2.4um2.4umSwitchable Operationin One Sensor*1Pixel*1Pixel*1Pixel6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2
15、-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference8 of 243-stacked Chip Diagram and Vertical TEM Images Mobile RS Pixel Top Layer Pixel with Minor Modification DRAM Capacitor To Reduce kTC Nois
16、eRSGSHSCDSTop-layerPixel array same as mobile RS pixelsMiddle-layerTransistors&Capacitors for GS Bottom-layerADC&LogicRS Signal PathGS Signal PathSiCap.CDSCDSPDPD+S/HPDS/H6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Glob
17、al Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference9 of 24Outline MotivationEfforts to enhance function of image sensorBenefits of global shutter for mobile application ApproachHybrid shutter CIS to maximize the benefits of GS and RS Proposed Hybrid Shutt
18、er CISPixel architectureOperational timing diagram ResultsMeasurement results,Images and Video Summary6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Soli
19、d-State Circuits Conference10 of 24Chip Diagram&Timing Diagram of HS CIS Top layer:Conventional 4-Tr.Pixel(0.6 4-PD 1.2-pitch pixel)Middle layer:Cap.and Tr.for GS(2.4-pitch pixel)Operational Timing DiagramTopLayerMiddle LayerRSGSBottom Layer6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switc
20、hable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference11 of 24RS mode Timing Diagram of HS CIS same as the existing 4-Transistor Operation 3 Conversion Gain modesRS mode1Pixel for 50M1Pixe
21、l for 12.5MLCG/MCGHCGTGSEL1LCG/HCGMCGMCG/HCGLCGConventional4-TransistorRS Operation(OFF All TransistorOn Middle Layer)HCG mode MCG mode LCG modeFD Cap 6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for
22、 Mobile Applications 2025 IEEE International Solid-State Circuits Conference12 of 24Chip Diagram of HS CIS with 2-layer PixelHS CIS50Mp12.5MpExposureOperationRSModeGSMode*1Pixel1.2um2.4um2.4umSwitchable Operationin One Sensor All-Pixel Output:Sampled on Cap.Simultaneously(global dump)RS modeGS mode1
23、Pixel for 50M1Pixel for 12.5MRolling Exposure of 1-Row PixelsSimultaneous Exposure of All PixelsGlobal Dump6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International
24、 Solid-State Circuits Conference13 of 24Operational Timing Diagram:Global Dump By SMP1&SMP2,RST&SIG on FD are sampled on Crst and Csig.Vertical Charge Summing on FD&Horizontal Voltage Averaging on Middle LayerGS modeLCG/MCGHCGTGGSELSEL1SEL2PSEL1PSEL2SMP1SMP2IBIASPC:Pre-Charge(In-Pixel Bias Tr.)LCG:L
25、ow Conversion GainMCG:Middle Conversion GainHCG:High Conversion GainPixelBinningRSTSIG light darkRSTSIG6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Sol
26、id-State Circuits Conference14 of 24Operational Timing Diagram:Global DumpCpara Mismatch between SMP1-PC&SMP2-PCVGSbetween RST and SIG sampling Sampling Mismatch makes Noise.Careful Layout of Tr.and Metal Layer is necessary to reduce Cp of SMP1/2-PCIbiasVGS-VTHRSTPIXEL1SIGPIXEL1RSTPIXEL2SIGPIXEL2VGS
27、VGSIDS1IDS2Variation of PC Tr.Vth Operating Point(VGS-VTH)Variation of Each Pixel+=FPNSMP1SMP2RSTSIGS/FPCPC Gate VoltageRST SamplingSIG SamplingVGSIDSS/F:Source FollowerPC:Pre-Charge(In-Pixel Bias Tr.)Fixed Pattern NoiseOP1OP26.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch
28、 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference15 of 24Operational Timing Diagram:Readout Z-node is pre-charged with FD node voltage before each ADC.After charge sharing between z-node and storage
29、 node(x or y)with SMP1 or 2 ON,RST and SIG ADC is performed.LCG/MCGHCGTGGSELSEL1SEL2PSEL1PSEL2SMP1SMP2z-node pre-charge(2-times)GS Readoutzxy6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Ap
30、plications 2025 IEEE International Solid-State Circuits Conference16 of 24HDR GS mode DSG(Dual Slope Gain)Pixel Comparator bandwidth is modulated by ramp slope.AG(Analog Gain)Ramp Slope Comp.BW ADC Noise AG x1 at Bright&AG x4 at Dark RN at Dark DR 6dB Comp.Comp.RMP1Comp.Comp.RMP1RMP2Low GainHigh Gai
31、nNormal GS mode:4K 120fpsHigh BWHigh BWHigh BWLow BW1 Pixel 2 ADC withLow&HighAnalog GainFinal Image Synthesizing2 ADC resultsHDR GS mode:4K 60fpsPixelPixel6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Mode
32、s for Mobile Applications 2025 IEEE International Solid-State Circuits Conference17 of 24Outline MotivationEfforts to enhance function of image sensorBenefits of global shutter for mobile application ApproachHybrid shutter CIS to maximize the benefits of GS and RS Proposed Hybrid Shutter CISPixel ar
33、chitectureOperational timing diagram ResultsMeasurement results,Images and Video Summary6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circui
34、ts Conference18 of 24Performance Summary&Chip Micrograph 52ke-FWC(Full Well Capacity)in both RS and GS mode 2.4e-RN thanks to x2 600fF Capacitor in 2.4 PixelRSGSSupply Voltage2.2V/1.05VPixel Pitch2.4 umResolution12.5 Mp(4096x3072)Frame Rate95 fpsPower Consumption mW700650CGuV/e-HCG108100MCG2725LCG13
35、.612.5FWC e-LCG,AG x152K52KPRNU%LCG,AG x10.50.5RN e-HCG,AG x161.72.4PLS dBNA-1303-stacked chip FWC52Ke-GS RN 2.4e-RS RN 1.7e-RN 3.3e-SamsungsGen.2 AR/VR GS(IEDM 2024)RN 5.5e-SamsungsAR/VR GS6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pi
36、tch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference19 of 24Performance Summary Less Power Consumption in GS modeRSGSSupply Voltage2.2V/1.05VPixel Pitch2.4 umResolution12.5 Mp(4096x3072)Frame Rate95 fpsPower Consumption mW700650CGuV/e-HC
37、G108100MCG2725LCG13.612.5FWC e-LCG,AG x152K52KPRNU%LCG,AG x10.50.5RN e-HCG,AG x161.72.4PLS dBNA-130GSRSRSRS requires 2 Pixel Loadsfor Horizontal AVG.6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for M
38、obile Applications 2025 IEEE International Solid-State Circuits Conference20 of 24Comparison of PerformanceThis WorkIEDM 2024Samsung Gen.2 GS for AR/VRIEDM 2023 9IEDM 2022 3ISSCC 2020 8IEDM 2019 10Pixel Pitch um2.42.22.21.82.32.2Structure3-layer stacked BSIVoltage-domain2-layer stacked BSIVoltage-do
39、main2-layer stacked BSIVoltage-domain3-layer stacked BSIVoltage-domain2-layer stacked BSIVoltage-domain2-layer stacked BSIVoltage-domainResolution12.5Mp(4096x3072)0.4Mp(640 x640)0.5Mp(1280 x400)1.3Mp(1280 x1024)1.0Mp(1280 x800)1.3Mp(1280 x1024)Frame Rate95 fps 12.5Mp120 fps 4K180 fps60 fps120 fps120
40、 fps120 fpsFWC e-LCG52K14K11K14K12K12KRN HCG2.4e-(240uV)2.7e-(330uV)3.8e-(760uV)1.8e-(324uV)2.1e-(294uV)3.1e-(713uV)FPN e-1.2 HCG1.37 HCG1.2 HCG-1.7Conversion GainuV/e-100 HCG25 MCG12.5 LCG122 HCG60 LCG200 HCG60 LCG180 HCG60 LCG140 HCG70 LCG230 HCG63 LCGPLS dB-130-130-100-130-105-1006.1:A 3-Stacked
41、Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference21 of 24Sample Images Switchable Operation between RS and GS 50Mp RS Mode HCG,AG x812.5Mp G
42、S Mode HCG,AG x8 6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference22 of 24Demo VideoRS 12.5Mp 60fpsEIT 1.3 msec,AG x12RS 12.
43、5Mp 60fpsEIT 16.5 msec,AG x1GS 12.5Mp 60fpsEIT 1.3 msec,AG x12Image Blur Flicker Band Image Blur Flicker Band Image Blur Flicker Band Trade-off of RS between Flicker Band and Image Blur 6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch
44、12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Conference23 of 24Outline MotivationEfforts to enhance function of image sensorBenefits of global shutter for mobile application ApproachHybrid shutter CIS to maximize the benefits of GS and RS Propo
45、sed Hybrid Shutter CISPixel architectureOperational timing diagram Results Summary6.1:A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2-Pitch 50MPixel Rolling Shutter and 2.4-Pitch 12.5MPixel Global Shutter Modes for Mobile Applications 2025 IEEE International Solid-State Circuits Con
46、ference24 of 24Summary We propose hybrid shutter CIS,which enables switchable operation between RS mode and GS mode on a single chip to maximize the benefits of both modes for mobile application.In 12.5Mp GS mode,FWC 52ke-RN 2.4e-and less power consumption compared to 12.5Mp RS mode are achieved.We
47、believe GS mode have the potential to offer a valuable user experience in mobile devices.Please come to our demo session(6.1)tonight(5-7 PM)Thank You for Your Attention!6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Backgr
48、ound-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference1 of 52An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold Seonghyeok Park1,2,Su-Hyun Han1,Jongbeom Kim1,Jubin
49、 Kang1,Jung-Hoon Chun2,3,Jaehyuk Choi2,3,Seong-Jin Kim41Ulsan National Institute of Science and Technology,Ulsan,Korea2SolidVue,Seongnam,Korea3Sungkyunkwan University,Suwon,Korea4Sogang University,Seoul,Korea6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based o
50、n Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference2 of 52Outline Introduction&Challenges Asynchronous Flash LiDAR SensorConceptual operating principleSensor implementationToF validation method Measurement Results Conclusion6.2
51、:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference3 of 52SPAD based Direct ToF(dToF)SensorIR EmitterObjectDistance=tTime-to-Digital Conve
52、rter(TDC)DEmitted LightReflected LightTimeTimetDetector6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference4 of 52Time Correlated Single
53、 Photon Counting6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference5 of 52Repetition Number for ToF Detection6.2:An Asynchronous 16090
54、Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference6 of 52Repetition Number for ToF Detection6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rate
55、s of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference7 of 52Repetition Number for ToF Detection6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Va
56、lidation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference8 of 52Far and High BGLLow SNRClose and Low BGLHigh SNRConventional Frame-based Sensor6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF
57、Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference9 of 52Previous WorkI.Gyongy,JSTQE,2023 Peak threshold based on background light intensity with simple statistics6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 2
58、50fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference10 of 52Concept of Asynchronous Sensor Operation6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validat
59、ion via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference11 of 52Delta-Intensity Quaternary Search(DIQS)hTDCS.Park,ISSCC,2022Easy peak detection within four time binsFew control signals due to simple operationSuitable for pixel-wise operation6.2:An Asynchr
60、onous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference12 of 52ToF Validation6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 t
61、o 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference13 of 52ToF Validation via Background LightBut B depends on NR.Complex calculation.Noise(X2)can be estimated with B.|X2|2B with 95%probability.6.2:An Asynchrono
62、us 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference14 of 52ToF Validation via Background LightBut B depends on NR.Complex calculation.Sparse exposure ti
63、me quantizationApproximated threshold6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference15 of 52Conceptual Pixel Operation Cycle is min
64、imum exposure time slot with NR=100.Pixels individually decide whether to change their State at the end of cycle.6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International So
65、lid-State Circuits Conference16 of 52Sensor Architecture Maximum sampling time for photons from the background light is 800s6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE Inter
66、national Solid-State Circuits Conference17 of 52Pixel Operation in State06.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference18 of 52Pix
67、el Operation in State1and State26.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference19 of 52Pixel Operation in State36.2:An Asynchronous
68、 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference20 of 52Pixel Read-Out6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250
69、fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference21 of 52Pixel Read-Out6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-A
70、daptive Threshold 2025 IEEE International Solid-State Circuits Conference22 of 52Pixel Read-Out6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits
71、 Conference23 of 52Pixel Read-Out with Fail Flag6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference24 of 52Background Light Adaptive Th
72、reshold The photons from the background light within one cycle is NBGL.To provide success rate over 95%,sample the photons within the same time as 16 cycles,16NBGL.=2,2 2+1 _=16 _=6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation v
73、ia a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference25 of 52Threshold Update as Exposure Time Nthis initialized to Nth_ref,calculated in State0.Nthis doubled when Ncyclebecomes power of 4,because the noise is proportional to the square root of exposure tim
74、e.6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference26 of 52Principle of ToF Validation Circuit =2,2 2+1 22 22+1 =2_=2 0=2,0,1,2,36.2:
75、An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference27 of 52Principle of ToF Validation Circuit =2,2 2+1 22 22+1 22 22+1,=22+1222+020,002 11
76、2 002 =2+1,2=2+121+020,02 12=12 =2=1=0=026.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference28 of 52Principle of ToF Validation Circuit
77、 =2,2 2+1 22 22+1 22 22+1,=22+1222+020,002 112 002 =2+1,2=2+121+020,02 12=12 =2=1=0=026.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conferen
78、ce29 of 52Principle of ToF Validation Circuit =2,2 2+1 22 22+1 22 0.230.2 0.30.097Coarse 10(1)Fine 0.4Maximum Distancem4550242 5.89.521Frame Ratefps3050N/A5 30205 250Depth Precision-1.5 cm13 cm3.5 cm 0.5%0.9 cm6 cmDepth Accuracy-2.5 cm5 cm2.9 cm 5%1 cm8 cmPower ConsumptionmW132706095%true detection
79、rate at 21 m up to 30 klux.6.2:An Asynchronous 16090 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold 2025 IEEE International Solid-State Circuits Conference52 of 52Thank you for your attention!6.3:SPAD Flash LiDAR
80、 with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference1 of 47SPAD Flash LiDAR with Chopped Analog Counter for 76 m Range and 120 klx Background LightHyun-Seung Choi1,2,Injun Park1,3,Byungchoul Park4,Dongseok Cho1,5,Myung-Jae Lee
81、1,and Youngcheol Chae1,31Yonsei University,Seoul,Korea2Korea Institute of Science and Technology,Seoul,Korea3XO Semiconductor,Seoul,Korea4Myongji University,Yongin,Korea5Samsung Electronics,Hwasung,Korea6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 I
82、EEE International Solid-State Circuits Conference2 of 47Motivation Autonomous Vehicles Robotics Flash LiDAR 3D imaging and distance measurementEffective in dynamic environments 6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-St
83、ate Circuits Conference3 of 47Flash LiDAR:Direct ToF PrincipleLiDARLaserDetectorTimeAmplitudetDistance(L)L=c tc:speed of lightt:time-of-flight Laser:Pulsed laser(Time-of-flight)Detector:Mostly SPAD(Single-photon avalanche diode)6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120kl
84、x Background Light 2025 IEEE International Solid-State Circuits Conference4 of 47Flash LiDAR:Indirect ToF PrincipleLiDARLaserDetectorTimeAmplitudeL=c:speed of light:phase delayf:modulation frequency Laser:Modulated laser(Phase delay)Detector:PD(Photodiode),SPADDistance(L)6.3:SPAD Flash LiDAR with Ch
85、opped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference5 of 47Survey on Flash LiDAR Performance Small photodiode area(90 m2)High resolution Photodiode Low SNR&Limited distance(300 m2)+Complex pixel circuit Low resolution 80101Distance mE
86、ffective Active Area m26040200102103JSSC18KatoJSSC14ChoISSCC18BamjiPD+I-ToFSPAD+D-ToFISSCC22ManuzzatoJSTQE24GyongyISSCC19HendersonJSSC22ParkISSCC21 Padmanabhan-Distance:100 m-Fill Factor:N/A6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE Internati
87、onal Solid-State Circuits Conference7 of 47Survey on Flash LiDAR Performance Region of Interest(ROI)Moderate SPAD area(100 400 m2)+Compact pixel circuit Long distance(40 80 m)80101Distance mEffective Active Area m26040200102103JSSC18KatoJSSC14ChoISSCC18BamjiPD+I-ToFSPAD+D-ToFISSCC22ManuzzatoJSTQE24G
88、yongyISSCC19HendersonJSSC22ParkROIEffective Active Area=Pixel Area Fill Factor6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference8 of 47Survey on Flash LiDAR Performance Moderate pixel pitch(32 m)+Compact
89、pixel circuit PD+I-ToFSPAD+D-ToFSPAD+I-ToF800Distance mPixel Pitch m604020040701020305060801001203D-StackedISSCC22ManuzzatoJSTQE24GyongyISSCC19HendersonJSSC22ParkISSCC21PadmanabhanSSCL20ParkJSSC21ParkVLSI24ChoJSSC18KatoJSSC14ChoISSCC18Bamji6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Ran
90、ge and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference9 of 47Survey on Flash LiDAR Performance Moderate SPAD area Moderate resolution Long distance(40 70 m)Effective Active Area=Pixel Area Fill FactorPD+I-ToFSPAD+D-ToFSPAD+I-ToF80101Distance mEffective Active Area m26
91、040200102103JSSC18KatoJSSC14ChoISSCC18BamjiISSCC22ManuzzatoJSTQE24GyongyISSCC19HendersonJSSC22ParkSSCL20ParkJSSC21ParkVLSI24Cho6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference10 of 47Design Challenges o
92、f SPAD-Based I-ToF Sufficient Bit DepthWhy?Accurate distance calculationHow?High-Bit counter(9-Bit)Fine Time StampingWhy?High modulation frequency(50 MHz)How?Short time step(100 klx)How?Additional suppression techniques6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Backgro
93、und Light 2025 IEEE International Solid-State Circuits Conference11 of 47Design Challenges of SPAD-Based I-ToF1-value of phase delay()=1Ntrg2+90 2Ntrg:Number of triggering photons:Average value of phase delayDepth precision()D=c4fmodc:Speed of lightfmod:Modulation frequency of laser diodeHigh depth
94、precision(500 Counter bit depth 9-Bit0.01%0.10%1.00%10.0%Depth Precision(D,70 m)100101102103104Number of triggering photons(Ntrg)500VLSI24 Cho6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference12 of 47SPAD
95、 with Passive Recharge Circuit Passive recharge circuit Long recharging time Long dead time Low maximum count rate(MCR)PhotonVATime(s)VA(V)VEXVBD+VEXVASPADVPRQuenchingResistor6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-Stat
96、e Circuits Conference13 of 47Proposed Pixel Analog Front-End(AFE)Active recharge circuit with a feedback loop Short recharging time Short dead time(3 ns)PhotonV2VAV1VBD+VEXVAV1V2SPADVEXTime(s)VA(V)6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE In
97、ternational Solid-State Circuits Conference14 of 47Proposed Pixel Analog Front-End(AFE)PMOS enable switch Disables SPAD operation PhotonVBD+VEXVAV1V2SPADVDDENVAENV2V16.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuit
98、s Conference15 of 47Proposed Pixel Analog Front-End(AFE)2ndinverter delay=NOR gate output pulse width(=1 ns)Pulses transferred within the fixed time window(TW)PhotonVBD+VEXVATWSPADV1V2TRGVDDENTWTRG1 nsENV2V16.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 20
99、25 IEEE International Solid-State Circuits Conference16 of 47Why Analog Counter?Digital counter Complex(9-Bit 1000 m2110 nm)Analog counter Compact(9-Bit 100 m2110 nm)Compact pixel pitch(40 m)Analog counter essential!VBD+VEXVDDENVATWTRGSPADPulseCounter32 mJSSC21,B.Park18 m12 m75 mJSSC22,S.Park43 m46
100、m Digital Counter Analog Counter 6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference17 of 47Charge-Sharing Analog CounterVBD+VEXVACNRSPADTWVORSTCIVDDClockGen.VOTEXPVAVOVDDSaturatedVO1VO2 3 transistors&2 ca
101、pacitors Compact counter size Counting step Output voltage Non-Uniform steps One direction counting No immunity to strong BGL JSSC16,Perenzoni6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference18 of 47Push
102、-Pull Analog CounterTEXPVATWVOTWVDVUErrorUnsaturatedVCMVDVU Two direction counting Immunity to strong BGL Counting step (VNL VTH)Uniform steps Up-Down counter gain mismatch Counting errors CIVORSTCPVDDVNLVPLVCMTWClockGen.VBD+VEXVARSPADTWClockGen.CNVO(VNL VTH)VLSI24,Cho6.3:SPAD Flash LiDAR with Chopp
103、ed Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference19 of 47Charge-Injection Analog CounterTEXPVAVOVDDSaturatedVO1VO2VREFVOVBD+VEXVACNRSPADTWVORSTCIVDDClockGen.VREF Counting step VREF Uniform steps One direction counting No immunity to s
104、trong BGL JSSC21,Park6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference20 of 47Chopped Charge-Injection Analog CounterTEXPVACHVOVCMVDVDUnsaturated Counting step VREF Uniform steps Utilization of chopper I
105、mmunity to strong BGL VOCHCHCHCHRSTVCMCIVREFVOVBD+VEXVACNRSPADTWVOClockGen.VREF6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference21 of 47Generation of Non-Overlapping PulsesVOCHCHCHCHRSTVCMCIVREFVBD+VEXVA
106、CNRSPADTWVOClockGen.VBD+VEXVATWENTRGARSPAD5 nsTRGAR0.7 ns AND gate delay Two non-overlapping pulses(=0.7 ns)Short time step=5 ns6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference22 of 47Phase Delay Calcul
107、ation 0&180 TWPhaseEmissionVOCHTEXPVCM V0 V180 2CHCHCHCHVCMCICHCHCHCHVCMCI0 180 0 180 V180=KV0=K()Subtraction of pulses:Phase 0 (CH)Phase 180 (CH)Chopping used for subtractionChopper6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Sol
108、id-State Circuits Conference23 of 47Phase Delay Calculation 90&270 TWPhaseEmissionCHTEXPCHCHCHCHVCMCICHCHCHCHVCMCI90 270 90 270 Subtraction of pulses:Phase 90 (CH)Phase 270 (CH)Chopping:Offset noise reduction&Simple calculation VOVCM V90 V270 2V270=K(/2 )V90=K(/2+)=+Chopper6.3:SPAD Flash LiDAR with
109、Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference24 of 47Multiple Chopping Operation 1 Chop If saturation occurs even with 1 chopping operation Error=Lost pulses in the first phaseTEXPCHTWVO+8V 8V4(SIG)+8(BGL)=122(SIG)+8(BGL)=101
110、2V 10V+2V 8VSaturated+8V 10V 2V 2VError6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference25 of 47Multiple Chopping Operation 2 Chop Saturation solved with multiple chopping operations N Chop BGL immunity
111、2NTEXPCHTWVO+8V 8V+6V 5V+V 6V V 6V 7V+2VCorrect7V 5V+2V2(SIG)+4(BGL)=61(SIG)+4(BGL)=52(SIG)+4(BGL)=61(SIG)+4(BGL)=56.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference26 of 47Multiple Chopping OperationBGL
112、Immunity a.u.87654321No Chop 1 Chop2 Chop4 Chop12Required Bit bit11109No Chop 1 Chop2 Chop4 Chop 4 Chop BGL immunity 8 12-Bit counter(No Chop)=9-Bit counter(4 Chop)6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits
113、Conference27 of 47Total Pixel Schematic&Layout Utilization of analog counter Compact pixel circuit BSI process MIM capacitor over SPAD High fill factorVBD+VEXVDDENVATWENTRGARVNCNVREFCHCHCHCHRSTVCMCIVOROWColumn LineSPADSPAD with Analog Front-EndChopped Analog CounterSource FollowerAFECounter32 m32 mS
114、PADSFMIM Capacitor(CI=260 fF)13.5 m10.8 m7.7 m5.7 m Process:110 nm BSI 6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference28 of 47Chip Micrograph Total Area=2.9 2.9 mm2 64 64 Pixel Array Pixel Pitch=32 m F
115、ill Factor=33%11-Bit Single Slope ADCs Frame Rate=50 fps64 64Pixel ArrayRamp Gen.Column ComparatorPixel Control Logic2.9 mm2.9 mmColumn CounterColumn SRAMColumn ScannerSense Amp.SS ADC Array6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE Internati
116、onal Solid-State Circuits Conference29 of 47Measured Photon Detection Probability High PDP:14.3%(850 nm)BSI process(2),metal reflector(1.2),BST(1.8)14.3%11.3%PDP%Wavelength nm201510508008509009506.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE Inte
117、rnational Solid-State Circuits Conference30 of 47Measured Linearity(Counter)+0.6 LSB 0.5 LSB+0.7 LSB 0.7 LSB Differential Non-Linearity(DNL)=0.5/+0.6 LSB Integral Non-Linearity(INL)=0.7/+0.7 LSB6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE Inter
118、national Solid-State Circuits Conference31 of 47Measurement Setup VCSEL LD boardEmission angle:20Optical power:5.96 mW Lens Field of View(FoV)19 19 Optical band-pass filterCWL:850 nmFWHM:10 nmTest BoardTarget6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2
119、025 IEEE International Solid-State Circuits Conference32 of 47Measured Depth Precision6.4cm Measured with 50 MHz at dark condition Measured depth precision:6.4 cm(0.08%)at 76 m6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-Sta
120、te Circuits Conference33 of 47Indoor Sample Image Depth image of Agrippa sculpture Modulation frequency=12.5 MHz Agrippa Sculpture Indoor Sample Image 6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference34
121、of 47Outdoor Sample Image with Chopping Frame rate=50 fps/Modulation frequency=3.125 MHz Maximum distance=20 m/Background light=120 klxNo Chop2 Chop Operation4 Chop Operation1 Chop OperationCode250200150100500Overall SaturationPartial SaturationPartial ImprovementSaturation Solved6.3:SPAD Flash LiDA
122、R with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference35 of 47Outdoor Sample Image(No Chop)Overall saturation under 120 klx 50 frame accumulation for clear image20m18m15mBGL=120 klxBGL=120 klx40m30m20mNo ChopNo ChopCode25020015
123、0100500Overall SaturationOverall Saturation6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference36 of 47Outdoor Sample Image(1 Chop)Partial saturation under 120 klx 50 frame accumulation for clear image20m18
124、m15mBGL=120 klxBGL=120 klx40m30m20m1 Chop Operation1 Chop OperationCode250200150100500Partial SaturationPartial Saturation6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference37 of 47Outdoor Sample Image(2 C
125、hop)Partial improvement of saturation under 120 klx 50 frame accumulation for clear image20m18m15mBGL=120 klxBGL=120 klx40m30m20m2 Chop Operation2 Chop OperationCode250200150100500Partial ImprovementPartial Improvement6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Backgrou
126、nd Light 2025 IEEE International Solid-State Circuits Conference38 of 47Outdoor Sample Image(4 Chop)Saturation mostly solved under 120 klx 50 frame accumulation for clear image20m18m15mBGL=120 klxBGL=120 klx40m30m20m4 Chop Operation4 Chop OperationCode250200150100500Saturation SolvedSaturation Solve
127、d6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference39 of 47Chip Power ConsumptionPixel CircuitSPADADCPixel DriverPower Consumption mW28.6710.20.530.056VoltageCurrentPowerPixel Circuit3.315 V8.65 mA28.67 m
128、WSPAD17 V0.6 mA10.2 mWADC1.263 V0.42 mA0.53 mWPixel Driver3.305 V0.017 mA0.056 mWTotal39.456 mW Power consumption=39.4 mW(120 klx)6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference40 of 47Performance Summ
129、aryParametersUnitThis WorkVLSI24ChoJSSC21ParkVLSI19ParkISSCC22ManuzzatoJSSC22ParkISSCC21PadmanabhanProcess-110 nm BSI110 nm BSI110 nm110 nm110 nm110 nm45 nm BSI 3D-StackedToF Type-SPAD-BasedIndirect ToFAPD-BasedIndirect ToFSPAD-BasedDirect ToFBGL Suppressionklx12090120(a)200303010Max.Depth Rangem767
130、050208.245100Depth Precisioncm6.4 711.356(b)271.5N/AFrame Ratefps503065962530N/APixel Resolution-64 6464 6464 6464 6464 6480 60256 128Pixel Pitchm3232323248757Fill Factor%333326.32112.910.4N/APDP VEX%14.3 2 V14.3 2 V5.85 1 VN/A54.5(c)6.6 V3 2.5 VN/AIllumination Wavelengthnm850850850820905905780Illum
131、ination PowermW5.96N/AN/AN/A5.8-9.33.05.0Chip Sizemm22.9 2.92.9 2.93 33 3N/A7.03 5.92.08 1.06Chip PowermW39.429.142.7N/A205.7132(d)51.9(a)Short integration and multiple-frame accumulation(b)Calculated Value(c)Measured 450 nm(d)SPAD power excluded6.3:SPAD Flash LiDAR with Chopped Analog Counter for 7
132、6m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference41 of 47Performance SummaryParametersUnitThis WorkVLSI24ChoJSSC21ParkVLSI19ParkISSCC22ManuzzatoJSSC22ParkISSCC21PadmanabhanProcess-110 nm BSI110 nm BSI110 nm110 nm110 nm110 nm45 nm BSI 3D-StackedToF Type-SPAD
133、-BasedIndirect ToFAPD-BasedIndirect ToFSPAD-BasedDirect ToFBGL Suppressionklx12090120(a)200303010Max.Depth Rangem767050208.245100Depth Precisioncm6.4711.356(b)271.5N/AFrame Ratefps503065962530N/APixel Resolution-64 6464 6464 6464 6464 6480 60256 128Pixel Pitchm3232323248757Fill Factor%333326.32112.9
134、10.4N/APDP VEX%14.3 2 V14.3 2 V5.85 1 VN/A54.5(c)6.6 V3 2.5 VN/AIllumination Wavelengthnm850850850820905905780Illumination PowermW5.96N/AN/AN/A5.8-9.33.05.0Chip Sizemm22.9 2.92.9 2.93 33 3N/A7.03 5.92.08 1.06Chip PowermW39.429.142.7N/A205.7132(d)51.9(a)Short integration and multiple-frame accumulati
135、on(b)Calculated Value(c)Measured 450 nm(d)SPAD power excluded6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference42 of 47Performance SummaryParametersUnitThis WorkVLSI24ChoJSSC21ParkVLSI19ParkISSCC22Manuzza
136、toJSSC22ParkISSCC21PadmanabhanProcess-110 nm BSI110 nm BSI110 nm110 nm110 nm110 nm45 nm BSI 3D-StackedToF Type-SPAD-BasedIndirect ToFAPD-BasedIndirect ToFSPAD-BasedDirect ToFBGL Suppressionklx12090120(a)200303010Max.Depth Rangem767050208.245100Depth Precisioncm6.4711.356(b)271.5N/AFrame Ratefps50306
137、5962530N/APixel Resolution-64 6464 6464 6464 6464 6480 60256 128Pixel Pitchm3232323248757Fill Factor%333326.32112.910.4N/APDP VEX%14.3 2 V14.3 2 V5.85 1 VN/A54.5(c)6.6 V3 2.5 VN/AIllumination Wavelengthnm850850850820905905780Illumination PowermW5.96N/AN/AN/A5.8-9.33.05.0Chip Sizemm22.9 2.92.9 2.93 3
138、3 3N/A7.03 5.92.08 1.06Chip PowermW39.429.142.7N/A205.7132(d)51.9(a)Short integration and multiple-frame accumulation(b)Calculated Value(c)Measured 450 nm(d)SPAD power excluded6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-Sta
139、te Circuits Conference43 of 47Performance SummaryParametersUnitThis WorkVLSI24ChoJSSC21ParkVLSI19ParkISSCC22ManuzzatoJSSC22ParkISSCC21PadmanabhanProcess-110 nm BSI110 nm BSI110 nm110 nm110 nm110 nm45 nm BSI 3D-StackedToF Type-SPAD-BasedIndirect ToFAPD-BasedIndirect ToFSPAD-BasedDirect ToFBGL Suppres
140、sionklx12090120(a)200303010Max.Depth Rangem767050208.245100Depth Precisioncm6.4711.356(b)271.5N/AFrame Ratefps503065962530N/APixel Resolution-64 6464 6464 6464 6464 6480 60256 128Pixel Pitchm3232323248757Fill Factor%333326.32112.910.4N/APDP VEX%14.3 2 V14.3 2 V5.85 1 VN/A54.5(c)6.6 V3 2.5 VN/AIllumi
141、nation Wavelengthnm850850850820905905780Illumination PowermW5.96N/AN/AN/A5.8-9.33.05.0Chip Sizemm22.9 2.92.9 2.93 33 3N/A7.03 5.92.08 1.06Chip PowermW39.429.142.7N/A205.7132(d)51.9(a)Short integration and multiple-frame accumulation(b)Calculated Value(c)Measured 450 nm(d)SPAD power excluded6.3:SPAD
142、Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference44 of 47Comparison with state-of-the-artsISSCC22ManuzzatoJSSC22ParkJSSC21ParkThisWorkVLSI24ChoISSCC21PadmanabhanBGL Suppression klxMaximum Depth Range m02040608010
143、012014001020304050607080901006.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference45 of 47Figure of Merits(FoM)FoM=Depth precision PowerFrame rate Pixel numberThis WorkVLSI24ChoJSSC21ParkISSCC22ManuzzatoJSSC
144、22Park102103104105Figure of Merits1622373623056661436.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light 2025 IEEE International Solid-State Circuits Conference46 of 47Conclusion SPAD-Based 6464 Flash LiDAR sensorIndirect ToF technique with backside illuminated(
145、BSI)processChopped charge-injection analog counter(Multiple chopping):9-Bit counter achieving 12-Bit effective performanceBackground light suppression up to 120 klxAchieves 76 m depth range with 6.4 cm depth precision6.3:SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Backgroun
146、d Light 2025 IEEE International Solid-State Circuits Conference47 of 47Conclusion SPAD-Based 6464 Flash LiDAR sensorIndirect ToF technique with backside illuminated(BSI)processChopped charge-injection analog counter(Multiple chopping):9-Bit counter achieving 12-Bit effective performanceBackground li
147、ght suppression up to 120 klxAchieves 76 m depth range with 6.4 cm depth precisionThank you for the attention!6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference1 of 43A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked D
148、igital Pixel SensorTsung-Hsun Tsai1,Kwuang-Han Chang2,Andrew Berkovich1,Raffaele Capoccia3,Song Chen1,Zhao Wang4,Chiao Liu1,Yi-Hsuan Lin2,Sheng-Yeh Lai2,Hao-Ming Hsu2,Hirofumi Abe5,Kazuya Mori5,Hideyuki Fukuhara5,Chih-Hao Lin2,Toshiyuki Isozaki5,Wei-Chen Li2,Wei-Fan Chou2,Masayuki Uno5,Rimon Ikeno5,
149、Masato Nagamatsu5,Guang Yang2,Shou-Gwo Wuu2,Lyle Bainbridge61Meta,Redmond,WA2Brillnics,Hsinchu,Taiwan3Meta,Zrich,Switzerland4Meta,Burlingame,CA5Brillnics,Tokyo,Japan6Sesame AI,San Francisco,CA 6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-S
150、tate Circuits Conference2 of 43Outline Motivation Technology Measurement Result Summary6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference3 of 43Outline Motivation Technology Measurement Result Summary6.4:A 400400 3.24m
151、117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference4 of 43Motivation AR glasses is a context-rich computing platform Tailor personalized messages and experiences6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 20
152、25 IEEE International Solid-State Circuits Conference5 of 43Motivation Many cameras are required to generate personalized data Small sensor is important to lightweight deviceSide CameraFront CameraInward Camera6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE Inte
153、rnational Solid-State Circuits Conference6 of 43ApplicationSimultaneous localization and mapping(SLAM)Good low-light High dynamic range Low power6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference7 of 43ApplicationSimult
154、aneous localization and mapping(SLAM)Hand Tracking(HT)Good low-light High dynamic range Low power High dynamic range Fast readout Low power6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference8 of 43ApplicationSimultaneous
155、 localization and mapping(SLAM)Hand Tracking(HT)Eye Tracking(ET)Good low-light High dynamic range Low power High dynamic range Fast readout Low power Good low-light Fast readout Low power6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State C
156、ircuits Conference9 of 43Sensor Requirement Global shutter VGA Low-light performance High dynamic range(HDR)Fast readout Low power Small size6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference10 of 43Sensor ChoiceCharge
157、DomainCMOS Image Sensor ProcessFront-illuminatedSensitivityNoiseSingle-Exposure Dynamic RangeReadout SpeedPowerSensor Dimension6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference11 of 43Sensor ChoiceCharge DomainVoltage
158、DomainCMOS Image Sensor ProcessFront-illuminatedBack-illuminatedStackingSensitivityNoiseSingle-Exposure Dynamic RangeReadout SpeedPowerSensor Dimension6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference12 of 43Sensor Cho
159、iceCharge DomainVoltage DomainDigital PixelCMOS Image Sensor ProcessFront-illuminatedBack-illuminatedStackingBack-illuminatedStackingSensitivityNoiseSingle-Exposure Dynamic RangeReadout SpeedPowerSensor Dimension6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE In
160、ternational Solid-State Circuits Conference13 of 43Sensor ChoiceCharge DomainVoltage DomainDigital PixelCMOS Image Sensor ProcessFront-illuminatedBack-illuminatedStackingBack-illuminatedStackingSensitivityNoiseSingle-Exposure Dynamic RangeReadout SpeedPowerSensor DimensionFocus of this work6.4:A 400
161、400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference14 of 43Outline Motivation Technology Measurement Result Summary6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Ci
162、rcuits Conference15 of 43Stacked Digital Pixel 2-layer stacked CIS and ADC pixels Pixel size reduction is limited by ADC circuit 6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference16 of 43Solution:AC-coupled*ADC*C.C.-M.L
163、iu,et al.,ISSCC,pp.124-126,2016.High-density 3D-MIM capOptimized for kTC noise3T singled-ended comparatorHigh PSRR and low leakage6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference17 of 43Pixel,Logic and SRAM Design*S.S
164、ugawa,et al.,ISSCC,pp.352-354,2005.5T pixel with LOFIC*In-pixel current loadCustomized logic10b 6T SRAMPower gating6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference18 of 43HDR Operation Triple quantization*(3Q)delivers
165、 single-exposure HDRGlobal shutter and pixel-parallel ADCTime-to-saturation(TTS)High conversion gain ADCLow conversion gain ADC*C.Liu,et al.,IEDM,2020.6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference19 of 432-Layer St
166、acked DPS Peripheral circuits increase die sizeCIS Pixel ArrayAnalog+DigitalADC Pixel Array2-layer DesignTop LayerBottom Layer6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference20 of 43Solution:3-Layer Stacked DPS Digita
167、l circuits moved to a third layer 2.471.85mm2(30%reduction from 2-layer design)CIS Pixel ArrayAnalog+DigitalADC Pixel ArrayCIS Pixel ArrayAnalogADC Pixel ArrayDigital2-layer Design3-layer DesignSize reductionSize reductionTop LayerBottom LayerTop LayerMiddle LayerBottom Layer6.4:A 400400 3.24m 117dB
168、-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference21 of 43Fixed-Pattern Noise(FPN)DPS has high FPN due to in-pixel ADCCaused by variation and low-power operationHigh FPN leads to feature detection error6.4:A 400400 3.24m 117dB-Dynamic-Range 3-
169、Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference22 of 43FPN Correction(FPNC)Off-chip FPNC increases system complexity Digital correlated double sampling*grows pixel sizeFPNC*M.-W.Seo,et al.,IEEE JSSC,Apr.2022,pp.1125-1137.6.4:A 400400 3.24m 117dB-Dynamic-Ran
170、ge 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference23 of 43Solution:Frame Averaging Unit(FAU)FAU generates reference frames for FPNCPseudo-dark frames capture pixel intrinsic FPN Recursive averaging:+=()+(+)6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer St
171、acked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference24 of 43Image Signal Processing(ISP)BLC integrated in FPNC for efficient design Configurable tone mapping for HDR Defective pixel correction(DPC)for certain applications6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer St
172、acked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference25 of 43FAU Initialization Initialization only once at sensor power-up Reference frame stored in a frame buffer6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-S
173、tate Circuits Conference26 of 43Normal Operation Reference frame sent to ISP in parallel with normal frame FPNC:ISP subtracts reference frame from normal frame6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference27 of 43Re
174、ference Frame Rolling Update FPN may change if temperature drifts significantly Triggered after readout,not affecting normal operation6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference28 of 43Additional Requirement for
175、SLAMSimultaneous localization and mapping(SLAM)Good low-light High dynamic range Low powerSufficient for reliable trackingSparse readout does not increase pixel sizeSparse regions 6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits
176、 Conference29 of 43Solution:Sparse Transmission(ST)Simultaneous localization and mapping(SLAM)Good low-light High dynamic range Low power Sparse transmission(ST)System power savingsSufficient for reliable trackingSparse readout does not increase pixel sizeSparse regions Sensor only sends data reques
177、ted by the algorithm6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference30 of 43Transmission Map(TM)Sensor uses a TM to select the regions for ST readoutEncoded to reduce map transmission timeDecoded on sensor prior to ST
178、 readoutEach map value selects a 22 pixel cluster2002001b1:activated0:deactivated6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference31 of 43TM Update and Data Packing TM is updated before readout begins Selected clusters
179、 are packed into individual lines6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference32 of 43ST Readout 5%TM transmits only 20 lines(400 lines for full frame)Power savings from fewer HS transmission states6.4:A 400400 3.2
180、4m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference33 of 43Outline Motivation Technology Measurement Result Summary6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits
181、Conference34 of 43Sensor Die and Characterization Board2.47 mm1.85 mmSensor PhotomicrographSensor Characterization Board6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference35 of 43Dark Noise Temporal noise not affected wi
182、th FPNC FPN significantly improved4.4 e-rms2.4 e-rms10.7 e-rms6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference36 of 43Photon Response Curve Wide intra-scene single-exposure HDRPD-ADC117 dBFD-ADCTTS6.4:A 400400 3.24m 1
183、17dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference37 of 43Sample Image(Gamma-enhanced)Capture setup(light off)Raw6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Confe
184、rence38 of 43Sample Image(Gamma-enhanced)ISP-enabled FPNC improves low-light details Tone mapping improves high-light featuresRaw6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference39 of 43ST ReadoutTM(white=activated)Rec
185、onstructed ST readout6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference40 of 43Performance BenchmarkSpecificationThis workTED 2022 2*JSSC 2022 3*JSSC 2018 5*Process technology45/40/4045/6565/2890/65Pixel size m3.244.64.
186、956.9Resolution(HV)400400512512166813641632896In-pixel memory10b10b22b15bLinear full well ke-5.5/18.7/3300*3.8/51/9000*716.6Noise floor e-rms4.44.24.65.15Dynamic range dB11712763.670.2Dark FPN e-rms2.4471.940.58Power mW3.06 30 fps5.75 30 fps116.2 30 fps746 660 fpsFoM*e-rmspJ0.00490.18096.061.24*2 R.
187、Ikeno,et al.,IEEE TED,2022.3 M.-W.Seo,et al.,IEEE JSSC,2022.5 M.Sakakibara,et al.,IEEE JSSC,2018.*Equivalent full well.*FoM=(power noise)/(number of pixels frame rate DRU);DRU=(saturation/gain)/noise.6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International
188、Solid-State Circuits Conference41 of 43Outline Motivation Technology Measurement Result Summary6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-State Circuits Conference42 of 43Summary First reported 3-layer stacked DPS 3.24m pixel size with s
189、ingle-ended comparator On-sensor FPNC enabled by FAUImprove tracking accuracy Configurable ST readoutReduce system power Suitable for AR glassesLowest FoM among published DPSs2.471.85mm2die size6.4:A 400400 3.24m 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor 2025 IEEE International Solid-
190、State Circuits Conference43 of 43Thank You6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference1 of 31A 25.2Mpixel 120frames/s Full-FrameGlobal-Shutter CMOS Image Sensorwith Pixel-Parallel ADCToshiki
191、 Kainuma,Ryo Wakamatsu,Kimitaka Wada,Tohru Takeda,Shota Ueyama,Hiroki Suto,Tsukasa Miura,Koushi Uemura,Masao Kimura,Masaki Sakakibara,Yusuke OikeSony Semiconductor Solutions Corporation,Atsugi,Japan6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 202
192、5 IEEE International Solid-State Circuits Conference2 of 31Outline Background Key technologies Characteristics Summary6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference3 of 31Outline Background Ke
193、y technologies Characteristics Summary6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference4 of 31Background(1/4)CMOS image sensors with rolling shutters currently dominate the market for consumer ca
194、meras A rolling shutter has limitations in image expressionFlash bandFlicker effectDistortionRolling shutterAddressTimeReadShutterExposure time6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference5 o
195、f 31Background(2/4)A global shutter dose not have rolling shutter degradation effects Full-fledged consumer cameras with global shutters have not been realized,particularly interchangeable lens camerasNo flash bandNo flicker effectNo distortionGlobal shutterAddressTimeReadShutterExposure time6.5:A 2
196、5.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference6 of 31Background(3/4)GS TechnologyCharge domainVoltage domainDigital domainStructureSensitivityBadSaturation signalBadRandom noiseBadImagePDADCFDPDCFDPD
197、MEMFD Previous studies have proposed various global shutter technologies6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference7 of 31Background(3/4)GS TechnologyCharge domainVoltage domainDigital doma
198、inStructureSensitivityBadSaturation signalBadRandom noiseBadImagePDADCFDPDCFDPDMEMFD The memory area and the light shield degrade the sensitivity and saturation signal6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-Stat
199、e Circuits Conference8 of 31Background(3/4)GS TechnologyCharge domainVoltage domainDigital domainStructureSensitivityBadSaturation signalBadRandom noiseBadImagePDADCFDPDCFDPDMEMFD The noise characteristics due to thermal noise of kT/C degrades captured images6.5:A 25.2-Mpixel 120-frames/s Full-Frame
200、 Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference9 of 31Background(3/4)GS TechnologyCharge domainVoltage domainDigital domainStructureSensitivityBadSaturation signalBadRandom noiseBadImagePDADCFDPDCFDPDMEMFD This technology might achiev
201、e the sensitivity,saturation signal and random noise for full-fledged consumer cameras6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference10 of 31Background(4/4)PaperJSSC201810JSSC202211TED202212VLS
202、I202313IEDM202314Pixel size m26.94.954.66.34.23ADC resolution bit141010108Frame rate fps6601200303030Total pixels Mpixels1.46 2.28 0.26 0.31 1.96 2MpixThis work25.2MpixFull-frameformatIssues:Random noise Power consumption High-speed readoutPixel-Parallel ADC2023For full-fledgedconsumer cameras ABC6.
203、5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference11 of 31Outline Background Key technologies Characteristics Summary6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with P
204、ixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference12 of 31Block diagramPixel chipPixel Bias6144(H)x 4104(V)PixelsCu-Cu Connection for Pixel ControlLogic chip DAC1536(H)x 16416(V)ADCs and 768 RepeatersPixel DriverSLVS-ECLogic DriverLogic DriverGC GenCDSADC8 Pix1 PixPixA part of
205、 Repeater2 ADC4 ADCADC6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference13 of 31 Noise Power SpeedLogic chip DACPixel DriverSLVS-ECGC GenCDS1536(H)x 16416(V)ADCs and 768 RepeatersREFPixelADCReset
206、LatchSignal LatchC3 key technologies Noise bandwidth control for low random noise Double latch configuration for low power consumption Pipeline readout from latches for high-speed readout123Repeater123DATAADCKFFR/WR/WFF16LatchABCADCKDATA6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS I
207、mage Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference14 of 31 Basic concept is same of the previous work 10 Double conversion gain for full-fledged consumer cameras Column circuit diagram10 M.Sakakibara,et al.,JSSC,Nov.2018,pp.3017-3025Pixel Chip6.5:A 25.2-Mpixe
208、l 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference15 of 31VCOINIVDDLVDDHFORCEVPFBVCRVCLIcmFDINI2REFNoise bandwidth control(1/4)Positive feedback structure helps to enhance operation speed without increasing stati
209、c current consumptiontVVPFBtVVCOVthNORw/o PFBw/PFB+VDDLIchargeIchargeIpfbPositive feedbackIchargeIpfb6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference16 of 31Noise bandwidth control(2/4)LV-NMOS c
210、apacitor*is connected to VPFB to limit the CM noise bandwidthtVVPFBVthNORVDDLtflip1 1tflip2VCOINIVDDLVDDHFORCEVPFBVCRVCLIcmFDINI2REFLower noise*I.Park,et al.,JSSC,Apr.2019,pp.898-9076.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE Internati
211、onal Solid-State Circuits Conference17 of 31Noise bandwidth control(3/4)AddressTimeADC&ReadoutColumn-parallelAddressTimeADC&ReadoutADCtimex 2 In the column-parallel ADC,the frame rate is affected significantly by the noise bandwidth control 1 frame1 frame6.5:A 25.2-Mpixel 120-frames/s Full-Frame Glo
212、bal-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference18 of 31Noise bandwidth control(4/4)AddressTimeADC&ReadoutColumn-parallelAddressTimeADC&ReadoutPixel-parallelADCR/OAddressTimeADC&ReadoutAddressTimeADC&ReadoutADCtimex 2 In the pixel-parallel
213、 ADC,the frame rate is almost not affected by the noise bandwidth controlADCR/O6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference19 of 31Double latch configurationSRAMLatchRepeaterREFIcmOutSignalR
214、esetResetSignalResetPrevious work 10,6.9m2OutResetThis work,5.94m2SignalWithoutFrame SRAMPowerReductionLatchREF15b Although its implemented double latches by the advanced process,it is achieved the smaller pixel size and low power consumptionLatchSREF15+1bLatchR13+1b6.5:A 25.2-Mpixel 120-frames/s Fu
215、ll-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference20 of 31Pipeline readout from latches(1/2)From latches to R/W buffers settling time is dominant for readout due to long common wire line(local bit line)Local Bit Line01WORD0Master
216、 Bit LineDATAADCKGCGenFFR/WR/WR/WFFFF1616Local Bit LineResetSignalWORD101WORD0WORD1Master Bit LineSettling dominanttLatchLatchLatchPrevious work 10FFFF6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Confe
217、rence21 of 31Pipeline readout from latches(2/2)High-speed readout from latches to R/W buffers is achieved by pipeline readout Local Bit Line LefttWORD R0L0R0L0R0L1R1WORD R1WORD L0WORD L1Local Bit Line RightMaster Bit LineResetSignalThis workDATAADCKGCGenFFR/WR/WR/WR/WR/WR/W1616Local BitLine RightLoc
218、al BitLine LeftMaster Bit LineLatchLatchLatchLatchLatchLatchFFFFFFFF6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference22 of 31Outline Background Key technologies Characteristics Summary6.5:A 25.2-
219、Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference23 of 31Implementation result(1/2)39.8 mm32.7 mm6144Hx 4104V25.2M PixelsDAC,Pixel DriverGC2BC,CDS1536Hx 16416V25.2M ADCs768 RepeatersBonding Interface5.0mBot
220、tom chipTop chipTop chip:90nm 1P4MBottom chip:40nm 1P10M6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference24 of 31Implementation result(2/2)39.8 mm32.7 mm6144Hx 4104V25.2M PixelsDAC,Pixel DriverGC
221、2BC,CDS1536Hx 16416V25.2M ADCs768 RepeatersTop chipBottom chip5.94 m5.94 mPixA part of repeaterADC5.94 m23.76 mCu-Cu connection6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference25 of 31Chip charac
222、teristicsSupply voltage2.9 V/1.1 VNum.of pixels6144Hx 4104V (25.2M)Pixel size5.94 m x 5.94 mOutput interface8ch x 9.216 Gbps/ch SLVS-ECMax frame rate120 fpsConversion gain62.7 V/e-24.8 V/e-Saturation signal15.8k e-40.0k e-Sensitivity101,000 e-/lxsINL+0.32%+0.33%FPN 0dB gain0.27 LSBrms0.20 LSBrmsComp
223、arator operation current25 nAPower consumption1545 mWRandom noise 0dB gain2.66 e-rms7.02 e-rmsDynamic range75.5 dB75.1 dBADC resolution14 bit6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference26 of
224、 31Performance comparisonPaperThis workJSSC201810JSSC202211JSSC20211VLSI202316ADCSSSSSSSSParallel architecturePixelPixelPixelColumnColumnGlobal shutterYesYesYesNoNoCIS/Logic process nm90/4090/6565/2890/4090/40ADC resolution bit1414101414Frame rate fps120660120044224Total pixels Mpixels25.211.46 2.28
225、 50.107.3 Random noise 0dB e-rms2.66 5.15*4.26 1.18 1.60 Power consumption mW1545746598.527601360FoM e-rmspJ/step0.083 0.243 0.456 0.090 0.081FoM=(power noise0dB)/(#of pixels fps 2(ADC resolution)*Calculated from the full well capacity of 38ke-and the DR of 79dB GS operates with a binning of 22 2.47
226、5-m pixels6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference27 of 31Captured imageExposure time:1/80000 s,23000 lux6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with P
227、ixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference28 of 31VideoCapture:120 fps,Play:15 fps6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference29 of 31Outline Background Key te
228、chnologies Characteristics Summary6.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference30 of 31Summary A 25.2Mpixel 120fps full-frame global shutter CMOS image sensor with pixel-parallel ADC is achie
229、ved by 3 key technologies:Noise bandwidth control 2.66e-rms0dBDouble latch configuration Pipeline readout from latches The sensor achieved an FoM(e-rms pJ/step)of 0.083,which is comparable to the state-of-the-art rolling shutter image sensors designed for full-fledged consumer cameras25Mp,14bit,120f
230、ps,1545mW1236.5:A 25.2-Mpixel 120-frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 2025 IEEE International Solid-State Circuits Conference31 of 31Thank you for your attention!6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-t
231、o-Phase ADC 2025 IEEE International Solid-State Circuits Conference1 of 48A 320 256 6.9mW 2.2mK-NETD 120.4dB-DRLW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADCYi Zhuo1,Hangyu Lu2,Ding Ma3,Zheng Zhou1,Linxiao Shen1,Yacong Zhang1,Zhongjian Chen1,Xixin Cao1,Yimao Cai1,Ning Li2,3,Weng
232、ao Lu11 Peking University,Beijing,China2 Hangzhou Institute for Advanced Study,UCAS,Hangzhou,China3 Shanghai Institute of Technical Physics Chinese Academy of Sciences,Shanghai,China6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE
233、 International Solid-State Circuits Conference2 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackground and Motivation6.6:
234、A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference3 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase E
235、xtractionPixel-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference4 of 48Long-wavelength Cry
236、ogenic IRFPA High sensitivity&Rapid response Ultra-low temperature operation Performance limited by cooling efficiencyPrecision AgricultureSpace ExplorationIndustrial SafetyHealth CareIRFPA:Infrared Focal Plane ArrayQWIP:Quantum Well Infrared PhotodetectorQWEtched gratingEtch stop layerIndium Pillar
237、QWIP IRFPA Pixel StructurePower Consumption6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference5 of 48Response=10.5 mNarrowbandResponse Low Quantum Efficiency Design Flexibility via Band E
238、ngineering High Uniformity&Scalability Narrowband ResponseExportabilityScalabilityIntegrabilitySystem CostPerformanceMCTQWIPMCT:Mercury Cadmium TellurideLWIR QWIP Cryogenic IRFPAphotocurrentDROIC:Digital Read-Out Integrated CircuitQWEtched gratingEtch stop layerIndium PillarQWIP IRFPA Pixel Structur
239、e6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference6 of 48 Demand:High FWC&Low Noise1=350=20*=minHigh HDR Low NETDHigh SNRHigh FWCLow Noise=HDRSDRLong-wavelength Cryogenic IRFPA ROICROIC
240、:Read-Out Integrated CircuitNETD:Noise Equivalent Temperature DifferenceFWC:Full Well ChargeHDR:High Dynamic RangeSDR:Standard Dynamic Range6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Confer
241、ence7 of 48Traditional Pixel-level ADCSS-ADCISSCC229TVLSI2310IF-ADCASSCC211TCASI1932-StepADCVLSI122TCASII225CintfsCounterVrefVintAnalog DigitalTGHigh Well CapacityHigher SNRHigh Quantization NoiseExplicit AmplifierHigh LinearityLow NoiseLimited SNRExplicit AmplifierLow Quantization NoiseHigher Resol
242、utionExtra HardwareExplicit AmplifierCintCFD1VRamp AZCLKCounterAnalogDigitalTGSS:Single SlopeIF:Current Frequency Conversion6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference8 of 48Tradi
243、tional Pixel-level ADCSS-ADCISSCC229TVLSI2310IF-ADCASSCC211TCASI1932-StepADCVLSI122TCASII225CintfsCounterVrefVintAnalog DigitalTGHigh Well CapacityHigher SNRHigh Quantization NoiseExplicit AmplifierHigh LinearityLow NoiseLimited SNRExplicit AmplifierLow Quantization NoiseHigher ResolutionExtra Hardw
244、areExplicit AmplifierCintCFD1VRamp AZCLKCounterAnalogDigitalTGSS:Single SlopeIF:Current Frequency Conversion6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference9 of 48Traditional Pixel-lev
245、el ADCSS-ADCISSCC229TVLSI2310IF-ADCASSCC211TCASI1932-StepADCVLSI122TCASII225CintfsCounterVrefVintAnalog DigitalTGHigh Well CapacityHigher SNRHigh Quantization NoiseExplicit AmplifierHigh LinearityLow NoiseLimited SNRExplicit AmplifierLow Quantization NoiseHigher ResolutionExtra HardwareExplicit Ampl
246、ifierCintCFD1VRamp AZCLKCounterAnalogDigitalTGSS:Single SlopeIF:Current Frequency Conversion6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference10 of 48SS-ADCIF-ADC2-StepADCCintfsCounterVr
247、efVintAnalog DigitalTGHigh Well CapacityHigher SNRHigh Quantization NoiseExplicit AmplifierLow Quantization NoiseHigher ResolutionExtra HardwareExplicit AmplifierAmplifier In ROIC Interference&Power ConsumptionTraditional Pixel-level ADCCintCFD1VRamp AZCLKCounterAnalogDigitalTGSS:Single SlopeIF:Curr
248、ent Frequency ConversionHigh LinearityLow NoiseLimited SNRExplicit Amplifier6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference11 of 48SS-ADCIF-ADC2-StepADCCintfsCounterVrefVintAnalog Dig
249、italTGHigh Well CapacityHigher SNRHigh Quantization NoiseExplicit AmplifierHigh LinearityLow NoiseLimited SNRExplicit AmplifierLow Quantization NoiseHigher ResolutionExtra HardwareExplicit AmplifierWithout AmplifierLow PowerLow NoiseScaling downTraditional Pixel-level ADCCintCFD1VRamp AZCLKCounterAn
250、alogDigitalTGSS:Single SlopeIF:Current Frequency Conversion6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference12 of 48Amplifier-less！Capacitor-less！Ultra-low Power！Photocurrent Drive Modu
251、lator Low DC Current Low Bus SwingHigh Saturation Value！Wide Range of Operating Temp.！QWIP fsPhotoconductive stageDigitalTGTGLCOPhase ReconstructorCounterProposed Pixel-level IP-ADCBusFully composed of digital circuitsIP:Current Phase Conversion6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with
252、Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference13 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel-level 20-bit Asynchronous Gray-code
253、Low-swing Bus Data Transfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference14 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Curr
254、ent-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE Intern
255、ational Solid-State Circuits Conference15 of 48Light Current-Controlled Oscillator Powered only by photocurrent!Time-encoding ADC with ring oscillators！I FI PPhase Modulation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE Interna
256、tional Solid-State Circuits Conference16 of 48Phase 0Each node is initialized,awaiting photocurrent.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference1
257、7 of 48Phase 1：P0 rising,P1=1,P2=0；The photocurrent is accumulated on the parasitic capacitance.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference18 of
258、 48Phase 2：P0 rising,P1 falling,P2=0；The voltage at P0 triggers the NMOS,causing P1 node to discharge.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conferenc
259、e19 of 48Phase 3：P0=1,P1=0,P2 rising；The photocurrent is accumulated on the P2 node.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference20 of 48Phase 4：P
260、0 falling,P1=0,P2 rising；The current discharges at the P0 node.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference21 of 48Phase 5：P0=0,P1 rising,P2=1；Th
261、e photocurrent is accumulated on the P1 node.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference22 of 48Phase 6：P0=0,P1 rising,P2 falling；The current di
262、scharges at the P2 node.Light Current-Controlled Oscillator6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference23 of 48 The charging and discharging occur alternately at different PN nodes
263、 Unlimited continuous quantization of photocurrent A 120 phase difference between the node signal Stable VP =(t)+N”120 P0P1P2PNLight Control Oscillator IlightPhotocurrent Power SupplyVCOMPixel-to-Pixel Stacked ConnectionVPP0P1P2IlightIlight(t)CLP1Light Current-Controlled Oscillator=+6.6:A 320256 6.9
264、mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference24 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPi
265、xel-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference25 of 48Phase Reconstructor Phase inf
266、ormation is shaped into a square wave Extract sub-phases with XOR logicFully Digital Circuits6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference26 of 48Phase Reconstruction 50%Duty cycle
267、High-VTHPMOS Low-VTHNMOS XOR Logic=6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference27 of 48Sub-phase Extraction 50%Duty cycle High-VTHPMOS Low-VTHNMOS XOR Logic=6.6:A 320256 6.9mW 2.2m
268、K-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference28 of 48Sub-phase ExtractionLow Quantization NoiseBetter Low-light Performance 50%Duty cycle High-VTHPMOS Low-VTHNMOS XOR Logic=6.6:A 320256 6.9mW 2.2mK-NETD 1
269、20.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference29 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel-level 20-bi
270、t Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference30 of 4820-bit Asynchronous Gray-code CounterFewer s
271、ampling errorsFewer transistors(akin to a conventional binary counter)6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference31 of 4820-bit Asynchronous Gray-code CounterPhase Division Coeffi
272、cientsNS:ND:Oscillator StageThis work:NS=3,ND=6 High FWC&High HDR20bit Counter6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference32 of 48Pixel-level CircuitsLight Control Oscillator Iligh
273、tP2P1P0Phase Reconstructor POP2P1P0fsCounter 20Bit AsyncGray CountersDoutHigh VTH MOSFETLow VTH MOSFETRSPhotocurrent Power SupplyVDDL Power SupplyVDD Power SupplyVCOMPixel-to-Pixel Stacked ConnectionPhase Division CoefficientsNS:ND:Oscillator StageThis work:NS=3,ND=6 =+Expression=6.6:A 320256 6.9mW
274、2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference33 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel
275、-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference34 of 48Low-swing Bus Data Transfer Circ
276、uitLength of Bus 8mmPreviousThis WorkBusColumn D-LatchVb13RS.CP2pFVDDCKPixelD-LatchCPRSBusCKPrevious This WorkCrosstalkPower Consumption6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference
277、35 of 48Low-swing Bus Data Transfer CircuitPixelBusColumn D-LatchVb13RS.Data=0Pull-up Pull-down D-Latch Receive 1VBus Vdsat1.8V26mVBus Swing Reduced to 26mVVDDGND0123Power(mW)ProposePrevious2.5mW0.9mW64%6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-t
278、o-Phase ADC 2025 IEEE International Solid-State Circuits Conference36 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Transfer CircuitBackgro
279、und and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference37 of 48LCO Temperature Drift Working EnvironmentLowest Temperature:10 KTypical Temperature:40 KVacuum Level:10-6 BarL
280、CO Temperature Drift（mixed QWIP）The cryostats suppresses the impact of temperature drift6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference38 of 48The Noise Performance Of The IRFPA020406
281、08010012014016018010-1100101102103104105106107SNR(dB)-140-120-100-80-60-40-200Input Amplitude(dBFS)Digital Code SNR Digital CodeDR=120.4dB109dB*Quantization noise included The Maximum SNR:109dB Dynamic range:120.4 dB=Nonlinearity mainly from QWIP6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with
282、 Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference39 of 48The NETD Of The LW-IRFPA012345678901.5K3K4.5K6K7.5KNumber of pixelsNETD(mK)1.62.22.83.44.0NETD 2.2mKLower PowerBetterNETD1.6mK6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with P
283、ixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference40 of 48The Power Consumption Of The IRFPAI/O25.4%Others34.5%Pixel27.1%Column13%2.6%2.2%22.3%8070605040302051015Power(mW)Input Amplitude(dBFS)20 BlackbodyBase PowerReconstructorSensorCounter80
284、70605040302051015Power(mW)Input Amplitude(dBFS)100 BlackbodyBase Power4.2%3.1%33.9%I/O20.5%Others27.8%Pixel41.2%Column10.5%ReconstructorSensorCounter6.9mW8.6mW6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-St
285、ate Circuits Conference41 of 48Image Pattern6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference42 of 48Image Pattern6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-Paralleled
286、Light-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference43 of 48Application Demo SF6 Gas DetectionGas Output Flow Rate1uL/s60KCryostats35 BackgroundBlackbodySF60.1uL/s6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-
287、to-Phase ADC 2025 IEEE International Solid-State Circuits Conference44 of 48320256ROIC（bottom)320 256LW QWIP Array(Top)9.4mm10.6mmQWIP Sensor Array320(H)256(V)D-Pixel ArrayROICPixel-to-PixelIndium ConnectionStacked IRFPA Array Uniformity MeasurementMeasured at 20 Blackbody FPN=0.57%Full Range ROIC F
288、PN FPN=0.23%Full Range FPN=0.97%Full Range IRFPA FPNIRFPA FPN After Calibration6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference45 of 48Comparison with Prior WorksThis Work1ASSCC212 VLS
289、I123TCAS I194VLSI236ISSCC189ISSCC2210TVLSI23CategoryIRFPAIRFPAHDR-CISProcess180nm40nm180nm90nm180nm180nm45/65nm(stack)55nmSupply Voltage1.8V1.1V-3-3.6/1.8V2.6/3.6V-3.3/1.2VArray Size/Pixel Pitch32025630m64051230m32025630m161615m32025618m32025617m3202564.6m3202562.9mFrame Rate60Hz60Hz 50Hz400Hz90Hz60
290、Hz30Hz30HzDynamic Range120.4dB105dB-127dB120dBFull Well Capacity36Ge-3Ge-3Ge-2.4Ge-3.8k/9Me-35.5ke-ADC Resolution20bit18bit16bit5bit15bit-10bit12bitTotal Power Consumption6.9mW250mW 72mW1.1mW14.11mW47mW5.75mW150mWSNR109dB90.1dB88dB82dB-NETD2.2mK1.8mK-52mK100mK-FoM 1*(fJ/step)0.1622.25 76.29-357 39.0
291、6FoM 2*(fJ/LSB)30.46243 428 470-Estimated from the figures in the paper Provide in subsequent journals of the paper*FoM18=PADC/(2Frame rate)2(ADC Resolution)*FoM23=Ptotal/(The number of pixels)(2Frame rate)2(SNR-1.76)/6.026.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-D
292、riven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference46 of 48OutlineMeasurement ResultsConclusionCircuit ImplementationLight Current-Controlled OscillatorPhase Reconstruction Circuit&Sub-phase ExtractionPixel-level 20-bit Asynchronous Gray-codeLow-swing Bus Data Tran
293、sfer CircuitBackground and Motivation6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference47 of 48ConclusionAchieves 120.4dB HDR,2.2mK NETD,6.9mW Typical Power ConsumptionA low-swing bus da
294、ta transfer circuitAn innovative ADC based on a per-pixel ring oscillator and a LCO for current-phase modulation powered only by photocurrentA light current-controlled oscillator(LCO)based modulator for IP-ADCA phase reconstruction circuit which reduces quantization noise by sub-phase extractionA pi
295、xel-level 20-bit asynchronous gray-code counter6.6:A 320256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-ParalleledLight-Driven 20b Current-to-Phase ADC 2025 IEEE International Solid-State Circuits Conference48 of 48THANK YOU!1 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Cal
296、ibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-State Circuits ConferenceA 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel
297、and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Junghwan Oh,Wiman Yoo,Dong-Kun Lee,and Jong-Seok KimHanyang University,Ansan,Korea2 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI O
298、LED-on-Silicon Displays Outline 2025 IEEEInternational Solid-State Circuits Conference Background Proposed OLEDoS SD-IC Architecture of SD-IC Small-Area SD-IC Fast SD-IC Small-DVO SD-IC Measured Result Performance Comparison Summary3 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset
299、Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Outline 2025 IEEEInternational Solid-State Circuits Conference Background Proposed OLEDoS SD-IC Architecture of SD-IC Small-Area SD-IC Fast SD-IC Small-DVO SD-IC Measured Result
300、Performance Comparison Summary4 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-State Circuits ConferenceImage:Apple,Vision ProBack
301、ground5 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-State Circuits Conference*120 FoV and 60PPD are required for realistic visi
302、on.Field of view(FoV)Pixel per degree(PPD)Required specificationField of view(FoV)Horizontal:120*,Vertical:120*Pixel per degree(PPD)60PPD*Resolution7.2K 7.2K(12060)(12060)Background-Resolution-6 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Ampl
303、ifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-State Circuits ConferenceFrame rate of at least 120Hz is required.Dizziness,blurred visionNo dizziness,clear visionLow frame rateHigh frame rateBackground-Frame Rate-7 of 516.7:A 10b Sourc
304、e-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-State Circuits ConferenceFoV60FoV120Large TV170cm440cmAR/VR display1,4K 2K(Display panel)1.2cm2.3cmMicr
305、o display75,4K 2K(Display panel)100cm200,4K 2K(Virtual screen)260cmBackground-Micro Display for AR/VR Device-8 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2
306、025 IEEEInternational Solid-State Circuits ConferenceSmall pixel area is required silicon substrate&CMOS processBackground-Pixel Size-Pixel area:71000m2Pixel area:11m2Glass substrate75,4K 2K(Display panel)170cm100cmLarge TVa-Si TFTOxide TFTLTPS TFTTransistor typeVDD500m142mVDD6m1.9mSingle crystallin
307、e siliconTransistor type1.2cmSi substrate1,4K 2K(Display panel)2.3cmMicro displayPixelPixel9 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternatio
308、nal Solid-State Circuits ConferenceApplicationAR glassVR headsetThis workManufacturerRokidXrealAppleMetaPico-Product nameJoy 2One ProVision ProQuest 3Pico 4 ultra-Release year202420252024202320242025TechnologyOLEDoSOLEDoSOLEDoSLCOSLCOSOLEDoSResolution(per eye)1920108019201080366032002064220821602160
309、40004000Diagonal size(inch)-0.551.412.482.560.9Pixel per inch(PPI)-3386121812006285Frame rate(Hz)12012010012090120Image-Background-AR/VR Device Application-GlassColor filterColor filterColor filterSilicon substrateLiquid Crystal-on-SiliconGlassOLEDOLEDOLEDSilicon substrateThin-film encapsulationOLED
310、-on-SiliconGlassLEDLEDLEDSilicon substrateLED-on-SiliconLiquid crystalLCoSOLEDoSLEDoS10 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays RGB4.0m1.33mRGB1pixelOLE
311、DoS source driverOLEDoS gate driverOLEDoS emission driverOLEDoS display panel 2025 IEEEInternational Solid-State Circuits Conference*1 pixel=3 sub pixels(R,G,B)Design specifications for OLEDoS display panelDiagonal size(A)0.9”PPI=(C 2)/A6285PPIResolution(C)4K 4K Pixel pitch=1inch/PPI4.0mSilicon subs
312、trateSource driverSource driverA4KOLED deviceRGBBackground-Architecture of OLEDoS Display-11 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays OLEDoS gate driverR
313、GBRGBRGBRGBRGBRGBOLEDoS source driver4.0m1.33m 2025 IEEEInternational Solid-State Circuits ConferenceRequirement:Small-area source driver IC(SD-IC)Narrow channel width Background-OLEDoS Challenge 1:Narrow Channel Width-1.33m4.0mRGBSD-IC(1CH)SD-IC(1CH)SD-IC(1CH)SD-IC(1CH)SD-IC(1CH)SD-IC(1CH)RGBOLEDoS
314、 display panel12 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays FHD,120Hz(OLED)1/8 tttFHD,60Hz(OLED)1-H time1-H time1/2 4K 4K,120Hz(OLEDoS)2.08sD 2025 IEEEInte
315、rnational Solid-State Circuits ConferenceRequirement:Fast SD-IC1-H=Number of row line frame rate 1Background-OLEDoS Challenge 2:Short 1-H Time-OLEDoS gate driverOLEDoS source driverRow#1Row#2Row#4000RGBRGBRGBRGBRGBRGBShort1-H timeOLEDoS display panel Short 1-H time13 of 516.7:A 10b Source-Driver IC
316、with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-State Circuits ConferenceRequirement:Small deviation of voltage output(DVO)SD-IC Background-OLEDoS Challenge 3:Volt
317、age Deviation-Voltage variation of SD-IC pixel current variation|IDRV|Large I 3nAPixel current range2.1V3.1VSmall I VTARGET10pAVDATA V TFT(for OLED)Si(for OLEDoS)GBRGRGBRGOLEDoS gate driverVDATA+VVDATAOLEDoS source driverIDRVVTARGETVDATAIDRV+IVTARGET+VVDATAROLEDoS display panel14 of 516.7:A 10b Sour
318、ce-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Outline 2025 IEEEInternational Solid-State Circuits Conference Background Proposed OLEDoS SD-IC Architecture of SD-IC Small-Area SD
319、-IC Fast SD-IC Small-DVO SD-IC Measured Result Performance Comparison Summary15 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays 2025 IEEEInternational Solid-Sta
320、te Circuits ConferenceProposed OLEDoS SD-IC-Architecture of SD-IC-VO8b LVDACSampling latchShift registerVR5b R-stringENCDSYNCLOADVRDN+1DND3DCSDNDEMUX8b R-stringHolding latch2b EMB-DACAMPDNDNCalibration unitCMUXVGVBVHVLDUTYPOLCAL_EXVREFL_DAC5VREFH_DACVREFL_CALVREFH_CALDN+13 to 23 Dec.3 to 23 Dec.2 to
321、 22 Dec.DNVREFIADDCPVRVCAL,HVIP,HVIP,LVINSmall AreaFast SettlingSmall DVO16 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Outline 2025 IEEEInternational Solid
322、-State Circuits Conference Background Proposed OLEDoS SD-IC Architecture of SD-IC Small-Area SD-IC Fast SD-IC Small-DVO SD-IC Measured Result Performance Comparison Summary17 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273
323、m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Small-Area SD-IC-1:3 DEMUX Structure-2025 IEEEInternational Solid-State Circuits ConferenceType1DEMUXNo DEMUXDriving time2.08sChannel width1.33mChannel area1Layout possibility Impractical layout Large areaType13H1.33mSD-IC(1CH)SD-IC(1CH)
324、SD-IC(1CH)RGB4m1.33m18 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Small-Area SD-IC-1:3 DEMUX Structure-2025 IEEEInternational Solid-State Circuits Conferen
325、ceType1Type2Type3DEMUXNo DEMUX1:31:3Driving time2.08s0.69s0.69sChannel width1.33m4.0m8.0mChannel area11/31/3Layout possibility Impratical layout The area reduction by 1/3 Require fast driving speedType13H1.33mSD-IC(1CH)SD-IC(1CH)SD-IC(1CH)RGB4m1.33mType21:3 DEMUX4mHSD-IC(1CH)RGB4m1.33mType31:3 DEMUX
326、 1:3 DEMUXSD-IC(1CH)8mSD-IC(1CH)H/2RGBRGB4m1.33m19 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Small-Area SD-IC-1:3 DEMUX Structure-2025 IEEEInternational S
327、olid-State Circuits Conference Practical layout Type1Type2Type3Type4DEMUXNo DEMUX1:31:31:3Driving time2.08s0.69s0.69s0.69sChannel width1.33m4.0m8.0m16.0mChannel area11/31/31/3Layout possibility The area reduction by 1/3 Require fast driving speedThis workType13H1.33mSD-IC(1CH)SD-IC(1CH)SD-IC(1CH)RGB
328、4m1.33mType21:3 DEMUX4mHSD-IC(1CH)RGB4m1.33mType31:3 DEMUX 1:3 DEMUXSD-IC(1CH)8mSD-IC(1CH)H/2RGBRGB4m1.33mType41:3 DEMUX1:3 DEMUX1:3 DEMUX1:3 DEMUXSD-IC(1CH)16 mSD-IC(1CH)H/4SD-IC(1CH)SD-IC(1CH)R G B R G B R G B R G B4mH/420 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibrati
329、on and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays LVMOSFETHVMOSFETLevel shifter8b HVDAC8b channel logicAMPVO8VREFLVREFHR-stringConventional 8b SD-ICVDAC1:3 DEMUXSingle stage DACVPIX1VPIX2VPIX3Logic DEC10b channel logic2b EMB-DAC AMPVO8VR
330、EFLVREFHR-stringProposed 10b SD-ICVDAC28b LVDAC1:3 DEMUXTwo stage DACVPIX1VPIX2VPIX3SYNCDLOADSYNCDLOAD1.2V LV MOSFETWMIN=0.12mLMIN=0.06mWL3.3V HV MOSFETWLWMIN=0.4mLMIN=0.5m 2025 IEEEInternational Solid-State Circuits ConferenceLarge size HV MOSFETSmall size LV MOSFETSmall-Area SD-IC-Low Voltage DAC-
331、Large area HVDACSmall area LVDACLV MOSFET small area No level shifter small area2b EMB-DAC AMP&logic decoder#of DAC switches small area8 TRs on a path 3 TRs on a path 21 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273m2/Ch
332、annel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays Silicon substrateP-wellN+N+P+P+P+N+P+P+N+N+P+N-wellN-wellN-wellLV MOSFET(DNW)HV MOSFETN-wellN+2.1V3.3V0V3.3VDeep N-wellLV MOSFET(DNW)and HV MOSFET structureOutput voltage range:2.1 to 3.1V Isolated LV MOSFET with deep N-well(DNW)can be used.2
333、025 IEEEInternational Solid-State Circuits ConferenceProposed SD-IC3.1VLVDAC3.1V2.1V(DNW)3.3V LV MOSFET small area 0VLV logicAMP3.1VPixelELVDDELVSSVPIXVoVLVDACDEMUXConventional SD-IC3.3V0V3.1V3.1V2.1V AMPHV level shifter3.1VPixel HV MOSFET large area ELVDDELVSSVPIXVoVHVDACHVDAC DEMUXSmall-Area SD-IC-LV MOSFET with DNW-22 of 516.7:A 10b Source-Driver IC with All-Channel Automatic Offset Calibration
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