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1、ISSCC 2025SESSION 21Compute and USB Power21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference1 of 56A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-St

2、age Converter with Regulated Resonant Switched-Capacitor Regulators Shengdao Ren,Yukan Du,Menglian Zhao,Zhichao Tan,Chushan Li,Yong Ding,Wuhua Li,Wanyuan Qu Zhejiang University,Hangzhou,China21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Swit

3、ched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference2 of 56Outline Motivation Proposed Two-stage Power Delivery StructureRegulated ReSC(RReSC)Stage Two-Stage Cooperative Control SchemeCircuit Implementation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency a

4、nd 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference3 of 56Outline Motivation Proposed Two-stage Power Delivery StructureRegulated ReSC(RReSC)Stage Two-Stage Cooperative Control SchemeCircuit Imp

5、lementation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference4 of 56Motivation Requirements for power supply:High efficiencyHigh

6、 power densityFast transient responseNVIDIA H100Power consumption:700 WMedical ResearchIndustrial AutomationMaterial Science High performance computing(HPC)is essential to science and industry,the growth in demand for HPC has led to a rapid increase in XPU power consumptionGenerative AI21.1:A 12A 89

7、.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference5 of 56Two-stage Structure(IBC+POL)for XPUs*IBC=Intermediate Bus Converter Advantages of the low voltage POLs:Low FOM devic

8、es High efficiencyHigh fsw High bandwidthSmall passives High density POLXPUIBC12V0.9VPOLPackageIntermediate Bus21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conferenc

9、e6 of 56XPUIBC12VPackageIntermediate Bus0.9VPOLPOLThe Key Part of the Two-stage structurePOL determines the core density&efficiency&transient performance21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE In

10、ternational Solid-State Circuits Conference7 of 56Three Types of POLsVREFCO-+EACINVOVINLCOVOVINCINCOVOVINCINCFLDOSwitched-inductor IVRSwitched-capacitor VR21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE

11、International Solid-State Circuits Conference8 of 56Low Dropout Regulator(LDO)-Advantages AMD,ISSCC17 High bandwidth Ultra high power density Easy integration w/.processorLDO1Core1LDONCoreN.XPU0.9V BusPackageIBC VREFCOILOAD-+EACINVO VINIIN21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V

12、Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference9 of 56LDO DisadvantagesVDS =VIN-VO+-VREFCOILOAD-+EACINVO VINIINMuch power is wasted in the power switchVINVoltsVO1.8V0.9VEnergy lossEnergy received by load Low energy uti

13、lization ratio of input capacitor 21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference10 of 56LDO DisadvantagesCINprovides the instantaneous powerLow power Large

14、CINis requiredVREFCOILOAD-+EACINVO VINIIN21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference11 of 56Switched-Inductor IVR-AdvantagesIntel,APEC14LCOVOVINCIN Good

15、efficiency Decent VOregulation21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference12 of 56LCOVOVINCINSwitched-Inductor IVR-Advantages Reduced requirement for CINE

16、nergy loss Small VDSon switchesVDS+-CINenergy is saved by LVIN(Buck)VoltsVO1.8V0.9V1.8VVIN(LDO)Energy received by load21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Co

17、nference13 of 56Switched-Inductor IVR-Disadvantages Complex inductor technology Complicated package and PDN design Complex high bandwidth controller designFIVRXPU1.8V BusPackageIBC William J.,TPEL20Thin-film Mag.Ind.William J.,ECTC14Package ind.Krishna,ECTC21Coax MIL21.1:A 12A 89.3%Peak Efficiency a

18、nd 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference14 of 56Switched Capacitor VR(SCVR)Intel,VLSI24VINCOVOCF1CF2CIN High efficiency at fixed VCR High power density Low energy utilization ratio VO

19、regulation v.s.efficiency trade-off21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference15 of 56SCVR-Advantages 100%efficiency near ideal VCR High density is possi

20、ble Simple PDN designPower switches and ctrl.High density capWith high density caps.(Super MIM/DTC)Intel,VLSI24Effi.VCRidealVCR100%1uF/mm221.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Sol

21、id-State Circuits Conference16 of 56SCVR Disadvantages*Output energy per cycle(EOUT):()Effi.=VINVOCFILOADFor 99%effi.VIN=1.8V,=Energy utilization ratio=.trade-off High effi.at high EOUTLarge capacitance is needed21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Re

22、gulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference17 of 56SCVR VCR v.s.Output PowerVINVOCF1CF2Intel,JSSCC15 Reconfig.improves efficiency for different VCRsVINVOCF1CF2VINVOCF1CF2VIN:VO=2:1VINVOCF1CF2VINVOCF1CF2VIN:VO=3:221.1:A 12A 89.3%Peak Efficien

23、cy and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference18 of 56SCVR VCR v.s.Output Power:.However,load capacity decreases severelyROUT*VINVOIO1.7 X21.1:A 12A 89.3%Peak Efficiency and 26mV Unders

24、hoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference19 of 56Comparison of the POL SchemesEnergy Utilization Ratio&Load CapacityEfficiency TransientDensityVOregulationLDOTrade-offsBuck*SCVR*?How to obtain all t

25、he advantages?*Require very high fSW*Decrease efficiency*Require large flying cap21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference20 of 56Proposed Resonant Swi

26、tched Capacitor-EfficiencyEnergy Utilization Ratio&Load CapacityDensityTransientPerformanceVORegulationReSCResonant operationZCS operation&no charge sharing loss Nearly 100%efficiencyVINVOCrLrILOAD21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonan

27、t Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference21 of 56Proposed ReSC-Energy Utilization Ratio(1.8V/0.9V)Pure SCReSCVCFof flying cap.99%effi.18 mV54 mVEnergy Utilization Ratio(EUR)8%24%VINVOCrLrILOAD3x 3 X improvement of energy utilization ratio and load capaci

28、ty EfficiencyEnergy Utilization Ratio&Load CapacityDensityTransientPerformanceVORegulationReSC21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference22 of 56Proposed

29、 ReSC Power DensityResonant operation benefits a sub-nH Lrat low fsw High power density&low design complexityEfficiencyEnergy Utilization Ratio&Load CapacityDensityTransientPerformanceVORegulationReSCVINVOCrLrILOAD21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with

30、Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference23 of 56Proposed ReSC Transient Performance Regulation states significantly improves transient responseVINVOCrLrILOADVINVOCrLrILOADInsert regulation statesFast VOregulationEfficiencyEnergy Utiliza

31、tion Ratio&Load CapacityDensityTransientPerformanceVORegulationReSC21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference24 of 56Proposed ReSC VOregulation Global c

32、ontrol loop enables high-efficiency VOregulationEfficiencyEnergy Utilization Ratio&Load CapacityDensityTransientPerformanceVORegulationReSCIBCHV BusIntermediate BusRReSC PoLVOControl 2Control 121.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Sw

33、itched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference25 of 56Proposed Circuit Diagram1stIBC Stage(12/24V to 1.8V)High efficiency and high conversion ratioPhase 3RReSC PoLS1S2S3S4Phase 1Phase 2Lr1Cr1Lr2Cr2Lr3Cr3VMID VO VREFCLK DividerCLKTypeIIIS1-4CLKS1S3PLLPhaseShiftCon

34、trollerVPLX1LX2L1L2DSD Based IBCQ1Q2Q3Q440V ext.GaN FETSW1SW2DSDControllerTypeIIIQ1-4VREF_MID CLK221.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference26 of 56Prop

35、osed Circuit Diagram2ndPOL Stage(1.8V to 0.9V)High power density and high efficiency Fast transient responseVREF_MID S1S3PLLPhase 3RReSC PoLS1S2S3S4Phase 1Phase 2Lr1Cr1Lr2Cr2Lr3Cr3VMID VO VREFCLK DividerCLKTypeIIIS1-4CLKVPLX1LX2PhaseShiftControllerL1L2DSD Based IBCQ1Q2Q3Q440V ext.GaN FETSW1SW2DSDCon

36、trollerTypeIIIQ1-4CLK21stIBC Stage(12/24V to 1.8V)High efficiency and high conversion ratio21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference27 of 56Proposed Ci

37、rcuit Diagram2ndPOL Stage(1.8V to 0.9V)High power density and high efficiency Fast transient response1stIBC Stage(12/24V to 1.8V)High efficiency and high conversion ratioPLL Based Global Controller Regulate VMIDfor performance improvementPhase 3RReSC PoLS1S2S3S4Phase 1Phase 2Lr1Cr1Lr2Cr2Lr3Cr3VMID V

38、O VREFCLK DividerCLKTypeIIIS1-4CLKVPLX1LX2PhaseShiftControllerL1L2DSD Based IBCQ1Q2Q3Q440V ext.GaN FETSW1SW2DSDControllerTypeIIIQ1-4CLK2VREF_MID S1S3PLL21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE Int

39、ernational Solid-State Circuits Conference28 of 56Outline Motivation Proposed Two-Stage Power Delivery StructureRegulated ReSC(RReSC)StageTwo-Stage Cooperative Control SchemeCircuit Implementation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage C

40、onverter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference29 of 56IOUTILrS1S2S3S4t Non-regulation Mode of the ReSCVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTTSW/2TSWNon-regulation modeVO VIN/221.1:A 12A 89.3%Peak Efficiency and

41、 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference30 of 56Regulation Modes of the ReSCS1S2S3S4phase leadS1S2S3S4phase lagShifting phase of S3 for VOregulationBoost Mode:VO VIN/2Buck Mode:VOVIN/2)

42、12 The input source powers the resonator and the loadVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUT21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators

43、2025 IEEE International Solid-State Circuits Conference32 of 56t ILrS1S2S3S4IOUTOperation States of the Boost Mode(VOVIN/2)1234Resonator powers the loadVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUT21.1:A 12A 89.3%Peak Efficiency and

44、26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference33 of 56Equivalent Circuits in the Boost ModeThe same with a conventional Boost converterVIN/2LrVCr VIN/2Replace Crwith a voltage sourceVIN/2LrVOV

45、INVOCrLrCOILOADS1S2S3S4VINVOCrLrCOILOADS1S2S3S4VINVOCrLrCOILOADS1S2S3S4VINVOCrLrCOILOADS1S2S3S421.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference34 of 56VINVOCr

46、LrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTIOUTILrS1S2S3S4t Operation States of the Buck Mode(VOVIN/2)141VINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTConverter draws energy from the CO21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Res

47、onant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference35 of 56IOUTILrS1S2S3S4t Operation States of the Buck Mode(VOVIN/2)14Less input energy is delivered the loadConverter powers the load2VINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S

48、2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUT21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference36 of 56IOUTILrS1S2S3S4t Operation States of the Buck Mode(VOVIN/2)1432Le

49、ss energy for powering the load Converter powers the loadVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVINVOCrLrCOILOADS1S2S3S4IOUTVOdecreases21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capaci

50、tor Regulators 2025 IEEE International Solid-State Circuits Conference37 of 56IOUTILrS1S2S3S4t Problem of the Regulation ModeBoost modeBuck modeTime for powering the load Fast transientresponse Reduced effi.(Compared with non-regulation mode)How to address this trade-off?21.1:A 12A 89.3%Peak Efficie

51、ncy and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference38 of 56Outline Motivation Proposed Two-Stage Power Delivery StructureRegulated ReSC(RReSC)Stage Two-Stage Cooperative Control SchemeCircu

52、it Implementation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference39 of 56IBCHV BusRReSC PoLVOGoal of the Cooperative Control S

53、chemet ILrS1S2S3S4phase leadBoost ModeILrS1S2S3S4phase lagt Buck ModeVO,VMIDVO VMID/2 =3 0For high efficiency =0Regulate VMID to decrease|until|=0VMID21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE Inter

54、national Solid-State Circuits Conference40 of 56IBCHV BusRReSC PoLVOUTOperation Principle of the Control SchemeVrampt ILrS1S2S3S4phase lead1234VC,VPIn Boost Mode,S1 leads S3 in phase(0)ANDS1DQCLKRSTDQCLKRSTS3VREF_MIDCPLLControllerof IBCDriverSignalsVMID/2VOUTBoost ModeRReSCPoL21.1:A 12A 89.3%Peak Ef

55、ficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference41 of 56IBCHV BusRReSC PoLVOUTOperation Principle of the Control SchemeVrampt ILrS1S2S3S4phase lead1234VC,VPControllerof IBCDriverSig

56、nalsANDS1DQCLKRSTDQCLKRSTS3VREF_MIDCPLLVMIDBoost Mode 0Increase VMIDRReSCPoL21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference42 of 56IBCHV BusRReSC PoLVOUTt IL

57、rVrampS1S2S3S424phase equalTSW/2TSW/2Operation Principle of the Control SchemeWith the increasing of VMID,decreases to 0 for non-regulation mode operationHigh effi.can be achievedControllerof IBCDriverSignalsANDS1DQCLKRSTDQCLKRSTS3VREF_MIDCPLLVMID/2VOUTRReSCPoL21.1:A 12A 89.3%Peak Efficiency and 26m

58、V Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference43 of 56Outline Motivation Proposed Two-Stage Power Delivery StructureRegulated ReSC(RReSC)Stage Two-Stage Cooperative Control SchemeCircuit Implemen

59、tation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference44 of 56Phase 3RReSC PoLS1S2S3S4Phase 1Phase 2Lr1Cr1Lr2Cr2Lr3Cr3L1L2VMID

60、 VO VREFCLK DividerTypeIIIDSDControllerCLKDSD Based IBCTypeIIIQ1-4Q1Q2Q3Q440V ext.GaN FETCLK2VREF_MID SW1SW2LX1LX2S1-4PLLPhaseShiftControllerS1S3VPVCCLKPhase Shift ControllerVRAMPCLK+-DQCLKQCMP1DQCLKQLogic&TdeadS1S2S3S4VC+-CMP2VPDFF1DFF2PSC converters two voltages into two square waves(S1and S3)with

61、 different phasesPhase Shift Controller(PSC)21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference45 of 56VRAMPCLK+-DQCLKQCMP1DQCLKQLogic&TdeadS1S2S3S4VC+-CMP2VPDFF

62、1DFF2VrampDFF1DFF2CMP1CMP20.5 x TSWVC,VPTSW0.5 x TSWPhase Shift ControllerBy comparing VCand VPwith a ramp,comparators output two signals with different phases21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 I

63、EEE International Solid-State Circuits Conference46 of 56Phase Shift ControllerDFFs reshape the outputs of comparators into square waves with different phasesVrampDFF1DFF2CMP1CMP20.5 x TSWVC,VPTSW0.5 x TSWVRAMPCLK+-DQCLKQCMP1DQCLKQLogic&TdeadS1S2S3S4VC+-CMP2VPDFF1DFF221.1:A 12A 89.3%Peak Efficiency

64、and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference47 of 56Outline Motivation Proposed Two-Stage Power Delivery StructureRegulated ReSC(RReSC)Stage Two-Stage Cooperative Control SchemeCircuit I

65、mplementation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference48 of 56Chip Micrograph and PCB PhotoPHASE12050 um3100 umPHASE2PH

66、ASE3LSH&DRV&FETLSH&DRV&FETLSH&DRV&FETCTLINPUT DECAPINPUT DECAPINPUT DECAPPOL1POL2IBCLOAD BANKCr1Cr2Cr31stIBC Stage:Switches:Off-chip GaNs Inductors:1 uH X 2 Flying cap:4.7 uF CMID:80 uF2ndRReSC Stage:Process:65nm CMOS Inductors:0.85 nH X 3(PCB trace inductor)Flying Cap:1 uF X 3 Output Cap:24 uF6.3 m

67、m221.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference49 of 56Steady-state WaveformsTwo chips are usedIBCRReSC(POL1)RReSC(POL2)VMIDVO16A Max6A MaxVO2IL1/IL2VMID=1

68、.79VVO=900mV1usSW1/SW25V1A1.1MHz100ns1V9MHzLX1/LX2VMID=2.03VVO=909mVIL1/IL2Avg.IL 2.92A SW1/SW21us5V1A100ns1VLX1/LX21stIBC2ndPOLTotal Load=0ATotal Load=12A21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE

69、International Solid-State Circuits Conference50 of 56Load Transient Test 26 mV undershoot 4A/20ns load step VMIDis optimized by the global controller according to the load condition Load Transient with RReSC PoL1 close-loopIO14A0A20nsVO1VMIDIL150mV50us5us5usBoostNon-regulation in steady-stateBuck20n

70、sBoostBuck100mV4A4AOptimum elevated value26mV20mVAvg.IL1 0.75A Avg.IL1 1.73A 21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference51 of 56Load Transient Test and D

71、VS TestLoad Transient with RReSC PoL1 open-loopIO1VO1VMIDIL150mV50mV4A4A75 mV4A0A50usRReSC PoL1 dynamic voltage scaleVREFVO1VMIDIL1100mV200mV100mV4A850mV750mV850mV750mV50usAvg.IL1 1.67A ts 1.62usts 0.75us A large voltage drop will appear with POL1 in open-loop mode DVS test with VO1changing between

72、0.75V and 0.85V under a 3A load21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference52 of 56Efficiency Under Different Conditions75%85%95%IO(A)024681012EFF.(%)0123

73、45612-1.2V12-1.5V12-1.8V12-2.0V24-1.8V75%85%95%IO(A)EFF.(%)01234561.2-0.6 V1.5-0.75V1.8-0.9 V2.0-1.0 V70%80%90%IO(A)EFF.(%)12-0.6 V12-0.75V12-0.9 V12-1.0 V24-0.9 VPeak 94.2%Peak 96.0%Peak 89.3%1stIBC Stage 2ndReSC Stage Overall System94.2%peak efficiencyat 12V/2V96%peak efficiencyat 2V/1V89.3%peak e

74、fficiencyat 12V/1V21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference53 of 56Summary and ComparisonAPEC 2014 1ISSCC 20202VLSI 20243ISSCC 20234This workArchitectu

75、reTwo-Stage Architecture1stStageTopologyBuck-3-level BuckDSDVIN/VORange3.1-20V/0.6-5VNR/1.5-2.5V-12-20V/3.2-4.2V12-24V/1.2-2VPeak Eff.86.5%NR-94.2%95.2%*/94.2%*2ndStageTopologyMultiphase BuckSCVR(4:1/4:3)SCVR(3:1/4:1)SCVR(4:1)RReSCProcess22nm CMOS65nm CMOS16nm CMOS65nm CMOS65nm CMOSVIN/VORange1.8V/0

76、.6-1.1V1.5-2.5V/0.5-1.1V3 or 4V/1V3.2-4V/0.75V-1V1.2-2V/0.6-1VL/CNRAircore InductorNRMOS+MOM+MIMOn-die MIMNRIPD cap.,test w/MLCC0.85nH/1uFtest w/MLCC&trace ind.Peak Eff.90%1.7V/1.05V82%1.8V/0.9V90.6%3V/1V92.4%4V/0.95V96%2V/1VSystemLoad Current16 A5 A7 A6 A12 AUnder/over-shoot voltage50mV/NRNR/NR40mV

77、/0mV26mV/20mV(Close loop)75mV/0mV(Open loop)Vo:8.5A step/1nsVo:1.2-1.8AVO1:50-650 mAVO2,VO3:650mAVO1:0-4 A/20nsVO2:3APeak Eff.77.85%77.9%*-87.4%92.2%*/89.3%*Without/*With 1st stage driver loss;*Assumed 95%1st stage efficiency 4;Estimated from reported data 4;NR Not reported21.1:A 12A 89.3%Peak Effic

78、iency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference54 of 56Outline Motivation Proposed Two-Stage Power Delivery StructureRegulated ReSC(RReSC)Stage Two-Stage Cooperative Control SchemeCir

79、cuit Implementation Measurement Results Conclusions21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference55 of 56ConclusionsTwo-stage power delivery structure Suita

80、ble for XPU power supply The 2ndstage POL converter is the keyRegulated ReSC POL converter Resonant operation high and high utilization of caps Small inductance high power density and fast transient responseTwo-stage cooperative control scheme Regulated VMIDto improve overall efficiency and load cap

81、acity21.1:A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators 2025 IEEE International Solid-State Circuits Conference56 of 56Thank you!21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing a

82、nd Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference1 of 47A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile ApplicationsWoojin Hong,Hyebong Ko,Jinwoo So,Woonhyung Heo,Yonghwan Cho,Jeongdu

83、 Yoo,Ho-Sung Son,Youngwoo Chung,Dong-Joon Kim,Youngwoo Park,Byeonghyeon Jin,Sungkyu Cho,Minkyu Kwon,Kyungmin Park,Daewoong Cho,Jung Wook Heo,Sungwoo Lee,Sungwoo Moon,Hyoung-Seok Oh,Hwayeal YuSamsung Electronics,Hwaseong,Korea21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VC

84、FBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference2 of 47Outline Motivation and ChallengesHigh-Power Battery Charging and Power SharingFlying Capacitor Voltage(VCF)Balancing Dual-Input Bidirectional 3-Level Battery ChargerOperational Prin

85、cipleCoarse-Fine VCFBalancerFrequency Foldback Controller Measurement Results Conclusion21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference3 of 47Motivation#1The re

86、cent trends for foldable mobile phones requireSmaller-form factors with smaller passive devicesHigh-power battery charging with a wide input range*source:Samsung Galaxy21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications

87、2025 IEEE International Solid-State Circuits Conference4 of 47Motivation#1USB-PD uses wide voltage ranges to increase power densityHigh VIN(12 V)with smaller IINresulting in smaller loss in USB cableLVOUTVINRCABLE(0.1 1)Large IR Drop+-VUSB-PD 5 VBuckChargerICBattery 3.4 4.6 VVCR=VOUT/VINLarge IBATLa

88、rge IINLVOUTVINRCABLE(0.1 1)VUSB-PD 12 VBuckChargerICBattery 3.4 4.6 VLarge IBATSmall IIN 5 VPLOSS=PSW +PCOND Charger IC requires High Eff.at higher VIN Wide voltage conversion ratio(VCR)21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable M

89、obile Applications 2025 IEEE International Solid-State Circuits Conference5 of 47Motivation#1USB-PD uses wide voltage ranges to increase power densityHigh VIN(12 V)with smaller IINresulting in smaller loss in USB cableConventional VIN(5 V)induces large IR drop resulting in VIN VOUTLVOUTVINRCABLE(0.1

90、 1)Large IR Drop+-VUSB-PD 5 VBuckChargerICBattery 3.4 4.6 VVCR=VOUT/VINLarge IBATLarge IINLVOUTVINRCABLE(0.1 1)VUSB-PD 12 VBuckChargerICBattery 3.4 4.6 VLarge IBATSmall IIN VIN/2LargerIINDi)VCF is balancedii)VCF is unbalancedFlying capacitor voltage(VCF)is ideally balanced at VIN/221.2:A Dual-Input

91、Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference7 of 47Motivation#1Flying capacitor voltage(VCF)is ideally balanced at VIN/2But,parasitic Cap.and phase mismatch lead VCFto be unba

92、lancedMore stress on TRs.and low efficiency due to larger IINDRMS current3-level topology has advantagescompared to 2-levelLower VLXswing level by Low voltage stress on TRs.Less switching losses at high VIN PSW=CV2fSWHigher effective fSWby 2 Smaller passive LC filters Lower IINDrippleLIINDVINCFVOUTQ

93、1Q2Q3Q4VLXCOUTVCF+-VCFIINDVLXVIN/2VIN/2VCFIINDVLXVIN/2 VIN/2LargerIINDi)VCF is balancedii)VCF is unbalanced21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference8 of 4

94、7Prior Works of VCFBalancing(1/2)Duty mismatch generates the difference of charging/discharging timesAccurate VCFbalancing can be achievedSlow speed due to the finite BW with analog feedback loopX.Liu,et.al,JSSC 2018DPWM1VRAMPVRAMP_SVERR_CAL1VERR_CAL2DPWM2VCFVIN/2LongTChargingShortTDischarging VINVC

95、FCFVOUTDPWM1DPWM2DPWM1VRAMPVRAMP_SVREFQ1Q2Q3Q4VLXVERRGDGDGDGDEADPWM2DPWM2DPWM1LIINDCOUTVEACalibrationVERR_CAL1VERR_CAL2VCFVIN/221.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circu

96、its Conference9 of 47Prior Works of VCFBalancing(2/2)State-based VCFbalancing was presented using the comparatorFast VCFbalancing can be achievedWorse noise immunity against VCFripple nearby VCF VIN/2S.Lee,et.al,ISSCC 2023DCHDDISVCFVIN/2VCOMPHigh VCF-stateDMLow VCF-state VINVCFCFVOUTDPWM1DPWM2DPWM1V

97、REFQ1Q2Q3Q4VLXVERRGDGDGDGDEADPWM2DPWM2DPWM1LIINDCOUTControlLogicVCFVIN/2VCSVCOMPCKDQDCHDDISDMDMVPWM21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference10 of 47Motiva

98、tion#2Another trend for mobile applications is wireless power sharingwhich allows one mobile device to charge another deviceTwo devices can be charged at the same time.Dual-input bidirectional 3-level battery charger IC is desired*source:SamsungLIINDBatteryVBATOTGAdapterPowerSharingWireless Chg.ICHG

99、IWCBatteryChargerPSUPPLYPCONSUMEIFORWARDIREVERSEPSUPPLYPCONSUMERWIREDRWIRELESS21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference11 of 47Outline Motivation and Chal

100、lengesHigh-Power Battery Charging and Power SharingFlying Capacitor Voltage(VCF)Balancing Dual-Input Bidirectional 3-Level Battery ChargerOperational PrincipleCoarse-Fine VCFBalancerFrequency Foldback Controller Measurement Results Conclusion21.2:A Dual-Input Bidirectional 3-Level Battery Charger wi

101、th Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference12 of 47Proposed Dual-Input 3-Level Battery Charger Dual-Input(QCHG,QWC)+3-Level Converter(Q1 Q4)QCHG:Wired Charging(adapter)or USB OTG(on-the-go)QWC:Wireless Charging or

102、Power SharingLIINDVBYPCFBatteryVBATOTGVCHGVWCINAdapterPowerSharingWireless Chg.Q1Q2Q3Q4ICHGQCHGQWCIBATIWC21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference13 of 47

103、Working Principle(1/5)Travel adapter(T.A)is connected to charge the battery(VBAT)Regulation mode:Battery CC charging(IBATregulation)Battery state:Charging/Dir.of IIND:Forward IBATICHGITXIINDIBAT Reg.LeveltForward BuckModeReg.LoopHeavy LoadtttIBATICHGVBYPICHG Reg.Level Reverse BoostAdapter OFFBattery

104、 Dischg.Battery Chg.Batt.ChargingAdapter Detach+PowerShareBatt.Charging+PowerShareBatt.Discharging+PowerShareLIINDVBYPCFBatteryVBATVCHGAdapterQ1Q2Q3Q4ICHGQCHGIBATBat.Charging(IBAT Regulation)ICHG21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Fo

105、ldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference14 of 47Working Principle(2/5)Wireless power sharing device is connected with a light-load(ITX)Regulation mode:Battery CC charging(IBATregulation)Battery state:Charging/Dir.of IIND:Forward IBATICHGITXIINDIBAT Reg.Level

106、tForward BuckModeReg.LoopHeavy LoadtttIBATICHGVBYPICHG Reg.Level Reverse BoostAdapter OFFBattery Dischg.Battery Chg.Batt.ChargingAdapter Detach+PowerShareBatt.Charging+PowerShareBatt.Discharging+PowerShareLIINDVBYPCFBatteryVBATVCHGVWCINAdapterPowerSharingQ1Q2Q3Q4ICHGQCHGQWCIBATITXICHGBat.Charging(IB

107、AT Regulation)21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference15 of 47Working Principle(3/5)As ITXincreases,ICHGreaches the maximum current limit levelRegulation

108、 mode:CC charging ICHGcurrent limited(ICHGregulation)Battery state:Charging/Dir.of IIND:Forward IBATICHGITXIINDIBAT Reg.LeveltForward BuckModeReg.LoopHeavy LoadtttIBATICHGVBYPICHG Reg.Level Reverse BoostAdapter OFFBattery Dischg.Battery Chg.Batt.ChargingAdapter Detach+PowerShareBatt.Charging+PowerSh

109、areBatt.Discharging+PowerShareLIINDVBYPCFBatteryVBATVCHGVWCINAdapterPowerSharingQ1Q2Q3Q4ICHGQCHGQWCIBATITXBat.ChargingICHG(ICHG Regulation)21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid

110、-State Circuits Conference16 of 47Working Principle(4/5)As ITXheavily increases,insufficient power supplied from the batteryRegulation mode:ICHGcurrent limited(ICHGregulation)Battery state:Charging Discharging/Dir.of IIND:Forward Reverse IBATICHGITXIINDIBAT Reg.LeveltForward BuckModeReg.LoopHeavy Lo

111、adtttIBATICHGVBYPICHG Reg.Level Reverse BoostAdapter OFFBattery Dischg.Battery Chg.Batt.ChargingAdapter Detach+PowerShareBatt.Charging+PowerShareBatt.Discharging+PowerShareLIINDVBYPCFBatteryVBATVCHGVWCINAdapterPowerSharingQ1Q2Q3Q4ICHGQCHGQWCIBATITXBat.DischargingICHG(ICHG Regulation)21.2:A Dual-Inpu

112、t Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference17 of 47Working Principle(5/5)If T.A is detached,the charger operates as the reverse boost converterRegulation mode:QCHGcurrent l

113、imited Input voltage(VBYP)regulationBattery state:Discharging/Dir.of IIND:Reverse IBATICHGITXIINDIBAT Reg.LeveltForward BuckModeReg.LoopHeavy LoadtttIBATICHGVBYPICHG Reg.Level Reverse BoostAdapter OFFBattery Dischg.Battery Chg.Batt.ChargingAdapter Detach+PowerShareBatt.Charging+PowerShareBatt.Discha

114、rging+PowerShareLIINDVBYPCFBatteryVBATVWCINPowerSharingQ1Q2Q3Q4QWCIBATITXBat.Discharging(VBYP Regulation)21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference18 of 47

115、Full Structure of Proposed 3-Level ChargerPower StageQCHG,QWC:Dual-inputQ1 Q4:3-levelQBAT:battery regulationControllerLoop selectorAverage current-mode control(ACMC)with DCR sensor and IINDpolarity detectorCoarse-Fine VCFbalancer Fast and accurate VCFbalancingFrequency foldback controller Wide volta

116、ge conversion ratio(VCR)VBYP VSYSLIINDVBYPVCFCFBatteryVBATCSYSO.T.GVCHGRDCRRCSCCSDPWM1DPWM2VERR_PVG1VG2VG3VG4VSYSVBATIBATVTRI_0VTRI_180VMINCBYPVWCT.ATXWireless Chg.VREF_CSQ1Q2Q3Q4ICHGIWCQBATCBATQCHGQWC VERR_NIBATLoop SelectorINDPOLGmISYSIOTGITXVLXAuto-Calibrated Frequency FoldbackControllerVCSVERRBi

117、-dir.IQ1 SensorBi-dir.IQ4 SensorGDLSGDLSGDLSGDFine VCF BalancerCoarse VCF BalancerVCFZCSQ1ZCSQ4EABi-dir.QCHG SensorBi-dir.QWC SensorVCF_HVCF_LINDPOLVCFSensorNon-overlapGate ControllerZCSQ1ZCSQ4EAICHGIWCEAEAEAVREF_CS21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing

118、 and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference19 of 47ACMC-Based Duty GenerationACMC can inherently provide bidirectional duty signalsDPWM1and DPWM2 VBAT/VBYPregardless of IINDdirectionOnly VCFcharging/discharging phases are different between b

119、uck/boostDPWM1DPWM2IIND0AVCSVREF_CSVMINa)VBAT/VBYP 0.5DPWM1DPWM2VTRI_0VTRI_180VERRVCFVCFVBYP LIINDVBYPVCFCFBatteryVBATRDCRRCSCCSDPWM1DPWM2DPWM1VSYSVBATIBATVTRI_0VTRI_180VMINVREF_CSQ1Q2Q3Q4CBATIBATLoop SelectorGmVLXVCSVERRGDGDGDGDEAEAICHGIWCEAEAEADPWM2DPWM2DPWM121.2:A Dual-Input Bidirectional 3-Level

120、 Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference20 of 47Outline Motivation and ChallengesHigh-Power Battery Charging and Power SharingFlying Capacitor Voltage(VCF)Balancing Dual-Input Bidirectional 3-

121、Level Battery ChargerOperational PrincipleCoarse-Fine VCFBalancerFrequency Foldback Controller Measurement Results Conclusion21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuit

122、s Conference21 of 47Proposed Coarse-Fine VCFBalancer(1/4)Fine VCFbalancer provides IVCFto make duty mismatch purposelySlow but accurate VCFbalancing if VCF_LOW VCF VCF_HIGHVSSVCF_HVCF_LEAVBYPVERRVERR_PVERR_NR1R1R1GmVCFDPWM0_PREDPWM180_PRE000111VCFHIGHINDPOLVCFLOWSYNCSELVCFCoarse VCF BalancerFine VCF

123、 Balancer 1VBYP/2R1R2/2R3/2R1R2/2R3/2R2+R3=R1VBYP/2+VBYP/2-IVCFVCF SensorVTRI_0VTRI_180VBYPVCF_LVCF_HDQ000111DQDPWM_0DPWM_180DPWM180_PREDPWM0_PREDQPWM SwapDPWM1DPWM2VVCF_HIGHVCFVVCF_LOWVBYP/2FineCoarseCoarseVCF BalancingDPWM2DPWM1DPWM2DPWM1VVCF_HIGHandVVCF_LOWcan be generated by ratio of R2and R3sat

124、isfying R1=R2+R321.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference22 of 47Proposed Coarse-Fine VCFBalancer(2/4)Coarse VCFbalancer activated,if VCF VVCF_HIGHor VCF

125、VVCF_LOWBased on VCFstates,DPWM0and DPWM_180are swapped each otherVCF VVCF_LOW Duty 0.5VSSVCF_HVCF_LEAVBYPVERRVERR_PVERR_NR1R1R1GmVCFDPWM0_PREDPWM180_PRE000111VCFHIGHINDPOLVCFLOWSYNCSELVCFCoarse VCF BalancerFine VCF Balancer 1VBYP/2R1R2/2R3/2R1R2/2R3/2R2+R3=R1VBYP/2+VBYP/2-IVCFVCF SensorVTRI_0VTRI_1

126、80VBYPVCF_LVCF_HDQ000111DQDPWM_0DPWM_180DPWM180_PREDPWM0_PREDQPWM SwapDPWM1DPWM2DPWM180_PREVVCF_HIGHVCFVVCF_LOWDPWM0_PRESYNCSELVCFDPWM_180DPWM_00101000021.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE Intern

127、ational Solid-State Circuits Conference23 of 47Proposed Coarse-Fine VCFBalancer(3/4)VCF VVCF_HIGH Duty 0.5VSSVCF_HVCF_LEAVBYPVERRVERR_PVERR_NR1R1R1GmVCFDPWM0_PREDPWM180_PRE000111VCFHIGHINDPOLVCFLOWSYNCSELVCFCoarse VCF BalancerFine VCF Balancer 1VBYP/2R1R2/2R3/2R1R2/2R3/2R2+R3=R1VBYP/2+VBYP/2-IVCFVCF

128、 SensorVTRI_0VTRI_180VBYPVCF_LVCF_HDQ000111DQDPWM_0DPWM_180DPWM180_PREDPWM0_PREDQPWM SwapDPWM1DPWM20111011101DPWM180_PREVVCF_HIGHVCFVVCF_LOWDPWM0_PRESYNCSELVCFDPWM_180DPWM_0Coarse VCFbalancer activated,if VCF VVCF_HIGHor VCF VVCF_LOWBased on VCFstates,DPWM0and DPWM_180are swapped each other21.2:A Du

129、al-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference24 of 47Proposed Coarse-Fine VCFBalancer(4/4)Depending on direction of IIND,duties(DPWM1and DPWM2)are swappedIf not,ripple

130、 of IINDwould be maximized with a significant imbalanced VCFVSSVCF_HVCF_LEAVBYPVERRVERR_PVERR_NR1R1R1GmVCFDPWM0_PREDPWM180_PRE000111VCFHIGHINDPOLVCFLOWSYNCSELVCFCoarse VCF BalancerFine VCF Balancer 1VBYP/2R1R2/2R3/2R1R2/2R3/2R2+R3=R1VBYP/2+VBYP/2-IVCFVCF SensorVTRI_0VTRI_180VBYPVCF_LVCF_HDQ000111DQD

131、PWM_0DPWM_180DPWM180_PREDPWM0_PREDQPWM SwapDPWM1DPWM2MeasurementsNegative IIND5 V4 s2 AIINDVLXVCF5 V5 V4 s2 A5 VIINDVLXVCF0 A 2.5 V(-)0.5 V0 ABalanced VCF to VBYP/2Unbalanced VCFLarge IIND rippleWithDPWM1 DPWM2swapWithoutDPWM1 DPWM2swap21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coa

132、rse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference25 of 47Outline Motivation and ChallengesHigh-Power Battery Charging and Power SharingFlying Capacitor Voltage(VCF)Balancing Dual-Input Bidirectional 3-Level Battery ChargerOper

133、ational PrincipleCoarse-Fine VCFBalancerFrequency Foldback Controller Measurement Results Conclusion21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference26 of 47Propo

134、sed Frequency Foldback Controller(1/4)VERR-controlled OSC varies the period of triangular waveforms(VTRI)Depending on VERRstates,the shape of VTRIare differentA replica branch(at C1)restricts the minimum fSWby for stability VTRI_0VTRI_180DeMUXVTRI Gen.w/Auto Cal.VFOLD_LVFOLD_HCLK0CLK180VHYS_CLKSELCL

135、KVTRI Gen.w/Auto Cal.OSCICONTCLKOSC/4VERRDQDelayPhase SplitterVERR-Controlled OSCOn-/Off-TimeFoldback Sel.GmGmICONTVERRVDDICLKC1One shotCLKVREFVRAMPVCLAMPVSS4ICLKICONTICLKICONTC2CDD1=CDD241134113QDM1QDM2C1=C2VBPVERR-controlled OSC21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fi

136、ne VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference27 of 47Proposed Frequency Foldback Controller(2/4)When VERRis lower than VFOLD_L,on-time foldback is enteredVTRI_0and VTRI_180have the valley point with flattened periods at the tops

137、ynchronized by CLK0and CLK180,respectivelyVTRI_0VTRI_180DeMUXVTRI Gen.w/Auto Cal.VFOLD_LVFOLD_HCLK0CLK180VHYS_CLKSELCLKVTRI Gen.w/Auto Cal.OSCICONTCLKOSC/4VERRDQDelayPhase SplitterVERR-Controlled OSCOn-/Off-TimeFoldback Sel.GmGmICONTVERROn-time Foldback VERR VFOLD_HVTRI_0VTRI_180DeMUXVTRI Gen.w/Auto

138、 Cal.VFOLD_LVFOLD_HCLK0CLK180VHYS_CLKSELCLKVTRI Gen.w/Auto Cal.OSCICONTCLKOSC/4VERRDQDelayPhase SplitterVERR-Controlled OSCOn-/Off-TimeFoldback Sel.GmGmICONTVERRVTRI_0CLK0CLKVERRVTRI_180CLK180SELCLKOn-time FoldbackOff-time FoldbackVFOLD_HVFOLD_LDPWM1DPWM221.2:A Dual-Input Bidirectional 3-Level Batte

139、ry Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference29 of 47Proposed Frequency Foldback Controller(4/4)Foldback turned OFF,when VFOLD_L VERR VFOLD_H.Depending on selected foldback mode,SELCLKsends either CLK0or

140、CLK180to each VTRIgeneratorFoldback OFFVFOLD_L VERR VFOLD_HVTRI_0VTRI_180DeMUXVTRI Gen.w/Auto Cal.VFOLD_LVFOLD_HCLK0CLK180VHYS_CLKSELCLKVTRI Gen.w/Auto Cal.OSCICONTCLKOSC/4VERRDQDelayPhase SplitterVERR-Controlled OSCOn-/Off-TimeFoldback Sel.GmGmICONTVERRVTRI_0CLK0CLKVERRVTRI_180CLK180SELCLKOn-time F

141、oldbackOff-time FoldbackVFOLD_HVFOLD_LDPWM1DPWM221.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference30 of 47Comparison Range of duty ratio is typically limited due t

142、o minimum on-/off-timesto guarantee TRs.turn-on/-off times,settling of current sensor,etc.With proposed control,the effective duty ratio can be extended for wide VCRConventionalProposed frequency foldbackVTRI_0DPWM1DPWM2VTRI_180VERRMin.On-timeMin.Duty or VCR LimitationVTRI_0DPWM1DPWM2VTRI_180VERRMin

143、.Off-timeMax.duty or VCR LimitationVTRI_0VTRI_180VERRDPWM1DPWM2VTRI_0VTRI_180DPWM1DPWM2VERRi)On-time foldbackii)Off-time foldback21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Cir

144、cuits Conference31 of 47Auto-Calibrated VTRIGenerator(1/4)VTRIgenerator with two current-controlled OTAs(CCOTA)and auto-cal.logicTwo CCOTAs act like both voltage clamper and comparatorOperating waveforms(SELCLK=H)Logic w/auto-calibrationUDVTRI_HVTRICOMPLVTRI_LCLK0IOTA_HITRIVDDVSSVTRIUDVSSVDDVTRI_LVT

145、RI_HCOMPLITRIVBPVBNCOMPHITRICAL4:0MP1MP2MN1MN2CTRIVTRI_HVTRI_LRSQCLK0COMPLRSQBCLK180SELCLKMUXUPCAL4:05-BitUp CounterRDQ32-CycleCounterFINISHCALUDCOMPHCOMPHFINISHCAL21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025

146、 IEEE International Solid-State Circuits Conference32 of 47Auto-Calibrated VTRIGenerator(2/4)When VTRIreaches VTRI_L,upper CCOTA triggers COMPLMismatched-input TRs toggle COMPL,acting like comparatorLogic w/auto-calibrationUDVTRI_HVTRICOMPLVTRI_LCLK0IOTA_HITRIOperating waveforms(SELCLK=H)VDDVSSVTRIU

147、DVSSVDDVTRI_LVTRI_HCOMPLITRIVBPVBNCOMPH2ITRIITRIITRIIOTA_LITRICAL4:0MP1MP2MN1MN2CTRIVTRI_LITRIITRIVTRI_HVTRI_LRSQCLK0COMPLRSQBCLK180SELCLKMUXUPCAL4:05-BitUp CounterRDQ32-CycleCounterFINISHCALUDCOMPHCOMPHFINISHCAL21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing an

148、d Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference33 of 47Auto-Calibrated VTRIGenerator(3/4)Then,UD is low triggered then raises VTRIto VTRI_HLogic w/auto-calibrationUDVTRI_HVTRICOMPLVTRI_LCLK0IOTA_HITRIOperating waveforms(SELCLK=H)VDDVSSVTRIUDVSSVDDV

149、TRI_LVTRI_HCOMPLITRIVBPVBNCOMPHITRICAL4:0MP1MP2MN1MN2CTRIVTRI_HVTRI_LRSQCLK0COMPLRSQBCLK180SELCLKMUXUPCAL4:05-BitUp CounterRDQ32-CycleCounterFINISHCALUDCOMPHCOMPHFINISHCAL21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applicatio

150、ns 2025 IEEE International Solid-State Circuits Conference34 of 47Auto-Calibrated VTRIGenerator(4/4)When VTRIreaches VTRI_H,lower CCOTA acts as a voltage clamperMismatched-input TRs produce IOTA_Hthat equals to ITRI,making VTRIbe VTRI_HLogic w/auto-calibrationUDVTRI_HVTRICOMPLVTRI_LCLK0IOTA_HITRIOpe

151、rating waveforms(SELCLK=H)VTRI_HVDDVSSVTRIUDVSSVDDVTRI_LVTRI_HCOMPLITRIVBPVBNCOMPHITRIIOTA_H2ITRIITRIITRICAL4:0MP1MP2MN1MN2CTRI=ITRIVTRI_HVTRI_LRSQCLK0COMPLRSQBCLK180SELCLKMUXUPCAL4:05-BitUp CounterRDQ32-CycleCounterFINISHCALUDCOMPHCOMPHFINISHCAL21.2:A Dual-Input Bidirectional 3-Level Battery Charge

152、r with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference35 of 47Small-Signal Analysis of CCOTA Speed of CCOTA is important because used as both clamper and comparatorLow-impedance inside CCOTA 1/gm High-frequency poles1-pol

153、e system with a dominant pole(p1)at CTRInode Fast response can be possibleCTRIVDDVSSVTRIUDVSSVDDVTRI_LVTRI_HITRIMP1MP2MN1MN2p1 High Z Low Z Low Z Low Z Low Z Low Z Low ZITRI3ITRI3ITRILoop 1UD=HLoop 2UD=LP1 1ron/p2CTRI DC Gain 43gmn/p1ron/p2 GBW 43gmn/p1CTRI 21.2:A Dual-Input Bidirectional 3-Level Ba

154、ttery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference36 of 47Auto-VTRISlope Calibration Auto-calibration logic matches between two different VTRIgeneratorshaving different capacitor,current,and TRs.mismatch.A

155、djusts ITRIto match the slopes of VTRI_0and VTRI_180using the counterRSQCLK0COMPLRSQBCLK180SELCLKMUXUPCAL4:05-BitUp CounterRDQ32-CycleCounterFINISHCALUDCOMPHCOMPHFINISHCALLogic w/auto-calibrationUDVTRICOMPHUPCAL4:0ITRIFINISHCAL32-cycleCal.FinishedAuto-calibration period+1+1+1+1+1+1+1+1ITRI stays21.2

156、:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference37 of 47Outline Motivation and ChallengesHigh-Power Battery Charging and Power SharingFlying Capacitor Voltage(VCF)Ba

157、lancing Dual-Input Bidirectional 3-Level Battery ChargerOperational PrincipleCoarse-Fine VCFBalancerFrequency Foldback Controller Measurement Results Conclusion21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEE

158、E International Solid-State Circuits Conference38 of 47Chip Micrograph Process130-nm BCD Process Power TRs.Dual-Input:QCHG/QWC3-Level:Q1 Q4Battery CC/CV Regulation:QBAT SizeTotal:18.48 mm2w/o MCU&USB PD:10.39 mm221.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing an

159、d Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference39 of 47Measured Dual-Input Bidirectional Op.(1/2)Wired charging(adapter)+Wireless power sharingVCFbalancing(VCHG/2)can be achieved regardless of the direction of IIND1 s5 V2 A 2.5 VVCHGVWCICHGIBATITXV

160、LXVCFPower sharing active0.6 A1.4 A 0.7 A(-)0.4 AT.AdetachICHG Reg.1.2 A0 V0 A0 A0 V0 V5 V0 ABattery ChargingBattery DischargingBattery state:Converter mode:Regulation:Forward BuckReverse BoostIBATICHGVBYP21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide

161、VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference40 of 47Measured Dual-Input Bidirectional Op.(2/2)Wireless charging+Wired OTG deviceAs IOTGincreases,IWCis regulated instead of ICHG1 s5 V2 A 2.5 VOTG device active0.6 A1.4 A 0.7 A(-)0.4 AIWC Reg.1.2 A0 V0 A0

162、 A0 V0 V5 V0 ABattery ChargingBattery DischargingBattery state:Converter mode:Regulation:Forward BuckReverse BoostIBATIWCVBYPWireless Chg.detachVCHGVWCIWCIBATIOTGVLXVCF21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications

163、2025 IEEE International Solid-State Circuits Conference41 of 47Measured Frequency Foldback(1/2)Off-time foldback operation VCHG6 4.75 V,VBAT4.4 V,IBAT3.0 AIn heavy-load CCM,fSWis lowered from 700 kHz to 250 kHzMeanwhile,VCFis well balanced from 3 V to 2.4 V,equals to VCHG/2VCHGVBATVLXVCF6 V3 V3 A4.4

164、 V4.75 V2.4 V200 s5 V5 V2 V4 sfSW 0.7 MHzfSW 0.25 MHzIBAT2 A4 s21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference42 of 47Measured Frequency Foldback(2/2)On-time fo

165、ldback operation VCHG9 12 V,VBAT3.4 V,IBAT150 mAIn light-load DCM,fSWis lowered from 700 kHz to 250 kHzMeanwhile,VCFis well balanced from 4.5 V to 6 V,equals to VCHG/2VCHGVBATVLXVCF9 V12 V3.4 V4.5 V6 V150 mA200 s10 V5 V5 V2 VfSW 0.7 MHzfSW 0.25 MHz4 s4 s2 AIBAT21.2:A Dual-Input Bidirectional 3-Level

166、 Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference43 of 47Auto-Calibrated VTRIGeneratorAuto-Calibration ONVTRI_0and VTRI_180are having same rising/falling slopesVCFis well balanced and the ripple of IIN

167、Dis minimizedAuto-calibration OFFVCFis slightly unbalanced and the ripple of IINDbecomes largerIINDVLXCalibration ONCalibration OFFIINDVLX2 V4 s2 ARegular VLXBalanced VCFIrregular VLX2 V4 s2 AUnbalanced VCF21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide

168、 VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference44 of 47Measured Charging Efficiency Peak charging efficiency:96.8%VCHG5.0 V,VBAT4.6 V,IBAT1.0 A21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable

169、 Mobile Applications 2025 IEEE International Solid-State Circuits Conference45 of 47Comparison Table of Hybrid Charger ICsTPE 24 5ISSCC 23 8VLSI 23 9This workTopology3-L Buck3-L 2-Stage BuckHybrid Buck-Boost3-L BuckTechnology180-nm CMOS180-nm BCD180-nm BCD130-nm BCDVIN(V)5 125 245 124.75 12VOUT(V)3

170、5.52.8 4.23 83.4 4.6L170 nH2.2 H1.5 H330 nHCF22 F5.8+10 F22 F 210 F 2fSW1.5 MHz1.2 MHz0.5 0.8 MHz0.7 MHzChip Size(mm2)7.03569.46.7618.48(Total)10.39(w/o MCU+USB PD)Peak Efficiency96.02%(9 V/4 V/0.5 A)94.8%(5 V/3.6 V/1 A)96.5%(9 V/7 V/1.5 A)96.8%(5 V/4.6 V/1.0 A)#.of InputSingleSingleSingleDualMax.VC

171、R Buck-84%(5 V/4.2 V/3 A)88.9%*(9 V/8 V/3.75 A)92.6%(4.75 V/4.4 V/3 A)VCFBalancingS&HDuty mismatch-Coarse-FineBidirectional Op.BidirectionalForwardForwardSeamless Bidirectional*:Estimated value from the measured efficiency graph.21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fin

172、e VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference46 of 47Outline Motivation and ChallengesHigh-Power Battery Charging and Power SharingFlying Capacitor Voltage(VCF)Balancing Dual-Input Bidirectional 3-Level Battery ChargerOperational

173、 PrincipleCoarse-Fine VCFBalancerFrequency Foldback Controller Measurement Results Conclusion21.2:A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCFBalancing and Wide VCR for Foldable Mobile Applications 2025 IEEE International Solid-State Circuits Conference47 of 47ConclusionPr

174、oposed Dual-Input Bidirectional 3-Level Battery ChargerDual-input+3-level topology supporting both wired/wireless connectionsPeak charging efficiency of 96.8%Coarse-Fine VCFBalancerachieves fast and noise immune VCFbalancingregardless of direction of IINDduring bidirectional operationFrequency Foldb

175、ack Controlextends the effective duty ratiowith error-controlled OSC and auto-calibrated VTRIgenerator using CCOTAMax.VCR of 92.6%IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Track

176、ing for USB-to-2-Cell Bidirectional Power Transfer1 of 30 2025 IEEE International Solid-State Circuits ConferenceYunho Lee,Hyunjun Park,Minsu Kim,Woojoong Jung,Hongseok Kim,and Hyung-Min LeeKorea University,Seoul,KoreaA 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converte

177、r with Adaptive Target Current Tracking forUSB-to-2-Cell Bidirectional Power TransferIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Tra

178、nsfer2 of 30 2025 IEEE International Solid-State Circuits Conference Motivation Proposed Bidirectional Converter Proposed AHI bidirectional topology Normalized ILand loss analysis Normalized-IL(NIL)based adaptive IBATcontrol Measurement Results ConclusionOutlineIEEE Biomedical Circuits and Systems C

179、onference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer3 of 30 2025 IEEE International Solid-State Circuits Conference Motivation Proposed Bidirectional Converter Proposed A

180、HI bidirectional topology Normalized ILand loss analysis Normalized-IL(NIL)based adaptive IBATcontrol Measurement Results ConclusionOutlineIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Curr

181、ent Tracking for USB-to-2-Cell Bidirectional Power Transfer4 of 30 2025 IEEE International Solid-State Circuits ConferenceMotivationIn the forward mode 2-cell devices are charged by a 5V USB travel adapterIn the On-The-Go(OTG)mode 2-cell devices power other portable devices with 5VA high-efficiency

182、5V-to-2-cell bidirectional converter is requiredIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer5 of 30 2025 IEEE International

183、Solid-State Circuits ConferenceNo IL-reduction in both modesMax.voltage stress=1/2VBATPrior Works:1-31-2 Conventional Bidirectional SystemUSB AdapterIL(OTG)=IOTG2-cellDeviceIBAT5V SystemConventionalBuck/BoostTopologyForward Mode(Boost)On-The-Go Mode(Buck)5V(VUSB=VOTG)IOTGDCRIL(FM)=MIBAT6-8.4V(VBAT)I

184、L(OTG)IL(FM)L IL(OTG)=IOTGL IL(FM)=MIBATVUSBVOTGVBATJ Max.VDS=VBAT123 Bidirectional 3-Level ConverterTPEL 2024No IL-reduction in both modesMax.voltage stress=VBAT(8.4V)IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Conver

185、ter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer6 of 30 2025 IEEE International Solid-State Circuits ConferencePrior Works:4-5No IL-reduction in both modesMax.voltage stress=1/3VBAT4 Symmetric Hybrid Buck-BoostISSCC 20235 Bilaterally-Symmetrical Buck-BoostISSC

186、C 2024IL(OTG)IL(FM)VUSBVOTGAVSCAVSCVBATL IL(FM)=MIBATL IL(OTG)=IOTG32J Max.VDS=VBAT13IL(OTG)IL(FM)VBATVUSBVOTGL Max.VDS=VBATJ IL(FM)=IBATM+13J IL(OTG)=IOTGM+13Reduced ILin both modesMax.voltage stress=VBATIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inducto

187、r-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer7 of 30 2025 IEEE International Solid-State Circuits Conference Motivation Proposed Bidirectional Converter Proposed AHI bidirectional topology Normalized ILand loss analysis

188、Normalized-IL(NIL)based adaptive IBATcontrol Measurement Results ConclusionOutlineIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transf

189、er8 of 30 2025 IEEE International Solid-State Circuits ConferenceAlways Half-ILin both modes Low conduction loss(High efficiency)All 5V Tr.used Only low voltage 5V process(Low cost)8.48.28.07.86.46.26.05.88.6VUSB=5VVOTG=5VVBAT=6-8.4VBuck(VOTG/VBAT)=0.6-to-0.83Boost(VBAT/VUSB)=1.2-to-1.68Target VCROp

190、erational Target Range1008060402002-cell Voltage(V)State-Of-Charge(%)USB Adapter2-cellDeviceIBAT5V SystemVUSB=5VIOTGVBAT=6-8.4VAHI-Bidirectional Conv.IL(FM)IBATIL(OTG)IOTGBoost Mode(Charger)Buck Mode(On-The-Go)VOTG=5VVBAT=6-8.4VProposed Always-Half-IL(AHI)Bidirectional ConverterIEEE Biomedical Circu

191、its and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer9 of 30 2025 IEEE International Solid-State Circuits Conference Forward mode(Boost)-Max.VDSstress=VUS

192、B(S1-3)-IL=M/2IBAT=1/2IL,Conv(*IL,Conv=MIBAT)-VCF1=VUSB&VCF2=VBAT VUSB-6-SW/1-L/2-CFLYVUSBS4VX1CF1S2S3S1VX2S5S6CF2LVBATIBATCBAT2VUSBVBATIL(FM)1:DVUSBS4VX1CF1S2S3S1VX2S5S6CF2VBATIBATCBATVUSB2VBAT-VUSB2:1-DLIL(FM)Always reduced IL(IL(FM)IBAT)All 5V Tr.usedForward Mode Operation:Boost IEEE Biomedical C

193、ircuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer10 of 30 2025 IEEE International Solid-State Circuits Conference On-The-Go mode(Buck)-Max.VDSstre

194、ss=VOTG(S1-3)-IL=1/2IOTG=1/2IL,Conv(*IL,Conv=IOTG)-VCF1=VOTG&VCF2=VBAT VOTGAlways reduced IL(IL(OTG)IOTG)Always dual-path deliveryS4VX1CF1S2S3S1VX2S5S6CF2VBATIBATCBATVOTG2VBAT-VOTGLIL(OTG)1:DVOTGIOTGS4VX1CF1S2S3S1VX2S5S6CF2LVBATIBATCBAT2VOTGVBATIL(OTG)2:1-DVOTGIOTGOn-The-Go Mode Operation:Buck IEEE

195、Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer11 of 30 2025 IEEE International Solid-State Circuits Conference Motivation Proposed

196、Bidirectional Converter Proposed AHI bidirectional topology Normalized ILand loss analysis Normalized-IL(NIL)based adaptive IBATcontrol Measurement Results ConclusionOutlineIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional C

197、onverter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer12 of 30 2025 IEEE International Solid-State Circuits ConferenceNormalized Inductor Current(NIL)VCR(=VBAT/VUSB)1.61.41.21.31.41.51.7NIL=IL/IBATNormalized Inductor Current(Boost Mode)1.21.00.80.6Always 50%IL

198、Reduction1.80.41.01.11.61.8Target VCR1.681.2=IL,Conv VUSB=5V5ISSCC247ISSCC246ISSCC18This workTPEL243Highest ILreduction within the target range for both modesAlways reduced by 50%compared to IL,Conv0.40.50.60.70.80.91.01.1NIL=IL/IOTG0.50.60.70.80.91.0VCR(=VOTG/VBAT)Normalized Inductor Current(Buck M

199、ode)Target VCR0.83Always 50%IL Reduction0.6=IL,Conv VOTG=5VThis workJSSC1983TPEL245ISSCC24IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Powe

200、r Transfer13 of 30 2025 IEEE International Solid-State Circuits ConferenceNormalized Conduction Loss(1/2)VUSBCF1RON2S3S1S6CF2LVBAT1:DRON4DCRILRON5ICF2(1)VUSBS4CF1S22:1-DLRON1S5CF2VBATDCRRON3RON6ILICF1(2)Ex)Forward mode(Boost)PCond=D IL2(DCR+RON2)+ICF2(1)2RON4+(IL+ICF2(1)2RON5 +(1-D)IL2(DCR+RON6)+ICF

201、1(2)2RON1+(IL+ICF1(2)2RON3*PCondcalculation referenced by 5IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer14 of 30 2025 IEEE In

202、ternational Solid-State Circuits ConferenceNormalized Conduction Loss(2/2)Lowest Pcondwithin most of target range for both modes*Assume the same RONfor all(without considering HV-Tr)&DCR=6RONNormalized Conduction Loss(Boost Mode w/o LDMOS)1.266.46.87.27.688.4VBAT(V)PCond/PCond,Conv1.00.80.60.4VUSB=5

203、VDCR=6RONMax57%Min39%*PCond,Conv=(MIBAT)2(DCR+RON)Target VCR rangeThis work5ISSCC247ISSCC246ISSCC18TPEL243Normalized Conduction Loss(Buck Mode w/o LDMOS)1.266.46.87.27.688.4VBAT(V)PCond/PCond,Conv1.00.80.60.4VOTG=5VDCR=6RONMin39%Max57%*PCond,Conv=IOTG2(DCR+RON)Target VCR rangeThis work8JSSC19TPEL243

204、ISSCC245IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer15 of 30 2025 IEEE International Solid-State Circuits Conference Motivat

205、ion Proposed Bidirectional Converter Proposed AHI bidirectional topology Normalized ILand loss analysis Normalized-IL(NIL)based adaptive IBATcontrol Measurement Results ConclusionOutlineIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bi

206、directional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer16 of 30 2025 IEEE International Solid-State Circuits ConferenceOverall System Architecture Power Stage-All 5V Tr used On-The-Go Mode Loop-Voltage regulation(Voltage mode control)Forward Mode Lo

207、op-Current regulation(Average current mode control)VBATS1VG5VG1VREFVS/HtS/HS6CF2VG6VX2S4LS2CF1S3VG4VG3VG2VX1S5CBATProposed Power Stage(All 5V Tr)VAx1/2CurrentSensorEN_CCType-Comp.tS/HVRAMPEN_OTGVEA_CLVEA_VLType-Comp.VREF_VLIBATVCONHLEN_OTGVBATVUSBVG2PhaseCC/CVModeDutyEN_OTGEN_CCSPHLSF for S6Bootstra

208、pfor S3&S5VBSTVX1VUSBVBATLS&Gate DrvVSFDMAXLogicControlVG1VG2VG3VG4VG5VG6Voltage Regulation LoopCurrent Regulation LoopAverage CurrentMode ControlRSPWM LogicNIL-Based Adaptive IBAT ControllerLHVUSBVOTGCAS/H Constant Current Charging-NIL based IBATcontrolIEEE Biomedical Circuits and Systems Conferenc

209、e21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer17 of 30 2025 IEEE International Solid-State Circuits ConferenceNormalized-IL(NIL)Based Adaptive IBATControl(1/2)Hybrid topolo

210、gy-ILis a function of duty(IL IBAT)IL=NIL(D)IBATIBATICF=+*NIL(D)=IL/IBATConstant IL,AVGcontrol-IBATdeviates from the target IBATdepending on VBAT-Constant current charging cannot be achievedTarget IBATVBATErrorIBATILVBATConstant IL,AVGIBATIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-P

211、eak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer18 of 30 2025 IEEE International Solid-State Circuits ConferenceVCONVS/HVRAMPILVCA1/2VCAIBAT,AvgAdaptively track Target IBATVBATTarget IBAT,A

212、vgNormalized-IL(NIL)Based Adaptive IBATControl(2/2)Constant current charging regardless of VBAT&DutyAdaptively track the target IBATfor any VBATdeviationstttS/HIL,AVGDTRSAverage-PointSensingTVRAMPILS/HVCA1/2VCAVCON*NIL(D)=IL/IBATIf)VCON=NIL(D)VREFNegativeFeedbackCAVCONIL,AVGRS=NIL(D)IBATRS=NIL(D)VRE

213、F IBAT=VREFRSIL,AVGRS(VS/H)Target IBAT Controlled by VREFVCAIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer19 of 30 2025 IEEE I

214、nternational Solid-State Circuits Conference1/NILVREFNILDuty-to-1/NILConverterReciprocal Converter*NIL=IL/IBAT=1/(2-D)NIL-BasedAdaptive IBAT ControllerDutyTime1/VVTimeVCONVREFNIL(D)=ConceptualBlock DiagramDAnalogSubtractorAverageGenerator2VDV(2-D)VC1VUSBVRST1VVV-T*=1/NIL(D)DutyC1VUSBVRSTVT-VtReciVRE

215、FR1VoltTimeConverterTime1/VoltConverterVREFNIL(D)VCONS/Ht1VVV-TVtReciVT-VtVtReciVCON1/NIL(D)R1VSlope=1/NIL(D)R1C1DD-to-1/NIL Conv.Reciprocal Conv.AdaptiveVCONGeneration(1/2)Duty-to-1/NILconverter:Duty signal 1/NILVReciprocal converter Step 1:Generates reciprocal conversion timing(tReci)IEEE Biomedic

216、al Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer20 of 30 2025 IEEE International Solid-State Circuits ConferenceAnalogSubtractorAverageGenera

217、tor2VDV(2-D)VC1VUSBVRST1VVV-T*=1/NIL(D)DutyC1VUSBVRSTVT-VtReciVREFR1VoltTimeConverterTime1/VoltConverterVREFNIL(D)VCONS/Ht1VVV-TVtReciVT-VtVtReciVCON1/NIL(D)R1VSlope=VREFR1C1DD-to-1/NIL Conv.Reciprocal Conv.1/NILVREFNILDuty-to-1/NILConverterReciprocal Converter*NIL=IL/IBAT=1/(2-D)NIL-BasedAdaptive I

218、BAT ControllerDutyTime1/VVTimeVCONVREFNIL(D)=ConceptualBlock DiagramDAdaptiveVCONGeneration(2/2)Reciprocal converter Step 2:Generates IBATcontrol signal VCON(=VREFNIL)by using tReciIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirec

219、tional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer21 of 30 2025 IEEE International Solid-State Circuits Conference Motivation Proposed Bidirectional Converter Proposed AHI bidirectional topology Normalized ILand loss analysis Normalized-IL(NIL)based

220、 adaptive IBATcontrol Measurement Results ConclusionOutlineIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer22 of 30 2025 IEEE In

221、ternational Solid-State Circuits ConferenceDie MicrographControllerNIL-Based Adaptive IBAT ControllerCBST1CBST2CBST2S1S2S3S5S6S42.7mm2.4mmFabricated in a 180-nm process using only 5V Tr.L=4.7uH,CF1=CF2=COUT=10uF,FSW=1MHzIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Alwa

222、ys-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer23 of 30 2025 IEEE International Solid-State Circuits ConferenceSteady-State Waveforms600ns200mAIOTG=1AIL,Avg=0.5AVX1VX22VOTGVBATVOTG2VBAT-VOTGVBAT=7.2VVOTG=5V2

223、VSteady State(7.2V-to-5V,IOTG=1A)VBAT=7.2VVUSB=5VVX1VX2IL,Avg=0.74AIBAT=1A2VUSBVBAT2VBAT-VUSBVUSB600ns200mA2VSteady State(5V-to-7.2V,IBAT=1A)Boost Mode(Current Regulation)Buck Mode(Voltage Regulation)In Boost mode(VUSB=5V,VBAT=7.2V,IBAT=1A)ILreduced by 26%In Buck mode(VBAT=7.2V,VOTG=5V,IOTG=1A)ILred

224、uced by 50%IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer24 of 30 2025 IEEE International Solid-State Circuits ConferenceTrans

225、ient Response WaveformsILVUSB=5VVBAT=7.6VVBAT=7.2V40s40mVVCONIBAT=1A200mV100mA400mA180mA JAdaptively tracking target IBATJControl the IL,Avg by VCONVBAT Step-up Response(7.2V-to-7.6V)IOTG=0AIOTG=1AIOTG=0AILVOTG=5V110mV40s200mA100mVEdge time:400ns16s14sLoad Transient Response(VBAT=7.2V,0A-to-1A)Boost

226、 Mode(Current Regulation)Buck Mode(Voltage Regulation)In Boost mode(VUSB=5V,VBAT=7.2V7.6V,Target IBAT=1A)IBATadaptively tracks the target IBAT(=1A)for VBATstep-up In Buck mode(VBAT=7.2V,VOTG=5V,IOTG=0A1A/1A0A)Undershoot=110mV/Overshoot=100mVIEEE Biomedical Circuits and Systems Conference21.4:A 97.4%

227、-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer25 of 30 2025 IEEE International Solid-State Circuits ConferencePower Efficiency-Boost ModeIBAT(A)979593918987850.20.40.60.81.21.06.4V6.8V7

228、.2V8.4V7.6V8V6VVBATPeak Efficiency97.4%400mAEfficiency(%)97.4%Measured Eff.w/DCR=11.5m VUSB=5V(DCR=11.5m)7.67.97.1mm979593918987850.20.40.60.81.21.06.4V6.8V7.2V8.4V7.6V8V6VVBATEfficiency(%)Peak Efficiency96%500mAIBAT(A)96%Measured Eff.w/DCR=295m VUSB=5Vmm1.22.52.0(DCR=295m)For low DCR(=11.5m),Peak E

229、ff.=97.4%IBAT=400mA,VCR=1.36 For high DCR(=295m),Peak Eff.=96%IBAT=500mA,VCR=1.36IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfe

230、r26 of 30 2025 IEEE International Solid-State Circuits ConferencePower Efficiency-Buck ModeIOTG(A)979695949291900.20.40.60.81.21.0Efficiency(%)1.41.693986.4V6.8V7.2V8.4V7.6V8V6VVBATPeak Efficiency96.2%600mA96.2%Measured Eff.w/DCR=295m VOTG=5Vmm1.22.52.0(DCR=295m)IOTG(A)979695949291900.20.40.60.81.21

231、.0Efficiency(%)1.41.69398Peak Efficiency97%600mA6.4V6.8V7.2V8.4V7.6V8V6VVBAT97%Measured Eff.w/DCR=11.5m VOTG=5V(DCR=11.5m)7.67.97.1mmFor low DCR(=11.5m),Peak Eff.=97%IBAT=600mA,VCR=0.74For high DCR(=295m),Peak Eff.=96.2%IBAT=600mA,VCR=0.74IEEE Biomedical Circuits and Systems Conference21.4:A 97.4%-P

232、eak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking for USB-to-2-Cell Bidirectional Power Transfer27 of 30 2025 IEEE International Solid-State Circuits Conference The highest reduction of ILin both directionsComparison TableA VCR=VOUT/VINT

233、his workTechnologyTopologyBoostNominal VIN VNominal VOUT VFSW MHzL H510.18m6-8.4Peak Eff.VCRABoostBuck4.797.4%1.3697%0.7411.5295COUT F/CF F10/10 x296%1.3696.2%0.74DCR mAlways Reduced ILC(ILCCMTransition to wider bandwidth in DCM mode and back to regular bandwidth mode in CCM based on DCM detection.-

234、202ns-102ns-2ns98ns198ns298ns398ns498ns598ns698ns798nsVoutDCM HoldLoad IndicatorDCM operationCCM operationTransient performance with adaptive compensation 622mV597mV572mV547mV522mV497mV472mV447mV422mVDifferent compensation recipe21.5:A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Lig

235、ht Load Efficiency Peak of 86%,Featuring an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS 2025 IEEE International Solid-State Circuits Conference20 of 23Autonomous Transition between statesDuring a load decrease,FIVR moves from H

236、S-SS-DCM gradually through ZCD comparator sensing.During a sudden load increase,FIVR moves from DCM-HS(depending on load condition)for faster transient responseVoutCCM operationSSDCM operationBack to CCM-2s-1s0s1s2s3s4s5sDCM active6s7s8sSoft switching496mV546mV596mV646mV696mV746mV796mV846mV896mV90mV

237、 peak-to-peak5A step 1A/ns load slew rate35mV21.5:A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light Load Efficiency Peak of 86%,Featuring an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS 2025 IEEE International

238、 Solid-State Circuits Conference21 of 23Loop Stability&Regulation BandwidthRegulation loop stability is ensured across different modes of operation.Phase180120600-60-120-18010k100k1M10M100M1G21.5:A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light Load Efficiency Peak of 86%,Featuri

239、ng an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS 2025 IEEE International Solid-State Circuits Conference22 of 23BenchmarkingISSCC 2019 3ISSCC 2017 4ISSCC 2022 7This WorkTechnology14nm14nm4nm3nm FinFETInductorIn-packageIn-packa

240、geIn-packageIn-packageFsw70MHz100MHz50MHz60 MHzL(per phase)10nF1.5nH5nH3nHVin range1.6V1.51.8V1.5 to 1.8VVout range1.2V1.151V0.5 to 1.4Peak Efficiency88%84%91.5%1.8Vin/1.1Vout86%1.75Vin/0.75VoutEfficiency 1%of Imax72%N/A Analog DISLDO21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an

241、 SoC 2025 IEEE International Solid-State Circuits Conference6 of 64Motivation:Digital vs Analog VOUT:Digital DISLDO Analog DISLDO Current Efficiency:Digital DISLDO Analog DISLDO21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Confere

242、nce7 of 64 Digital DISLDO Uneven ILOAD(resistor in triode)Motivation:Digital vs Analog 21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference8 of 64Motivation:Digital vs Analog Digital DISLDO Uneven ILOAD(resistor in triode)Anal

243、og DILSDO Even ILOAD(current source in saturation)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference9 of 64Motivation:Digital vs Analog SoC NoiseDigital DISLDO Noise-tolerant 21.6:A 2A Fully Analog Distribution LDO with Nois

244、e Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference10 of 64Motivation:Digital vs Analog SoC NoiseDigital DISLDO Noise-tolerant Analog DISLDO Noise-sensitive 21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits C

245、onference11 of 64Motivation:Digital vs Analog 21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference12 of 64Outline Motivation Proposed Analog Distribution LDOSoC Noise-Immune Design Methodology SoC Noise Cancelling Amplifier DC

246、 Current Correction Integrator Current Balancing Design MethodologyLoop Analysis and Circuit Implementation Measurement Results Conclusion21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference13 of 64Proposed Analog Distribution

247、 LDO Blue Metal:Path(1)Green Metal:Path(2)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference14 of 64Proposed Analog Distribution LDO Sensitive to SoC Noise Blue Metal:Path(1)Green Metal:Path(2)21.6:A 2A Fully Analog Distribu

248、tion LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference15 of 64Proposed Analog Distribution LDO Sensitive to SoC Noise Blue Metal:Path(1)Green Metal:Path(2)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-Sta

249、te Circuits Conference16 of 64Proposed Analog Distribution LDO Blue Metal:Path(1)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference17 of 64SoC Noise-Immune Design Methodology Blue Metal:Path(1)Add Noise Coupling Path21.6:A 2

250、A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference18 of 64SoC Noise-Immune Design Methodology Blue Metal:Path(1)Add Noise Coupling Path21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International So

251、lid-State Circuits Conference19 of 64Path(1)Noise-Immune System SoC Noise Cancelling Amplifier(SNCA)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference20 of 64Path(1)Noise-Immune System SoC Noise Cancelling Amplifier(SNCA)Com

252、mon Mode Noise Rejection(CMNR)CMNR21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference21 of 64SoC Noise-Immune Design Methodology Green Metal:Path(2)Single Metal Line21.6:A 2A Fully Analog Distribution LDO with Noise Immunity

253、for an SoC 2025 IEEE International Solid-State Circuits Conference22 of 64Path(2)Noise-Immune System Single Metal Line DCCIs Low Frequency Pole21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference23 of 64Path(2)Noise-Immune Sys

254、tem Single Metal Line DCCIs Low Frequency Pole SoC Noise is filteredFiltered21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference24 of 64Outline Motivation Proposed Analog Distribution LDOSoC Noise-Immune Design Methodology SoC

255、 Noise Cancelling Amplifier DC Current Correction Integrator Current Balancing Design MethodologyLoop Analysis and Circuit Implementation Measurement Results Conclusion21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference25 of

256、64Current Balancing Design Methodology DC Current Correction integrator(DCCI)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference26 of 64Current Balancing Design Methodology21.6:A 2A Fully Analog Distribution LDO with Noise Im

257、munity for an SoC 2025 IEEE International Solid-State Circuits Conference27 of 64Current Balancing Design Methodology21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference28 of 64Current Balancing Design Methodology Main LDO&1 A

258、uxiliary LDO21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference29 of 64Current Balancing Design Methodology Main LDO&1 Auxiliary LDO N:1 Current SensorCurrent SensorCurrent Sensor21.6:A 2A Fully Analog Distribution LDO with N

259、oise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference30 of 64Current Balancing Design Methodology Main LDO&1 Auxiliary LDO N:1 Current Sensor Correction Loop(TCOR)21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Cir

260、cuits Conference31 of 64Current Balancing Design Methodology Main LDO&1 Auxiliary LDO N:1 Current Sensor Correction Loop(TCOR)Slow Loop21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference32 of 64Current Balancing Design Method

261、ology21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference33 of 64Current Balancing Design MethodologyIPMIPAIPMIPA21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circui

262、ts Conference34 of 64Current Balancing Design MethodologyIPMIPAIPMIPA21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference35 of 64Outline Motivation Proposed Analog Distribution LDOSoC Noise-Immune Design Methodology SoC Noise

263、Cancelling Amplifier DC Current Correction Integrator Current Balancing Design MethodologyLoop Analysis and Circuit Implementation Measurement Results Conclusion21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference36 of 64Loop

264、Analysis Simple Block Diagram21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference37 of 64Loop Analysis Main LDO VOUTRegulationTM21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Sol

265、id-State Circuits Conference38 of 64Loop Analysis Main LDO VOUTRegulationTM21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference39 of 64Loop Analysis Aux.LDO VOUTRegulation1.TFL21.6:A 2A Fully Analog Distribution LDO with Noise

266、 Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference40 of 64Loop Analysis Aux.LDO VOUTRegulation2.TFH21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference41 of 64Loop Analysis Aux.LDO VOUTRegulation1.TFL

267、2.TFH Correlation Local LoopTCOR21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference42 of 64Loop Analysis Aux.LDO VOUTRegulation1.TFL2.TFH Correlation Local LoopTCOR21.6:A 2A Fully Analog Distribution LDO with Noise Immunity f

268、or an SoC 2025 IEEE International Solid-State Circuits Conference43 of 64Loop Analysis 1.TFL21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference44 of 64Loop Analysis 1.TFL21.6:A 2A Fully Analog Distribution LDO with Noise Immu

269、nity for an SoC 2025 IEEE International Solid-State Circuits Conference45 of 64Loop Analysis 1.TFL21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference46 of 64Loop Analysis 2.TFH21.6:A 2A Fully Analog Distribution LDO with Nois

270、e Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference47 of 64Loop Analysis 2.TFH21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference48 of 64Loop Analysis 2.TFH21.6:A 2A Fully Analog Distribution LDO wit

271、h Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference49 of 64Loop Analysis Aux.LDO VOUTRegulation1.TFL2.TFH21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference50 of 64Loop Analysis21.6:A 2A Fully

272、Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference51 of 64Loop Analysis21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference52 of 64Loop Analysis Main LDO=Aux.LDOSame

273、Gain&BW21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference53 of 64Loop AnalysisLow Frequency21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference54 of 6

274、4Loop AnalysisHigh Frequency21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference55 of 64Circuit Implementation21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits

275、Conference56 of 64Outline Motivation Proposed Analog Distribution LDOSoC Noise-Immune Design Methodology SoC Noise Cancelling Amplifier DC Current Correction Integrator Current Balancing Design MethodologyLoop Analysis and Circuit Implementation Measurement Results Conclusion21.6:A 2A Fully Analog D

276、istribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference57 of 64Chip Micrograph1.Power TR2.GEA+Core LDO+CML3.Aux.LDO+Self Biasing Circuit+RC Ladder4.DCCI1+2+321.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International S

277、olid-State Circuits Conference58 of 64SoC Noise Rejection RC Ladder Modeling21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference59 of 64Current Balancing21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 20

278、25 IEEE International Solid-State Circuits Conference60 of 64Load Transient Waveforms CLOAD=1 nF 235 mV undershoot occurs during 1 mA to 2 A transition21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference61 of 64Comparison Tabl

279、e21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference62 of 64Outline Motivation Proposed Analog Distribution LDOSoC Noise-Immune Design Methodology SoC Noise Cancelling Amplifier DC Current Correction Integrator Current Balanc

280、ing Design MethodologyLoop Analysis and Circuit Implementation Measurement Results Conclusion21.6:A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC 2025 IEEE International Solid-State Circuits Conference63 of 64ConclusionsThis work proposes a Fully Analog Thermal Distribution LDOAchi

281、eve Current Sharing Accuracy of 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=1

282、2V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 26412768514586821.7:Merging Hybrid and Multi-Phase Topologi

283、es:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference65 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPlan HCDVin V/VO V

284、12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm

285、322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 264127685145868 S

286、upports wide range VO21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference66 of 75Table of Comparisons1410121113This WorkISSCC 2022

287、ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPlan HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H

288、2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.3

289、48.38.06Maximum Current Density(A/cm3)78.359350 264127685145868 Supports wide range VO Wide VCR21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Cir

290、cuits Conference67 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPlan HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F

291、4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88

292、.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 264127685145868 Supports wide range VO Wide VCR High IO21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Co

293、nversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference68 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPlan HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13

294、.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V

295、91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 264127685145868 Supports wide range VO Wide VCR High IO Flexible FSW21.7:Merging Hybrid and Mult

296、i-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference69 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPl

297、an HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.

298、5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 2

299、64127685145868 Supports wide range VO Wide VCR High IO Flexible FSWAble to use compact inductors with large RDCR21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE Internationa

300、l Solid-State Circuits Conference70 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPlan HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying

301、Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91

302、%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 264127685145868 Supports wide range VO Wide VCR High IO Flexible FSWAble to use compact inductors with large RDCR Good efficiency performance21.7:Merging Hybrid

303、and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference71 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024P

304、lan HEPlan HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N

305、.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.

306、359350 264127685145868 Supports wide range VO Wide VCR High IO Flexible FSWAble to use compact inductors with large RDCR Good efficiency performance Compact passives volume21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Convers

307、ion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference72 of 75Table of Comparisons1410121113This WorkISSCC 2022 ISSCC 2023ISSCC 2023ISSCC 2023ISSCC 2024Plan HEPlan HCDVin V/VO V12/0.9-1.89-16/0.6-1.612/0.6-1.212/1-1.812/1-1.812/0.3 1.1Min.(1/VCR)Peak 75%13.3320

308、2012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)6535.283.2161.92Peak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%

309、1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9VTotal Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.348.38.06Maximum Current Density(A/cm3)78.359350 264127685145868 Supports wide range VO Wide VCR High IO Flexible FSWAble to use compact inductors wit

310、h large RDCR Good efficiency performance Compact passives volume Good current density 21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Con

311、ference73 of 75Summary3x smaller volume inductorsfor same max output ripple6-interleavingExtends duty cycle by 300%suited for wide conversion ratiosSmaller passives:Larger bandwdith=3 1345Current balancing between the phases2Lower stress voltage across switches621.7:Merging Hybrid and Multi-Phase To

312、pologies:A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference74 of 75Summary3x smaller volume inductorsfor same max output ripple6-interleavingExtends duty cycle by 300%suited fo

313、r wide conversion ratiosSmaller passives:Larger bandwdith=3 1345Current balancing between the phases2Lower stress voltage across switches6Significant benefits can be achieved by merging the hybrid converters and Multi-phase converters 21.7:Merging Hybrid and Multi-Phase Topologies:A 6-Phase Triple-S

314、tep-Down DC-DC Converter Achieving up to a 60:1 Voltage Conversion Ratio and 868A/cm3Current Density 2025 IEEE International Solid-State Circuits Conference75 of 75Q&AQuestions?Contact:mkamelucsd.edu(Mahmoud Hmada)Thank you for listeningThis work was supported in part by the Power ManagementCenter(P

315、MIC)an NSF I/UCRC,award number 205280921.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference1 of 43HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance ComputingZhiguo Tong*1,Zhewen Yu*1,2,Junwei Huang1,Xian

316、gyu Mao1,3,Bernhard Wicht4,Rui P.Martins1,and Yan Lu1,2,31University of Macau,Macao,China,2Tsinghua University,Beijing,China,3UM Hetao IC Research Institute,Shenzhen,China,4Leibniz University Hannover,Hannover,Germany21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 202

317、5 IEEE International Solid-State Circuits Conference2 of 43Converter Ring Structure for Processor Power Delivery Multi-phasehybridDC-DCconverter-ring(HOOP).XPUCell#nCell#n+1Cell#xCell#x+1Cell#m+1Cell#mPower Ring for Current BalanceBack Ring for Phase SheddingCell#NCell#1Y.Lu,ISSCC15 Multi-phase swit

318、ched capacitorDC-DC converter-ring.21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference3 of 43Whats the“HOOP”A ring structure of DC-DCconverters.Hybrid DC-DC converterswith the power ring(O)and the back ring(O)forcomp

319、uting Power delivery.The power ring for autocurrent balance.Thebackringforphase shedding.Wukong tight hoop Nezha universe hoopXPUCell#nCell#n+1Cell#xCell#x+1Cell#m+1Cell#mPower Ring for Current BalanceBack Ring for Phase SheddingCell#NCell#121.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High P

320、erformance Computing 2025 IEEE International Solid-State Circuits Conference4 of 43Outline Background and Motivation Proposed HOOP Structure and Circuit Implementation Operation Principle Current Balance Analysis Phase Shedding Implementation Fast Transient Response and System Diagram Measurement Re

321、sults Conclusion21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference5 of 43Background GPU TDP Evolution Almost 1.5x power increase every two years.“Power wall”limitation for GPU design.Stronger power capability and hi

322、gher conversion efficiency solution needed.2010201520202025020040060080010001200Thermal Design Power(W)Year NVIDIA GPU Series AMD GPU Series Intel GPU SeriesGF106GM107P100 V100A100H100B200MI250XMI300XGaudi2Gaudi3Source:AMD,MI325X(1000W)Power SupplyGK106MI325XAlmost 1.5x Power Increase Every Two Year

323、s!21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference6 of 43Multi-Phase DC-DC ConverterVINCurrent Balance ControllerBuckPWM1PWMN.VOUT.IL1ILNBuckPWM2IL2.BuckVINSwitched Capacitor.VOUTSwitched CapacitorSwitched Capacit

324、orMultiphase Capacitive Converter(MCC)Reduced output voltage ripple and input current ripple.Fully Integrated.Simple balance control.x Efficiency(like linear regulator).x Bulky inductor for each phase.x Complex balance control.Efficiency(ideally 100%).Multiphase Inductive Converter(MIC)21.8:HOOP:A S

325、calable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference7 of 43Cross-Connected CFs for Inductor Current BalancingL1VOUTL2IL1IL2L1VOUTIL1=IL2 Smaller current ripple,faster response.Auto-current balance technique.x Incapable of phase sh

326、edding.x Reduced light load efficiency.C.Wang,TPEL21 Multiple-phase 3-level converter with cross-connected flying capacitors.21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference8 of 43L1L2L3L4L6L5L8L7ICBInter-Channel

327、Balancing(ICB)VOUTICBICBICBIL2=IL3IL4=IL5IL6=IL7IL8=IL1Prior Arts-CF-Based Auto Inductor Current BalanceJ.Cho,VLSI22 Auto-current balance technique.Scalable to multiple converters.x Incapable of phase shedding.x Reduced light load efficiency.VINL1L2VOUTIL1IL2IL1=IL2 Single converter current balance.

328、Multiple converters current balance.21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference9 of 43Prior Arts Easy-Scalable Multiple Phase ConverterLVOUTCOUTVDCVINCF1S1S2S3S4N phasesJ.Yang,CICC24 Easy-scalable structure.I

329、mproved light load efficiency.x Current balance control needed.L1VINCF1S1S2S3S4VINCF1S1S2S3S4L2IL1IL2VOUT21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference10 of 43Outline Background and Motivation Proposed HOOP Stru

330、cture and Circuit Implementation Operation Principle Current Balance Analysis Phase Shedding Implementation Fast Transient Response and System Diagram Measurement Results Conclusion21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Cir

331、cuits Conference11 of 43XPUCell#x+1Cell#m+1Cell#mCell#nCell#n+1Cell#xCell#NCell#1Proposed HOOP Structure(1/4)Converter cells paralleled and arranged in a ring configuration.Deliver large current.Minimum on-board resistance loss.21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Co

332、mputing 2025 IEEE International Solid-State Circuits Conference12 of 43XPUCell#x+1Cell#m+1Power Ring for Current BalanceCell#mCell#nCell#n+1Cell#xCell#NCell#1Proposed HOOP Structure(2/4)Converter cells paralleled and arranged in a ring configuration.Deliver large current.Minimum on-board resistance

333、loss.The power ring for auto current balance.Transfer a portion of inductor current to the next cell.21.8:HOOP:A Scalable Hybrid DC-DC Converter Ring for High Performance Computing 2025 IEEE International Solid-State Circuits Conference13 of 43XPUCell#nCell#n+1Cell#xCell#x+1Cell#m+1Cell#mPower Ring for Current BalanceBack Ring for Phase SheddingCell#NCell#1Proposed HOOP Structure(3/4)Converter cel