《Session 21Compute and USB Power.pdf》由會員分享，可在線閱讀，更多相關《Session 21Compute and USB Power.pdf（29頁珍藏版）》請在三個皮匠報告上搜索。
1、Session 21 Overview:Compute and USB Power POWER MANAGEMENT SUBCOMMITTEEThe overarching theme of this session is design innovation in power converter topologies and control yielding simple and robust circuits that broadly achieves the following:1)inherently reducing passive needs;2)effective volume u
2、tilization of existing passives through continuous conduction;and 3)auto current and voltage balancing across the many phases or passives within.The session has excellent representation ofinnovationsin the compute and USB area from both industry as well as university researchers spanning from basic
3、buck converters to hybrid yet inductive converters as well as a resonant SC converter and a digital LDO.Overall,we have five papers covering 12V-to-1V converters with currents over 4.5A.Session Chair:John Pigott NXP Semiconductors,Chandler,AZ Session Co-Chair:Rinkle Jain Nvidia,Portland,OR 372 2025
4、IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE1:30 PM 21.1 A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-t o-1V Two-St age Convert er wit h Regulat ed Resonant Swit ched-Capacit or Regulat ors Shengdao R
5、en,Zhejiang University,Hangzhou,China In Paper 21.1 from Zhejiang University,Hangzhou,China describes a 12-to-1V two-stage converter with regulated resonant switched-capacitor regulators using 65nm CMOS and reaching 89.3%efficiency.1:55 PM 21.2 A Dual-Input Bidirect ional 3-Level Bat t ery Charger w
6、it h Coarse-Fine VCF Balancing and Wide VCR for Foldable Mobile Applicat ions Woojin Hong,Samsung Electronics,Hwaseong,Korea In Paper 21.2 from Samsung Electronics,Hwaseong,Korea introduces a dual-input bidirectional 3-Level battery charger with VCF balancing and a wide input from 4.65-to-12V for mo
7、bile applications using 0.13m BCD and reaching 96.8%efficiency.2:20 PM 21.3 A Segment ed-Int erlacing Mult i-Phase Hybrid Convert er wit h Inherent ly Aut o-Balanced ILs and Boost ed IL Slew Rat e During Load Transient s Jiacheng Yang,University of Macau,Macau,China In Paper 21.3 from University of
8、Macau covers a Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs using a 180nm BCD process which reaches 92.9%efficiency and can deliver 6A.3:35 PM 21.6 A 2A Fully Analog Dist ribut ion LDO wit h Noise Immunit y for an SoC Jeong-Hun Kim,Sogang University,Seoul,Korea In Paper 21.6 from S
9、ogang University,Seoul,Korea describes a 2A analog distribution LDO for a SoC in a 28nm technology with excellent noise immunity in an SoC application.4:00 PM 21.7 Merging Hybrid and Mult i-Phase Topologies:A 6-Phase Triple-St ep-Down DC-DC Convert er Achieving up t o a 60:1 Volt age Conversion Rat
10、io and 868A/cm3 Current Densit y Mahmoud Hassan Kamel Hmada,University of California,San Diego,CA In Paper 21.7,researchers from University of California San Diego,California,USA describe a merged hybrid and multi-phase implementation of a 6-phase triple-step-down DC-DC converter which can reach 91%
11、efficiency and deliver 7A using a 0.18m process at a current density of 868A/cm.4:25 PM 21.8 HOOP:A Scalable Hybrid DC-DC Convert er Ring for High-Performance Comput ing Zhiguo Tong,University of Macau,Macau,China In Paper 21.8 from University of Macau,Macao,China presents a scalable hybrid DC-DC co
12、nverter with a power ring for current balance and a back ring for phase shedding,named as HOOP.Implemented in 0.18m BCD,this converter can reach 90.2%efficiency and deliver up to 16A.4:50 PM 21.9 A 20MHz&1MHz Dual-Loop Non-Uniform-Mult i-Induct or Hybrid DC-DC Convert er wit h Specified Induct or Cu
13、rrent Allocat ion and Fast Transient Response Junwei Huang,University of Macau,Macau,China In Paper 21.9,from University of Macau,Macao,China presents a 20MHz&1MHz dual-loop multi-inductor hybrid DC-DC converter with non-uniform current allocating optimizing both up and down transient performance as
14、 low as 6.3%using a 0.18m BCD technology.3:00 PM 21.5 A Fully Int egrat ed Mult i-Phase Volt age Regulat or wit h Enhanced Light-Load-Efficiency Peak of 86%,Feat uring an Aut onomous Mode Transit ion from Hard-Swit ching t o Soft-Swit ching t o Discont inuous Conduct ion Mode in 3nm FinFET CMOS Kish
15、an Joshi,Intel,Santa Clara,CA In Paper 21.5 from Intel,Santa Clara,California,USA presents a 60MHz integrated multi-phase regulator which features an autonomous mode transition from hard-switching to soft-switching to discontinuous conduction mode using a 3nm FinFET technology.ISSCC 2025/February 18
16、,2025/1:30 PM373 DIGEST OF TECHNICAL PAPERS 2:45 PM 21.4 A 97.4%-Peak-Efficiency Always-Half-Induct or-Current Hybrid Bidirect ional Convert er wit h Adapt ive Target Current Tracking for USB-t o-2-Cell Bidirect ional Power Transfer Yunho Lee,Korea University,Seoul,Korea In Paper 21.4 from Korea Uni
17、versity,Seoul,Korea covers a half-inductor-current hybrid bidirectional converter performing USB to 2-cell bidirectional power transfer reaching 97.4%efficiency using a 0.18m technology and only requiring 5V transistors.21374 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION
18、21/COMPUTE AND USB POWER/21.1979-8-3315-4101-9/25/$31.00 2025 IEEE21.1 A 12A 89.3%Peak Efficiency and 26mV Undershoot 12-t o-1V Two-St age Convert er wit h Regulat ed Resonant Swit ched-Capacit or Regulat ors Shengdao Ren,Yukan Du,Menglian Zhao,Zhichao Tan,Chushan Li,Yong Ding,Wuhua Li,Wanyuan Qu Zh
19、ejiang University,Hangzhou,China The ever-hungry computing needs for data centers and automotive applications require a large output current at sub-1V voltages.On the other hand,the input voltage of power converters must be raised to ease the I2R loss on the system voltage bus.The high input voltage
20、 and large output current requirements impose significant challenges on the converter efficiency,density,and speed,which are all crucially important for high performance computing devices.The two-stage-regulator approach emerges as a promising solution which interfaces the high input voltage with an
21、 intermediate bus converter(IBC)and supplies the processors with a high-density point of load converter(PoL),as is shown in Fig.21.1.1 1-5.Usually,the IBC converts the high input voltage into a lower intermediate bus,VMID,with high efficiency while the low-voltage PoL achieves high density and fast
22、responses.Compared with single stage 12V-to-1V converters 6-18,the two-stage solution shows a better potential for vertical power delivery since the low-voltage PoL can fully exploit the advanced active/passive processes.Since the PoL normally determines the core power density and the transient perf
23、ormance,significant design effort has been invested into the PoL design.Figure 21.1.1 describes a qualitative comparison between the four possible PoL architectures:1)low-dropout regulators(LDO);2)inductive integrated voltage regulators(IVR);3)switched-capacitor voltage regulators(SCVR);and 4)the pr
24、oposed regulated resonant switched-capacitor converter(RReSC).The LDO regulator displays excellent power density while severely sacrificing efficiency.The IVR demonstrates excellent transient and dynamic voltage scaling(DVS)performances,however,this comes at the cost of complicated inductor design,m
25、edium density,and high design complexity.By taking advantage of high-density deep trench or super MIM capacitors,the SCVR arises as a promising high-density solution.Nevertheless,its low energy utilization ratio,which is defined as the energy transferred to load every switching cycle versus the ener
26、gy stored by the storage element,could seriously limit its load capacity,transient and DVS performances.In order to address the above issues,Fig.21.1.1 presents a two-stage 12-to-1V converter with a regulated resonant switched-capacitor PoL.By inserting a parasitic trace inductor into the switched-c
27、apacitor PoL,the resulting resonant converter can show a decent energy utilization ratio,leading to an extended load capacity with excellent efficiency and a small impact on density.Additionally,the resonant operation of the switched-capacitor circuit paves the way for PoL voltage regulation,which c
28、an be vitally important for load transient and DVS performance.In this work,the output regulation is achieved by the 2nd stage RReSC PoL,while the 1st stage IBC adaptively generates an optimum output VMID for the PoL.Therefore,during steady-state,the RReSC always operates with the optimum fixed 2:1
29、conversion ratio,achieving an exceptionally high efficiency.During the transients,the closed-loop PoL can respond immediately,leading to excellent transient performances.Figure 21.1.2 depicts the proposed overall circuit architecture and the corresponding RReSC operation states.Here,the IBC adopts a
30、 double-step-down converter with four 40V off-chip GaN FETs,while the PoL employs a three-phase resonant switched-capacitor converter using parasitic trace inductors.The RReSC utilizes a phase-shift control scheme for the closed-loop PoL regulation and generates an optimum reference voltage VREF_MID
31、 for the IBC with a phase-locking-loop(PLL).From the figure,the RReSC works in four operation states 1-4,in which the switches S1/S2 form a complementary switching pair,S3/S4 form another complementary pair,and the duty cycles of S1-S4 are always 50%.Figure 21.1.3(top)shows the phase shift control m
32、echanism for the RReSC voltage regulation.When the phase of S1 leads that of S3,the PoL operates in boost mode with states 1234,by which Vo1/2VMID is achieved.When the phase of S1 and S3 are the same,the PoL enters the non-regulation condition,alternating between states 24 to realize an output of Vo
33、1/2VMID.Similarly,when the phase of S1 lags that of S3,the PoL operates in buck mode with states 2143,by which VoVP,S1 leads the phase of S3 with the PoL in boost mode.When VC=VP,there is zero phase between S1 and S3,coinciding with the PoL in non-regulation mode.When VC0.5 Control Achieving 2x Tran
34、sient Inductor Current Slew Rate and 0.73 Theoretical Minimum Output Undershoot of DSD,”ISSCC,pp.1-3,Feb.2022.10 J.Yuan et al.,“A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9us 1%Settling Time for a 3A/20ns Load Transient,”ISSCC,pp.1-3,Feb.2022.11 X.Yang et al.,“A 5A 94.5%Peak Efficienc
35、y 916V-to-1V Dual-Path Series-Capacitor Converter with Full Duty Range and Low V.A Metric,”ISSCC,pp.196-198,Feb.2023.12 X.Zhang et al.,“A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC-DC Converter With Inherent Current Equalization Characteristics,”IEEE JSSC,vol.59,n
36、o.9,pp.2895-2906,Sept.2024.13 Y.Ji et al.,“A 12V-Input 1V-1.8V-Output 94.7%-Peak-Efficiency 685A/cm3-Current-Density Hybrid DC-DC Converter with a Charge Converging Phase,”ISSCC,pp.458-460,Feb.2024.14 W.-L.Zeng et al.,“A 12V-lnput 1V-1.8V-Output 93.7%Peak Efficiency Dual-Inductor Quad-Path Hybrid DC
37、-DC Converter,”ISSCC,pp.10-12,Feb.2023.15 Y.-C.Kuo et al.,“A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6%High Efficiency and Fast Transient Response,”IEEE Symp.VLSI Circ uits,pp.1-2,June 2024.16 Z.Wang et al.,“A Ten-Level Series-Capacitor 24-to-1-V DC-DC Conv
38、erter With Fast In Situ Efficiency Tracking,Power-FET Code Roaming,and Switch Node Power Rail,”IEEE JSSC,vol.59,no.7,pp.2029-2041,July 2024.17 K.Wei et al.,“A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation,”ISS
39、CC,pp.190-192,Feb.2020.18 G.Cai et al.,“A Compact 12V-to-1V 91.8%Peak Efficiency Hybrid Resonant Switched-Capacitor Parallel Inductor(ReSC-PL)Buck Converter,”ISSCC,pp.198-200,Feb.2023.19 C.Schaef et al.,“A IMax Fully Integrated Multi-Phase Voltage Regulator with 91.5%Peak Efficiency at 1.8 to 1V,Ope
40、rating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS,”ISSCC,pp.1-3,Feb.2022.20 W.J.Lambert et al.,“Study of Thin Film Magnetic Inductors Applied to Integrated Voltage Regulators,”IEEE Tra ns.Powe r El e c tronic s,vol
41、.35,no.6,pp.6208-6220,June 2020.376 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.2979-8-3315-4101-9/25/$31.00 2025 IEEE21.2 A Dual-Input Bidirect ional 3-Level Bat t ery Charger wit h Coarse-Fine VCF Balancing and Wide VCR for Foldable Mobile
42、Applicat ions Woojin Hong,Hyebong Ko,Jinwoo So,Woonhyung Heo,Yonghwan Cho,Jeongdu Yoo,Ho-Sung Son,Youngwoo Chung,Dong-Joon Kim,Youngwoo Park,Byeonghyeon Jin,Sungkyu Cho,Minkyu Kwon,Kyungmin Park,Daewoong Cho,Jung Wook Heo,Sungwoo Lee,Sungwoo Moon,Hyoung-Seok Oh,Hwayeal Yu Samsung Electronics,Hwaseon
43、g,Korea The on-going trends for foldable mobile phones require smaller form factors and high-density battery charging with a wide-input range to reduce the battery charging time.Thus,multi-level or hybrid converters can be a solution to reduce the size of passive devices and to achieve a higher effi
44、ciency at high input voltages compared with 2-L converters 1-4.Another trend for mobile applications is wireless power sharing,which allows one mobile device to charge another device(e.g.,smart watch,phone,or earbuds).If a travel adapter(T.A)is attached to the mobile device,wireless power sharing ca
45、n allow two devices to be charged at the same time.To support this feature,the dual-input bi-directional 3-level charger is proposed as shown in Fig.21.2.1(top left).The dual-input SWs(QCHGand QWC)support wired and wireless battery charging,respectively,while the USB on-the-go(O.T.G)and wireless pow
46、er sharing are connected to each switch.Figure 21.2.1(top right)presents the proposed bi-directional charger operations.When the power sharing is activated with a load current(ITX)during battery charging,the adapter increases the charging current(ICHG)to supply power toVWCwhile simultaneously chargi
47、ng the battery.As the wireless device requires more current fromITX,ICHGincreases until it reaches anICHGregulation level.Then,theICHGregulation current dominates whileIBATdecreases.IfITXfurther increases to a heavy load,ICHGis no longer sufficient to provide bothITXandIBAT and as a result the batte
48、ry begins to supply the insufficient current toVWC.At this point,the inductor current(IIND)flows from the battery to the input,where the charger operates as the boost converter because the battery becomes a supplier.When the adapter is detached,the charger supplies power from the battery while regul
49、ating the bypass voltage(VBYP).In a prior work 5,a bidirectional 3-L charger was presented.However,it does not support a seamless mode transition between the buck and reverse boost operations.In addition,the flying capacitor voltage(VCF)balancing is important to ensure stable switching operations in
50、 multi-level converters.In 6,aVCFbalancing loop generates a difference between the VCFcharging and discharging times untilVCFis balanced.This analog feedback loop has varying bandwidth that depends on the inductor current.In 7,a state-basedVCFbalancing method was proposed.It can rapidly bringVCFto V
51、IN/2,because the charging or discharging phase is repeatedly selected by detectingVCFstates using the comparator.AfterVCFis balanced,however,the phase selection is performed only on the small ripple ofVCF,which might causeVCFfluctuationsdue to the noise or offset of the comparator.Furthermore,these
52、two works do not support bidirectional operation.Another challenge for battery chargers is to extend the voltage conversion ratio(VCR).The large charging current for the fast charging induces a large input voltage drop due to the cable resistance.In that case,the converter must operate with a higher
53、 VCR and a larger duty ratio.When the battery is fully charged,on the other hand,the charger begins reducing the charging current,resulting in the converter entering into discontinuous conduction mode(DCM)where the duty ratio rapidly decreases depending on the inductor current.However,minimum on/off
54、 times are usually required to guarantee the response times of the other circuits,which limits the range of the duty and conversion ratios.To solve the aforementioned challenges,this paper proposes the following:1)a dual-input bidirectional 3-L structure,which can support battery charging while simu
55、ltaneously supplying power to wireless power sharing devices;2)a coarse-fine VCF balancing method,which can enhance the noise immunity and the balancing speed;and 3)a frequency foldback scheme,which extends the effective duty ratio range to have a wider VCR.Figure 21.2.1(bottom left)shows the top st
56、ructure of the proposed battery charger.The control method is based on average-current mode control(ACMC),which generates the duty ratio using the inner loop with the inductor current information(VCS)and a dominant outer loop error voltage(VMIN)selected by a minimum loop selector.The controller also
57、 includes the coarse-fineVCFbalancer,the frequency foldback controller,and anIINDpolarity detector helping to achieveVCFbalancing regardless of the direction ofIIND.The waveforms during bidirectional operation are shown in Fig.21.2.1(bottom right).The DCR sensor can trackIINDin both directions with
58、the higher(lower)VCSthanVREF_CSwhenIINDflows a forward(reverse)direction.The duty ratio is determined by the ratio ofVBYPandVBATregardless of the direction ofIIND,because Q1(Q2)and Q4(Q3)switch in a complementary way 5.The only difference between buck and boost operations are theVCFcharging and disc
59、harging phases.Figure 21.2.2(top left and right)show the proposed coarse-fineVCFbalancer and its timing diagram,respectively.In the case where VCF_LOW VCF VCF_HIGH,the fineVCFbalancer generatesIVCFand produces a voltage difference betweenVERR_PandVERR_Nto generate the duty mismatch,as shown in Fig.2
60、1.2.2(top right).IfVCFdiverges from the two boundary levels,a courseVCFbalancer is activated to controlVCFin a faster way,which produces new duty signals by combining OR/AND-logic gates.When VCF is higher(lower)thanVCF_HIGH(VCF_LOW),the combinational logic leads theVCFcharging(discharging)phase to c
61、hange to the discharging(charging)phase in both the higher and lower than 50%-duty cases.It is noted that this phase changes only at the rising edge of both the LOWs and HIGHs of the duty signals to avoid glitches.The proposedVCFbalancer helps to achieve fastVCFcontrol and enhance noise immunity.Als
62、o,VCF_HIGHandVCF_LOWcan be easily generated using the ratio of R2and R3.It is also important that the charging and discharging phases are opposite depending on the direction ofIIND,as shown in Fig.21.2.1(bottom right).Thus,duty signals should be switched with each other.Figure 21.2.2(bottom left)sho
63、ws the switching waveforms at a negativeIINDof-0.3A,whereVLXandIINDfluctuate when the duty signals are not switched.Figure 21.2.3(top left)shows the proposed auto-calibrated frequency foldback controller.WhenVERR is higher(lower)thanVFOLD_H(VFOLD_L),the control current(ICONT)slows down the output fr
64、equency of the OSC(CLK).Figure 21.2.3(top right)presents the circuit diagram of the OSC with variable current(4ICLK-ICONT)in the C2 branch.The replica branch (C1 branch)restricts the minimum frequency of the CLK by the quarter to ensure loop stability.The dummy transistors(QDM1 and QDM2)can equal th
65、e net capacitances of the C1 and C2 nodes to increase the frequency clamping accuracy.The phase splitter generates 180 phase-shifted clock signals(CLK0 and CLK180).VTRI generators provide the triangular signals(VTRI_0 and VTRI_180)that are synchronized with either CLK0 or CLK180 depending on the val
66、ue ofVERR.Figure 21.2.3(bottom right)shows the detailed waveforms.WhenVERR VFOLD_H synchronizes the peak point of the triangular waveforms with different CLK signals than with the on-time foldback case,resulting in a larger effective duty ratio.The SELCLK signal sends either CLK0 or CLK180 to eachVT
67、RI generator depending on the selected foldback mode.Figure 21.2.4(top left and right)present theVTRI generator with two current-controlled OTAs(CCOTA)and the auto-calibration logic.Figure 21.2.4(top right)shows its operational waveforms in the case of on-time foldback.IfVTRI reaches VTRI_L,the uppe
68、r CCOTA triggers COMPL by acting like a comparator.A low-triggered UD signal then raisesVTRI toVTRI_H,so that the lower CCOTA generates its output current(IOTA_H)to clampVTRI.At this point,the different size ratio of the input transistors can makeIOTA_H equal toITRI when its input voltages are ident
69、ical,which meansVTRI is clamped toVTRI_H.It is also important that the CCOTA has to operate with a fast response because it is used as both a comparator and a voltage clamper.Thus,the low-node impedances of the CCOTA provide a fast response time with only one dominant pole(p1)at the CTRI node.In add
70、ition,VTRI0 andVTRI180 are generated by two differentVTRI generators having different mismatch and variations.Therefore,the auto-calibration logic adjustsITRI to match the slopes ofVTRI_0 andVTRI_180 by using the counter,as shown in Fig.21.2.4(bottom right).Before starting the slope-calibration,theV
71、ERR-based OSC is disabled andITRI is set to the highest value.The COMPH signal is used to get information on the slopes ofVTRI and it counts up until the UP signal does not occur when decreasingITRI.Figure 21.2.4(bottom left)shows the measurement waveforms after the slope-calibration.VLX shows a reg
72、ular waveform andVCF can be well balanced compared to when the calibration is off.The proposed battery charger has been fabricated using a 0.13m BCD process(Fig.21.2.7).Figure 21.2.5(top left)shows the measured waveforms during both the battery charging and power sharing.AsITX is loaded to 0.6A,IBAT
73、 decreases to about 0.7A becauseICHG cannot increase with a 1.2A regulation setting.AfterITX further increases to 1.4A,the battery begins discharging to supply more power toITX,where the charger seamlessly transitions to the reverse boost operation.If the T.A is detached,the battery discharging curr
74、ent increases to 2A andVBYP is regulated to 5V.Figure 21.2.5(top right)shows the measured charging efficiency.Figure 21.2.5(bottom left)presents the on-time foldback operation.With a light charging current in DCM operation,the charger enters on-time foldback to provide a lower duty ratio,which slows
75、 downfSW to almost 250kHz atVCHG=12V.The off-time foldback can be measured during the line transient at a heavy load,as shown in Fig.21.2.5(bottom right).AtVCHG=4.75V,this low-dropout voltage leads to a higher duty ratio with anfSW of almost 250kHz.The comparison table of the state-of-the-art hybrid
76、 battery chargers is shown in Fig.21.2.6.Figure 21.2.1:Top st ruct ure of t he proposed dual-input bi-direct ional 3-L bat t ery charger and it s operat ing waveforms.Figure 21.2.2:Circuit implement at ion of t he proposed coarse-fine VCF balancer and it s t iming diagram.Figure 21.2.3:Circuit diagr
77、am and operat ional waveforms of t he proposed frequency foldback operat ion.Figure 21.2.4:Circuit implement at ion and operat ional waveforms of t he proposed aut o-calibrat ed VTRI generat or.Figure 21.2.5:Measured waveforms of t he proposed dual-input bidirect ional 3-L bat t ery charger.Figure 2
78、1.2.6:Comparison t able wit h t he st at e-of-t he-art hybrid chargers.ISSCC 2025/February 18,2025/1:55 PM377 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 21.2.7:Chip micr
79、ograph.Re f e re nc e s:1 C.Hardy,Y.Ramadass,K.Scoones and H.-P.Le,“A Flying-Inductor Hybrid DC-DC Converter for 1-Cell and 2-Cell Smart-Cable Battery Chargers,”IEEE Journal of Solid-State Circuits,vol.54,no.12,pp.3292-3305,Dec.2019.2 A.Mishra,W.Zhu,B.Wicht and V.D.Smedt,“An All-1.8-V-Switch Hybrid
80、Buck-Boost Converter for Li-battery-Operated PMICs Achieving 95.63%Peak Efficiency Using a 288-m DCR Inductor,”IEEE Transactions on power Electronics,vol.38,no.3,pp.3444-3454,March 2023.3 Y.Karasawa,T.Fukuoka and K.Miyaji,“A 92.8%Efficiency Adaptive-On/Off-Time Control 3-Level Buck Converter for Wid
81、e Conversion Ratio with Shared Charge Pump Intermediate Voltage Regulator,”2018 IEEE Symposium on VLSI Circuits,2018.4 J.-I.Seo,B.-M.Lim,W.-J.Choi,Y.-S.Noh and S.-G.Lee,“A 95.1%Efficiency Hybrid Hysteretic Reconfigurable 3-Level Buck Converter With Improved Load Transient Response,”IEEE Transactions
82、 on Power Electronics,vol.37,no.12,pp.14916-14925,Dec.2022.5 Y.-Y.Lin,Y.-R.Huang,C.-J.Chen,Y.-C.Lin and T.-W.Huang,“A Bidirectional Three-Level Converter Control With Shared Control Circuit and Single-Point Sensing for Flying Capacitor Balance,”IEEE Transactions on Power Electronics,vol.39,no.1,pp.1
83、015-1027,Jan.2024.6 X.Liu,C.Huang and P.K.T.Mok,“A High-Frequency Three-Level Buck Converter With Real-Time Calibration and Wide Output Range for Fast-DVS,”IEEE Journal of Solid-State Circuits,vol.53,no.2,pp.582-595,Feb.2018.7 S.-J.Lee et al.,“A 95.3%5V-to-32V Wide Range 3-Level Current Mode Boost C
84、onverter with Fully State-based Phase Selection Achieving Simultaneous High-Speed VCF Balancing and Smooth Transition,”2023 IEEE International Solid-State Circuits Conference(ISSCC),2023.8 C.Hardy and H.-P.Le,“A 21W 94.8%-Efficient Reconfigurable Single-Inductor Multi-Stage Hybrid DC-DC Converter,”2
85、023 IEEE International Solid-State Circuits Conference(ISSCC),2023.9 S.Yeo,U.Hyeon,M.Kim,J.Kim and K.Cho,“A 19.8W/29.6W Hybrid Step-Up/Down DC-DC Converter with 97.2%Peak Efficiency for 1-Cell/2-Cell Battery Charger Applications,”2023 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology an
86、d Circuits),2023.378 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.3979-8-3315-4101-9/25/$31.00 2025 IEEE21.3 A Segment ed-Int erlacing Mult i-Phase Hybrid Convert er wit h Inherent ly Aut o-Balanced ILs and Boost ed IL Slew Rat e During Load T
87、ransient s Jiacheng Yang1,Rui P.Martins1,2,Mo Huang1 1University of Macau,Macau,China 2Instituto Superior Tecnico/University of Lisboa,Lisbon,Portugal In datacenters,direct conversion from a 12V input voltage VIN intermediate bus to point-of-load(PoL)is a common practice for powering computing chips
88、 1,2.The increasing computing power necessitates multiple-phase(MP)converters.To reduce power loss,it is crucial to minimize the guard band(between VMIN and VLOAD)that accommodates the output voltage undershoot during load transients.This can be achieved by instantaneously increasing the inductor cu
89、rrent(IL)slew rate(SR)by energizing all inductors simultaneously in a MP converter 3,4.Furthermore,balancing the ILs of a MP converter is pivotal for mitigating thermal issues and ensuring system reliability.However,the conventional MP buck,along with MP hybrid converters like MPCCC 5 and IL-MSD 6,e
90、xhibit significant IL imbalance due to duty cycle D mismatches among phases.Consequently,these converters require IL sensing in each phase and close-loop D adjustments,increasing design complexity and power consumption.While 7 addresses IL mismatch,it has unequal DC values of ILs,leading to uneven h
91、eat dissipation in the inductors.In Fig.21.3.1,the 3-path 4-state 3P4S converter 8 features inherent IL balancing.It employs 3 inductors,a switched-capacitor SC circuit that consists of 6 power switches M1-M6,and 2 flying capacitors CF1 and CF2.The SC has 3 output ports P1-3,that are each connected
92、to one inductors switching node.To prevent M5-6 overstressing,the energizing periods of the 3 inductors must not overlap.This limits the maximum IL SR to(VIN/33VO)/L during step-up load transients,where VO is the output voltage,and L is the inductance.Additionally,the maximum VCR from the non-overla
93、pping operation is 1/9,resulting in a relatively low VO when VIN=12V,potentially increasing the output current and thus the power loss in the power delivery network PDN.To address these issues while preserving IL auto balancing,we propose a segmented-interlacing(SI)converter based on 3P4S(Fig.21.3.1
94、).We first segment the SC into 3 parallel-connected sub-SCs(SCA-C),each using the same circuit as the original SC,but with the size of the power switches and the CFs scaled to 1/3.Subsequently,we interlace the P1-3 of each sub-SC.We remove the M6 of each sub-SC due to the interlacing.This SI convert
95、er inherits most of the benefits of the original 3P4S,such as IL and VCF auto balance.Meanwhile,Fig.21.3.1 shows their calculated V-A metrics,revealing that they have almost equal efficiency and density when VCR 1/9.Moreover,the overlapping allows simultaneous inductor charging by turning on M1 of e
96、ach sub-SC(as“ALL ON”mode).This leads to a significantly higher SR of(VIN3VO)/L,greatly reducing VO undershoot.Figure 21.3.1 shows that the SR ratio of SI to 3P4S is 5 when VCR 0.05.Furthermore,the segmentation enables fSW downsize control,enhancing light-load efficiency 9.Figure 21.3.2 illustrates
97、the issue of IL imbalance in a conventional 2-phase buck converter due to mismatch on D(D1D2=D),where IL=IL1IL2(eq.1)is inversely proportional to series resistance RS.When RS is small,IL increases dramatically with D,due to the difference in input charges QON1 and QON2(IL=QON/TON,TON is the period o
98、f Buck receiving QON).In contrast,by designing an inherent-balance topology that ensures equal QONs even in the presence of D,the resultant IL(eq.2)becomes independent of RS and inversely proportional to load resistance(RL,around two orders of magnitude smaller than RS).This greatly reduces IL.In hy
99、brid converters,CF charge balance facilitates achieving equal QONs.One example is in the sub-SC of SI.As shown in Fig.21.3.2,the CFs output charge to P1-3(Q1-3)remain equal(with switching-node parasitic capacitances ignored),while the interlacing equalizes the total QON(QON)of each inductor,explaine
100、d as follows.Each sub-SC can work in four states:in state-n(n=1-3),the CFs output charge to Pn,while in state-4,M4 and/or M5 turn on,without CF charge output to Pn.When VCR 1/9,D overlap occurs,eliminating state-4 but introducing state-13(combination of state-1 and 3).The ILs remain balanced as in V
101、CR 1/9(t op),schemat ic of SI convert er(bot t om).Figure 21.3.4:Measured st eady-st at e and st art-up waveforms(t op),measured efficiency(bot t om).Figure 21.3.5:Measured load t ransient waveforms of“normal cont rol”(t op)and“All ON”cont rol(bot t om).Figure 21.3.6:Performance summary and comparis
102、on wit h st at e-of-t he-art works.ISSCC 2025/February 18,2025/2:20 PM379 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 21.3.7:Chip micrographs(left),PCB phot o(t op right)
103、and passive component s of power t rain(bot t om right).Re f e re nc e s:1 Y.-C.Kuo et al.,“A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6%High Efficiency and Fast Transient Response,”IEEE VLSI,pp.1-2,June 2024.2 H.-J.Choi et al.,“A 92.7%Peak Efficiency 12V-to
104、-60V Input to 1.2V Output Hybrid DC-DC Converter Based on a Series-Parallel-Connected Switched Capacitor,”ISSCC,pp.156-158,2024.3 T.Hu et al.,“A 12-to-1 Flying Capacitor Cross-Connected Buck Converter With Inserted D 0.5 Control for Fast Transient Response,”IEEE JSSC,vol.58,no.11,pp.3207-3218,Nov.20
105、23.4 J.Yuan et al.,“A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9 s 1%Settling Time for a 3A/20ns Load Transient,”ISSCC,pp.1-3,Feb.2022.5 J.Yang et al.,“A 12V-to-PoL CCC-Based Easy-Scalable Multiple-Phase Hybrid Converter with Auto VCF Balancing and Inactive CF Charging,”IEEE CICC,pp.1
106、-2,April 2024.6 X.Zhang et al.,“A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DCDC Converter With Inherent Current Equalization Characteristics,”IEEE JSSC,vol.59,no.9,pp.2895-2906,Sept.2024.7 M.Gong et.al.,“A 90.4%Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With
107、 Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer,”IEEE JSSC,vol.58,no.4,pp.1002-1014,April 2023.8 Y.Huang et al.,“A 90.7%4-W 3P4S Hybrid Switching Converter Using Adaptive VCF Rebalancing Technique and Switching Node Dual-Edge tdead Modulation for Extreme 48V/1V Direct DC
108、-DC Conversion,”IEEE VLSI,pp.178-179,June 2022.9 X.Yang et al.,“An 8A 998A/inch3 90.2%Peak Efficiency 48V-to-1V DC-DC Converter Adopting On-Chip Switch and GaN Hybrid Power Conversion,”ISSCC,pp.466-468,Feb.2021.10 D.Yan et al.,“Direct 48-/1-V GaN-Based DCDC Power Converter With Double Step-Down Arch
109、itecture and MasterSlave AO2T Control,”IEEE JSSC,vol.55,no.4,pp.988-998,April 2020.11 H.Han et al.,“A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2 Slew Rate All-Hysteretic Mode,”IEEE VLSI,pp.182-183,June 2022.380 2025 IEEE Internat
110、ional Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.4979-8-3315-4101-9/25/$31.00 2025 IEEE21.4 A 97.4%-Peak-Efficiency Always-Half-Induct or-Current Hybrid Bidirect ional Convert er wit h Adapt ive Target Current Tracking for USB-t o-2-Cell Bidirect ional Power Transf
111、er Yunho Lee,Hyunjun Park,Minsu Kim,Woojoong Jung,Hongseok Kim,Hyung-Min Lee Korea University,Seoul,Korea In modern portable devices,bidirectional power transfer has been increasingly critical,particularly in those using a 2-cell battery such as tablets,portable gaming consoles,and power banks.In fo
112、rward mode(FM),these devices are predominantly charged via a 5V USB travel adapter(VUSB),ensuring compatibility with widely available power supplies.In on-the-go(OTG)mode(OM),these 2-cell devices act as a 5V source,transferring power to the other portable device when needed.Conventional bidirectiona
113、l converters 1-2 utilize the boost topology in FM and the buck topology in OM(top left of Fig.21.4.1).However,these approaches result in a large current flowing through the inductor(L),leading to significant DC resistance(DCR)losses and reduced efficiency in both operating modes.This issue is furthe
114、r compounded by the trend toward extremely compact portable devices,where size constraints force the use of a smaller L with inherently higher DCR.Furthermore,a 2-cell battery voltage(VBAT=6-8.4V)necessitates the use of high-voltage(HV)transistors,which substantially increases the costs.In prior DC-
115、DC converters(bottom left of Fig.21.4.1),the bidirectional three-level converter has validated the feasibility of bidirectional operation 3.This approach can reduce the voltage stress of power switches even within the VBAT range,thereby mitigating the need for HV transistors.However,this converter s
116、till suffers from high inductor current(IL)similar to that of conventional topologies.Another bidirectional converter is the symmetric hybrid buck-boost converter that operates with a wide voltage conversion ratio(M)in both directions 4.When applied to a voltage of VBAT,this converter can reduce the
117、 maximum voltage stress(MVS)of the power switches to 1/3VBAT.However,the efficiency of this topology is constrained by higher IL than the output current(IBAT or IOTG)in both bidirectional operations.Similarly,the bilaterally-symmetrical hybrid buck-boost converter is also potentially capable of bidi
118、rectional operation 5.This converter can reduce IL in both buck and boost operations,but the battery-side power switches are still subjected to the full range of VBAT(=6-8.4V),necessitating the use of HV transistors.To overcome these limitations,this paper proposes an always-half-IL(AHI)bidirectiona
119、l converter that not only reduces IL in both directions to improve efficiency but also eliminates the need for HV transistors,which is crucial for cost reduction as shown in Fig.21.4.1(top right).The operation of the proposed converter is illustrated in Fig.21.4.1(bottom right).When charging the 2-c
120、ell device from VUSB,the converter operates in boost mode.During the 1 phase,the switches S2,S4,and S5 are turned on,delivering power to the battery with an LC dual-path that utilizes L and a flying capacitor of the battery side(CF2).The switching node voltages of the USB side(VX1)and battery side(V
121、X2)become 2VUSB and VBAT in 1,respectively.During the 2 phase,the switches S1,S3,and S6 are turned on,and power is transferred to the battery through L with VX1=VUSB and VX2=2VBATVUSB.In boost mode,the MVS of the switches is VUSB while the power is delivered to the output continuously in both 1 and
122、2.Additionally,thanks to the dual-path technique,IL becomes MIBAT/2,which is half of the conventional boost converter IL(IL,Conv),where IBAT is the battery charging current.On the other hand,when the 2-cell device operates as a 5V source(VOTG),the converter operates in buck mode where operation is r
123、eversed compared to boost mode.During 1,switches S1,S3,and S6 are turned on,delivering power from the battery through the dual-path using L and a flying capacitor(CF1)connected to VOTG with VX1=VOTG and VX2=2VBAT-VOTG.During 2,switches S2,S4,and S5 are turned on,and power is delivered to the other d
124、evice utilizing L and CF2 with VX1=2VOTG and VX2=VBAT.In buck mode,the power is delivered to VOTG with always-dual-path,reducing IL to the half of conventional buck converter IL(i.e.,IL=0.5IL,Conv).Consequently,the proposed converter offers two key advantages:1)The MVS of switches is VUSB in boost m
125、ode and VOTG in buck mode,enabling the design without requiring HV transistors;and 2)IL is halved in both modes compared to prior topologies,reducing DCR losses and improving efficiency in bidirectional operation.Figure 21.4.2(top)shows the normalized IL(NIL)comparison of the proposed converter with
126、 prior works in both modes.The proposed converter achieves always-reduced IL relative to the output current(IBAT or IOTG)which is the half of IL,Conv,demonstrating superior IL reduction compared to other works within the target range in both modes.Figure 21.4.2(bottom)presents the theoretically calc
127、ulated conduction loss(PCond)normalized to conventional PCond(PCond,Conv)with the same RON for all switches.When using a compact inductor with a high DCR of 6RON,the proposed converter achieves a 39-to-57%reduction in conduction loss for both modes,demonstrating the lowest conduction loss across mos
128、t of the target VBAT range.Moreover,considering that the works in 5-6 need to use HV transistors with higher RON,the normalized PCond difference between the prior and proposed converters may become larger when actually implemented in the VBAT range.Figure 21.4.3 shows the top block diagram of the pr
129、oposed converter including the controller and power stage.In boost mode,average current mode control(ACMC)is employed to regulate IBAT during constant current charging.The ACMC loop regulates IBAT by controlling the average inductor current(IL,Avg).However,IL,Avg of the hybrid converter,which typica
130、lly reduces IL,differs from IBAT.Thus,IL,Avg should be adaptively controlled to ensure a constant IBAT under varying operating ranges.To address this,this paper proposes the NIL-based adaptive IBAT controller(NB-AIC)that utilizes the ratio between IL and IBAT(NIL=IL/IBAT).Figure 21.4.3(bottom left)d
131、epicts the conceptual operation of IBAT control using the NB-AIC.When VREF represents the target IBAT,NB-AIC generates VCON as the product of NIL and VREF.The sample and hold(S/H)senses IL at the point where it is equal to IL,avg(tS/H)and outputs the IL sense voltage(VS/H).The ACMC loop adjusts IL,a
132、vg to ensure that IBAT tracks the target IBAT by utilizing the error amplifier(CA)in the current regulation loop with negative feedback,which takes VS/H and VCON as inputs.Thus,the ACMC loop with NB-AIC effectively compensates for current deviations,ensuring that IBAT accurately tracks the target IB
133、AT even under varying VBAT.Figure 21.4.3(top right)presents the conceptual block diagram of the NB-AIC.The NB-AIC first converts D into the reciprocal of NIL(1/NIL)using the Duty-to-1/NIL converter,where D is duty ratio.This value is subsequently converted back to its reciprocal by the reciprocal co
134、nverter(RECI-CV)and then multiplied by VREF to output VCON.The Duty-to-1/NIL converter is composed of an average generator and an analog subtractor.The RECI-CV converts 1/NIL into its reciprocal timing(TRECI)using a voltage-to-time converter.TRECI is processed by the time-to-1/volt converter to prod
135、uce the reciprocal voltage using an S/H.Finally,the NB-AIC generates VCON as the product of NIL and VREF based on the D.The proposed converter was fabricated in a 0.18m process using only low-voltage(LV)transistors(5V).Figure 21.4.4(top left and right)shows the measured steady state waveforms in boo
136、st and buck modes,respectively.In boost mode,the converter regulates IBAT for battery charging with IL,Avg=0.74A when VUSB=5V,VBAT=7.2V,and IBAT=1A.Under buck mode,the converter operates as a votlage regulator for OTG with IL,Avg=0.5A when VOTG=5V,VBAT=7.2V,and IOTG=1A.The measured waveforms also ve
137、rify that IL is reduced when compared to the output current(IBAT or IOTG)in both modes.Figure 21.4.4(bottom left)shows the measured step-up response of VBAT(7.2V to 7.6V)with target IBAT of 1A.As discussed,even with variations in VBAT,the NB-AIC effectively controls IL,Avg via VCON,ensuring that IBA
138、T adaptively tracks the target IBAT.Figure 21.4.4(bottom right)shows the measured load transient response in buck mode with VBAT=7.2V and VOTG=5V.The waveform shows that the undershoot and overshoot are 110mV and 100mV during the load step with IOTG from 0A to 1A and from 1A to 0A within a 400ns edg
139、e time,respectively.Figure 21.4.5 presents the measured efficiency under various output currents(IBAT or IOTG)for both modes.In boost mode with VUSB=5V and VBAT=6.8V,the converter achieves peak efficiencies of 97.4%using a large-volume inductor with an 11.5m DCR and 96%with a compact-volume inductor
140、 with a 295m DCR,as shown in Fig.21.4.5(top).In buck mode with VBAT=6.8V and VOTG=5V,the peak efficiencies were 97%with an 11.5m DCR inductor and 96.2%with a 295m DCR inductor,as shown in Fig.21.4.5(bottom).Thanks to the reduced IL in both modes,the converter achieves over 96%peak efficiencies in bo
141、th modes even when using a 6mm3 small-volume L.Figure 21.4.6 shows the performance comparison of the proposed converter with state-of-the-art works.The proposed converter outperforms the other works in its ability to reduce IL in both directions,ensuring the always-half-reduced IL compared to the ou
142、tput current(IBAT or IOTG)within the target range.This effective IL reduction leads to the highest peak efficiency among other works.Figure 21.4.7 shows a chip micrograph of the proposed converter.Ac k nowl e dge me nt:This work was supported by the Ministry of Trade,Industry&Energy(RS-2022-00154983
143、),Korea.Chip fabrication was supported by LX Semicon,Seoul,Korea.Figure 21.4.1:Convent ional bidirect ional syst ems(t op-left)and st at e-of-t he-art DC-DC convert ers(bot t om-left).The proposed AHI-bidirect ional convert er wit h t arget volt age range(t op-right)and operat ion principle(bot t om
144、-right).Figure 21.4.2:Comparisons of t he normalized induct or current and conduct ion loss bet ween t he proposed convert er and prior works in boost mode(left)and buck mode(right).Figure 21.4.3:Top block diagram of t he proposed AHI convert er(t op-left)wit h t he proposed normalized-IL based adap
145、t ive IBAT cont roller(right)and operat ion principle(bot t om-left).Figure 21.4.4:Measured waveforms of st eady st at e and VBAT st ep-up response in boost mode(left).Measured waveforms of st eady st at e and load t ransient response in buck mode(right).Figure 21.4.5:Measured power efficiency of t
146、he proposed convert er wit h DCR=11.5m and DCR=295m in boost mode(t op)and buck mode(bot t om).Figure 21.4.6:Performance summary and comparison wit h t he st at e-of-t he-art designs.ISSCC 2025/February 18,2025/2:45 PM381 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits Con
147、ferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 21.4.7:Chip micrograph.Re f e re nc e s:1 2-Cell,2-A Boost-Mode Battery Charger With Power Path,USB On-The-Go Boost(OTG)For USB Input,BQ25883 Datasheet,Texas Instruments Inc.2 2-Cell Li-Ion or Li-Polymer
148、Switching Charger Compatible with 5V Input and Integrated,Bidirectional Charge/Discharge with Cell Balance,MP2639A,Monolithic Power Systems Inc.3 Y.-Y.Lin et al.,“A Bidirectional Three-Level Converter Control with Shared Control Circuit and Single-Point Sensing for Flying Capacitor Balance,”IEEE Tra
149、 ns.Powe r El e c tron.,vol.39,no.1,pp.1015-1027,Jan.2024.4 C.Lin et al.,“A Wide 0.1-to-10 Conversion-Ratio Symmetric Hybrid Buck-Boost Converter for USB PD Bidirectional Conversion,”ISSCC,pp.194-196,Feb.2023.5 D.-H.Kim et al.,“A 96.9%-Peak-Efficiency Bilaterally-Symmetrical Hybrid Buck-Boost Conver
150、ter Featuring Seamless Single-Mode Operation,Always-Reduced Inductor Current,and the Use of All CMOS Switches,”ISSCC,pp.146-148,Feb.2024.6 S.-U Shin et al.,“A 95.2%Efficiency Dual-Path DC-DC Step-up Converter with Continuous Output Current Delivery and Low Voltage Ripple,”ISSCC,pp.430-432,Feb.2018.7
151、 M.Kim et al.,“A 96.5%Peak Efficiency Duty-Independent DC-DC Step-Up Converter with Low Input-Level Voltage Stress and Mode-Adaptive Inductor Current Reduction,”ISSCC,pp.160-162,Feb.2024.8 Y.Huh et al.,“A Hybrid Structure Dual-Path Step-Down Converter with 96.2%Peak Efficiency Using 250-m Large-DCR
152、Inductor,”IEEE JSSC,vol.54,no.4,pp.959-967,Apr.2019.382 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.5979-8-3315-4101-9/25/$31.00 2025 IEEE21.5 A Fully Int egrat ed Mult i-Phase Volt age Regulat or wit h Enhanced Light-Load-Efficiency Peak of
153、86%,Feat uring an Aut onomous Mode Transit ion from Hard-Swit ching t o Soft-Swit ching t o Discont inuous Conduct ion Mode in 3nm FinFET CMOS Kishan Joshi1,Avinash Shreepathi Bhat2,Christopher Schaef2,Keng Chen3,Edward Lee2,Yura Kocharyan1,Ajay Janardanan2,Dinesh Ganta2,Huanhuan Zhang3,Maximilian G
154、eppert2,Prescott Mclaughlin1,Arvind Raghavan1,Sivaraman Masilamani3,Syed Askari2,Kelly Livingston2 1Intel,Santa Clara,CA 2Intel,Hillsboro,OR 3Intel,Hudson,MA Modern-day computing systems demand a lot of power,especially driven by AI workloads.With an explosion in data size,there is a corresponding i
155、ncrease in the current consumption of SoCs,which can reach hundreds of Amperes 1-2.This creates some unique challenges for power delivery systems.Fully integrated voltage regulators(FIVRs)provide the unique benefit of highly localized power delivery,which can help mitigate supply droop events and ad
156、dress current surges 3-7.For data center applications,average energy consumption is affected by both peak power-hungry modes and idle low-power data retention states.When these power delivery systems are scaled to support larger workloads,the corresponding idle power consumption scales accordingly.F
157、rom this,we can surmise that while peak power efficiency is an important metric for FIVRs,in recent days,FIVRs or any power delivery system must maintain high efficiency even at idle load conditions without impacting the overall transient response or the droop on the output.Prior work toward achievi
158、ng this includes forcing regulator operation in soft-switching and Discontinuous Conduction Modes(DCM);however,this has the disadvantage of higher ripple and lower efficiency in high current draw scenarios 3,7.In this paper,a FIVR that has an autonomous mode transition from hard-switching to soft-sw
159、itching to DCM is presented.The FIVR uses a novel high-precision,high-speed comparator that observes the low-side power switch during every switching cycle to detect negative inductor current and enable soft switching of the high-side power switch.An auxiliary detection circuit monitors the load cur
160、rent and changes the mode of operation to DCM when the load current is very low.One of the by-products of the transition between Continuous Conduction Mode(CCM)and DCM is the impact on the output in terms of overshoot and undershoot.Any undershoot on the FIVR output can directly impact the minimum s
161、upply voltage specification of the SoCs being powered and needs to be addressed adequately.This paper also discusses DCM droop improvement techniques that use the autonomous mode transition into DCM based on load current(hitherto known as auto-DCM)and the compensation network to improve the DCM to C
162、CM transition.The system-level diagram of the proposed FIVR is presented in Fig.21.5.1.The autonomous mode transition is achieved through the high-speed,high-precision comparator shown in the figure,which achieves accurate Zero Current Detection(ZCD).This determines the levels at which the FIVR tran
163、sitions from CCM Hard-Switching(HS)to CCM Soft-Switching(SS)to DCM.The comparator observes the switching node Vx when the NMOS is ON.When(Vx VSS)becomes positive,the comparator output goes high.SS_hold goes high and stays high as long as a positive pulse is detected within the comparator window.SS_h
164、old being high for a predetermined number of cycles makes SS_active high,which is used to adjust the on-time of the PWM pulses going into the power train and achieve soft-switching.When the load current is extremely low,the valley of the inductor current can go quite negative.A similar comparator fo
165、r DCM has been configured to monitor the voltage across the NMOS to infer this negative valley and change the operation of the FIVR to DCM.In auto-DCM,DCM_hold needs to stay high(low)for a longer predetermined period for entry(exit)to happen.DCM_hold is tracked,and if DCM_hold stays continuously hig
166、h,a signal called DCM_active is set to high,indicating DCM operation.This longer tracking period is necessary to add hysteresis to the mode transition so that the FIVR does not keep switching modes during a slow-changing load scenario.The hysteresis in the comparator and the delay added towards gene
167、rating the DCM_active and DCM_hold signals are necessary to ensure a stable auto-mode transition.The main issue with the CCM-DCM-CCM transition is the impact of overshoot/undershoot on the output.If the load current is sufficiently low in DCM,the FIVR can operate in a pulse-skipping mode when the co
168、mpensator output is below a set threshold.This helps to improve low load efficiency but it can also impact droop.To address this,the DCM_active signal is used to change the compensator setting to a higher bandwidth setting through the configurable resistor R1-3 and capacitor C1-3 in the compensator.
169、This ensures that when the auto-DCM circuit detects a transition back to CCM(DCM_active goes low),the FIVR makes a fast transition to CCM,and the compensator is able to catch up quickly,being in a higher bandwidth setting.Once the FIVR recovers from the droop,the bandwidth is changed back to the ori
170、ginal CCM compensator RC setting.In addition,the threshold voltage for DCM pulse-skipping is changed adaptively with the output voltage so that the compensator voltage during DCM pulse-skipping can track the output voltage.This helps to ensure that the overshoot seen on entry from CCM into DCM is mi
171、tigated and the undershoot on DCM exit is reduced.Figure 21.5.2 presents the implementation of the soft switching delay circuit to control the upper PMOS transistor in the power train.Figure 21.5.3 presents the proposed FIVR efficiency measurement.The DCM operation can greatly boost the light load e
172、fficiency to around 82%.However,without the soft switching mode,when the circuit exits the DCM,the efficiency will drop to 75%as the load is not large enough for CCM.However,with the help of soft switching,the efficiency around this load range can be greatly improved.The best efficiency during soft
173、switching is very close to the peak efficiency of the CCM regulation.Figure 21.5.4 presents the load transient performance,with Fig.21.5.4(a)showing a zoomed-in view of the auto transition from DCM to CCM with different compensation recipes.With a fine-tuned compensation configuration,the output dro
174、op caused by the load surge can be improved by 20mV.In Fig.21.5.4(b),a complete mode transition is recorded.When the load drops,the circuit enters soft switching mode,followed by DCM regulation.From the PWM waveform,it can be clearly noticed that pulse skipping occurs during DCM regulation.When the
175、load surges fast enough,DCM and soft switching are reset simultaneously to provide full driving capability as fast as possible to improve the transient performance.The Bode plots of the proposed FIVR are presented in Fig.21.5.5.Due to the circuit characteristics,the DCM bandwidth is much smaller tha
176、n the CCM bandwidth,so there are two sets of compensation settings for the circuit to achieve better transient performance,as described above.The proposed circuit is fabricated using Intel 3nm FinFET technology.The comparison table is shown in Fig.21.5.6 between the proposed FIVR and other prior art
177、s.The die-photo and experiment settings are shown in Fig.21.5.7.Figure 21.5.1:The syst em-level diagram of t he proposed FIVR wit h aut o ZCD and soft swit ching feat ures.Figure 21.5.2:DCM and soft swit ching cont rol for t he upper PMOS t ransist or.Figure 21.5.3:Measured efficiency of t he propos
178、ed FIVR vs.load current.Figure 21.5.4:Transient performance of t he proposed FIVR during t ransit ion(a-t op)from DCM t o CCM wit h different compensat ion adjust ment s,and(b-bot t om)from CCM t o DCM and t hen fast t ransit ion t o CCM.Figure 21.5.5:Bode plot of DCM(left)and CCM(right)wit h differ
179、ent compensat ion,t est ed at different t emperat ures.Figure 21.5.6:Comparison t able bet ween t he proposed regulat or and prior designs.ISSCC 2025/February 18,2025/3:00 PM383 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND RE
180、FERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 21.5.7:Experiment al set up and die micrograph.Re f e re nc e s:1 K.Chen,et al.,“Buck Circuit Design with Pseudo-Constant Frequency and Constant On-time for High Current Point-of-Load Regulation,”IEEE Trans.Circuits Syst.I,Reg.Papers vol.68,no.3,pp
181、.4062-4075,2021.2 W.Gomes et al.,“Ponte Vecchio:A Multi-Tile 3D Stacked Processor for Exascale Computing”,ISSCC,pp.42-43,Feb.2022.3 C.Schaef et al.,“A Fully Integrated Voltage Regulator in 14nm CMOS with Package Embedded Air-Core Inductor Featuring Self-Trimmed,Digitally Controlled Variable On-Time
182、Discontinuous Conduction Mode Operation”,ISSCC,pp.154-155,Feb.2019.4 H.K.Krishnamurthy et al.,“A Digitally Controlled Fully Integrated Voltage Regulator with On-Die Solenoid Inductor with Planar Magnetic Core in 14nm Tri-Gate CMOS”,ISSCC,pp.336-337,Feb.2017.5 N.Sturcken et al.,“A 2.5D Integrated Vol
183、tage Regulator Using Coupled MagneticCore Inductors on Silicon Interposer Delivering 10.8A/mm2”,ISSCC,pp.400-402,Feb.2012.6 K.Bharath et al.,“Integrated Voltage Regulator Efficiency Improvement using Coaxial Magnetic Composite Core Inductors”,ECTC,pp.1286-1292,June 1 to July 4,2021.7 C.Schaef et al.
184、,“A 12A Imax,Fully Integrated Multi-Phase Voltage Regulator with 91.5%Peak Efficiency at 1.8 to 1V,Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS”,ISSCC,pp.306-307,Feb.2022.384 2025 IEEE International Solid-S
185、tate Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.6979-8-3315-4101-9/25/$31.00 2025 IEEE21.6 A 2A Fully Analog Dist ribut ion LDO wit h Noise Immunit y for an SoC Jeong-Hun Kim1,Young-Jun Jeon1,Won-Gyu Kim1,Jaeseung Lee2,Jun-Hyeok Yang2,Sung-Wan Hong1 1Sogang University,Seoul,Ko
186、rea 2Samsung Electronics,Hwaseong,Korea As system-on-chip(SoC)technologies advance,devices have suffered from significant thermal dissipation.Because long-term exposure to high temperature degrades SoC performance,it is necessary to manage the temperature in the devices.Consequently,low-dropout regu
187、lators(LDO)that supply the load current(ILOAD)by distributing the ILOAD through multiple power transistors have been introduced 1-5.In these distribution LDOs(DISLDOs),it is critical to balance the currents supplied by each power transistor(MP)for effective thermal distribution.There are two approac
188、hes to implementing the DISLDO:1)digital DISLDOs;and 2)analog DISLDOs.In the SoC,the noise becomes severe as the SoC advances.Since the MPs of the DISLDO need to be located far from each other and transfer signals to each other,digital DISLDOs are highly suitable for SoCs because digital DISLDOs del
189、iver digital signals to each other,which are more insensitive to noise than analog signals 1-5,as shown in Fig.21.6.1(top).However,digital LDOs usually consume a larger static current,which results in a lower current efficiency,and a larger output voltage ripple.Furthermore,in digital DISLDOs,ILOAD
190、might not be evenly distributed if the parasitic resistances of the power lane are different.This is because the MPs in digital DISLDOs are considered as resistors since the MPs operate in the triode region,and the output voltage is determined by the voltage division.On the other hand,analog DISLDOs
191、 can evenly distribute ILOAD regardless of the parasitic resistances of the power lane because the MPs in the analog LDO normally operate in the saturation region,which considers the transistors as current sources.However,as mentioned previously,the noise from the SoC interferes with the analog sign
192、als transferred between MPs.Therefore,the output of analog DISLDOs becomes considerably noisy.For this reason,analog DISLDOs have not been practical for use in SoCs.To address these issues,we propose a fully analog SoC-noise-immune(SNI)DISLDO,as shown in Fig.21.6.1(bottom).The SNI DISLDO comprises a
193、 main LDO and auxiliary LDOs,and the number of auxiliary LDOs is flexible;in this design,we selected three.The main LDO and auxiliary LDOs share a global error amplifier(GEA)which controls the overall current provided by the main and auxiliary LDOs.To balance the currents provided by the main LDO an
194、d each auxiliary LDO,a DC current correction integrator(DCCI)is used.The DCCI composes a negative feedback loop(correction loop,TCOR)which adjusts the current provided by the auxiliary LDO to make it the same as that of the main LDO.The DCCI has a pole at a sufficiently-low frequency to avoid a stab
195、ility issue caused by TCOR.In addition,the SNI DISLDO has an immunity to the noise in the SoC,which is critical in the analog DISLDO.The SoC noise can be imposed on the signal path through a long metal line which connects the main LDO and auxiliary LDOs.The path(1)from each auxiliary LDO to the main
196、 LDO is connected to the input of the DCCI.Since the DCCI has such a low-frequency pole,the noise imposed on this signal is filtered by the DCCI.On the other hand,the path(2)from the main LDO to each auxiliary LDO should not use the filter to avoid generating an additional pole on the signal path.Th
197、erefore,in this design,the signal from the GEA is delivered to each auxiliary LDO in parallel with the signal from the DCCI.These parallel lines are implemented close to each other to impose identical noise which is removed by an SoC noise cancellation amplifier(SNCA).As a result,the proposed DISLDO
198、 operates properly even when the SoC noise is severe.Figure 21.6.2 shows a schematic of the SNI DISLDO.The main LDO includes the GEA,a core LDO,and the DCCI,while the auxiliary LDOs have an identical structure to the core LDO.The core LDO and the auxiliary LDOs comprise the SNCA,buffer,and MP.Theref
199、ore,each of them adopts a local Miller capacitor(CML)to compensate for the output pole of the SNCA(fp,SNCA).Similarly,a global Miller capacitor(CMG)is used to compensate for the output pole of the GEA(fp,GEA).To eliminate the SoC noise issue on the signal path(2)from the main LDO to each auxiliary L
200、DO,the SNI DISLDO uses SNCAs with noise coupling paths(NCP),as previously mentioned.The SNCA has a differential input structure,and its input signals are currents provided through the NCP in the main LDO.To convert these currents to voltages,the SNCA uses resistors instead of diode-connected transis
201、tors to maintain the resistance irrespective of the current level.Since the noise from the SoC is almost identically imposed on the input currents,the noise can be removed by the differential input of the SNCA.Additionally,because of the long distance,the control signal from the main LDO to each aux
202、iliary LDO may be delayed,which degrades the transient response.However,since each auxiliary LDO has a CML which couples the output of the LDO(VOUT)and the input of the buffer(VIB),each LDO can directly respond to the VOUT transition.Accordingly,the proposed DISLDO achieves a fast transient response
203、 regardless of the delay from the main LDO to auxiliary LDOs.Meanwhile,the DCCI balances the current supplied by the MP of the main LDO(MPM)and the MPs of auxiliary LDOs(MPA,ns).For stable operation,the DCCI should slowly integrate the error between currents provided by MPM(IPM)and MPA,n(IPA,n).To d
204、o that,the error between IPM and IPA,n is integrated to the integration capacitor(CINT)during a considerably short time(ton)and the integrated voltage(V2)is held during the rest of period(T ton).Consequently,the CINT is effectively enlarged.During the T ton,the buffer holds the output of the error a
205、mplifier(V1)to V2,which prevents V1 from being saturated to VIN or GND.V2 adjusts the reference current(IREF)of each SNCA to balance IPM and IPA,n.Figure 21.6.3 shows a block diagram of the SNI DISLDO including the main LDO and only one auxiliary LDO for a simple explanation.The main LDO has one fee
206、dback loop(TM)regulating VOUT.On the other hand,the auxiliary LDO has two feedback loops regulating VOUT:1)a loop that passes the DCCI(TFL);and 2)a loop that bypasses the DCCI(TFH).Since TFL and TFH are correlated with TCOR,the frequency response of TCOR affects TFL and TFH.As shown in Fig.21.6.3(ri
207、ght-top),TCOR generates poles of TFL and TFH in common at the unity gain frequency of TCOR(fu,COR).On the other hand,a dominant pole of TCOR generated by the DCCI(fp,DCCI)becomes a zero of TFH because only the TFH bypasses the DCCI.Therefore,TFL and TFH are respectively more dominant at lower and hi
208、gher frequencies than fu,COR,while they are crossed at fu,COR.The overall feedback loop of the auxiliary LDO is obtained by merging TFL and TFH,and this is the same as TM,which means that the main LDO and each auxiliary LDO operate identically.Meanwhile,for stable operation,all feedback loops need t
209、o be stable.Since TCOR has the pole of fp,SNCA,which is located at a relatively low frequency by a local Miller capacitor CML,it is important to locate the fp,DCCI at a much lower frequency than fp,SNCA.If it is not,TCOR might be unstable as shown in Fig.21.6.3(right-bottom).In the proposed design,t
210、his can be possible even with a small CINT of 2 pF because the CINT is effectively amplified 10,000 times in the DCCI.Figure 21.6.4 illustrates the common noise imposed on the signal path(2)from the main LDO and auxiliary LDOs.It is important to implement the two metal lines as close together as pos
211、sible and to avoid placing any metal pattern in parallel near the signal paths.This ensures that the same noise is imposed on both lines,which effectively cancels the common noise using the SNCA.In this prototype,the coupling between complicated metal patterns in the SoC is modelled as RC ladders,as
212、 shown in Fig.21.6.4(top-right),and noises in the SoC are applied to the RC ladders as random noise.When the noise is not commonly applied to inputs of the SNCA(Case 1),the SNI DISLDO cannot properly cancel the noise and the noise is shown at VOUT,as shown in Fig.21.6.4(bottom-left).On the other han
213、d,when the noise is commonly applied(Case 2),the SNI DISLDO properly cancels the noise,as shown in Fig.21.6.4(bottom-right).Figure 21.6.5(top)shows transient responses under various conditions with a load capacitor(CLOAD)of 1nF,which effectively models the load requiring a large ILOAD.In transition,
214、the currents provided by each MP become slightly different for a short time and finally become the same.This is because of the RC ladders used for modeling the SoC noise shown in Fig.21.6.4.Despite the RC ladders,the LDO can achieve a sufficiently fast transient response owing to CML.Since the curre
215、nts from the MPs are properly balanced owing to the DCCI,as shown in Fig.21.6.5(bottom-right),the heat is evenly distributed in the chip.Since only the SNI DISLDO is implemented using an analog LDO,the current efficiency can be much higher than that of any others,as shown in Fig.21.6.6(top-right).A
216、performance comparison is shown in Fig.21.6.6(bottom).The SNI DISLDO solves the problem caused by SoC noise,which is the main limitation of analog DISLDOs.Therefore,the proposed LDO performs better due to the advantages of analog LDOs,such as better load/line regulations and lower quiescent current
217、while providing larger current per unit LDO.A chip micrograph is shown in Fig.21.6.7.Ac k nowl e dge me nt:This work was supported by National Research Foundation of Korea(NRF)Granted funded by the Korea government(MSIT)under Grant RS-2023-00207919 and IITP-2024-RS-2023-00260091,and by Samsung Elect
218、ronics Co.,Ltd(IO220818-02092-01).Figure 21.6.1:Challenge of previous digit al and analog DISLDOs and t he concept of t he proposed SoC noise immune analog DISLDO.Figure 21.6.2:Full schemat ic of t he proposed SNI DISLDO;effect ive capacit ance amplificat ion for current balancing;and concept ual la
219、yout for SoC noise immunit y.Figure 21.6.3:Simplified block diagram of proposed SNI DISLDO(left);loop analysis demonst rat ing ident ical operat ion of main and auxiliary LDOs(right).Figure 21.6.4:Met al layout st rat egies and noise modeling in SNI DISLDO(t op);measurement of t he noise cancellat i
220、on(bot t om).Figure 21.6.5:Measured load t ransient waveforms at various VINs and VOUTs(t op),current waveforms and chip t emperat ure measurement s w/o and w/DCCI(bot t om-left),load regulat ion plot and current sharing accuracy(bot t om-right).Figure 21.6.6:Measured line t ransient waveform and cu
221、rrent efficiency plot (t op);performance comparison(bot t om).ISSCC 2025/February 18,2025/3:35 PM385 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 21.6.7:Chip micrograph.Re
222、 f e re nc e s:1 Y.-J.Lee,W.Jang,H.-H.Bae,J.-H.Cho and H.-S.Kim,“34.7A/mm2 Scalable Distributed All-Digital 6 6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network:A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS,”2024 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I
223、SSCC),San Francisco,CA,USA,2024,pp.272-274.2 X.Mao,Y.Lu and R.P.Martins,“A Fully Synthesizable All-Digital Dual-Loop Distributed Low-Dropout Regulator,”in IEEE Journa l of Sol id-Sta te Circ uits,vol.59,no.6,pp.1871-1882,June 2024.3 D.-H.Jung et al.,“A Distributed Digital LDO with Time-Multiplexing
224、Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS,”2021 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2021,pp.414-416.4 S.Bang et al.,“A Fully Synthesizable Distributed and Scalable All-Digital LDO
225、in 10nm CMOS,”2020 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e -(ISSCC),San Francisco,CA,USA,2020,pp.380-382.5 S.J.Kim,D.Kim,Y.Pu,C.Shi,S.B.Chang and M.Seok,“0.5-1-V,90-400-mA,Modular,Distributed,3 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation,”in I
226、EEE Journa l of Sol id-Sta te Circ uits,vol.56,no.9,pp.2781-2794,Sept.2021.6 B.Talele,R.Magod,K.Kunz,S.Manandhar and B.Bakkaloglu,“A Scalable and PCB-Friendly Daisy-Chain Approach to Parallelize LDO Regulators with 2.613%Current-Sharing Accuracy Using Dynamic Element Matching for Integrated Current
227、Sensing,”2020 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e -(ISSCC),San Francisco,CA,USA,2020,pp.494-496.386 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.7979-8-3315-4101-9/25/$31.00 2025 IEEE21.7 Merging Hybrid and Mult i-Phas
228、e Topologies:A 6-Phase Triple-St ep-Down DC-DC Convert er Achieving up t o a 60:1 Volt age Conversion Rat io and 868A/cm3 Current Densit y Mahmoud Hassan Kamel Hmada1,Wen-Chin Brian Liu1,Gal Pillonnet2,Patrick Mercier1 1University of California,San Diego,CA 2CEA-Lti,Grenoble,France Modern processors
229、 demand highly efficient solutions to meet challenging voltage and current requirements,such as delivering over 1A at voltages below 1V.This drives the need for efficient point-of-load DC-DC converter topologies capable of large step-down conversion with high current density,typically from a 12V inp
230、ut.Conventional single-phase buck converters often struggle to operate at wide voltage conversion ratios(e.g.,VCR=12:1)and with high current(e.g.,1A),in part because the required inductance to process the full input voltage at a small duty ratio needs to be large,resulting in significant volume,as s
231、hown in Fig.21.7.1(top left).Hybrid converters(Fig.21.7.1,middle left),which introduce flying capacitors to reduce voltage excursions across inductors 1-5,can help reduce inductor volume.However,in single-inductor hybrid designs,the output inductor still processes the entire output current,requiring
232、 an inductor with a high saturation current(ISAT)and a low DCR,resulting in a larger-than-desired volume 1,6.Additionally,flying capacitor sizes tend to increase with current,complicating scalability 7.On the other hand,multi-phase buck converters(Fig.21.7.1,bottom right)are commonly used in industr
233、y 8,9 to exploit the fact that,as shown in the inductor survey in Fig.21.7.1(top right),multiple compact inductors can achieve a higher cumulative ISAT than a single larger inductor for the same effective DCR,all in a smaller volume.However,multi-phase buck converters still must process the entire i
234、nput voltage across each inductor,necessitating a larger inductance value than a hybrid converter,making the trade-off between hybrid and multi-phase approaches unclear and still underexplored in the literature.Since adding inductors is essentially“free”in the sense that for the same effective DCR,t
235、he total volume is lower,this paper explores the benefits of increasing the number of compact inductors rather than adding many flying capacitors.Most prior art that does explore this is either limited to only 2 inductors and often uses more than 2 flying capacitors,or does not target high currents
236、or current densities,limiting the advantage offered by utilizing many compact inductors and resulting in current densities that do not exceed 700A/cm 5,10-15.This paper presents a 2C3L triple-step-down(TSD)DC-DC converter(Fig.21.7.1,bottom right)that synergizes the strengths of a 3-phase buck conver
237、ter(3P-buck)with those of a 2C1L hybrid converter(2C1L-HC),in a similar way to a double-step-down converter 16,17,while achieving performance that surpasses the sum of the two approaches individually.The 2C3L TSD architecture:1)divides the output current across three paths,reducing the inductor volt
238、age-second product by 3,which allows each inductor to occupy compact ceramic capacitor-like footprints(volume 75%in the HE mode,as shown in Fig.21.7.5(bottom left).The comparison in Fig.21.7.5(bottom right)highlights the achievable VCR against current density in both the HE and HCD modes(with effici
239、ency 70%)versus prior work.Notably,the TSD-HE achieves a 37%higher VCR than the best prior work,with a 6.5 higher current density.In HCD mode,the TSD remains competitive,offering 2 the VCR with a 21%higher current power density.Figure 21.7.6 compares this work to prior art 12V converters.By effectiv
240、ely combining hybrid and multi-phase topologies,the TSD achieves the highest current density,reaching up to 868A/cm.Due to relaxed ISAT and RDCR constraints,these results demonstrate that adding inductors can be more advantageous in high-current scenarios than relying on complex capacitor networks,p
241、aving the way for extending the 2CxL TSD implementation.Simultaneously,the TSD offers a duty cycle width that is 3 larger,enabling extreme VCRs of up to 60:137%higher than the best prior workwhile maintaining the highest current density.Additionally,the TSD can operate at high frequencies,further re
242、ducing inductor volume.Die and PCB photos are shown in Fig.21.7.7.Ac k nowl e dge me nt:This work was supported in part by the Power Management Center(PMIC)an NSF I/UCRC,award number 2052809.Figure 21.7.1:Induct or volume t rends,survey,research t rends on DC-DC convert ers,and proposed t opology.Fi
243、gure 21.7.2:Proposed t opology phases,operat ion waveforms(right),and swit ch summary t able(bot t om).VOS1S3S6S7VINC2L1L2CLRLC1S4S5S8L3S2VOS1S3S6S7VINC2L1L2CLRLC1S4S5S8L3S2VOS1S3S6S7VINC2L1L2CLRLC1S4S5S8L3S2VOS1S3S6S7VINC2L1L2CLRLC1S4S5S8L3S2Phase-5Phase-1 IL1 IL1 IL1 IL1 IL2 IL2IL3 IL3 IL3 IL2 IO
244、IO IO IO IL2Phase-3Phase-2,4,6Self-balancing&soft dis/chargeVSW1,2VSW5VSW6VSW7VSW8VSW3,4VLX1VLX3VLX2IL1IL3IL2VCN1VCP1VC1VLX1VCP2VC2VINVIN/30V2VIN/3VIN/30VVIN/3VIN/3IO/3IO/3IOUTIO IL3VIN/30VVIN/30VVIN/30V6-equivalent rippleLarger duty cycleSmaller Terminal VoltageHV Device(12V MOSFET)LV Device(5V MOS
245、FET)VCP1VCN1VCP2VLX2VLX1VLX3VLX2VLX3VLX2VLX1VLX3VLX2VLX1VLX3 IL1=IL2=IL3=IO/3IO/3VIN/32VIN/3S1S2S3S4S5S6S7S8Switch TypeHVHVHVHVHVLVLVLVMax.Stress(VDS/VIN)2/31/312/32/31/31/31/3IRMS/Io11/31/300001/31/33001/31/301/31/30500002/31/301/32,4,6000001/31/31/3135135135135135VIN/3VIN/3103Inductance(nH)1001011
246、02Inductor Volume(mm3),RDCR,Max=30m10203040506070Maximum RDCR00.511.522.53ISAT/Volume(A/mm3)VOC2L1L2CLRLC1L3VINS3S4S5S6S7S8S1S2PMICVOVINVL 0.33VIN VOUT2mm1.2mm0.8mm3.2mm2mm2.5mmInd.A:ISAT=8.0A,Vol.=16mm3Ind.B:ISAT=4.1A,Vol.=1.92mm3 Inductor Volume Vs.InductanceBenefit of Splitting Inductors at High
247、Current Inductor AInductor BVOUTVIND=3x smaller volume inductors for same max output ripple 6-interleavingD Extends duty cycle by 300%Suited for wide conversion ratios Smaller passives:Larger bandwdithState of the ArtProposed Architecture:Triple Step Down(TSD)Vol.20mm3Ind.A Small D:limiting VCR&FSWF
248、or the same RDCR,FSW 3VOUTVIND=240330470Vnd.ALCLRLVOVINCLRLLSwitched CapacitorsSwitchesProcesses full IO:bulky inductor IOProcesses full VIN:bulky inductorDVINSplit inductors forhigher IO capabilityAdding front-capacitive networkfor smaller inductors&wider VCR IOInd.required for TSDVol.=1.92mm33x In
249、ductor Bs are 64%smaller than 1x Inductor A Vol.9.6mm3Vol.75%13.33202012126040Max.Load Current A 455457FSW MHz210.81111.5Flying Capacitor2 x 2.2F4x 10F2 x 22F2 x 10F3 x 22uF3 x 10F1 x 22F2 x 2.2FInductor2 x 0.74H0.68H1H2 x 1H1H3 x 0.68H3 x 0.47HRDCR m14.5N.A.N.A.4810.5571729Volume mm322.484.48(c)653
250、5.283.2161.92Output Capacitor10.6F22F100F22F22F10F22FPeak Vo(Vin=12V)86.8%1.2V84.6%0.9V94.5%1.2V93.4%1V91.3%1.2V91.8%1V92.3%1.589%1V93.7%1.2V92%1V(a)92.9%1.2V91%1V(a)91%1.1V89.02%0.9V88.3%1.1V86.9%0.9V(%)Vout,IOUT,MAX81%1.2V(a)77.5%0.9V(a)82%1.2V,5A83%1V,5A(a)81%1.2V,5A(a)78%1V,5A(a)85.3%1V,4A84.8%1
251、.2V,5A83.5%1V,5A(a)82.1%1.2V,5A79.5%1V,5A(a)82%1V,7A80.6%0.9V,7A82.8%1V,5.5A78.4%0.9V,7ADie Area mm22.83.8618.888.556.3Total Passive Volume(d)mm351.1(c)84.48(c)14.315.1739.387.318.38.06Maximum Current Density(A/cm3)78.359350 26412768538286801234567Load Current(A)405060708090Efficiency(%)102030405060
252、VIN/VO6065707580859095Peak Efficiency(%)VO=0.3VFSW=1MHzPlan HE:High EfficiencyPlan HCD:High Current DensityEfficiency vs.Voltage Conversion RatioMax VIN/VO at Max Current Density Where 70%Ability to increase FSW for higher current densityVIN=12V02004006008001000Current Density(A/cm3)101520253035Maxi
253、mum 1410121113,Plan A13,Plan BPlan HEPlan HCD91%VO=1.1VVO=1.1VVIN=12V0.4V0.5V0.6V0.7V0.9VL HE=680nH,FSW=1MHzVery large conversion ratioL HCD=470nH,FSW=1.49MHzL=680nH,RDCR=17m88.3%1.1V 0.3V1VFSW=1.49MHzVIN=12V0.4V0.5V0.6V0.7V0.8V0.9VL=470nH,RDCR=29m SN1=H HH=O=Hz=1MHFH,DCRO=1 1VV=O O=01234567Load Cur
254、rent(A)405060708090Efficiency(%)0.8V21%200%14.7x higher current density37%6.5XVolume=16mm3Volume=1.92mm3VIN/VO8.3x Smaller volume inductorsISSCC 2025/February 18,2025/4:00 PM387 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND RE
255、FERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 21.7.7:Chip micrograph(t op left),PCB(t op right),component s list (bot t om left),and surface area.HV&LV PowerSwitchesAnalog ControlsLevel shifers&DriversLevel Shifters&DriversLevel Shifters&Drivers3150m2000mFlying capacitorsInductorsDiearea16%45%
256、39%Area Contribution of Main Components Flying capacitorsInductors8%73%19%DieareaPlan HCDPlan HE49%less totalareaC1CINC2L1L2L3CLFlip Chip17mm14mmComponent Name Nominal ValueFootprint(Size)(mm)Flying CapacitorsC1,C22.2F1.6 x 0.8 x 0.9 0603Input CapacitorCIN10F1.6 x 0.8 x 0.9 0603Output CapacitorCL(Pl
257、an HE)10F1.6 x 0.8 x 0.9 0603CL(Plan HCD)22F1.6 x 0.8 x 0.9 0603InductorsL1,L2,L3(Plan HE)L1,L2,L3(Plan HCD)680nH470nH3.2 x 2.5 x 22 x 1.2 x 0.8Re f e re nc e s:1 Z.Xia and J.Stauth,“A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9%Peak Efficiency Tolerating 0.6V/s Input Slew
258、 Rate During Startup,”2021 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2021,pp.256-258,doi:10.1109/ISSCC42613.2021.9365763.2 C.Schaef et al.,“A 93.8%Peak Efficiency,5V-Input,10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide
259、Output Voltage Range and Flying Capacitor Precharging,”2019 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e -(ISSCC),San Francisco,CA,USA,2019,pp.146-148,doi:10.1109/ISSCC.2019.8662475.3 J.Xue and H.Lee,“A 2MHz 12-to-100V 90%-efficiency self-balancing ZVS three-level DC-DC regulator wit
260、h constant-frequency AOT V2 control and 5ns ZVS turn-on delay,”2016 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2016,pp.226-227,doi:10.1109/ISSCC.2016.7417989.4 T.Hu,M.Huang,Y.Lu and R.P.Martins,“A 12V-to-1V Quad-Output Switched-Capacitor Buck Converter
261、with Shared DC Capacitors Achieving 90.4%Peak Efficiency and 48mA/mm3 Power Density at 85%Efficiency,”2023 IEEE International Sol id-State Circuits Conf erence(ISSCC),San Francisco,CA,USA,2023,pp.184-186,doi:10.1109/ISSCC42615.2023.10067463.5 X.Yang et al.,“An 8A 998A/inch3 90.2%Peak Efficiency 48V-
262、to-1V DC-DC Converter Adopting On-Chip Switch and GaN Hybrid Power Conversion,”2021 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2021,pp.466-468,doi:10.1109/ISSCC42613.2021.9366005.6 X.Liu,C.Huang and P.K.T.Mok,“A High-Frequency Three-Level Buck Converter
263、 With Real-Time Calibration and Wide Output Range for Fast-DVS,”in IEEE Journa l of Sol id-Sta te Circ uits,vol.53,no.2,pp.582-595,Feb.2018,doi:10.1109/JSSC.2017.2755683.7 S.S.Amin and P.P.Mercier,“A Fully Integrated Li-Ion-Compatible Hybrid Four-Level DCDC Converter in 28-nm FDSOI,”in IEEE Journa l
264、 of Sol id-Sta te Circ uits,vol.54,no.3,pp.720-732,March 2019,doi:10.1109/JSSC.2018.2880183.8 Texas Instruments,“LM3754 Scalable 2-Phase Synchronous Buck Controller with Integrated FET Drivers and Linear Regulator Controller,”Accessed on Sep.1,2024.9 Analog Devices,“LTC3861:Dual,Multiphase Step-Down
265、 Voltage Mode DC/DC Controller with Accurate Current Sharing Data Sheet,”Accessed on Sep 1,2024.10 X.Yang et al.,“A 5A 94.5%Peak Efficiency 916V-to-1V Dual-Path Series-Capacitor Converter with Full Duty Range and Low V.A Metric,”2023 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSC
266、C),San Francisco,CA,USA,2023,pp.196-198,doi:10.1109/ISSCC42615.2023.10067802.11 W.-L.Zeng et al.,“A 12V-lnput 1V-1.8V-Output 93.7%Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter,”2023 IEEE International Sol id-State Circuits Conf e re nc e (ISSCC),San Francisco,CA,USA,2023,pp.10-12,do
267、i:10.1109/ISSCC42615.2023.10067710.12 G.Cai,Y.Lu and R.P.Martins,“A Compact 12V-to-1V 91.8%Peak Efficiency Hybrid Resonant Switched-Capacitor Parallel Inductor(ReSC-PL)Buck Converter,”2023 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2023,pp.198-200,doi:1
268、0.1109/ISSCC42615.2023.10067303.13 Y.Ji,J.Jin and L.Cheng,“A 12V-Input 1V-1.8V-Output 94.7%-Peak-Efficiency 685A/cm3-Current-Density Hybrid DC-DC Converter with a Charge Converging Phase,”2024 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2024,pp.458-460,d
269、oi:10.1109/ISSCC49657.2024.10454573.14 T.Hu,M.Huang,Y.Lu and R.P.Martins,“A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D0.5 Control Achieving 2x Transient Inductor Current Slew Rate and 0.73 Theoretical Minimum Output Undershoot of DSD,”2022 IEEE Inte rna tiona l Sol i
270、d-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2022,pp.1-3,doi:10.1109/ISSCC42614.2022.9731669.15 H.Han et al.,“A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2 Slew Rate All-Hysteretic Mode,”2022 IEEE Symposium on VL
271、SI Technol ogy and Circuits(VLSI Technol ogy and Circuits),Honolulu,HI,USA,2022,pp.182-183,doi:10.1109/VLSITechnologyandCir46769.2022.9830233.16 J.Yuan,Z.Liu,F.Wu and L.Cheng,“A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9mu mathrmS$1%Settling Time for a 3A/20ns Load Transient,”2022 IEE
272、E Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),San Francisco,CA,USA,2022,pp.1-3,doi:10.1109/ISSCC42614.2022.9731701.17 Texas Instruments,“TPS54A20 8-V to 14-V Input,10-A,up to 10-MHz SWIFT Step Down Converter datasheet,”Accessed on Sep.1 2024.18 Y.Zhu,N.M.Ellis and R.C.N.Pilawa-Po
273、dgurski,“Comparative Performance Analysis of Regulated Hybrid Switched-Capacitor Topologies for Direct 48 V to Point-of-Load Conversion,”2023 IEEE Ene rgy Conve rsion Congre ss a nd Exposition(ECCE),Nashville,TN,USA,2023,pp.3313-3320,doi:10.1109/ECCE53617.2023.10362157.388 2025 IEEE International So
274、lid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POWER/21.8979-8-3315-4101-9/25/$31.00 2025 IEEE21.8 HOOP:A Scalable Hybrid DC-DC Convert er Ring for High-Performance Comput ing Zhiguo Tong*1,Zhewen Yu*1,2,Junwei Huang1,Xiangyu Mao1,3,Bernhard Wicht4,Rui P.Martins1,Yan Lu1,2,3 1Uni
275、versity of Macau,Macau,China 2Tsinghua University,Beijing,China 3UM Hetao IC Research Institute,Shenzhen,China 4Leibniz University Hannover,Hannover,Germany *Equally Credited Authors(ECAs)In the AI era,demands of computing power grow exponentially,driving the need for power delivery solutions that o
276、ffer stronge r power capability,highe r efficiency and f a ste r response,toge the r 1.To satisfy the enormous current demand,tens or hundreds of point-of-load converters operate in parallel to multiply the output current capability.However,maintaining high efficiency in multi-phase converters requi
277、res dedicated current-balance control among each converter phase(Fig.21.8.1).Traditionally,this is achieved by integrating a global digital controller,which monitors the inductor currents and adjusts the PWM signals to ensure current balancing.However,as the number of phases(N)increases,the complexi
278、ty of maintaining current balance escalates,presenting additional challenges 2.Hence,an inherent auto-current-balancing characteristic of the DC-DC converter is highly desirable.Prior arts 3-5 leverage the charge balance properties of capacitors to obtain automatic inductor current balancing.Similar
279、 approaches have been employed to balance inductor currents in conventional buck and three-level converters 6-8.However,when these hybrid structures are used in parallel to increase output capability,ensuring the current balance between different converters remains a significant challenge.In this pa
280、per,we have designed a Hybrid converter with a power ring(O)for current balance and a back ring(O)for phase shedding for computing Power delivery,as a HOOP.The proposed converter features a ring-shaped structure around the xPU loads,facilitating automatic current balancing and easy extension to any
281、number of converter phases.This approach involves extracting a small,fixed portion of the inductor current from each branch and passing it to the next branch,i.e.each branch also incorporates the same portion of current from the previous branch.As a result,if a current mismatch occurs between two ad
282、jacent inductors,the difference in the sink and source currents across the branches will automatically correct the imbalance.To further enhance efficiency across varying load currents,a phase shedding back ring is also incorporated.The extracted current from each cell can be fed into either the next
283、 cell or the first cell,ensuring efficient operation under different load conditions.This auto-balanced ring structure simplifies the power delivery layout for xPU applications.By placing the converter on the backside of the load in a ring configuration,the current can be delivered vertically to the
284、 xPUs via short paths,greatly reducing both the on-board and in-package IR losses 9.To demonstrate the concept,this work presents the designed module with the proposed hybrid ring cells(HRCs).The HRC(Fig.21.8.2)incorporates two flying capacitors and two inductors.Each HRC consists of two branches,wi
285、th each branch operating in three distinct states.In phase X,inductor LX charges flying capacitor CFX.In phase X,inductor LX discharges the preceding capacitor CFX-1.In phase X,inductor LX is de-magnetized.Since CFX-1 is utilized in both the X-1 and X phases,these two phases must be interleaved.The
286、duty cycles of states X and X are set to the same duration,DT.By applying the voltage-second balance principle in the inductors and charge balance in the flying capacitors,we can conclude that the inductor currents automatically balance across different inductors and the flying capacitor voltages wi
287、ll equalize as well.Besides,despite the absence of a dedicated charging path to maintain a fixed voltage on the flying capacitors,a natural balancing loop ensures that the flying capacitor voltage stabilizes at VIN/2 10,11.Figure 21.8.2(bottom)illustrates an example of the proposed HOOP module with
288、three HRCs.In this configuration,the three HRCs are connected in parallel,with the POST pin of each chip connected to the PRE pin of the subsequent chip.Additionally,all of the BACK pins are all connected to the PRE pin of the first chip.For phase shedding,the HRCs can be configured into two modes:a
289、ctive mode and sleep mode.In active mode operation,each HRC can either connect forward to the next one or return to the first HRC to form a complete current balance loop.In sleep mode,the HRC is inactive,enhancing efficiency at lower output currents.Moreover,to achieve fast transient response,a tran
290、sient mode is also introduced.In this mode,all power branches operate in the phase,simultaneously increasing the current in all inductors and thereby enhancing the load transient response performance 5.Figure 21.8.3(left)illustrates the block diagram of the designed HRC,which integrates all power tr
291、ansistors(M1-M7),along with their drivers,bootstrap circuits,and controller,into a single chip.Switches M1 and M2 are implemented using 6V LDMOS,while M3-M7 are implemented using 12V LDMOS.For switches M1-M5,a conventional cascaded bootstrap structure with an active diode implemented by PMOS can be
292、used 12,13.However,switch M6 presents a challenge because its source terminal is connected to the POST pin,and the operating mode of the subsequent chip is not fixed.If the subsequent chip is in sleep mode for phase shedding,the bootstrap capacitor of M6 cannot be charged,preventing M6 from operatin
293、g correctly.To address this issue,we use the bootstrap capacitor of M7 to charge that of M6.The bootstrap capacitor of M7 is charged from that of M3,based on the principle that VBACK equals to VIN/2 and SW1 switches between VIN/2 and 0.This approach ensures that all power switches operate correctly,
294、without being affected by the phase shedding of other chips.Besides,due to the long distance between M3 and M7 in the layout,a discrete off-chip capacitor,CBOOT7,is placed in parallel with the on-chip bootstrap capacitor.Moreover,an off-chip capacitor is also added to maintain the DC voltage of the
295、BACK node and to address minor misalignment of the phases of the first and the last active chips.Due to its inherent auto-current-balance property,the HOOP can be controlled simply using a primary-secondary voltage mode PID control,without sensing any inductor currents.The duty cycle is generated by
296、 the first HRC chip and send to each HRC.Furthermore,because adjacent converters operate out of phase,propagation delay is not a major concern.A mode transition protector is introduced to eliminate ultra-short-pulse signals during mode transitions and to protect the chip.For hybrid converters,transi
297、tioning a chip from sleep mode to active mode presents another challenge,the flying capacitor and bootstrap voltages must be maintained during sleep mode.If these voltages are not maintained,the power switches may experience overvoltage and fail to operate correctly when the chip is reactivated 14.I
298、n this work,we address this issue by incorporating dedicated diodes DCLAMP and MCLAMP,along with parasitic diodes DBS7 and DM7,to clamp the voltages of the flying capacitors and bootstrap capacitors,as shown in Fig.21.8.3(top right).According to the load current level and load transients,the HRC chi
299、ps switch between four modes,following the rules given in Fig.21.8.3(bottom right).Figure 21.8.4(top left)shows the HRC start-up waveforms,demonstrating the auto current balance and flying capacitor voltage balance across the entire VIN range.Figure 21.8.4(top right)presents the steady-state wavefor
300、ms of a single HRC chip at an IOUT of 3A,achieving a current mismatch of only 40mA and an output voltage ripple of 18mV.Figure 21.8.4(bottom left)shows the measured waveforms during phase shedding,with the second chip disabled or enabled.Figure 21.8.4(bottom right)shows the detail of phase shedding
301、process,highlighting the voltage leakage and the effect of the voltage clamp.Figure 21.8.5(top left)exhibits the current balance performance in the presence of inductor mismatch,demonstrating the tolerance of current balance against path impedance.Despite significant differences in inductance values
302、,L1(2H,204m)and L2(1H,48m),the inductor currents exhibit only a 90mA mismatch.Figure 21.8.5(top right)illustrates the load transient response with a load increase from 300mA to 3A within 80ns.With the HRCs operating in transient mode,not only do IL1 and IL2 rise together,but IL3 and IL4 of the sleep
303、 mode HRCs also help charge the output capacitor,accelerating the recovery of the output voltage and reducing the voltage droop by 50%.The implemented HOOP module achieves a peak efficiency of 90.2%at 1A for a single chip and a peak efficiency of 87.2%at 4.2A for four chips,with a maximum output cur
304、rent of 16A.Figure 21.8.5(bottom right)presents the analysis of additional power loss in the ring.In the case of four HRCs operating at 12-to-1V with an output current of IOUT,the current transmitted across the ring path is only IOUT/8,with a duty cycle of 1/12.At the peak efficiency point of 4A,thi
305、s loss accounts for just 0.06%of the output power.Figure 21.8.6 provides the comparison table of the HOOP module with state-of-the-art designs 15,highlighting that this work offers an easily-scalable,auto-current-balanced solution with the highest power density and significant current density.As sho
306、wn in Fig.21.8.7,the proposed HRC chip,fabricated in the 0.18m BCD process,occupies a die area of 4.56mm2 with two 10F(0402)flying capacitors soldered on the die.Each HRC occupies an area of 21.5mm2 with two 1H(0806)inductors on the top side,and other passive components on the back side.The four-chi
307、p HOOP module occupies an area of 16x16mm2 with all components on the top side of the PCB and the load on the back side,demonstrating its suitability for vertical power delivery applications.Ac k nowl e dge me nt:This work was supported by the National Natural Science Foundation of China(62122001),t
308、he Hetao SZ-HK S&T Project(HTHZQSWS-KCCYB-2023030),the Macau Science and Technology Development Fund(FDCT/0023/2022/A1 and 004/2023/SKL).Corresponding Author:Yan Lu.Figure 21.8.1:The mult i-phase buck convert er and t he proposed current balance st rat egy feat uring a HOOP st ruct ure.Figure 21.8.2
309、:The proposed hybrid ring cell(HRC)and it s operat ion principle.Figure 21.8.3:The block diagram of t he proposed HRC chip and t he circuit implement at ion.Figure 21.8.4:The measured st art-up,st eady st at e,and phase shedding waveforms.Figure 21.8.5:The measured current balance,load t ransient re
310、sponse waveforms,efficiency and loss analysis.Figure 21.8.6:The comparison t able wit h t he st at e of art works.ISSCC 2025/February 18,2025/4:25 PM389 DIGEST OF TECHNICAL PAPERS 21 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9
311、/25/$31.00 2025 IEEEFigure 21.8.7:The chip micrograph,PCB implement at ion and component s list.Re f e re nc e s:1 Y.Lu et al.,“An Overview of Hybrid DCDC Converters:From Seeds to Leaves,”in IEEE Open Journal of the Solid-State Circuits Society,vol.4,pp.12-24,2024.2 Monolithic Power Systems,“MP2880:
312、single-loop,20 phase,digital multi-phase controller with PMBus interface for AVSBus”.3 J.Yuan,Z.Liu,F.Wu,and L.Cheng,“A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9mu mathrmS$1%Settling Time for a 3A/20ns Load Transient,”in IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I
313、SSCC),Feb.2022,pp.13.4 H.Han et al.,“A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2 Slew Rate All-Hysteretic Mode,”in 2022 IEEE Symposium on VLSI Te c hnol ogy a nd Circ uits(VLSI Te c hnol ogy a nd Circ uits),Jun.2022,pp.182183.5
314、T.Hu,M.Huang,R.P.Martins,and Y.Lu,“A 12-to-1 Flying Capacitor Cross-Connected Buck Converter With Inserted D 0.5 Control for Fast Transient Response,”IEEE Journa l of Sol id-Sta te Circ uits,vol.58,no.11,pp.32073218,Nov.2023.6 J.-H.Cho et al.,“A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integr
315、ated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns,”in IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),Feb.2022,pp.13.7 C.Wang,Y.Lu,M.Huang,and R.P.Martins,“A Two-Phase Three-Level Buck DCDC
316、Converter With X-Connected Flying Capacitors for Current Balancing,”IEEE Sol id-Sta te Circ uits Le tte rs,vol.3,pp.442445,2020.8 J.-H.Cho,H.-H.Bae,G.-W.Lim,T.-H.Kong,J.-H.Yang,and H.-S.Kim,“A Fully-Integrated 0.9W/mm2 79.1%-Efficiency 200MHz Multi-Phase Buck Converter with Flying-Capacitor-Based In
317、ter-Inductor Current Balancing Technique,”in 2022 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Jun.2022,pp.196197.9 C.Hardy et al.,“A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing,”in 2023 IEEE Inte rna
318、 tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),Feb.2023,pp.182184.10 R.H.Wilkinson,T.A.Meynard,and H.du Toit Mouton,“Natural Balance of Multicell Converters:The Two-Cell Case,”IEEE Tra nsa c tions on Powe r El e c tronic s,vol.21,no.6,pp.16491657,Nov.2006.11 Z.Ye,Y.Lei,Z.Liao,and R.C.N.Pila
319、wa-Podgurski,“Investigation of Capacitor Voltage Balancing in Practical Implementations of Flying Capacitor Multilevel Converters,”IEEE Tra nsa c tions on Powe r El e c tronic s,vol.37,no.3,pp.29212935,Mar.2022.12 Z.Ye,Y.Lei,W.-C.Liu,P.S.Shenoy,and R.C.N.Pilawa-Podgurski,“Improved Bootstrap Methods
320、for Powering Floating Gate Drivers of Flying Capacitor Multilevel Converters and Hybrid Switched-Capacitor Converters,”IEEE Tra nsa c tions on Powe r El e c tronic s,vol.35,no.6,pp.59655977,Jun.2020.13 C.Schaef et al.,“A 93.8%Peak Efficiency,5V-Input,10A Max ILOAD Flying Capacitor Multilevel Convert
321、er in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging,”in 2019 IEEE Inte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (ISSCC),Feb.2019,pp.146148.14 J.Yang,T.Hu,M.Huang,Rui.P.Martins,and Y.Lu,“A 12V-to-PoL CCC-Based Easy-Scalable Multiple-Phase Hybrid Converter wi
322、th Auto VCF Balancing and Inactive CF Charging,”in 2024 IEEE Custom Inte gra te d Circ uits Conf e re nc e (CICC),Apr.2024,pp.12.15 Analog Devices,“MAX77542,16VIN/16A Quad-phase High-Efficiency Buck.”390 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 21/COMPUTE AND USB POW
323、ER/21.9979-8-3315-4101-9/25/$31.00 2025 IEEE21.9 A 20MHz&1MHz Dual-Loop Non-Uniform-Mult i-Induct or Hybrid DC-DC Convert er wit h Specified Induct or Current Allocat ion and Fast Transient Response Junwei Huang*1,Xiangyu Mao*1,2,Zhiguo Tong1,Zhewen Yu1,Wenjie Yang1,Chi-Seng Lam1,Rui P.Martins1,Yan
324、Lu1,2,3 1University of Macau,Macau,China 2UM Hetao IC Research Institute,Shenzhen,China 3Tsinghua University,Beijing,China *Equally Credited Authors(ECAs)High-efficiency,high-power-density,and fast transient response DC-DC converters are in high demand for consumer,automotive,and industrial applicat
325、ions.In recent years,many integrated hybrid converters have been developed to enhance efficiency and current density 1-4,in which the series-capacitor buck(SCB)converters 3 and 4 are particularly favored for their relative simplicity.Figure 21.9.1(left)shows the Dickson SC hybrid Buck converter(DSC-
326、HB)5,which offers the advantages of inherent inductor current balance and reduced inductor voltage stress.To mitigate high-voltage device switching losses,converters with high voltage conversion ratios typically operate at lower switching frequencies,resulting in a reduced loop bandwidth(1/10-to-1/5
327、 of the operating frequency)and requiring larger inductors.This constrains the inductor current slew rate during load transients and deteriorates the transient performance.This limitation is pronounced in DSC-HB topologies,where multiple output inductors cannot simultaneously increase current during
328、 transients.Previous works 6 and 7 addressed this limitation by simultaneously activating all inductors,achieving a 2 increase in the inductor current slew rate and improving the load transient performance.However,for load step-down transients,the inductor currents falling slew rate is still constra
329、ined by the low VOUT and large inductance.As higher operating frequencies enable wider loop bandwidths and smaller inductors yield higher inductor current slew rates,this paper proposes a dual-loop non-uniform-multi-inductor hybrid DC-DC(LLSC)converter with specified current allocation(SCA)targeting
330、 fast load transient response(Fig.21.9.1,right).Unlike the traditional DSC-HB converter with 4V(VIN/3)and 8V(2VIN/3)flying capacitor voltages,the proposed design works with 7V and 2V flying capacitor voltages,incorporating a 2V DC capacitor voltage.Within this 2V range,a high-frequency low-voltage b
331、uck converter is designed to improve the load transient performance.During steady-state operation,the inductor current ratio of the proposed LLSC converter is adjusted to 5:5:2.During the load transients,the high-frequency buck converters rapid response allows the inductor current in L3 to immediate
332、ly increase or decrease,reducing the output voltage undershoot or overshoot.In addition,this converter eliminates one high-voltage device,and the use of a smaller inductor L3 also increases the power density.Sigma converters 8 and 9 can also separate the voltage rails.However,in Sigma converters,the
333、 ratio of the voltage rails depends on VOUT.As VOUT changes,the voltage stress on all switches also changes,which is not suitable for applications with a wide VOUT range.In contrast,in the proposed converter,once the 2V rail is set,the voltage stress on all switches remains constant.Figure 21.9.2(top)illustrates the operating principle of the proposed converter,which operates in two frequency rang
0731-84720580
sgpjbg002
工作日 9:30 - 18:00
研報
新質生產力
DeepSeek?
低空經濟
大模型
AI Agent
AI Infra
具身智能
自動駕駛
寵物
銀發經濟
人形機器人
企業出海
算力
微短劇
薪酬
白皮書
創新藥
人工智能
AI產業
信息科技
互聯網
消費經濟
汽車交通
電商零售
傳媒娛樂
醫藥健康
投資金融
能源環境
地產建筑
傳統產業
英文報告
其它
最新報告
中英對照
全文搜索
報告精選
PDF上傳翻譯
多格式文檔互轉
入駐&報告售賣
會員權益
機構報告
券商研報
財報庫
專題合集
英文報告
數據圖表
會議報告
其他資源
行業聚焦
芯片產業
熱點概念
全球咨詢智庫
人工智能
500強
新質生產力
會議峰會
新能源汽車
企業年報
互聯網
公司研究
行業綜觀
消費教育
科技通信
醫藥健康
人力資源
投資金融
汽車產業
物流地產
電子商務
傳統產業
傳媒營銷
其它
2025低空經濟/低空產業報告合集（共49套打包）
2025年智算中心/AIDC/AI數據中心研究報告合集（共37套打包）
AI、科技與通信
廣告、傳媒與營銷
消費、零售與支付
HR、文化與旅游
金融、保險與投資
能源、環境與工業
醫療制藥與大健康
物流、地產與建筑
其他行業
AI ? 科技 ? 通信
數字化
金融財經
智能制造
電商傳媒
地產建筑
醫療醫學
能源化工
其他行業
收藏
下載
2025-05-20
AI查數
行業數據
政策法規
商業模式
產業鏈
競爭格局
市場規模
產業概述
其它
2025年
AI讀財報
年報
一季報
半年報
三季報
IPO招股書
社會責任報告
A股
IPO申報
港股
美股&全球
新三板
掃碼登錄
手機快捷登錄
賬號登錄
