戴翔-使用硬件加速Tokio.pptx

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1、第三屆中國第三屆中國Rust開發者大會開發者大會使用硬件加速使用硬件加速Tokio演講人：Loong.Dai,Cathy.LuLoong DaiIntel云原生工程師微軟MVPDapr、Thanos、Golangci-lint的Maintainer現在主要專注于服務網格領域，探索云原生軟硬件結合新范式Github ID:daixiang0自我介紹Cathy LuIntel軟件工程師專注于NFV,電信網絡云化等方案Why need Tokio?Rust does not provide async runtime in std libTokio is good enoughTokioTokios

2、 APIs are memory-safe,thread-safe,and misuse-resistant.This helps prevent common bugs,such as unbounded queues,buffer overflows,and task starvation.ReliableBuilding on top of Rust,Tokio provides a multi-threaded,work-stealing scheduler.Applications can process hundreds of thousands of requests per s

3、econd with minimal overhead.Fastasync/await reduces the complexity of writing asynchronous applications.Paired with Tokios utilities and vibrant ecosystem,writing applications is a breeze.EasyThe needs of a server application differ from that of an embedded device.Although Tokio comes with defaults

4、that work well out of the box,it also provides the knobs needed to fine tune to different cases.FlexibleTokioCore Queue-Based Modules in Tokio Channel SchedulerTokio uses Channel for communication between threads(incl.pthread,co-routines).Channel allows a unidirectional flow of information between t

5、wo end-points:the Sender and the Receiver.Channel Type:SPSC,SPMC,MPMC,MPSC.SendersReceiveSendersSendersReceiveReceiversPerf Gaps:CAS(Compare And Swap)cant perfectly scale with core count.Tokio ChannelKeyTokio SchedulerPerf Gap:Synchronization is required for stealingSoftware Queue IssuesProducerEnqu

6、eue SoftwareDequeue SoftwareHead and Tail pointersDequeue SoftwareDequeue SoftwareEnqueue SoftwareProducerConsumerConsumerConsumerSynchronization latencyMemory/Cache latencyCPU cycles latencyDLB：Dynamic Load BalanceDLBDLBEnqueue LogicHead and Tail pointersDequeue Logic&Load BalancerProducerProducerC

7、onsumerConsumerConsumerNo Synchronization latencyNo memory/cache latencyNo CPU cyclesDLB-Assist Channel IntroHardwareSendersReceiveSendersSendersReceiveReceiversChannel/QueueDLB-Assist Channel removes the penalty of CAS to achieve a safety-guaranteed,lock-free and scalable channel.Intel Confidential

8、Department or Event Name12Intel ConfidentialMiNetRun Rust Channel12DLB-Assist Channel OverviewHardware-Direct offloadingCant carry generic typeEscape safety trackMessage-Ownership TrackingTakes messages ownership Avoid message being dropped.Message-ID Reclaiming Reclaim Message-IDTransfers Message-I

9、D through HWSendersReceiversChannelHardwareHardwareProducerConsumerGive OwnershipTake OwnershipMessage-ID Reclaiming Message-Ownership TrackingDLB-Assist Channel Compatible channel interfaceCompatible featuresEscape?MPMC TestScenarioMPMC channel allows:Adding new entries from any core or threadPicki

10、ng the next entry by any core or threadConclusion:DLB channel scales with core count much better than SW channelsCore count 2 shows advantageFrom the Pictures:SW channels depicted in red and yellow line drop with the core count increasing because of data race among Ps and Cs.DLB channel depicted in

11、blue line scales well until it reaches the hardware limitationNote:Both are P bound in the evaluation scenario0246810121416182012345678910 11 12 13 14 15 16 17 18 19 20Throughput/Relative ValueNumber of Core Pairs3 means 3 producer cores and 3 consumer coresMPMC Throughput BenchmarkDLB_LibDLBCrossbe

12、amFlumeMPSC TestScenarioMPSC channel allows many threads sending to one place.Conclusion:DLB channel is more stable than SW channels Core count 2 shows advantageFrom the Pictures:SW channels depicted in origin and purple line,drop with the number of P increasing and reach to a stable data.DLB channe

13、l depicted in blue line increases at first and then keeps stable.Note:All are C bound in the evaluation scenario0.5124816326412345678Throughput/Relative ValueNumber of Producer CoresMPSC Throughput Benchmark系列2系列3系列4系列5DLBTokioCrossbeamStdDLB-Assist Scheduler Design Each processor has own run queue DLB does balanceNext Step Do benchmark for different scenarios Upstream Optimize applicability Thank you！