SNIA-SDC23-Jurski-Loewen-Constantine-Orozco-Overcoming-SMBus-limitations-with-I3C.pdf

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1、1|2023 SNIA.All Rights Reserved.Virtual ConferenceSeptember 28-29,2021Overcoming SMBus Limitations with I3CPresented by:Janusz Jurski(Intel),Myron Loewen(Solidigm),Anthony Constantine(Intel),Juan Orozco(Intel)Bryan Kelly(Microsoft),Zbigniew Lukwinski(Intel)Co-authors:2|2023 SNIA.All Rights Reserved.

2、AgendaSMBus LimitationsI3C-based SolutionExperimentationSummary&Call to Action3|2023 Storage Developer Conference.Intel,Solidigm,Microsoft.All Rights Reserved.SMBus Limitations4|2023 SNIA.All Rights Reserved.SMBus/I2C Sideband Management Overview SMBus/I2C sideband interface used by all PCIe/CXL for

3、m factors,incl.storage No common I2C/SMBus addressing architecture ARP expected by CEM Spec but often not implemented(ARP optional in SMBus spec)system vendors maintain address databases to avoid collisions vendor-dependent proprietary solutions used instead,typically involving I2C/SMBus MUX Securit

4、y expectations drive MUX-based architectures prevents peer-to-peer communications Legacy use cases simple communication driven by only BMC with quick responses by endpoints(FRU read,temp sensor,etc.)low bandwidth sufficient(typically 100kHz)BMCMUXEndpoint 2Endpoint 1Endpoint 3SMBusSMBus5|2023 SNIA.A

5、ll Rights Reserved.MCTP over SMBus w/MUX&Advanced Use Cases Dont Work MCTP over SMBus expects continuous SMBus expectation not valid in systems with MUX SMBus arbitration does not work over MUX-based I2C/SMBus Endpoints try to transmit when MUX switched away eollowing the specifications,due to no AC

6、K,they retry and drop packets after a couple of milliseconds MCTP over SMBus with MUX generally unusable for:long-running tasks(SPDM,etc.)asynchronous communication(alerts,events,notifications,etc.)streaming from endpoint(telemetry,etc.)large MCTP messages fragmented into many MCTP packets(frequent

7、packet losses in these scenarios)MUX switching during ongoing transmission truncated transactions interpreted/consumed with unpredictable consequences many SMBus devices hang due to glitchesEndpoint1MUX switched away to device 2MUX switched inMUXPacket dropBMC6|2023 SNIA.All Rights Reserved.Packet L

8、osses with Typical SMBus MUX Configuration1.Sample successful request-response sequence when SMBus MUX not switched away2.Failure when SMBus MUX switched away to another device2a.Retry every 4.6us(no ACK when SMBus MUX switched away)7|2023 SNIA.All Rights Reserved.Workarounds Today Long running task

9、s or large MCTP messages:BMC waiting idle for endpoint to process the request and respond 100s of milliseconds wasted with every transaction proprietary or higher-protocol control commands pause/resume device responses NVMe-MI standardizes this approach to some extent(with NVMe-MI-specific assumptio

10、ns)retries(usually dont work)no way for the device to be aware of the MUX being switched away retries repeat same sequence with same result every vendor is different No workaround for truly asynchronous communication8|2023 Storage Developer Conference.Intel,Solidigm,Microsoft.All Rights Reserved.I3C

11、-based Solution9|2023 SNIA.All Rights Reserved.Industry Landscape with I3C MIPI I3C Basic natural upgrade to address SMBus/I2C limitations Upgrade details defined in EDSFF specification(SNIA SFF-TA-1009 revision 3.1,published January 6th,2023)Expecting other form factors to follow EDSFF solution SNI

12、A is donating EDSFF I3C solution to other standards organizations to keep specs aligned PCIe Architectural Out-of-Band Management under review MCTP I3C Binding defined by DMTF Common I3C HUB specification(Intel RDC#766079)with standard pinout and registers(HW and SW drop-in compatible)Renesas part n

13、umbers:RG3MxxB12B0 NXP part numbers:P3H2x4x Off-the shelf components already available from multiple vendors10|2023 SNIA.All Rights Reserved.I3C Addresses SMBus Limitations Clear addressing architecture all devices support dynamic address Comprehends MUX-based and MUX-less topologies:BMC is initiato

14、r driving clock(redundancy supported)Only BMC performs packet writes and reads Endpoints do not initiate transactions BMC optionally enables IBIs from endpoints(useful in MUX-less topology or with HUB)Improves security:peer-to-peer communications must go thru I3C Controller(typically BMC)Other impro

15、vements:supports in-band interrupts(IBIs)supports in-band reset/recovery 12.5Mbps in SDR mode,25Mbps in DDR mode11|2023 SNIA.All Rights Reserved.MCTP I3C Binding(DSP0233)Single I3C Controller only BMC initiates read/write transactions works well even with traditional MUXes Optional IBIs improve effi

16、ciency but no data loss if dropped I3C CCCs to standardize behaviors,e.g.:discover capabilities(e.g.,protocol)MTU negotiation IBI enable/disable Binding improves robustness over pure MIPI I3C Basic added error detection and recovery mechanismsBus Controller(typically BMC)Endpoint112|2023 SNIA.All Ri

17、ghts Reserved.I3C Discovery Flow as per EDSFF Specification Discover if any I3C-capable devices are attached Using I3C reserved 0 x7E address Discover if any SMBus-only devices are attached using ARP or static address scan Stay in SMBus mode if at least one SMBus-only device present on targeted EDSF

18、F port I3C-capable devices still must be backwards compatible MCTP over SMBus binding in use Switch to I3C if all devices on targeted EDSFF port support I3C transition to lower voltage MCTP over I3C binding in use Each downstream port can operate at either I3C or SMBus independently SMBus ModeHost:D

19、id a device ack?Host:Broadcast 0 x7E DISEC hotjoin DISHJ SMBus VoltageYes(ACK)Host:Broadcast 0 x7E ENEC hotjoin ENHJ I3C Basic Voltage/FrequencyHost/Device:I3C Basic I3C Basic voltage/frequencyHost:Initialize I3C Basic?YesNoHost:SMBus device discovery.Static address or 0 xC2(for ARP)No(NACK)Host/Dev

20、ice:SMBus SMBus VoltageHost:SMBus pull-ups off,I3C Basic pull-ups onDevice:After 0 x7E transaction,meet Tsmb2i3c.Ready for I3C Basic signalingYes(ACK)Host:Does Host need to reset the I3C Basic interface?Device:ACKNoHost:Redo I3C Basic detection?Hot plug event?YesYesNoHost:Hold SMBCLK/I3CCLK low for

21、T2wrst or through other hardware means(e.g.,SMRST#)Host:I3C Basic pull-ups off,SMBus pull-ups onHost:Does HostNeed to reset the SMBusinterface?NoDevice(I3C Basic):Disable SMBus mode on any 0 x7E transactionDevice:Meet Tdcl and Ti3c2smbDevice:Allow ACK of SMBus addressesHost:Hold SMBCLK/I3CCLK low fo

22、r T2wrst or through other hardware means(e.g.,SMRST#)YesHost:Did a device ack?No(NACK)YesNoHost:SMBus device discoveryHost:SMBus only device discovered?No(no SMBus only devices)YesHost:I3C Basic Target Reset(Optional)Host:Broadcast 0 x7E DISEC hotjoin DISHJ SMBus VoltageHost:ContinueI3C Basic detect

23、ion?Taken from SFF-TA-1009 Rev 3.113|2023 SNIA.All Rights Reserved.I3C HUB Solves SMBus Issues&Enables Transition to I3C No arbitration or address issues for legacy SMBus downstream port SMBus agent allows asynchronous and bi-directional communication with multiple SMBus endpointsno endpoint devices

24、 changes needed to avoid SMBus limitations SMBus agents enable concurrent and independent communication on each port supports“SMBus busy signaling”for flow control to prevent packet losses with protocols such as MCTP no bus switching during transmission as in existing SMBus/I2C Muxes Supports mix of

25、 SMBus and I3C devices downstream ports independently operate in I3C transparent mode or SMBus agent mode port in I3C mode allows for electrical isolation while maintaining same logical I3C network(protocol transparent)supports voltage translation Reduces number of SMBus/I3C ports needed on BMCs up

26、to 8 downstream ports two upstream ports(allowing upstream device redundancy)14|2023 Storage Developer Conference.Intel,Solidigm,Microsoft.All Rights Reserved.ExperimentationIntel,Solidigm,Aspeed,Renesas,Introspect,Microchip,Microsoft,Total Phase,and Aardvark registered and unregistered trademarks,s

27、ervice marks,and logos are the property of their owners.Unauthorized use is strictly prohibited.15|2023 SNIA.All Rights Reserved.MotherboardProdigyI3C GeneratorNVMe Drive Back PlaneI3C HUBController Port1I3C HUBController Port1Controller Port0CP0_VCCIOCP1_VCCIOT Port0T Port1T Port2T Port3TP_VCCIO0TP

28、_VCCIO1Controller Port0CP0_VCCIOCP1_VCCIOT Port0T Port1T Port4T Port5T Port2T Port3T Port6T Port7NVMe Drives(I3C or SMBus)TP_VCCIO0TP_VCCIO1I2C devices(EEPROM,Temp Sensor)NVMe Drive Back PlaneI3C HUBController Port1Controller Port0CP0_VCCIOCP1_VCCIOT Port0T Port1T Port4T Port5T Port2T Port3T Port6T

29、Port7NVMe Drives(I3C or SMBus)TP_VCCIO0TP_VCCIO1CP_SEL/RSTI2C devices(EEPROM,Temp Sensor)NVMe Drive Back PlaneI3C HUBController Port1Controller Port0CP0_VCCIOCP1_VCCIOT Port0T Port1T Port4T Port5T Port2T Port3T Port6T Port7NVMe Drives(I3C or SMBus)TP_VCCIO0TP_VCCIO1CP_SEL/RSTI2C devices(EEPROM,Temp

30、Sensor)VDDINVDDINVDDINVDDINI3C HUBController Port1Controller Port0CP0_VCCIOCP1_VCCIOT Port0T Port1T Port4T Port5T Port2T Port3T Port6T Port7TP_VCCIO0TP_VCCIO1VDDINPCIe CEMPCIe CEMI3C Electricals in typical Storage back plane 2-wire(I3C/SMBus)Channel Topologies5”CableDevice ConnectivityPhysical Topol

31、ogy1st Back Plane2nd Back Plane3rd Back Plane1st Back Plane2nd Back Plane3rd Back PlaneMotherboard16|2023 SNIA.All Rights Reserved.I3C Electricals in typical Storage back plane 2-wire(I3C/SMBus)Channel TopologiesI3C SCL on 1st Back PlaneI3C SCL on 2nd Back PlaneI3C SCL on 3rd Back PlaneI3C IO Voltag

32、e:1.8VI3C Open Drain Frequency:100KHzI3C Push-pull Frequency:10MHzOperating Conditions:Typical silicon,temp,voltage 17|2023 SNIA.All Rights Reserved.System Architecture for PCIe/CXL BMC with I3C Controller(Aspeed AST2600)OpenBMC FW with MCTP over I3C binding support HUB(Renesas RG3M87B12)Enables SMB

33、us to I3C transition as per EDSFF SFF-TA-1009 specification Fixes MCTP over SMBus multi-initiator related challenges with multiplexers Common HUB specification(drop-in compatible devices from multiple sources)I3C-capable device(Microchip PIC18F16Q20)Supports MCTP over I3C binding with sample command

34、s Legacy SMBus device(emulated with Total Phase Aardvark)Unaware of I3C Unable to work efficiently with multiplexed SMBus(separate experimentation)Introspect SV4E logic analyzerI3C-capable Solidigm SSDIntel Reference BoardBMCAspeed AST2600HUBRenesas RG3M87B12Microchip PIC18F-Q20MicrocontrollerI3C2-w

35、ire busLogic Analyzer(trace capture)probeSMBus-only DeviceTotal Phase Aardvark Experimentation Setup18|2023 SNIA.All Rights Reserved.Experimentation Flow with only I3C-capable Devices1.DISEC in SMBus mode(I3C-capable device ACKs)2.SMBus discovery2a.No SMBus device ACKed3.DISEC in SMBus mode(triggers

36、 switch to I3C mode)4.Voltage transition 3.3V to 1.8V(I3C transactions follow next slides)19|2023 SNIA.All Rights Reserved.Experimentation MCTP request and response in I3C modewith IBII3C-capable device responds in I3C modeRequest+IBI+ResponseRequestIBI+Response20|2023 SNIA.All Rights Reserved.Exper

37、imentation MCTP request and response in I3C mode with pollingI3C-capable device responds in I3C modeRequest+2 x GETSTATUS+ResponseRequestResponseGETSTATUS21|2023 Storage Developer Conference.Intel,Solidigm,Microsoft.All Rights Reserved.Summary&Call to Action22|2023 SNIA.All Rights Reserved.Summary&C

38、all to Action Experimentation confirmed off-the-shelf devices enable backward-compatible transition from SMBus to I3C and address key SMBus limitations MCTP over I3C works well regardless of system architecture MCTP over SMBus works well when MUX is replaced by I3C HUB no endpoint device changes nee

39、ded Adopt consistent(and backward-compatible)solution in other industry specifications PCI-SIG:PCI-SIG Protocol WG Sideband Ad-hoc WG,U.2/SFF,M.2 OCP:Datacenter NVMe SSD Specification,Datacenter Secure Control Module(DC-SCM)2.0,OCP NIC 3.0,OCP Firmware Recovery,DC-MXIO/DC-MHS,OCP OAI/UBB/OAM,Make your product plans!Intels reference platform HW ready now,OpenBMC FW aligned with PCIe 6.0 Solidigm ready to co-validate with additional partners in 202423|2023 SNIA.All Rights Reserved.Please take a moment to rate this session.Your feedback is important to us.