Session 32Isolated Power and Gate Drivers.pdf

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1、Session 32 Overview:Isolated Power and Gate Drivers POWER MANAGEMENT SUBCOMMITTEEIsolated Power and Gate Drivers are critical f or ensuring saf ety and reliability in harsh industrial environments,such as electric vehicles and industrial automation.This session aims to showcase some of the best work

2、 in the isolated power and gate drivers area,f eaturing novel topologies that of f er high conversion ef ficiency,reduced electromagnetic interf erence(EMI),and advanced power regulation f or isolated converters,as well as precise gate control techniques f or GaN gate drivers.Session Chair:Lin Cheng

3、 University of Science and Technology of China Hef ei Anhui,China Session Co-Chair:Shusuke Kawai Toshiba,Kawasaki,Japan 526 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE4:50 PM 32.4 A Dual-L

4、C-Resonant Isolat ed DC-DC Convert er Achieving 65.4%Peak Efficiency and Inherent Backscat t ering Qiao Huang,University of Science and Technology of China,Hef ei,China In Paper 32.4,University of Science and Technology of China presents a dual-LC-resonant isolated DC-DC converter incorporating inhe

5、rent backscattering,which enhances ef ficiency and eliminates the need f or a digital isolator.The design achieves 65.4%peak ef ficiency and 1.5W maximum output power.5:05 PM 32.5 A 2W 53.2%-Peak-Efficiency Mult i-Core Isolat ed DC-DC Convert er wit h Embedded Magnet ic-Core Transformer Achieving CI

6、SPR-32 Class-B EMI Compliance and 5mV Ripple Dongf ang Pan,University of Science and Technology of China,Hef ei,China In Paper 32.5,University of Science and Technology of China and Hef ei CLT Microelectronics present a multi-core isolated DC-DC converter with an embedded magnetic-core transf ormer

7、to reduce EMI and output voltage ripple.The design achieves 53.2%peak ef ficiency and less than 5mV ripple while meeting CISPR-32 Class-B EMI compliance.5:20 PM 32.6 A Dynamic-RON-Diminished Bidirect ional GaN Load Swit ch wit h Inrush Current Prot ect ion and Spike At t enuat ion Po-Jui Chiu,Nation

8、al Yang Ming Chiao Tung University,Hsinchu,Taiwan In Paper 32.6,National Yang Ming Chiao Tung University,Chip-GaN Power Semiconductor,Realtek Semiconductor,and Taiwan Semiconductor Research Institute present a GaN load switch f or bidirectional current transf er and reverse current blocking.It achie

9、ves 91.4%inrush current reduction and 89.5%overshoot reduction.4:25 PM 32.3 An Accurat e Secondary-Side Cont roller wit h GaN-Based CGS Isolat ed Driver Achieving Sub-1%Error On-Chip Sensing Chi-Yu Chen,National Yang Ming Chiao Tung University,Hsinchu,Taiwan In Paper 32.3,National Yang Ming Chiao Tu

10、ng University,Chip-GaN Power Semiconductor,Realtek Semiconductor and Taiwan Semiconductor Research Institute present a GaN-based CGS isolated driver f eaturing an accurate secondary-side controller f or precise dead-time control.It achieves less than 3ns delay to turn on/of f GaN-based rectifiers.IS

11、SCC 2025/February 19,2025/3:35 PM527 DIGEST OF TECHNICAL PAPERS 4:00 PM 32.2 A Single-Link Mult i-Domain-Out put (SLiMDO)Isolat ed DC-DC Convert er wit h Passive Magnet ic Flux Sharing for Local Energy Dist ribut ion and Rx Behavior Sensing-Based Global Power Modulat ion Jianqiang Jiang,Iowa State U

12、niversity,Ames,IA In Paper 32.2,Iowa State University introduces a single-link multi-domain-output(SLiMDO)isolated DC-DC converter,providing two regulated outputs and achieving global power modulation via a single FPC micro-transf ormer with passive magnetic flux sharing and Rx behavior sensing.The

13、design achieves 62.6%peak ef ficiency at 610mW and 1.13W maximum output power.3:35 PM 32.1 A 180MHz 45.3%-Peak-Efficiency Isolat ed Convert er Using Q-Downsize Class-D Power Amplifier wit h Inherent Shoot-Through Current Blocking and High Tolerance for Efficiency Despit e Frequency Misalignment s Ti

14、an Xia,University of Macau,Macau,China In Paper 32.1,The University of Macau and Instituto Superior Tecnico/University of Lisboa present an isolated DC-DC converter with a Q-downsize Class-D power amplifier with inherent shoot-through current blocking.The design achieves 45.3%peak ef ficiency and 1W

15、 maximum output power at 180MHz,while meeting CISPR-32 Class-B certification.32528 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/32.1979-8-3315-4101-9/25/$31.00 2025 IEEE32.1 A 180MHz 45.3%-Peak-Efficiency Isolat ed Convert er Using Q-D

16、ownsize Class-D Power Amplifier wit h Inherent Shoot-Through Current Blocking and High Tolerance for Efficiency Despit e Frequency Misalignment s Tian Xia*1,Qiujin Chen*1,Shujing Wang1,Rui P.Martins1,2,Mo Huang1 1University of Macau,Macau,China 2Instituto Superior Tecnico/University of Lisboa,Lisbon

17、,Portugal *Equally Credited Authors(ECAs)Isolated DC-DC converters 1-8 with low electromagnetic interf erence(EMI)are crucial f or system saf ety and reliability in harsh industrial environments.Typically,input-to-output dipole radiation caused by the common-mode(CM)current ICM across the isolation

18、barrier leads to EMI issues(Fig.32.1.1)9.A common practice to reduce dipole radiation is to suppress the variation of CM voltages(VCM)on the transf ormer 1,2,which is achieved by f ully symmetrical transmitter(TX)topologies.Meanwhile,a transf ormer pair with coils routed in opposite directions cance

19、ls magnetic field,f urther improving EMI perf ormance 3.The Class-D power amplifier(PA)topology is symmetrical and ef ficient f or low-f requency applications 4,5.However,due to significant gate drive loss(PG switching f requency fSW),this topology is not a good fit f or high-f requency applications

20、 that benefit f rom smaller passive components.For example,3 reported that its PG contributes 57%of the power loss with a 100MHz fSW.In contrast,the Class-D oscillator 2 is suitable f or high-f requency scenarios because of its gate loss recycling.Yet,when the oscillation nodes voltages VPP and VPN

21、swing between VTHN and VDD|VTHP|(VTHN and VTHP are the threshold voltages of the NMOS and PMOS),the NMOS and PMOS are simultaneously turned on.This results in a large shoot-through current IS-T,that seriously degrades the power conversion ef ficiency(PCE)and may damage the transistors.In 2 the gates

22、 of the transistors are AC-coupled to VPP and VPN with DC-biases of VBP and VBN respectively.This eliminates IS-T at the cost of increased turn-on resistance RON and conduction loss.Increasing the sizes of the power transistors 2 can reduce RON,but this leads to increased silicon area and lower osci

23、llation f requency.A symmetrical Q-downsize Class-D PA is proposed to address these issues.Figure 32.1.1 presents the schematic,consisting of two cross-coupled(passively-driven)MOS pairs MP1,2 and MN1,2,along with f our actively-driven switches DP1,2 and DN1,2.The sizes of DP1,2 and DN1,2 are much s

24、maller compared to MP1,2 and MN1,2.Theref ore,this topology essentially downsizes the charge of the power transistors f rom a conventional PA.Additionally,the two inductors L1 and L2 that are placed between the cross-coupled pairs blocks IS-T.These inductors,coupled to the secondary coils,transf er

25、power to the receiver(RX).Compared to 2,this topology does not require lowering the bias voltages to avoid IS-T,leading to a reduced conduction loss.The Q-downsize topology achieves a simulated 72.7%TX PCE with VDD/VOUT=5V/5V and POUT=1W,at targeted 180MHz switching f requency(fSW),while 2 presented

26、 a 71%TX PCE with the same conditions,but at 90MHz fSW.The PCE of the Q-downsize scheme should improve f urther at a lower fSW.Figure 32.1.2 illustrates the working principles of the Q-downsize scheme.For simple understanding,we directly connect the switching nodes VN1-2 and VP1-2 to the gate of MN2

27、-1 and MP2-1,respectively,and assume the swings of the switching nodes do not overstress the power transistors.Additionally,we assume simultaneous turn-on and turn-of f of power switches at the same side(e.g.MN1 and MP1).We divide the PA operation into 6 states:states 1 to 3 and their complementary

28、states C1 to C3.In state 1,the gate drive signal S=0,turning of f MN1,DN1,MP1 and DP1.During this state,L1 recycles the charge f rom the capacitance at VN1(CN1)to that at VP1(CP1),making VN1 VDD|VTHP|,thus turning of f MN2 and MP2.Meanwhile,DN2 and DP2 are turned on and they conduct L2 energizing cu

29、rrent.When VN1 reaches 0 and VP1 reaches its peak value,we set S=1,transitioning the PA to state 2.In this state,DN1 and DP1 are turned on,energizing L1.DN2 and DP2 are turned of f,allowing L2 to resonate with the capacitance at VN2 and VP2(CN2 and CP2).MN1 and MP1 remain of f during this state,and

30、thus DN1 and DP1 conduct L1 energizing current.When the resonating VN2 and VP2 exceed their VTHs,the PA enters state 3,where MN1 and MP1 are turned on to conduct most of the inductor current IL1.State 3 lasts until the resonating VN2 and VP2 f all back to their VTHs,f ollowed by the complementary st

31、ates C1,C2,and C3.With cross connections,the power transistors MN1-2,MP1-2 are passively driven,with their gate charge QP recycled.The actively-driven transistors DN1-2 and DP1-2 have gate drive loss.However,DN1-2 and DP1-2 only conduct inductor currents in states 1,2,C1,and C2,which together occupy

32、 a small portion of the entire switching cycle due to the sinusoidal shape of both VN1 and VN2.Consequently,we choose small sizes f or DN1-2 and DP1-2.The ratio of AA to AA+AP is denoted as,where AA and AP are the total areas of the actively-driven and the passively-driven transistors,respectively.T

33、he optimum value(OPT)arises f rom the derivative of the total transistor power loss PLOSS/|=OPT=0.Eq.1 gives the expression of PLOSS 10,including conduction loss(inversely proportional to area)and switching-related loss(proportional to the area)f or both the actively-and the passively-driven transis

34、tors.The Q-downsize scheme eliminates the high switching-related loss(the bAPfSW term in eq.1)of the passively-driven transistors.The calculated OPT 1(T3/T)3,where T is the total duration of states 1-3(or C1-C3),and T3 is the duration of state 3(or C3).Incorporating the process parameters,OPT is aro

35、und 1:4 in this design.The Q-downsize scheme is analogous to using a downsized ef f ort(QA),to push a huge boulder(weighing QP)f rom one of the unstable equilibrium points(determined by the cross-connected MN1-2,MP1-2)to the other one,and then pushing it back again.It is interesting to investigate w

36、hether negative ef f ects exist in the presence of misalignment between fSW and oscillation f requency fOSC.As shown in Fig.32.1.3,when fSW fOSC,the durations of state 1 and C1 are shortened or even eliminated.Although this leads to non-ZVS in DN1-2 and DP1-2 as well,the current conducted by DN1-2 a

37、nd DP1-2 is greatly reduced,mitigating the PCE degradation.Figure 32.1.3 depicts the simulated PCE versus fSW,with POUT=0.5W and VDD/VOUT=5V/5V.The PCE peaks around 175MHz(fOSC),while it drops significantly when fSW 100m f rom EM simulations.This leads to great power loss especially in heavy-load co

38、nditions.Figure 32.1.4 shows the measured steady-state wavef orms of the 5V output voltage VOUT and the hysteresis output ENRX at VDD=5V and POUT=0.5W.Zoomed-in wavef orms reveal that the measured VCM is less than 400mV,due to the symmetrical structure.This enhances EMI perf ormance.Figure 32.1.4 al

39、so presents the measured PCE of the Q-downsize converter at VOUT=5V and fSW=180MHz with dif f erent VDD values.The converter achieves a peak PCE of 45.3%at POUT=0.5W and maintains a 42%PCE at a maximum 1W POUT.Simulations show that the PCE at 1W POUT is improved by more than 3%if we double the numbe

40、r of bond wires connected to each transf ormer terminal.Moreover,Fig.32.1.4 depicts the measured PCE with f requency misalignments.The PCE peaks at fSW=180MHz and it decreases by 2.7%when the fSW is 20MHz higher,while it drops significantly when fSW 1W Isolated Power Transf er System Using Fully Int

41、egrated Magnetic-Core Transf ormer,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e -(I SSCC),San Francisco,CA,USA,pp.244-246,Feb.2019.5 Y.Zhuo et al.,“A 52%Peak Ef ficiency 1-W Isolated Power Transf er System Using Fully Integrated Transf ormer With Magnetic Core,”I EEE J ourna l of

42、Sol id-Sta te Circ uits,vol.54,no.12,pp.3326-3335,Dec.2019.6 W.Qin et al.,“An 800mW Fully Integrated Galvanic Isolated Power Transf er System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e -(I SSCC),San Francisco,CA,USA,pp.246

43、-248,Feb.2019.7 T.Hu et al.,“A 750mW,37%Peak Ef ficiency Isolated DC-DC Converter with 54/18Mb/s Full-Duplex Communication Using a Single Pair of Transf ormers,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),San Francisco,CA,USA,pp.504-506,Feb.2024.8 T.Hu et al.,“An Isolated

44、 DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transf ormers,”I EEE J ourna l of Sol id-Sta te Circ uits,early access.9 Analog Devices,AN-0981,“Recommendations f or Control of Radiated Emissions with isoPower Devices”,Rev.C,Accessed on Nov.27,2021.10 B.J.Baliga,“Power semicon

45、ductor device figure of merit f or high-f requency applications,”I EEE El e c tron De vic e Le tte rs,vol.10,no.10,pp.455-457,Oct.1989.530 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/32.2979-8-3315-4101-9/25/$31.00 2025 IEEE32.2 A Sin

46、gle-Link Mult i-Domain-Out put (SLiMDO)Isolat ed DC-DC Convert er wit h Passive Magnet ic Flux Sharing for Local Energy Dist ribut ion and Rx Behavior Sensing-Based Global Power Modulat ion Jianqiang Jiang,Lei Zhao,Junyao Tang,Cheng Huang Iowa State University,Ames,IA Galvanically isolated DC-DC con

47、verters are gaining more attention in industry f or industrial automation and electrical vehicles(e.g.,motor drives,battery management systems),consumer electronics(e.g.,power adapters,gate drivers f or hybrid converters),grid-tied devices,and medical applications.They are used to provide protection

48、 between domains while being able to transmit power through the isolation barrier.With the increase of system complexity,multiple outputs with each operating at a dedicated domain are widely used,e.g.f or high-/low-side/floating gate drivers f or converters or motor drivers,and sensor/control/commun

49、ication circuits at dif f erent modules/packs f or battery management systems,etc.Only 1 can provide two outputs with a single micro-transf ormer,however,its outputs are at the same domain.For miniaturization,recent research has led to developing in-package solutions with micro-transf ormers 1-10.Th

50、e transf ormer designs in 2-6 require special process,increasing the cost,while the power ef ficiency is limited due to the relatively low quality and inductance,thus leading to higher conduction and switching losses(100MHz f or 3,8).In terms of closed-loop control,early designs 2-5 typically utiliz

51、ed Pulse Width Modulation(PWM)or Pulse Frequency Modulation(PFM)f or power regulation.However,additional digital isolators are required to transmit control signals between the transmitter(Tx)and the receiver(Rx).The work in 1 introduced discrete f requency modulation(DFM)with Rx output rotation f or

52、 Tx power control and Rx voltage regulation.However,the rotation relied on communications between the two Rx outputs within the same domain,and digital isolators were also required between Tx and Rx.As shown in Fig.32.2.1,in this work,we propose a single-link multi-domain-output(SLiMDO)isolated DC-D

53、C converter,achieving:1)multi-domain outputs(two outputs in this prototype)sharing one single power micro-transf ormer;2)these outputs are locally regulated at Rx with automatic energy distribution through passive magnetic flux sharing;3)the Tx power is globally modulated by sensing Rx inherent beha

54、vior without Rx actively generating control signals in steady state.This does not require dedicated digital isolators but it is instead controlled through the power micro-transf ormer,managing both Rx outputs simultaneously;4)the micro-transf ormer is f abricated using standard polyimide-based 2-lay

55、er 130m-thick flexible printed circuits(FPC)and it f eatures three windings:one on the primary side connected to the Tx,and two interleaved on the secondary side,each connected to an Rx;5)the converter measures 62.6%peak ef ficiency around 600mW and a maximum power of 1.13W;and 6)the converter also

56、achieves a decent load transient response.Figure 32.2.2 illustrates the detailed block diagram of the proposed SLiMDO converter.The Tx chip converts DC to AC with a H-bridge power stage driving an LLC resonant tank f or energy transmission across the isolation barrier via the micro-transf ormer.The

57、DFM module provides 17 power levels with dif f erent switching f requencies ranging f rom 7.6MHz to 23.8MHz to regulate the global power.The two Rx chips are identical,each consisting of a f ull-bridge active rectifier that can operate in one of three modes(normal,open and short)that are used f or l

58、ocal voltage regulation and transient enhancement.These three modes are sensed by the Tx chip through the power link f or global power modulation and will be discussed later.Both Rx chips share an identical three-mode control scheme.Norma l Mode:when Vout is below the preset ref erence Vref,each Rx

59、f unctions as a typical active rectifier that receives power in every cycle and converts VAC f rom the coil to DC Vout f or each domain.Ope n Mode:when Vout rises above Vref due to excess power,MP1,MP2,MN1,and MN2 are turned of f to stop receiving power and to prevent Vout f rom increasing f urther

60、until Vout is no longer higher than Vref.Short Mode:if Vout drops below a lower threshold Vtr it is used to trigger the Tx to operate at the max-power level to suppress voltage droops during significant load transients.The short mode lasts f or only 1 clock period and then operation returns to norma

61、l mode automatically.During short mode,MP1 and MP2 are turned of f while MN1 and MN2 are turned on,f orming a closed current loop with the coil,causing a significant impedance change that is reflected to the Tx chip,allowing the Tx side to sense short mode and respond accordingly.When there are mult

62、iple output domains,the energy is automatically shared through the interleaved coils as passive magnetic flux sharing(PMFS).That is,if either output has a lighter load,say Rx1 f or instance,Vout1 will eventually exceed Vref 1 and enter open mode due to excess power.According to Lenzs law,the magneti

63、c field generated by the Rx current always opposes the original magnetic field generated by the Tx.When Rx1 enters open mode,The disappearance of the induced current leads to an increase in the total magnetic flux and also a change in the/rate,thus consequently,a higher electromotive f orce is induc

64、ed in Rx2 because of the shared magnetic flux.Essentially,the energy rejected by the open mode of one Rx will be absorbed by the other Rx,achieving auto balancing without the need f or any active control.Figure 32.2.3 shows the overall operating principle of the proposed through-power-link controlle

65、d DFM.As shown in Fig.32.2.2,the DFM is controlled by three signals:UW(upward),DW(downward),and RS(reset),which cause the system power to increase,decrease,or reset to the maximum power level,respectively.The UW signal is automatically generated by the Tx itself,while the DW and RS signals are gener

66、ated af ter sensing specific behavior of the Rx using the f ollowing mechanism.When there is more power than needed f or both Rx domains,they will eventually enter open mode simultaneously,resulting in a significant increase in reflected load impedance seen at the Tx side.This increase is reflected

67、in a voltage droop across the resonant capacitor voltage,Vcr.A peak voltage tracking circuit is used to sense this change,which consists of two parts.In the first part,an adaptive gain amplifier converts Vcr into a rectified DC half-wave voltage,Vcap.Because the resonant current varies with the tota

68、l transmitted power,Vcr can fluctuate by 100 under dif f erent load conditions.To prevent output voltage distortion and to reduce the dif ficulty of the subsequent peak detection circuit,the amplifiers gain is adjusted dynamically according to the Tx system power level.This ensures that the peak val

69、ue of Vcap remains within the desired range of 0.7-to-2.7V in every cycle.In the second part,a periodic peak detection circuit samples and holds the maximum Vcap value of each cycle to detect the change between every two consecutive cycles.If the peak voltage of the current cycle drops below kDW tim

70、es that of the previous cycle,a DW signal is generated to reduce the systems power level by one.The value of kDW is selected to ensure that only significant voltage drops,caused by both Rx chips entering open mode simultaneously,can trigger the DW signal.This prevents premature power level adjustmen

71、ts bef ore energy balancing is completed through PMFS.On the other hand,if no DW signal is received within a period of tuw af ter the last DW,a UW signal is generated spontaneously to increase the power level by one to make sure there is more than enough power transmitted.The tuw period is dynamical

72、ly adjusted f or ef ficiency optimization by using additional shif t registers and state-machine logic to record the sequence of control signals and identif y then reduce excessive and unnecessary power-level changes.The self-generated UW and Rx-triggered DW signals f orm a hysteresis closed-loop co

73、ntrol that ensures the system operates at or between appropriate power levels during steady state.As f or the RS signal,if either Rx has a significant load transient that triggers its short mode,the Tx-reflected impedance decreases significantly and results in a sharp voltage rise on Vcap.The peak v

74、oltage detector can catch this change and immediately generate an RS signal to increase the Tx power level to its maximum level f or droop reduction.Unlike the DW signal,which requires both Rx chips to be in open mode,the impedance change caused by either Rx in short mode is large enough to trigger

75、an RS signal.Both the Tx and Rx chips are f abricated in 0.18m standard CMOS with 3.3V devices.Figure 32.2.4 shows the measured wavef orms during a 50-to-150mA load transient with Vout1 regulated at 2.8V,while Vout2 is regulated at 3.3V with a fixed 50mA loading,to verif y the closed-loop operation.

76、The measured digital signals indicating the Tx power level adjustments are also shown in Fig.32.2.4.In the wavef orms,“0-15”represent the Tx power levels 0-15,while“31”represents level 16.Figure 32.2.5 shows the measured ef ficiency versus the total output power in two dif f erent voltage configurat

77、ions.With 3.3V/2.8V and 2.8V/2.2V output conditions,the peak ef ficiency is measured to be 62.6%and 57.9%,and the maximum power is measured at 968mW and 1131mW,respectively.Figure 32.2.6 shows the comparison table with prior micro-transf ormer-based works.This work,f or the first time,achieves multi

78、ple-domain outputs using only a single micro-transf ormer.Additionally,both closed-loop voltage regulation f or the isolated Rx outputs and Tx power modulation are achieved through the micro-transf ormer without the need f or dedicated data links.Please note that the input/output voltage range of th

79、is work is limited by the 3.3V process,while the proposed techniques can be extended to higher voltages if needed in dif f erent applications.Due to the identical Rx circuity and the simplicity of the Tx global power modulation,this technique can also be extended to more Rx domains with dif f erent

80、Rx winding designs.Figure 32.2.1:Proposed Single-Link Mult iple-Domain-Out put Isolat ed Convert er.Figure 32.2.2:Syst em block diagram,and t he operat ion principles of t he Rx,Tx,and syst em cont rol of t he proposed SLiMDO convert er.Figure 32.2.3:Timing diagram and t rigger st rat egy of t he pr

81、oposed Rx-behavior-sensing-based DFM cont rol.Figure 32.2.4:Measured waveforms wit h zoom-in st eady-st at e and load-t ransient waveforms.Figure 32.2.5:Measured efficiency in t wo different volt age configurat ions.Figure 32.2.6:Comparison wit h st at e-of-t he-art micro-t ransformer-based designs.

82、ISSCC 2025/February 19,2025/4:00 PM531 DIGEST OF TECHNICAL PAPERS 32 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 32.2.7:Chips and FPC micro-t ransformer phot os wit h measured charact erist ics.Re f

83、e re nc e s:1 J.Jiang,J.Tang,L.Zhao,C.Zhan and C.Huang,“A 63%Ef ficiency 1.29-W Single-Link Multiple-Output(SLiMO)Isolated DC-DC Converter Using FPC Micro-Transf ormer with Local Voltage and Global Power Regulations,”in IEEE Journal of Solid-State Circuits,vol.59,no.3,pp.804-816,March 2024.2 Z.Yue,S

84、.Ma,T.Zhao,W.Qin,Y.Zhao,Y.Guo and B.Chen,A 52%Peak-Ef ficiency 1W Isolated Power Transf er System Using Fully Integrated Magnetic-Core Transf ormer,in I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),Feb.2019.3 L.Li,X.Fang,and R.Wu,“An 11MHz Fully Integrated 5kV Isolated DC-DC

85、 Converter Without Cross-Isolation-Barrier Feedback,”in I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),Feb.2020.4 D.Pan et al.,“A 1.25W 46.5%-Peak-Ef ficiency Transf ormer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Waf er-Level Packaging Achieving 50mW/mm2

86、 Power Density,”in I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),Feb.2021.5 T.Zhao,Y.Zhuo and B.Chen,“An isolated DC-DC converter with f ully integrated magnetic core transf ormer,”2017 IEEE Custom Integrated Circuits Conf erence(CICC),Austin,TX,USA,2017.6 P.Lombardo,V.Fior

87、e,E.Ragonese and G.Palmisano,“A f ully-integrated half-duplex data/power transf er system with up to 40Mb/s data rate,23mW output power and on-chip 5kV galvanic isolation,”2016 I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),Feb.2016.7 D.Pan et al.,“A 1.2W 51%-Peak-Ef ficienc

88、y Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard,”in I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),2022.8 T.Hu,M.Huang,R.P.Martins and Y.Lu,“A 750mW,37%Peak Ef ficiency Isolated DC-DC Converter w

89、ith 54/18Mb/s Full-Duplex Communication Using a Single Pair of Transf ormers,”2024 I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),Feb.2024.9 Texas Instruments Datasheet,ISOW784x High-Perf ormance,5000-VRMS Reinf orced Quad Channel Digital Isolators with Integrated High-Ef fi

90、ciency,Low-Emissions DC-DC converter,.Available online.10 Analog Devices,ADuM6020/ADuM6028:low emission,5 kV isolated DC-to-DC converters,Available online.532 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/32.3979-8-3315-4101-9/25/$31.00

91、 2025 IEEE32.3 An Accurat e Secondary-Side Cont roller wit h GaN-Based CGS Isolat ed Driver Achieving Sub-1%Error On-Chip Sensing Chi-Yu Chen1,Tz-Wun Wang1,Po-Jui Chiu1,Yu-Ting Huang1,Xiao-Quan Wu1,Chien-Wei Cho1,Sheng-Hsi Hung1,Yu-Tse Shih1,Ke-Horng Chen1,Kuo-Lin Zheng2,Ying-Hsi Lin3,Shian-Ru Lin3,

92、Tsung-Yen Tsai3,Hann-Huei Tsai4 1National Yang Ming Chiao Tung University,Hsinchu,Taiwan 2Chip-GaN Power Semiconductor,Hsinchu,Taiwan 3Realtek Semiconductor,Hsinchu,Taiwan 4Taiwan Semiconductor Research Institute,Hsinchu,Taiwan LLC resonant converters are commonly used as f ront-end converters in se

93、rvers and electric vehicle chargers due to their sof t-switching capabilities,including zero-voltage switching(ZVS)and zero-current switching(ZCS)1-5.Conventional synchronous rectifiers(SR)use power switches to increase ef ficiency by replacing diodes 6-8 to handle root-mean-square(RMS)currents up t

94、o 11A.However,due to the high on-resistance(Ron)of high-voltage Bipolar-CMOS-DMOS(BCD)power switches,the ef ficiency gain is only 1.8%.In contrast,a Gallium Nitride(GaN)-based SR can f urther reduce power loss to 2.0%,but the lack of a body diode increases losses during dead time(Fig.32.3.1 top lef

95、t)9,10.Additionally,GaN-based rectifiers are typically made larger to reduce Ron and prevent current collapse.Theref ore,a driver with strong driving capability,zero delay,and precise sensing f or SR on/of f timing is essential.Conventional drivers in 11-13 have three key issues(Fig.32.3.1 top middl

96、e).First,the large parasitic capacitance CGS of the rectifier MREC limits the slew rate of VG,which extends the entire turn-on transition in 11-13.Second,the gate-source voltage(VGS)of M2 is reduced by the diode D1,preventing M2 f rom f ully turning on 12,13.Third,the constant current VTH,D/R constr

97、ains the charge-sharing process f rom Cboot1 to CGS2,extending the turn-on time of M2 13.Even with a well-controlled delay,the sensing circuits determining MREC on/of f timing are crucial f or managing dead time.Theref ore,a precise ZCS mechanism is needed to generate the driving signal(Fig.32.3.1 t

98、op right).However,the bulky current transf ormer(CT)on the power line induces additional conduction loss and reduces power density 14.Another sensing method involves using a current mirror to replicate and downscale the current in ML and convert it to a voltage signal with a resistor 15.However,this

99、 resistor causes a mismatch in VGS between ML and MREP,meaning that the current through ML may not be an exact multiple of the current through MREP.Additionally,the Ron of MREP has nonlinear variations,causing VCS to inaccurately reflect the actual current passing through ML.The timing diagram(Fig.3

100、2.3.1 bottom lef t)highlights an issue in ZCS control:if the rectifier turns of f prematurely due to a sensing error,significant reverse conduction loss occurs,reducing ef ficiency and creating a hot spot in the SR.Conversely,if the rectifier turns of f late due to a driver delay,a shoot-through cur

101、rent is dissipated by the SR f rom VOUT to ground.The bottom right of Fig.32.3.1 shows the LLC converter with the GaN-based accurate on/of f SR control(AOSC).The AOSC is composed of a tri-enhancement GaN driver(TGD)with a delay of less than 3ns,which can turn on/of f the GaN-based SR correctly.Furth

102、ermore,the error-eliminated GaN sensor(EGS)can accurately sense the current without adding extra losses,reducing the sensing error to less than 1%.Finally,the zero-crossing GaN detector(ZGD)can compensate f or driver delay,f urther enhancing ef ficiency during dead time.The TGD driver shortens the t

103、urn-on transition and guarantees suf ficient turn-on voltage with the inclusion of three improvements(Fig.32.3.2 upper lef t).The top right of Fig.32.3.2 shows the CGS isolated technique,through which Vboot branches of f f rom the gate node VG of MREC,preventing CGS f rom clamping the slew rate of V

104、boot.Since the slew rate of Vboot is not limited by CGS,the gate node of ME3 that is connected to the top plate of Cboot1 increases significantly f aster than the source node VG.ME3 can provide more drive current during the conduction period by temporarily increasing its VGS.Theref ore,the turn-on t

105、ransition is shortened.The Vdiode shedding improvement is shown in the bottom lef t of Fig.32.3.2.Due to Vdiode,the pull-up switches ME2 and ME3 cannot be f ully turned on,limiting the driving current.Thus,VC1 in 12 is connected to the gate of ME4 with 2VDD-VTH to charge Cboot1 to VDD when the VPWM

106、is low,which guarantees that ME2 and ME3 are f ully turned on without being degraded by Vdiode in 12,13 when VPWM changes.The last improvement is the Ron degenerated accelerator(Fig.32.3.2 bottom middle).The constant current source VTH,D/R in 13 is replaced with a low-Ron GaN switch ME1 to accelerat

107、e the charge-sharing process f rom Cboot1 to the total gate-source capacitance CTOT.Prior art 11 requires an additional pre-driver to generate a gate voltage of 3VDD-2VTH,but the pre-driver increases the propagation delay.Conversely,the Ron degenerated accelerator locally generates and increases the

108、 gate voltage to 3VDD-VTH to recover the VTH voltage loss,eliminating the additional delay of the pre-driver.Besides,the VGS of ME1 is always clamped by Cboot2,so ME1 will not be overstressed either in steady state or during the on/of f transitions.The driver comparison with and without three improv

109、ements is shown in the bottom right of Fig.32.3.2,and the driving capability of the TGD is verified by the measured delay of 2.97ns,which reduces the delay by 60%.The EGS can accurately sense the current IREC of MREC without any additional conduction loss(Fig.32.3.3 top lef t).The single-stage high-

110、gain operational-amplifier(SHO)tracks the dif f erence between VP and VN,which detects the real-time current IREC that flows through Ron of MREC.To balance the input terminals VP and VN of the SHO,the sensing current ISEN flows through MREP2,which has an Ron that is m times larger than MREC,and f or

111、ces VP and VN to the same voltage level.Thus,the ratio of ISEN and IREC is 1/m since the Ron ratio of MREP2 and MREC is m.The EGS is activated immediately when VPWM and VZVS are both at a high level(Fig.32.3.3 upper right).The high level of VZVS ensures VD is equal to or lower than 0V,so the EGS sen

112、ses IREC without being damaged by high-voltage stress 2Vout due to the center-tap transf ormer during the of f time of MREC.Af ter that,the output VCS of the SHO is compared with two dif f erent ref erences VZCS_REF and VOCP_REF,and MREC is turned of f when IREC becomes zero or too large.There are t

113、wo f actors that af f ect the accuracy of EGS;one is the perf ormance of SHO,and the other is the Ron ratio between MREC and MREP2.The SHO adopts a common-gate amplifier due to its high bandwidth and f ast response 16,while the DC gain is also increased to 70dB by the cascaded structure to reduce th

114、e deviation of VP and VN(Fig.32.3.3 bottom lef t).High bandwidth and high DC gain ensure that ISEN can rapidly and accurately compensate VN.The Ron mismatch contributes to the sensing error when VGS mismatch occurs between MREC and MREP2.The VGS of MREC is fixed to VDD,so Ron remains unchanged.Howev

115、er,the VGS of MREP2 changes with the node VN if the gate node VG,REP2 is biased with a constant voltage.Thankf ully,by using a driver with a floating supply VG,REP2 is adjusted according to VN,and the VGS of MREP2 is also kept at VDD(Fig.32.3.3 bottom middle).Moreover,since the charging and discharg

116、ing timing of Csupply is in phase with Cboot1,Vdiode shedding is also applied to remove Vdiode.Thus,the EGS can significantly reduce the sensing error and precisely control the SR turn-of f timing.The I-V curve of MREP2 shown in the lower right corner of Fig.32.3.3 shows dif f erent slopes correspon

117、ding to dif f erent VGS values.Once VGS deviates f rom VDD,two f atal errors will occur.A lower VGS increases Ron and degrades the accuracy.On the contrary,a higher VGS degrades both Ron and the accuracy.Besides,MREP2 will f ace VGS overstress,causing the EGS to malf unction.With the help of the SHO

118、 and the floating supply,IREC can be accurately sensed by the EGS.Even with the short delay in the TGD,the MREC turn-on delay caused by the controller still results in power loss.Thankf ully,the ZGD compensates the delay by comparing VD with a positive threshold value rather than 0V(Fig.32.3.4 upper

119、 lef t).During the dead time of the SR,VD is scaled to generate VSEN,and VZVS_B is pulled low by MD3 af ter VSEN becomes lower than|VTH,D|(Fig.32.3.4 bottom lef t).Thus,when VD equals 0V,VZVS is pulled high to turn on MREC and compensate f or the delay caused by the controller.The power loss due to

120、the delay caused by the controller and driver during the on/of f transition is shown in the upper right of Fig.32.3.4,reaching maximum power losses of 0.26W and 2.3W,respectively,when the delay is 50ns.MREC has a turn-on/of f delay of 2.89ns/3.13ns,reducing power consumption to less than 0.5%even un

121、der heavy load conditions.The error f rom the current sensing also contribute to the power loss(Fig.32.3.4 middle right).Since the EGS reduces the current sensing error to less than 0.65%,the power loss is reduced to less than 0.4%.The lower right corner of Fig.32.3.4 shows the ef ficiency compariso

122、n of the LLC converter with the AOSC and the SR with CT control.The peak ef ficiency is 97.1%,and the ef ficiency is higher than 92%over the whole output loading range by reducing the additional conduction loss that is induced by the CT,the Ron of rectifier,and the imprecise dead-time control.The to

123、p lef t of Fig.32.3.5 shows the measured reverse conduction when MREC1 is turned of f prematurely.The issue also occurs when the MREC1 turn on is delayed since the shape of IREC1 during the on time of MREC1 is symmetric.The power loss is around 0.26W with VD1 dropping to around-2.3V.In contrast,dela

124、ying the MREC1 turn-of f leads to a shoot-through current with a maximum of 6A,causing a power loss of 2.3W(Fig.32.3.5 top right).At VOUT=12V and Iload=10A,the zoomed-in measurement of the MREC1 on/of f transition is also shown,where the delays af ter the zero crossing of VD1 and IREC1 are 2.89ns an

125、d 3.13ns,respectively(Fig.32.3.5 bottom).Thus,less than 0.5%of the power is wasted due to the short-delay driver and accurate sensing circuits.The comparison table in Fig.32.3.6 shows that the LLC converter with the AOSC reaches the lowest voltage conversion ratio of 0.0316 and achieves the highest

126、ef ficiency of 97.1%at Iload=6A.The chip micrograph is shown in Fig.32.3.7 in a 0.5m GaN process.Ac k nowl e dge me nt:The authors would like to thank Jui Jen Wu,Dr.Meng-Fan(Marvin)Chang,and Taiwan Semiconductor Manuf acturing Company(TSMC)Limited Joint Developed Project(JDP)f or their help.Figure 3

127、2.3.1:Issues in convent ional design and t he archit ect ure of LLC convert er wit h AOSC.Figure 32.3.2:Implement at ion of t he TGD and comparison by double pulse t est ing.Figure 32.3.3:Implement at ion and t iming diagram of t he EGS;I-V curve of t he MREC.Figure 32.3.4:Implement at ion and t imi

128、ng diagram of t he ZGD;power loss vs.non-idealit ies;efficiency vs.loading.Figure 32.3.5:Measured waveforms of MREC1 wit h t he non-idealit ies and wit h AOSC.Figure 32.3.6:Comparison t able wit h st at e-of-t he-art works.ISSCC 2025/February 19,2025/4:25 PM533 DIGEST OF TECHNICAL PAPERS 32 2025 IEE

129、E International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 32.3.7:Chip micrograph wit h a GaN area of 2.651.54mm.Re f e re nc e s:1 K.-B.Park,B.-H.Lee,G.-W.Moon and M.-J.Youn,“Analysis on Center-Tap Rectifier Voltage Oscil

130、lation of LLC Resonant Converter,”I EEE Tra nsa c tions on Powe r El e c tronic s,vol.27,no.6,pp.2684-2689,June 2012.2 W.Feng,F.C.Lee,P.Mattavelli and D.Huang,“A Universal Adaptive Driving Scheme f or Synchronous Rectification in LLC Resonant Converters,”I EEE Tra nsa c tions on Powe r El e c tronic

131、 s,vol.27,no.8,pp.3775-3781,Aug.2012.3 C.Fei,Q.Li and F.C.Lee,“Digital Implementation of Adaptive Synchronous Rectifier(SR)Driving Scheme f or High-Frequency LLC Converters With Microcontroller,”I EEE Tra nsa c tions on Powe r El e c tronic s,vol.33,no.6,pp.5351-5361,June 2018.4 M.Li,Z.Ouyang,M.A.E.

132、Andersen and B.Zhao,“Self-Driven Gate Driver f or LLC Synchronous Rectification,”I EEE Tra nsa c tions on Powe r El e c tronic s,vol.36,no.1,pp.56-60,Jan.2021.5 K.-W.Kim,H.-S.Youn,J.-I.Baek,Y.Jeong and G.-W.Moon,“Analysis on Synchronous Rectifier Control to Improve Regulation Capability of High-Freq

133、uency LLC Resonant Converter,”I EEE Tra nsa c tions on Powe r El e c tronic s,vol.33,no.8,pp.7252-7259,Aug.2018.6 Zhang,J.Wang,G.Zhang and Z.Qian,“A Hybrid Driving Scheme f or Full-Bridge Synchronous Rectifier in LLC Resonant Converter,”I EEE Tra nsa c tions on Powe r El e c tronic s,vol.27,no.11,pp

134、.4549-4561,Nov.2012.7 X.Zhu et al.,“A Sensorless Model-Based Digital Driving Scheme f or Synchronous Rectification in 1-kV Input 1-MHz GaN LLC Converters,”I EEE Transactions on Power El e c tronic s,vol.36,no.7,pp.8359-8369,July 2021.8 P.Amiri,C.Botting,M.Craciun,W.Eberle and L.Wang,“Analytic-Adapti

135、ve LLC Resonant Converter Synchronous Rectifier Control,”I EEE Tra nsa c tions on Powe r El e c tronic s,vol.36,no.5,pp.5941-5953,May 2021.9 E.A.Jones,F.F.Wang and D.Costinett,“Review of Commercial GaN Power Devices and GaN-Based Converter Design Challenges,”in I EEE J ourna l of Eme rging a nd Se l

136、 e c te d Topic s in Powe r El e c tronic s,vol.4,no.3,pp.707-719,Sept.2016.10 Y.-Y.Kao et al.,“A Monolithic GaN-Based Driver and GaN Power HEMT with Diode-Emulated GaN Technique f or 50MHz Operation and Sub-0.2ns Deadtime Control,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SS

137、CC),San Francisco,CA,USA,pp.228-230,Feb.2022.11 S.-Y.Lin et al.,“A GaN Gate Driver with On-chip Adaptive On-time Controller and Negative Current Slope Detector,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),Sa n F ra nc isc o,CA,USA,pp.306-308,Feb.2023.12 H.-Y.Chen et al.,“

138、A Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch with Temperature-compensated Fast Turn-on Technique f or Improving Reliability,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),San Francisco,CA,USA,pp.460-462,Feb.2021.13 T.-W.Wang et al.,“Multiple-Phase Accelerate

139、d Current Control in Bidirectional Energy Transf er of Automotive High-Voltage and Low-Voltage Batteries,”I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e (I SSCC),San Francisco,CA,USA,pp.308-310,Feb.2023.14 J.-D.Hsu,M.Ordonez,W.Eberle,M.Craciun and C.Botting,“LLC Synchronous Rectifica

140、tion Using Resonant Capacitor Voltage,”in I EEE Tra nsa c tions on Powe r El e c tronic s,vol.34,no.11,pp.10970-10987,Nov.2019.15 V.-S.Nguyen,R.Escof fier,S.Catellani,M.FaYolle-Lecocq and J.Martin,“Design,implementation and characterization of an integrated current sensing in GaN HEMT device by usin

141、g the current-mirroring technique,”2022 24th Europe a n Conf e re nc e on Powe r El e c tronic s a nd Appl ic a tions(EPE22 ECCE Europe),Hanover,Germany,2022,pp.1-9.16 Y.-T.Hsu,Z.-Y.Lin,J.-J.Lee and K.-H.Chen,“An Envelope Tracking Supply Modulator Utilizing a GaN-Based Integrated Four-Phase Switchin

142、g Converter and Average Power Tracking-Based Switch Sizing With 85.7%Ef ficiency f or 5G NR Power Amplifier,”I EEE J ourna l of Sol id-Sta te Circ uits,vol.56,no.10,pp.3167-3176,Oct.2021.17 M.Kauf mann,M.Lueders,C.Kaya and B.Wicht,“A Monolithic E-Mode GaN 15W 400V Of fline Self-Supplied Hysteretic B

143、uck Converter with 95.6%Ef ficiency,”2020 I EEE I nte rna tiona l Sol id-Sta te Circ uits Conf e re nc e -(I SSCC),San Francisco,CA,USA,pp.288-290,Feb.2020.534 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/32.4979-8-3315-4101-9/25/$31.0

144、0 2025 IEEE32.4 A Dual-LC-Resonant Isolat ed DC-DC Convert er Achieving 65.4%Peak Efficiency and Inherent Backscat t ering Qiao Huang*,Dongf ang Pan*,Zhengyu Chen,Lin Cheng University of Science and Technology of China,Hef ei,China *Equally Credited Authors(ECAs)Power delivery with galvanic isolatio

145、n is crucial f or ensuring saf ety and reliability in harsh industrial environments,where isolated DC-DC converters are widely used to meet stringent operational requirements.Compared with isolated DC-DC converters that use discrete transf ormers and components,integrated DC-DC isolated converters w

146、ith on-chip or in-package transf ormers can significantly reduce both cost and volume.However,these converters of ten suf f er f rom low ef ficiency.Figure 32.4.1 shows a typical isolated DC-DC converter,which consists of a transmitter(TX),a transf ormer(TF),and a receiver(RX).In existing designs,an

147、 LC oscillator is typically employed in the TX 1-3,while a f ull-bridge rectifier is used in the RX 1-6.The simulated power loss breakdown with a typical transf ormer shows ef ficiencies of 91%,81%,and 80%f or each respective part,resulting in an overall ef ficiency of just 59%.Furthermore,when addi

148、tional losses f rom parasitic elements are considered,state-of-the-art designs only achieve a peak ef ficiency of less than 52%4.In addition to these ef ficiency challenges,traditional approaches rely on digital isolators to transmit f eedback signals f rom the RX to the TX f or voltage regulation.W

149、hile ef f ective,this method significantly increases the overall cost of the converter.Some recent works have attempted to eliminate the need f or a digital isolator by implementing voltage regulation solely on the RX side without adjusting the power transmitted f rom the TX 3,or by using backscatte

150、ring with a reconfigurable 1/2 rectifier.Unf ortunately,these approaches have resulted in poor peak ef ficiencies of less than 37%.In this paper,we propose a dual-LC-resonant isolated DC-DC converter that achieves a 65.4%peak ef ficiency and incorporates inherent backscattering.As shown in Fig.32.4.

151、1,the f ull-bridge rectifier in the RX is replaced by another LC oscillator,chosen f or its high ef ficiency.While this might initially seem like using an existing structure in the RX,the underlying operation principle of the proposed topology is f undamentally dif f erent f rom previous designs.Uni

152、quely,the center-tapped point of the secondary coil is defined as the output node(VISO).This dual-LC resonant structure of f ers several significant advantages over the existing topologies.First,both the RX and TX achieve high ef ficiency due to the inherent high ef ficiency of the LC oscillator.Mor

153、eover,as explained later,the proposed operation f urther reduces conduction loss in the LC oscillator,thereby enhancing the overall ef ficiency.Simulation results demonstrate that the RX and TX achieve ef ficiencies of 95%and 94%respectively,under the same condition as conventional topologies,result

154、ing in an overall simulated ef ficiency of 70%a substantial improvement over conventional designs.Second,the proposed topology provides an inherent backscattering f eature f or voltage regulation,eliminating the need f or a dedicated digital isolator and thereby greatly reducing the silicon area and

155、 the design ef f ort.Third,the proposed topology enables a unified power stage f or both TX and RX,allowing a single chip and thus a single mask to be used f or both,f urther reducing cost and simplif ying manuf acturing and testing.Figure 32.4.2 shows the simplified equivalent half-circuit of the p

156、ower stage,utilizing a T-model of the transf ormer.Lr1 and Lr2 are the leakage inductances,while Lm1 and Lm2 are the magnetizing inductances of the primary and secondary coils,respectively.Ca1 and Ca2 represent the equivalent capacitances at node Va1 and Va2(Ca1=Ca2=Ca),respectively.For simplicity,t

157、he parasitic resistances of the transf ormer and the switches are not considered in this analysis.Given the symmetrical structure of the transf ormer,Lr1=Lr2=Lr and Lm1=Lm2=Lm.These inductances have corresponding currents Ir1 and Ir2(f or leakage inductances)and Im1 and Im2(f or magnetizing inductan

158、ces).Due to the ideal 1:1 transf ormer,Im1=Im2=Im and the relationships Ir1=Im+ITF and Ir2=Im-ITF hold,where ITF is the current flowing through the ideal transf ormer.The power stage operates in two phases,1 and 2.During 1,both Ma1 and Ma2 are turned on,causing the inductances Lr1,2 and Lm1,2 to be

159、magnetized.By assuming VIN=VISO,ITF becomes a constant current.Consequently,Ir1(or Ir2)and Im1(or Im2)share the same current slope of VIN/(Lr+Lm)(or VISO/(Lr+Lm).Both Ir1 and Ir2 linearly increase during this phase,with the negative part of Ir2 indicating that the output is being charged.Similar to

160、the operation of an LC tank oscillator,Ma1 and Ma2 are turned of f when Vb1 and Vb2 reach 0V,initiating 2 of the power stage.During 2,both sides are in a resonant state.According to Kirchhof f s Voltage Law(KVL),we can derive the equations f or ITF and Im,respectively.These equations reveal that ITF

161、 corresponds to a resonant circuit consisting of Lr and Ca,thus resulting in an oscillation f requency of fr=1/(2LrCa).Similarly,Im corresponds to a resonant circuit consisting of Lr,Lm and Ca,with an oscillation f requency of fm=1/(2(Lr+Lm)Ca).In f act,the wavef orm of Im resembles that of an LC os

162、cillator,as analyzed in detail in 7,since it essentially f unctions as one.Meanwhile,Ir1 and Ir2 are derived by adding or subtracting ITF f rom Im.As derived in 7,the oscillation f requency of the power stage is fosc=fm/1.3,and fr is pref erably designed to be 4fm/1.3 by properly selecting the coupl

163、ing coef ficient k of the transf ormer,where k is around 0.8 in this design.Although we assume VIN=VISO in the above analysis,this condition is not always required f or operation.Moreover,due to the ITF current,Vb1 and Vb2 remain at a high voltage level f or a longer duration,ef f ectively increasin

164、g the gate voltages of Ma1 and Ma2.This reduces the conduction resistances of Ma1 and Ma2 during 1,thereby minimizing conduction loss and f urther improving the ef ficiency of the LC oscillator compared with previous designs.Figure 32.4.3 illustrates the operating principle of the proposed hysteresi

165、s control using inherent backscattering f or voltage regulation,which is divided into f our states.In State 1,the converter operates as previously discussed to charge VISO.When VISO exceeds the high threshold voltage(VH),the signal ENRX is triggered f rom“1”to“0”,causing the converter to enter State

166、 2.In State 2,Mc2 is turned of f,and MFSK is turned on,shorting the RX resonator,which reduces the slope of Im in 1.This action results in a significant shif t in the oscillation f requency f rom fm to fr.The f requency shif t is detected by a f requency detector in the TX side,which in turn trigger

167、s the signal ENTX to switch f rom“1”to“0”,ef f ectively shutting down the TX by turning of f Mc1.The converter then enters State 3,where only MFSK remains on,and VISO is discharged by the load current.As VISO f alls below the low threshold voltage(VL),ENRX changes back to“1”,leading the converter in

168、to State 4.In State 4,MFSK is turned of f,and MC2 is turned on to initiate oscillation in the RX.This oscillation is coupled back to the TX and it is detected,which subsequently turns on Mc1 to return to State 1,activating the oscillation in the TX and allowing power to be transmitted to the RX.Than

169、ks to the proposed topology,the inherent backscattering f eature eliminates the need f or a dedicated digital isolator f or signal transmission.The chip was f abricated in a 0.18m BCD process that is used f or both TX and RX.Two copies of the chip are assembled with a pair of PCB transf ormers using

170、 1oz copper and an 80m FR4 insulator as a proof of concept.Figure 32.4.4 shows the measured steady-state wavef orms of the output voltage VISO and the ENTX signal at VIN=5V when the output powers POUT are 0.15W and 1.35W,respectively.With an output capacitor of 10F,the measured VISO shows ripples of

171、 95mV and 97mV,respectively.Figure 32.4.4 also shows the measured load-transient responses when POUT switches between 0.15W and 1.35W,showing negligible undershoot and overshoot and f ast responses,with a load regulation of 7.6mV/100mA.Figure 32.4.5 shows the measured ef ficiency of the converter at

172、 dif f erent conditions.A peak ef ficiency of 65.4%is achieved at 1.4W POUT with VIN/VISO=4.75V/5V,and the ef ficiency reaches 64.3%at 1.5W POUT with VIN/VISO=5V/5V.As shown in Fig.32.4.6,the proposed dual-LC-resonant topology provides an ef ficiency improvement of at least 13%compared with state-of

173、-the-art designs.Moreover,the proposed converter achieves inherent backscattering,eliminating the need f or a digital isolator.Figure 32.4.7 shows the die micrograph of the chip used f or both TX and RX along with the parameters of the transf ormer.Ac k nowl e dge me nt:This work was supported in pa

174、rt by the National Natural Science Foundation of China under Grant No.U23A20353.Corresponding author:Lin Cheng().Figure 32.4.1:Proposed dual-LC-resonant isolat ed DC-DC convert er and power breakdown.Figure 32.4.2:Operat ing principle of t he dual-LC-resonant t opology.Figure 32.4.3:Operat ing princ

175、iple of t he proposed hyst eresis cont rol using inherent backscat t ering for volt age regulat ion.Figure 32.4.4:Measured st eady-st at e and load-t ransient waveforms of t he proposed isolat ed DC-DC convert er.Figure 32.4.5:Measured efficiency of t he proposed convert er at different condit ions

176、and comparison wit h t he previously published works.Figure 32.4.6:Performance comparison of t he proposed isolat ed DC-DC convert er wit h st at e-of-t he-art designs.ISSCC 2025/February 19,2025/4:50 PM535 DIGEST OF TECHNICAL PAPERS 32 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2

177、025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 32.4.7:Die micrograph of t he TX/RX and t he phot o of t he t ransformer 3D view and EM simulat ion result s of t ransformers.Re f e re nc e s:1 W.Qin et al.,“An 800mW Fully Integrated Galvanic Isolated Power Transf er

178、 System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin,”I SSCC,pp.246-247,Feb.2019.2 D.Pan et al.,“A 1.25W 46.5%-Peak-Ef ficiency Transf ormer-in-Package Isolated DCDC Converter Using Glass-Based Fan-Out Waf er-Level Packaging Achieving 50mW/mm2 Power Density,”I SSCC,pp.468-469,Feb.2021.3

179、T.Hu et al.,“A 750mW,37%Peak Ef ficiency Isolated DC-DC Converter with 54/18Mb/s Full-Duplex Communication Using a Single Pair of Transf ormers,”I SSCC,pp.504-506,Feb.2024.4 Y.Zhuo et al.,“A 52%Peak-Ef ficiency 1W Isolated Power Transf er System Using Fully Integrated Magnetic-Core Transf ormer,”I S

180、SCC,pp.244-245,Feb.2019.5 D.Pan et al.,“A 1.2W 51%-Peak-Ef ficiency Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard,”I SSCC,pp.240-242,Feb.2022.6 D.Pan et al.,“An Isolated DC-DC Converter Using a Cross-Coupled Shoot-Throug

181、h-Free Class-D Oscillator with Low EMI Emissionsm,”I EEE J SSC,vol.59,no.10,pp.3457-3467,Oct.2024.7 L.Fanori et al.,“Class-D CMOS Oscillators,”I EEE J SSC,vol.48,no.12,pp.3105-3119,Dec.2013.8 L.Li et al.,“An 11MHz Fully Integrated 5kV Isolated DC-DC Converter Without Cross-Isolation-Barrier Feedback

182、,”I SSCC,pp.292-294,Feb.2020.536 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/32.5979-8-3315-4101-9/25/$31.00 2025 IEEE32.5 A 2W 53.2%-Peak-Efficiency Mult i-Core Isolat ed DC-DC Convert er wit h Embedded Magnet ic-Core Transformer Ach

183、ieving CISPR-32 Class-B EMI Compliance and 5mV Ripple Dongf ang Pan1,Weiwei Xu2,Litang Zhang1,Qiao Huang1,Lin Cheng1,2 1University of Science and Technology of China,Hef ei,China 2Hef ei CLT Microelectronics,Hef ei,China Integrated isolated DC-DC converters,using either on-chip 1-4 or package transf

184、 ormers 5-7,have been developed to minimize size and cost while achieving isolation ratings above 5kV and delivering around 1W of output power.As shown in Fig.32.5.1,these converters typically consist of an inverter,a transf ormer,and a rectifier.The inverter oscillates at f requencies in the tens-o

185、f-MHz range due to the limited inductance of the size-constrained transf ormer to transf er power,and it is switched on and of f by a PWM signal at around 1MHz to regulate the output voltage.However,this topology f aces several challenges:1)PWM control introduces severe conducted electromagnetic int

186、erf erence(EMI)(in the 150kHz to 30MHz range)that is caused by the discontinuous input current,and also leads to significant output voltage ripples due to discontinuous current delivery.While an EMI filter can be added at the input 8 and additional capacitors can be placed at the output to mitigate

187、these issues,cost and board area are greatly increased.2)Common-mode(CM)current(ICM)across the parasitic capacitance(CC)of the transf ormer results in input-to-output dipole radiation,causing severe radiated EMI(in the 30MHz to 1GHz range)7.ICM can be suppressed by using the symmetrical inverter str

188、ucture proposed in 6,7,but this comes at the cost of increased conduction loss.Frequency hopping techniques can help disperse radiation peaks at harmonic f requencies,but this introduces larger output ripples and adds circuit complexity 1.In this paper,we propose a multi-core isolated DC-DC converte

189、r that ef f ectively addresses the af orementioned challenges without incurring additional cost.As shown in Fig.32.5.1,the transf ormer is divided into N small transf ormers within the same total area.Each small transf ormer is paired with a scaled-down inverter and rectifier,f orming one of the cor

190、es in the proposed multi-core converter.Each core operates in an interleaved manner,transmitting 1/N of the total power to the output.Compared with the conventional topology,the proposed design of f ers significant advantages:1)The peak input current amplitude of each core is ef f ectively reduced b

191、y a f actor of N,greatly alleviating conducted EMI and reducing the output voltage ripple(VISO).Furthermore,due to the interleaved operation of each core,both the input and output currents of the converter are much more continuous.As a result,conducted EMI is suppressed by 40l gN dB,and VISO is redu

192、ced by a f actor of up to 1/N 2.2)The smaller transf ormers in each core exhibit significantly lower parasitic capacitance than that of the original large transf ormer,thereby reducing ICM.Moreover,the inverters in each core are designed to oscillate at slightly dif f erent f requencies,naturally di

193、spersing radiation peaks to f urther suppress radiated EMI without the need f or additional f requency-hopping circuits.In this work,N=4 is chosen f or demonstration.Figure 32.5.2 shows the structure of the 4-core transf ormer on a 4-layer package substrate.Copper traces on Layers 2 and 3,each 25m t

194、hick,70m wide,and with 3 turns,are used to f orm the primary and secondary coils.The top and bottom layers provide interconnections to the TX/RX chips.One challenge in designing the small transf ormer is the decreased coupling coef ficient due to the reduced coil dimensions,which leads to reduced ma

195、gnetic flux and compromised ef ficiency.To address this challenge,a 300m-thick Mn-Zn f errite sheet with a relative permeability of 100 at 100MHz is integrated into the substrate as a magnetic core f or the transf ormer.Adding the magnetic core in this manner does not significantly increase f abrica

196、tion cost compared with the on-chip transf ormer in 2,3,but it greatly improves perf ormance.The self-inductance of the primary coil is increased by 70%,and the coupling coef ficient is improved by 15.3%.Electromagnetic simulations show that the self-inductance/quality f actors of the primary and se

197、condary coils are 163nH/29 and 140nH/34 at 80MHz,respectively.As a result,the transf ormer achieves a coupling coef ficient of 0.83,enabling it to deliver over 2W of power.A 50m-thick polyimide layer serves as the isolation barrier between the primary and secondary coils,ensuring an isolation rating

198、 greater than 5kV.Figure 32.5.3 illustrates the block diagram of the proposed multi-core isolated converter.Each core incorporates an LC tank oscillator as the inverter and a f ull-bridge CMOS rectifier.The oscillation f requencies of the inverters are around 80MHz.Similar to the approach in 1-3,the

199、 PWM controller generates a PWM signal(PWM_RX)that is encoded into a dif f erential on-of f keying(OOK)signal and transmitted to the primary side.The decoded signal(PWM_TX)is used to generate f our interleaved signals(PWM)through a delay-locked loop(DLL).A phase detector monitors the phase dif f ere

200、nce between the rising edges of PWM_TX and PWM,converting this dif f erence into a control voltage(VC).This control voltage fine-tunes the delay cells,ensuring that the PWM signals maintain a precise 90 phase shif t relative to one another.Figure 32.5.3 also shows the two-step sof t-start control sc

201、heme in the isolated converter.In the first step,a gradually increasing duty-cycle signal PWM_TX is generated at the TX side,transmitting power to the RX and ramping up VISO in open loop.As VISO rises to the undervoltage lockout(UVLO)threshold,the control circuit at the RX side takes over,generating

202、 the signal PWM_RX and sending it to the TX side.Upon detecting the f eedback PWM signal at the TX decoder,control shif ts to closed-loop operation in the second sof t-start phase.VISO continues to rise,guided by the f eedback loop with an increasing ref erence on the RX side.The sof t-start process

203、 is completed when VISO reaches the target voltage of 5V.The RX and TX were f abricated using a 0.18m BCD process and assembled with an embedded magnetic-core package-substrate transf ormer within a 10121.8mm land grid array(LGA).Figure 32.5.4 shows the measured steady-state wavef orms of the output

204、 voltage ripple VISO and the PWM signal PWM_TX when VIN/POUT are 5V/0.4W and 5V/1.6W.With the proposed multi-core topology,the measured output voltage ripples are ef f ectively reduced to 2mV and 5mV,respectively,using a 10F output capacitor,confirming the ef f ectiveness in ripple reduction.As show

205、n in Fig.32.5.4,the transient overshoot and undershoot voltages are both 150mV,with a recovery time of 150s f or load steps between 0.4W and 1.6W at a 5V output.The measured wavef orm of VISO also demonstrates a smooth start-up process f or the converter.Figure 32.5.5 shows an 23dB improvement in co

206、nducted EMI with the proposed multi-core topology under the CISPR-32 Class-B standard.The converter meets Class-B limits at 0.5W output power(POUT)with 6.2dB margin without external filters or spread spectrum.Figure 32.5.5 also presents the radiated EMI perf ormance measured in a 3m semi-anechoic ch

207、amber.The radiation peaks are dispersed due to the dif f erent oscillation f requencies of each core.The converter passes CISPR-32 Class-B certification on a two-layer PCB without stitching capacitors,achieving a 6dB margin in horizontal field and a 13dB margin in vertical field at a 0.5W POUT.Figur

208、e 32.5.6 shows the measured ef ficiency of the proposed converter at dif f erent conditions.The peak ef ficiency reaches 53.2%at 1.7W POUT when VIN/VISO=4.5V/5V and the ef ficiency remains above 50%f or a 0.6-to-1.9W POUT range when VIN/VISO=5V/5V.The maximum POUT is 2.1W with VIN/VISO=5.5V/5V.Figur

209、e 32.5.6 also compares the perf ormance of the proposed isolated DC-DC converter with state-of-the-art designs.Thanks to the proposed multi-core architecture,the converter achieves CISPR-32 Class-B compliance f or both conducted and radiated EMI with the lowest cost and highest ef ficiency,and the s

210、mallest output ripples among the reported works.Figure32.5.7 shows the die micrograph of the RX and TX chips,along with a photo of the packaged converter.Ac k nowl e dge me nt:This work was supported in part by the National Natural Science Foundation of China under Grant No.U23A20353.Corresponding a

211、uthor:Lin Cheng().Figure 32.5.1:Proposed archit ect ure and cont rol solut ion for a mult i-core isolat ed DC-DC convert er,EMI performance comparison and challenges for mult i-core t ransformer.Figure 32.5.2:Implement at ion of t he embedded magnet ic-core t ransformers on a package subst rat e.Fig

212、ure 32.5.3:Block diagram of t he proposed mult i-core isolat ed DC-DC convert er.Figure 32.5.4:Measured st eady-st at e waveforms,load-t ransient and st art-up waveforms of t he proposed isolat ed DC-DC convert er.Figure 32.5.5:Measured conduct ed EMI under t he CISPR 32 st andard and measured radia

213、t ed EMI in a 3m semi-anechoic chamber under t he CISPR 32 st andard.Figure 32.5.6:Measured efficiency of t he proposed convert er at different condit ions and performance summary and comparison wit h previously published works.ISSCC 2025/February 19,2025/5:05 PM537 DIGEST OF TECHNICAL PAPERS 32 202

214、5 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 32.5.7:Die micrograph of t he TX and t he RX chips and t he phot o of t he proposed convert er in LGA package.Re f e re nc e s:1 W.Qin et al.,“An 800mW Fully

215、Integrated Galvanic Isolated Power Transf er System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin,”I SSCC,pp.246-247,Feb.2019.2 Z.Yue et al.,“A 52%Peak-Ef ficiency 1W Isolated Power Transf er System Using Fully Integrated Magnetic-Core Transf ormer,”I SSCC,pp.244-245,Feb.2019.3 Z.Yue et a

216、l.,“A 52%Peak Ef ficiency 1-W Isolated Power Transf er System Using Fully Integrated Transf ormer With Magnetic Core,”I EEE J SSC,vol.54,no.12,pp.3326-3335,Dec.2019.4 L.Li et al.,“An 11MHz Fully Integrated 5kV Isolated DC-DC Converter Without Cross-Isolation-Barrier Feedback,”I SSCC,pp.292-294,Feb.2

217、020.5 D.Pan et al.,“A 1.25W 46.5%-Peak-Ef ficiency Transf ormer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Waf er-Level Packaging Achieving 50mW/mm2 Power Density,”I SSCC,pp.468-470,Feb.2021.6 D.Pan et al.,“A 1.2W 51%-Peak-Ef ficiency Isolated DC-DC Converter with a Cross-Coupled

218、Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard,”I SSCC,pp.240-242,Feb.2022.7 D.Pan et al.,“An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator with Low EMI Emissionsm,”IEEE J SSC,vol.59,no.10,pp.3457-3467,Oct.2024.8 Texas Ins

219、truments,PMP22845,“Isolated 5-V Bias Supply f or Automotive CISPR 25,Class 5 Emissions,Ref erence Design,”Accessed on April.20,2021,.538 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 32/ISOLATED POWER AND GATE DRIVERS/32.6979-8-3315-4101-9/25/$31.00 2025 IEEE32.6 A Dynam

220、ic-RON-Diminished Bidirect ional GaN Load Swit ch wit h Inrush Current Prot ect ion and Spike At t enuat ion Po-Jui Chiu1,Tz-Wun Wang1,Xiao-Quan Wu1,Chi-Yu Chen1,Yu-Ting Huang1,Chien-Wei Cho1,Sheng-Hsi Hung1,Yu-Tse Shih1,Ke-Horng Chen1,Kuo-Lin Zheng2,Ying-Hsi Lin3,Shian-Ru Lin3,Tsung-Yen Tsai3,Hann-

221、Huei Tsai4 1National Yang Ming Chiao Tung University,Hsinchu,Taiwan 2Chip-GaN Power Semiconductor,Hsinchu,Taiwan 3Realtek Semiconductor,Hsinchu,Taiwan 4Taiwan Semiconductor Research Institute,Hsinchu,Taiwan In 48V electric vehicle(EV)power systems,high-side battery switching requires an advanced loa

222、d switch(LS)capable of bidirectional current flow and reverse current blocking f or ef ficient and saf e power management.During the battery charging phase,a single charger sequentially charges multiple battery cells(Fig.32.6.1 top lef t).The LS that is connected between the charger and the battery

223、cells must block reverse current in the of f state to prevent the charged battery f rom discharging.Moreover,during the battery discharge phase,the LS enables current to flow f rom the battery to the load.Theref ore,the LS requires bidirectional current transf er to charge the battery cells and powe

224、r the load.The conventional LS 1-6 adopts one power switch(PS)to transf er current f rom the first to the second terminal.However,the current may flow f rom the second terminal to the first terminal through the body diode,even if the PS is of f.To block the reverse current,LSs with back-to-back(B2B)

225、PSs are proposed in 7-9.Although the body diodes in opposite directions block the reverse current,these LSs do not provide a bidirectional current transf er path since their gate drivers(GD)are only f unctional when the voltage of a specified terminal is higher.In recent years,the bidirectional LS(B

226、LS)proposed in 10-12 can block reverse current and transf er current bidirectionally.However,the B2B PS inevitably doubles the on-resistance(Ron),significantly increasing the conduction loss.To minimize loss,Gallium Nitride(GaN)devices are particularly well-suited f or PS use due to their low Ron.Th

227、e cutting-edge technology of monolithic bidirectional GaN(Bi-GaN)13,14 f urther reduces the Ron compared to discrete B2B GaN PSs(Fig.32.6.1 middle lef t).Bi-GaN acts similarly to B2B GaN but with a smaller Ron due to common drain/source(CD/CS)terminals.The first mode(VG1S1=VG2S2=0V)and the second(VG

228、1S1=VG2S2=5V)exhibit bidirectional current blocking and transf er,respectively.In short,Bi-GaN is an excellent choice f or BLS.The bottom of Fig.32.6.1 shows the structures of 100V monolithic Bi-GaN with CS(MBS)and monolithic Bi-GaN with CD(MBD),where the length f rom gate to drain(Lgd)is about thre

229、e times the length of the gate to source(Lgs).Compared to discrete B2B topologies,the size of MBS is reduced by 13%,while MBD is significantly reduced by 38%,lowering area and Ron since Ron has a positive relationship with Lgs and Lgd.Besides,although the CS topology allows two gates to be driven by

230、 the same GD so that the two gates can be merged into one 13,14,overstress occurs during the turn-of f process since the source terminal is not available to bias(Fig.32.6.1 top right).When the input control signal(VPWM)goes f rom high to low,GD pulls the gate voltage(VG)down to the ground.The charge

231、 on the source terminal is gradually discharged by RLoad,leading to a large drop in the gate-to-source voltage(VGS)that may exceed the gate-to-source breakdown voltage.Thus,an additional turn-of f selector is required to control the gate terminal to short to the lower voltage of either the first ter

232、minal(VD1)or the second terminal(VD2).The turn-of f selector solves the overstress problem at the cost of complex control design.Based on the characteristics of the Bi-GaN devices and the consideration of the GD design,this work adopts MBD as the main PS to implement the BLS f or low cost,high ef fi

233、ciency,and more straightf orward GD design.Based on the previous design of GDs f or a single GaN PS 15,the corresponding GD f or MBD is shown in the top lef t of Fig.32.6.2.A large bootstrap capacitor Cbootx is connected between VGx and VSx to be bootstrapped to f ully turn on the MBD.Compared to th

234、e GD of a single GaN PS,an additional level shif ter is necessary to shif t up VPWM because the voltage domain of the GD is f rom VSx to a bootstrapped voltage(Vbootx).Worse still,an extra charge pump is required to charge Cbootx,occupying a large area since another set of bulky charge pump capacito

235、rs are needed.A dual-gate MBD requires duplicating the additional circuitry.In this work,the GD f or Bi-GaN eliminates level shif ters and requires only two Cbootxs in total(Fig.32.6.2 top right).Moreover,the GD with a driving current limiter(DCL)and spike-reduced turn-of f circuits(SRT)can prevent

236、Bi-GaN f rom suf f ering inrush current and protect on-chip devices f rom being damaged by overshoot voltages,respectively.The bottom of Fig.32.6.2 shows the critical issues in BLS design,such as the inrush current during turn-on and the spike in the input terminal during turn-of f.The bottom lef t

237、of Fig.32.6.2 shows the inrush current in a BLS.When VPWM is in the low state,the clock signals VCLK and VCLK_B are both reset to the low state,and the Cbootxs are charged by the higher voltage between VS1 and VS2.When VPWM goes f rom low to high,VGx is charged by the higher voltage between Vboot1 a

238、nd Vboot2,and the clock signals VCLK and VCLK_B make Cbootx f ully charge to ensure the stable VGxSx of the Bi-GaN.However,an inrush current occurs at the beginning of the on-state to charge CLoad f rom 0V to VIN.Moreover,VG2S2 suf f ers f rom overstress since VOUT is 0V originally.The bottom middle

239、 of Fig.32.6.2 shows the GD sof t-start using a small constant current.When VPWM goes f rom low to high,VGx,which is charged by a small current,rises slowly so that the issues of inrush current and overstress are solved.However,the gate leakage current of the GaN device(ILKGx)is significant and is p

240、roportional to VGS.The VGxSx of Bi-GaN stops rising and clamps below VGS,f ully-on when ILKGx equals the small driving current(IGx),increasing Ron and conduction loss since the Bi-GaN is not f ully turned on.The bottom right of Fig.32.6.2 shows the problem during turn-of f.When VPWM goes f rom high

241、to low,the Bi-GaN turns of f,and the input current flow stops abruptly.The high di/dt induces a high voltage spike due to the input parasitic inductance Lparx,which may increase the risk of GD damage.The top lef t of Fig.32.6.3 shows the architecture of the DCL,which can mitigate inrush current and

242、f ully turn on the Bi-GaN.When VPWM goes f rom low to high,the sof t start activates to raise Vsof t slowly.The user-define transconductance converts Vsof t to Ilimit,and Ilimit is mirrored to the current limiter.The source terminals of MP1 and MP2 are connected to Vbootx,so the driving current IDri

243、ve is limited by Ilimit.Thus,IGx is smoothly increased with Vsof t to charge VGx,alleviating the inrush current and the overstress of the Bi-GaN(Fig.32.6.3 bottom lef t).When the sof t start ends,Vsof t remains constant,and a larger Ilimit allows a strong IGx to compensate ILKGx and f ully turn on t

244、he Bi-GaN.The top right of Fig.32.6.3 shows the SRT to reduce the spike during turn-of f.When VPWM goes f rom high to low,MN11 and MN21 conduct to pull down the gate of MP11 and MP21 to short VGx to VSx and turn the Bi-GaN of f.The spike on VS1 is coupled to the gate of MP21 via C1.The source-to-gat

245、e voltage of MP21 decreases,which reduces the discharging current(Iof f)and slows down the turn-of f speed,thereby attenuating the spike voltage.Although the ultra-low Ron of Bi-GaN reduces conduction loss,the Ron increases af ter stress at high voltage and directly decreases the ef ficiency of BLS

246、over time.The top lef t of Fig.32.6.4 shows the dynamic Ron that is caused by“current collapse”16 in MBD.Electrons are trapped within the insulator due to the high voltage electric field between the gate and drain terminals in the of f-state.The longer the Bi-GaN is stressed,the more trapped electro

247、ns f orm a depleted two-dimensional electron gas(2DEG)and obstruct the current flow.Thus,the gradually increasing RON decreases ef ficiency.Worse still,electrons trapped on the dual gates of the MBD double the impact of the current collapse ef f ect,f urther exacerbating the increase in RON.The stan

248、dard GaN high electron mobility transistor(HEMT)with a gate field plate(GFP)exhibits the highest peak electric field at the gate edge.Adding a source FP(SFP)to GaN HEMTs 17,18 slightly suppresses the peak electric field,shif ting the peak to the edge of the SFP.The SFP GaN HEMT with a split SFP(SSFP

249、),an extension of SFP in segments,f urther reduces the peak electric field,resulting in a more even distribution of SFP and SSFP edges to mitigate current collapse.In the experimental results,the GFP MBD,the SFP MBD,and the SSFP MBD are nearly identical regarding on-resistance.However,af ter being b

250、urned f or 168 hours,the RON of the GFP MBD and the SFP MBD are increased by 41.9%and 38.2%,respectively.In comparison,the RON of the SSFP MBD is increased by only 28.5%,significantly reducing conduction loss caused by the dynamic Ron of the Bi-GaN during the on-state of BLS operation.The bottom of

251、Fig.32.6.4 shows the measured wavef orms of turn-on and turn-of f operation.Figure 32.6.5 shows the zoomed-in measurement result under a 48V VIN and a 25A ILoad with a 10F CLoad.The GD with Bi-GaN has a 347.4s rising propagation delay(Tpdr)and a 936.7s rising time(Tr)to turn on the Bi-GaN smoothly f

252、 or inrush current protection.It also has a 409.7ns f alling propagation delay(Tpdf)and a 483.6ns f alling time(Tf)to turn of f the Bi-GaN immediately f or reverse current blocking.The bottom lef t of Fig.32.6.5 shows that the inrush current is reduced by 91.4%under the maximum CLoad of 10F with DCL

253、 and is f urther reduced by 1.8%by tuning the user-defined transconductance.At a maximum ILoad of 25A,overshoot on VS1 is reduced by 89.5%,with SRT protecting the on-chip device while maintaining a f ast turn-of f speed(Fig.32.6.5 bottom right).Figure 32.6.6 shows that the BLS has a maximum VIN of 4

254、8V and ILoad of 25A with a low Ron of 11.2m achieved by adopting Bi-GaN as the main PS.The inrush current protection with dynamic driving current control allows the GD to f ully turn on the Bi-GaN f or minimized Ron without the risk of overcurrent.The SRT blocks the reverse current quickly without d

255、amaging the on-chip devices.Figure 32.6.7 shows the chip micrographs of the silicon driver in a 0.18m BCD process and the Bi-GaN in a 0.5m process.Ac k nowl e dge me nt:The authors would like to thank Jui Jen Wu,Dr.Meng-Fan(Marvin)Chang,and Taiwan Semiconductor Manuf acturing Company(TSMC)Limited Jo

256、int Developed Project(JDP)f or their help.Figure 32.6.1:Applicat ion of bidirect ional load swit ch and t he int roduct ion of monolit hic bidirect ional GaN.Figure 32.6.2:Archit ect ures of t he convent ional and Bi-GaN gat e driver and t he problems of Bi-GaN load swit ch.Figure 32.6.3:Archit ect

257、ures of t he driving current limit er(DCL)and spike-reduced t urn-off circuit s(SRT).Figure 32.6.4:Met hods t o improve t he problem of current collapse in MBD swit ch and t he measurement result s.Figure 32.6.5:Measured waveforms and st at ist ical dat a.Figure 32.6.6:Comparison t able wit h t he p

258、rior art s.ISSCC 2025/February 19,2025/5:20 PM539 DIGEST OF TECHNICAL PAPERS 32 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 32.6.7:Chip micrographs.Re f e re nc e s:1 Analog Devices,“12 V,2 A logic c

259、ontrolled high-side power switch,”ADP1290 datasheet,Dec.2014.2 Rohm Semiconductor,“1ch ultra small high side load switch,”BUS1DJC0GWZ datasheet,Mar.2014.3 Onsemi,“Integrated load switch,”FDC6324L datasheet,Dec.2021.4 Microchip,“67 m RDS(ON)2A high-side load switch in 0.85 mm x 0.85 mm FTDFN package,

260、”MIC94080 datasheet,Aug.2018.5 NXP,“Logic controlled high-side power switch,“NX5P2924D datasheet,June 2020.6 Texas Instruments,“4.5-V,1.5-A,7.5-m on-resistance f ast turn-on load switch with regulated inrush current,”TPS22999 datasheet,Nov.2023.7 Analog Devices,“Logic controlled,1 A,high-side load s

261、witch with reverse current blocking,”ADP198 datasheet,Oct.2011.8 Diodes Incorporated,“Single slew rate controlled load switch with true reverse current blocking,”AP22913 datasheet,May.2021.9 Richtek,“70m/55m,3A/2.5A/2A/1.5A/1A/0.5A high-side power switches with flag,”RT9742 datasheet,Jan.2020.10 Vis

262、hay,“6.5 m,bidirectional switch in compact WCSP,”SiP32101 datasheet,Apr.2022.11 NXP,“Bidirectional high-side power switch f or charger and USB-OTG applications,”NX5P3001 datasheet,May.2023.12 Diodes Incorporated,“Switch f or VBUS line with overvoltage,surge,and ESD protection,”AP22953 datasheet,Jan.

263、2022.13 Innoscience,“40V bi-directional GaN enhancement-mode power transistor,“INN040W048A datasheet,Aug.2023.14 Nexperia,“40 V,4.8 mOhm bi-directional Gallium Nitride(GaN)FET in a 2.1 mm x 2.1 mm Waf er Level Chip-Scale Package(WLCSP),“GANB4R8-040CBA datasheet,Aug.2024.15 X.Mu et al.,“Floating-doma

264、in Integrated GaN driver techniques f or DC-DC converters:A Review,“in I EEE Tra nsa c tions on Circ uits a nd Syste ms I:Re gul a r Pa pe rs,vol.70,no.9,pp.3790-3805,Sept.2023.16 G.Meneghesso et al.,“Current collapse and high-electric-field reliability of unpassivated GaN/AlGaN/GaN HEMTs,”in I EEE

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