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1、 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters1 of 73High-Speed Analog-to-Digital ConvertersVanessa Chen(vanessachencmu.edu)Carnegie Mellon UniversityFebruary 16th,2025 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHig

2、h-Speed Analog-to-Digital Converters2 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE Inter

3、national Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters3 of 73Introduction 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters4 of 73D-Band ReceiverSubTHz(100300 GHz)receivers for high data rate wireless commu

4、nications7-bit hybrid voltage-/time-domain ADC at 32GS/s in 22nm FinFET CMOSAgrawal 2023 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters5 of 73ADC/DAC-Based Coherent Optical TransceiverOffer more complex timing recovery for better performanc

5、eEnable more complex equalization to deal with channel lossesA 600Gbps receiver with 4x 105GS/s TI-SAR ADC in 16nm CMOSLi 2024 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters6 of 73OutlineIntroductionSampling and QuantizationSingle Channel A

6、DCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters7 of 73ADC B

7、ehavior ModelADCSampler followed by a quantizerDiscretize in time and amplitude 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters8 of 73Sampling TheoremIn order to prevent aliasing,we needThe sampling rate fs=2fsig,maxis called the Nyquist rat

8、eTwo ways to avoid aliasingSample fast enough to cover all spectral components,including frequencies outside band of interestLimit fsig,maxthrough filteringNo AliasingAliasing 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters9 of 73Ideal Track

9、-and-Hold CircuitTrack and hold(T/H)to avoid variations in input signal for quantizers T/HVinVoutVinttVoutttHTRACKHOLDCHVinVoutIdeal sampling and holdingIdeal sampling 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters10 of 73Circuit with a MOS

10、FET SwitchNonidealitiesFinite acquisition timeThermal noiseClock jitterSignal dependent hold instantTracking nonlinearityHold mode feedthrough and leakageCharge injection and clock feedthroughVinttVoutttHTRACKHOLDidealrealPedestal error 2025 IEEE International Solid-State Circuits ConferenceVanessa

11、ChenHigh-Speed Analog-to-Digital Converters11 of 73Finite Acquisition TimeAssume Vin and clock()are idealWorst case the output needs to settle from 0 to full scale voltage(VFS)VinttVouttt=0VFSVFStTs/2Track HoldCVinVoutR=RC=1 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Spe

12、ed Analog-to-Digital Converters12 of 73Finite Acquisition TimeSettling time constants required for least significant bit(LSB)settling of N-bit resolution,2=2 21222 ln 2 2N264.9107.61410.41813.2 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters

13、13 of 73Quantization of an Analog SignalQuantization step Quantization error has sawtooth shapeBounded by/2,+/2Transfer Functionx(Input)Vq(Quantized Output)Error eq=q-xx(Input)eq(Quantization Error)+/2-/2N=#of bitsVFS=full scale output=minimum resolvable input 1 LSB=2or =2 resolution 2025 IEEE Inter

14、national Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters14 of 73Encoding Example for a 3-Bit Quantizer23=8 distinct output codesDiagram on the left shows“straight-binary encoding”Quantization error grows out of bounds beyond code boundariesWe define the full scale

15、range(FSR)as the maximum input range that satisfies|eq|/2Implies that FSR=2B 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters15 of 73ADC Quantization CharacteristicAssume sine input:sin Signal power:=22Assume bit number:Quantization level:=22

16、Assume quantization noise is uniformly distributed between 2and+2Quantization noise power:=2+22=212Then signal-to-noise ratio(SNR)=622=3 221=6.02+1.76(dB)2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters16 of 73ADC Dynamic SpecificationsSpurio

17、us-Free Dynamic Range(SFDR)Ratio of input signal to maximum value of peak spurious or harmonic componentSignal to Noise-and-Distortion Ratio(SNDR)Ratio of RMS value of input signal to RMS sum of all other spectral components(including harmonics,but excluding DC)Effective Number of Bits(ENOB)The effe

18、ctive bit number of a specified converter with the equation=6.02 +1.76 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters17 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined

19、 ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters18 of 73Flash ADCsFastest single channel ADCComparison in one clock

20、 cycleNo latencyN-bit ADC requires 2N-1 comparatorsLarge power consumption at high resolutionsConversion time:+Power consumption:2 1+EncoderDigitalOutputVrefpVrefnAnalogInputRRRRRR11100ThermometerCodeBinaryCode 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-D

21、igital Converters19 of 73Ideal Voltage ComparatorFunctionCompare instantaneous values of two analog voltages(e.g.an input signal and a reference voltage)and generate a digital output voltage based on the polarity of that differenceVin+-Vout+-VDD(“Digital Out”)VoutVin“0”“1”2025 IEEE International Sol

22、id-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters20 of 73Comparator ExampleStrong-Arm LatchHigh-speed operationGood energy efficiencyVin+Vin-Vout+Vout-Ms3Mi1Mp1CKCKMs1Mn1Mn2Mp2Ms4CKMs2CKMi2MbCK 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Spee

23、d Analog-to-Digital Converters21 of 73Comparator Example-Operation(1)Reset:CK=low,Vin+Vin-,Vout+=Vout-=highPre-charge the internal nodes with PFETsStart the outputs at VDDTimeVoutAmpRegenerateResetLatcht2:Positive feedback turns ont1:CKt1t2Vout+Vout-Vin+Vin-Vout+Vout-Ms3Mi1Mp1CKCKMs1Mn1Mn2Mp2Ms4CKMs

24、2CKMi2MbCK 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters22 of 73Comparator Example-Operation(2)Amplify:CK=high,Vin+Vin-,Vout+Vout-(small difference)Both sides start moving down in different rates depending on inputsBuild a small differenti

25、al voltage between two sidesTimeVoutAmpRegenerateResetLatcht2:Positive feedback turns ont1:CKt1t2Vout+Vout-I1Vin+Vin-Vout+Vout-Ms3Mi1Mp1CKCKMs1Mn1Mn2Mp2Ms4CKMs2CKMi2MbCKI2 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters23 of 73Comparator Exa

26、mple-Operation(3)Regenerate:CK=high,Vin+Vin-,Vout+Vout-(logic level)Activated sequence:Mi1,Mi2 Mn1,Mn2 Mp1,Mp2Positive feedback turns onTimeVoutAmpRegenerateResetLatcht2:Positive feedback turns ont1:CKt1t2Vout+Vout-Vin+Vin-Vout+Vout-Ms3Mi1Mp1CKCKMs1Mn1Mn2Mp2Ms4CKMs2CKMi2MbCKI1 2025 IEEE Internationa

27、l Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters24 of 73Design ConsiderationsAccuracyOffset voltagesComparator matching determines resolutions of flash ADCsSpeedSmall-signal bandwidthSettling time or delay time,slew rateOverdrive recoveryPower dissipationOffset ca

28、libration to achieve low power consumption Van der Plas 2006,Chen 2013Input propertiesSampled data versus continuous timeCommon-mode rejectionInput capacitance and linearity of input capacitanceKickback noise 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Dig

29、ital Converters25 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International Solid-State

30、 Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters26 of 73SAR ADCBinary searchDAC output gradually approaches the input voltageComparator differential input gradually approaches zeroConversion time:+tcompincludes comparator delay and DAC settling timePower consumption:+Prefinclu

31、des reference generation and DAC switching energy 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters27 of 73Speed Limitations of Synchronous SAR ADCsCostHigh-speed internal clock neededSpeed LimitationWorst-case cycle timeMargin for clock jitte

32、r 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters28 of 73Asynchronous SAR ADC ConceptSelf-timed asynchronous comparisonsMaster clock used for synchronizing with the sample rateChen 2006 2025 IEEE International Solid-State Circuits Conference

33、Vanessa ChenHigh-Speed Analog-to-Digital Converters29 of 73Multi-bit SAR ADCLess clock cycles to reach the required resolutionMore hardware overheadHigher calibration complexity due to comparator offset mismatchChan 2017 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed A

34、nalog-to-Digital Converters30 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International

35、 Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters31 of 73Pipelined ADCsStages operate on the input signal like a shift registerNew output data every clock cycle Conversion time:+Power consumption:,+,Concurrent Stage Operation 2025 IEEE International Solid-State Circ

36、uits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters32 of 73Conversion Example(2 Bits/Stage)2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters33 of 73Conventional ImplementationT/H,DAC,summation node,and gain amplifier are usually

37、 implemented as a single switched-capacitor circuit block called a multiplying DAC(MDAC)Closed-loop implementation to achieve better accuracyClosed-loop bandwidth of the circuit must be high enough to achieve the desired settling accuracy at the given sampling rateLarge gain-bandwidth leads to large

38、 power consumption 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters34 of 73Speed-Up TechniquesMDAC with open-loop amplifierCan be(much)faster and power efficient,better headroom for advanced nodesMust calibrate for multiple non-idealitiesOthe

39、r popular amplifier architecturesRingAmp:Hershberg 2012,Lim 2014,Cao 2025Floating inverter amplifier(FIA):Tang 2020,Tang 2021Murmann 2003,Ali 2020,Gu 2025 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters35 of 73Comparison of Different Single-

40、Channel ADCsFlashSARPipelinedConversion Time+Power Consumption2 1+,+,Calibration2 1 comparator offsets1 comparator offsetInter-stage gain/offset alignment,ADC channel calibration 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters36 of 73ADC Top

41、ologies v.s.SpecificationsDifferent structures for different specifications 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters37 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipe

42、lined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters38 of 73Time-Interleaved ADCsIdentical ADCs interleaved in tim

43、e to achieve more parallelismADC1ADC2ADCMCLKM(t)CLK2(t)CLK1(t)Input(t)outputntimeCLK1CLK2CLKMCLK3CLKFSProcess mismatch is transformed into dynamic errors by the system operationOffset mismatchGain errorTiming skewBandwidth mismatchADC1ADC2ADCMM(t-M)2(t-2)1(t-1)input(t)outputnG1G2GMO1O2OMKurosawa 200

44、1,=2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters39 of 73Time-Interleaved ADC ExampleEach sub-ADC converts inputs one after another 4ch exampleCLK3(t)CLK2(t)CLK1(t)Input(t)OutputnCLK4(t)ADC1ADC2ADC3ADC41 2 3 4 111122223333444400.10.20.30.40

45、.5-120-100-80-60-40-200Frequency(GHz)Magnitude(dB)No mismatch fin=0.05 GHz SFDR:82.46 dB SNDR:61.91 dBN=8192fin*4-channel 10b ADC example 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters40 of 73Offset ErrorsPeriodically additive errors in tim

46、e domainproduce fixed pattern distortion in frequency domain1 2 3 4 1111222233334444 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters41 of 73Offset ErrorsDistortion is signal independent and appears at frequencies00.250.50.751-1-0.500.51TimeV

47、oltage ADC OutputOutput Error00.10.20.30.40.5-120-100-80-60-40-200Frequency(GHz)Magnitude(dB)Offset mismatch fin=0.05 GHz SFDR:48.82 dB SNDR:49.97 dBN=8192finDCfs/4fs/2*Error is pronounced for illustration*Offset mismatch=of 0.001 AmpOffset errors appear evenly along timeline 2025 IEEE International

48、 Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters42 of 73Gain MismatchesCause amplitude modulation of the input signalWorst at peaks and valleysNo influence at zero crossing1 2 3 4 1111222233334444 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenH

49、igh-Speed Analog-to-Digital Converters43 of 73Gain Mismatches00.250.50.751-1-0.500.51TimeVoltage ADC OutputOutput ErrorAll tones appear at frequencies corresponding to input signalThe spurs are signal dependent and appear at frequencies00.10.20.30.40.5-120-100-80-60-40-200Frequency(GHz)Magnitude(dB)

50、Gain mismatch fin=0.05 GHz SFDR:63.09 dB SNDR:56.93 dBN=8192fin-fin+fs/4fin+fs/4-fin+fs/2*Gain mismatch=of 0.001 AmpWorst at peaks and valleys*Error is pronounced for illustration 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters44 of 73Timing

51、 SkewUnequal spaced sampling points modulate the input samplesThe largest errors occur at the points with largest slew rateNo influence at peaks and valleys1 2 3 4 1111222233334444 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters45 of 73Timin

52、g Skew Low Input Frequency Distortion is signal dependent and appears at frequencies00.250.50.751-1-0.500.51TimeVoltage ADC OutputOutput Error00.10.20.30.40.5-120-100-80-60-40-200Frequency(GHz)Magnitude(dB)Timing mismatch fin=0.05 GHz SFDR:32.74 dB SNDR:28.47 dBN=8192fin-fin+fs/4fin+fs/4-fin+fs/2*Er

53、ror is pronounced for illustration*Timing skew=of 0.001 interleaved CLKLargest errors occur at crossing points 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters46 of 73Timing Skew High Input Frequency Distortion is signal dependent and appears

54、 at frequencies*Error is pronounced for illustration*Timing skew=of 0.001 interleaved CLKLargest errors occur at crossing points 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters47 of 73Bandwidth MismatchCombining gain mismatch and timing skew

55、High bandwidth by design to minimize effectCritical for very high frequency ADCs1 2 3 4 1111222233334444CVinVoutR=RC 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters48 of 73Bandwidth MismatchDistortion is signal dependent and appears at frequ

56、encies*Error is pronounced for illustration*Amp mismatch=of 0.001 Amp*Phase shift=of 0.001 interleaved CLK 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters49 of 73Error Source SummaryGain and Offset mismatch can be detected and corrected simp

57、ly by calculating the mean and standard deviation of each sub-ADC outputTiming skew errors are usually more difficult to reduceDifficult to sense,particularly at very high-speed operationOffset MismatchGain ErrorTiming SkewBandwidth MismatchInput AmplitudeIndependentDependentDependentDependentInput

58、FrequencyIndependentIndependentDependentDependent 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters50 of 732-Rank Track and HoldNo timing skew in the 2-rank T/H with a Rank1 T/H operating at full speedLarge power consumption4.3W in T/H and clo

59、ck distribution in this exampleSetterberg 2013 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters51 of 73TIADC Architecture Selection Time-interleaved architecture determines overall area and power efficiencyAssume 2-rank interleaving:N x MLimi

60、ting factors for TI-ADCSub-ADC speedRank1 sampler speed and settling BWClock generation and distribution complexityPower/area costIm 2020 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters52 of 73OutlineIntroductionSampling and QuantizationSing

61、le Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters

62、53 of 73Time Interleaving Errors CalibrationDetectionAnalog:tends to be limited in accuracy and hence impractical for 8b-12b,especially for timing.It can burden sensitive analog nodes.Digital:captures net effects(regardless of origins),though extracting desired errors is critical.Also,it could add l

63、atency and can become power hungry at full sample rate.CorrectionAnalog:direct but it can add more noise/jitter.Digital:it can become power hungry and add latencyCalibrations operationForeground calibration:need to take ADC off-line for a short period of timeBackground calibration:no interruption of

64、 ADC operation 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters54 of 73Foreground CalibrationWith a test signal to analyze channel characteristicsTest signals could be a ramp or sine waveTI-ADCCLK(t)Input x(t)Output xnDSPTest SignalTI-ADCCLK(

65、t)Input x(t)Output xnDSPTest SignalNormal operationUnder calibration 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters55 of 73Calibration with Fourier AnalysisDetect timing skew with Fourier analysis and a specific test sine waveCorrect errors

66、 by either mixed-signal feedback control or digital filtersADC1ADC2ADCMCLKM(t)CLK2(t)CLK1(t)Inputx(t)x1nFFTFFTFFTx2nxMnAmplitude1Phase1Amplitude2Phase2AmplitudeMPhaseMJenq 1990 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters56 of 73Correlati

67、on-Based Background CalibrationAn additional channel is used to estimate the cross-correlation of output signals between ADCMand ADCCALADC1ADC2ADCMCLKM(t)CLK2(t)CLK1(t)Inputx(t)x1nx2nxMnADCCALCLKCAL(t)xCALnDSP(Detection+Calibration)El-Chammas 2011 2025 IEEE International Solid-State Circuits Confere

68、nceVanessa ChenHigh-Speed Analog-to-Digital Converters57 of 73Correlation-Based CalibrationExpectation value is a monotonic function of timing skew when input BW is smallMaximize the expectation value to reduce timing skewThe calibration heavily relies on the statistics of the input signal El-Chamma

69、s 2011 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters58 of 73Other Timing Skew CalibrationReference ADC&window detection:Song 2017Self-referred:Elbornsson 2005,Razavi 2013Digital calibration based on blind identification:Elbornsson 2004,200

70、5Time-varying inverse filter approach:Seo 2005,Tertinek 2008,Johansson 2007,2008,Vogel 2009,2012,Saleem 2011Reference ADC and embedded time-to-digital calibration:Chen 2014 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters59 of 73High-Speed AD

71、C Measurement ConsiderationsTypical measurement setup for a differential ADCMinimize gain and phase imbalance to accurately measure harmonic distortionKull 2017 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters60 of 73High-Speed ADC Measuremen

72、t ConsiderationsHandling the high-speed digital outputsOutput decimationWith on-chip memoryOutput decimationKull 2017 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters61 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash

73、 ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationEmerging ApplicationsSummary 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters62 of 73Emerging App

74、licationsCryo-CMOS SAR ADC for Quantum ComputingKiene 2023 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters63 of 73Cryo-CMOS ADCs1 GS/s 6-8-bit 2x SAR ADCModified common-mode switching for cryogenic operationsFastest sampling cryo-CMOS ADCKie

75、ne 2023 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters64 of 73Measurement ChallengesLimited-area PCBAvoiding temperature cyclingKiene 2023 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Conve

76、rters65 of 73Cryo-CMOS ADC 18.87-bit 800 MS/s charge injection SAR ADCExploits the low thermal noise of the cryogenic environmentSmall CINto reduce requirements and power drain of the driver by using charge injection DAC(CI-DAC)Veraverbeke 2025 2025 IEEE International Solid-State Circuits Conference

77、Vanessa ChenHigh-Speed Analog-to-Digital Converters66 of 73Machine-Learning-Assisted ADCsAdopt bijective vector recovery mapping(VRM)for nonlinearity calibrationSuppresses both harmonic distortions and spursLu 2024Training ProcessBlock diagram of the ANN-based calibrator 2025 IEEE International Soli

78、d-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters67 of 73OutlineIntroductionSampling and QuantizationSingle Channel ADCsFlash ADCsSuccessive Approximation(SAR)ADCsPipelined ADCsTime-Interleaved ADCsDegradation of Random Mismatch on ADC PerformanceTiming-Skew CalibrationE

79、merging ApplicationsSummary 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters68 of 73SummaryFor single channel ADCs,many techniques for different architectures can be applied to achieve the desired specificationsSelection of the suitable archi

80、tecture for different applicationsOptimization of time-interleaving Architecture selectionSub-ADC type/performanceRank1 sampler speed and settling BW requirementClock generation and distribution complexityOverhead of timing skew calibration that is one of the biggest challenges,particularly for ultr

81、a-high-speed operationsEmerging ApplicationsCryo-CMOS ADCs for Q-bit sensingMachine-learning-assisted ADCs 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters69 of 73Papers to See at ISSCC 2025Pipelined ADCs24.1(3GS/s 12b)24.2(1GS/s 14b)TI ADC:2

82、4.3(2.2GS/s 8.4b)24.5(72GS/s 9b)24.6(16GS/s 12b)24.7(10GS/s 8b)24.8(12GS/s 9b)Time domain ADC24.4(3GS/s 10b)Cryo-CMOS ADC:18.8 2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters70 of 73ReferencesA.Agrawal et al.,“18.2 A 128Gb/s 1.95pJ/b D-band

83、receiver with integrated PLL and ADC in 22 nm FinFET,”ISSCC,2023.G.Li et al.,18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS,ISSCC,2024.G.Van der Plas et al.,“A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process,”ISSCC,200

84、6.V.H.-C.Chen and L.Pileggi,“An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI,”VLSI Circuits,2013.M.S.W.Chen and R.W.Brodersen,“A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13m CMOS,”ISSCC,2006.C.-H.Chan et al.,“A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset

85、calibration,”ISSCC,2017.B.Murmann and B.E.Boser,“A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”,ISSCC,2003.A.Ali et al.,“A 12b 18GS/s RF sampling ADC with an integrated wideband Track-and-Hold amplifier and background calibration,”ISSCC,2020.2025 IEEE International Solid-State

86、 Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters71 of 73ReferencesM.Gu et al.,“A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration,”ISSCC 2025.B.Hershberg et al.,”Ring Amplifiers for Switched-Capacitor Circuits,”ISSCC,2012.Y.Lim and M.P.Fly

87、nn,“A 100 MS/s 10.5b 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers,”ISSCC,2014.Y.Cao et al.,“A 14b 1GS/s Single-Channel Pipelined ADC with a Parallel-Operation SAR Sub-Quantizer and a Dynamic-Deadzone Ring Amplifier,”ISSCC,2025.X.Tang et al.,“9.5 a 13.5b-ENOB second-order no

88、ise-shaping SAR with PVT-robust closed-loop dynamic amplifier,”ISSCC,2020.X.Tang et al.,“A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier,”ISSCC,2021.N.Kurosawa et al.,“Explicit analysis of channel mismatch effects in time-interle

89、aved ADC systems,”TCAS-I,March 2001.B.Setterberg et al.,“A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction,”ISSCC,2013.J.Im et al.,“A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Ba

90、sed RX Analog Front-End in 7nm FinFET,”ISSCC,2020.2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters72 of 73ReferencesY.-C.Jenq,Digital spectra of nonuniformly sampled signals:a robust sampling time offset estimation algorithm for ultra high-sp

91、eed waveform digitizers using interleaving,TIM,Feb.1990.M.El-Chammas and B.Murmann,A 12GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,JSSC,Apr.2011.J.Song et al.,“A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration”,JSSC,Oct.

92、2017.J.Elbornsson et al.,”Blind equalization of time errors in a time-interleaved ADC system”,TSP,April 2005.B.Razavi,“Design Considerations for Interleaved ADCs”,JSSC,Aug.2013.J.Elbornsson et al.,“Blind Adaptive Equalization of Mismatch Errors in a Time-Interleaved A/D Converter System”,TCAS-I,Jan.

93、2004.M.Seo et al.,“Comprehensive digital correction of mismatch errors for a 400-Msamples/s 80-dB SFDR time-interleaved analog-to-digital converter,”TMTT,March 2005.S.Tertinek and C.Vogel,“Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a DifferentiatorMultiplier Cascade,”TCAS-I,Sep

94、.2008.2025 IEEE International Solid-State Circuits ConferenceVanessa ChenHigh-Speed Analog-to-Digital Converters73 of 73ReferencesH.Johansson et al.,“Least-Squares and Minimax Design of Polynomial Impulse Response FIR Filters for Reconstruction of Two-Periodic Nonuniformly Sampled Signals,”TCAS-I,Ap

95、ril 2007.H.Johansson et al.,“A Least-Squares Filter Design Technique for the Compensation of Frequency Response Mismatch Errors in Time-Interleaved A/D Converters,”TCAS-II,Nov.2008.C.Vogel and S.Mendel,“A Flexible and Scalable Structure to Compensate Frequency Response Mismatches in Time-Interleaved

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