SESSION 22 - High-Speed Analog-to-Digital Converters.pdf

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1、ISSCC 2024SESSION 22High-Speed Analog-to-Digital Converters22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference1 of 52Yuefeng Cao1,Minglei Zhang1,Yan Zhu1,Rui P.Martins1,2and

2、Chi-Hang Chan11State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,Macau,China2Instituto Superior Tecnico/Universidade de Lisboa,Portugal 22.1 A 12GS/s 12b 4 Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer22.1:A 12GS/s 12b 4

3、Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference2 of 52OutlineMotivationComprehensive Calibration of TI ErrorsConceptImplementationLinearized Input BufferHigh-Speed ChannelMeasurement Result

4、sConclusions22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference3 of 52MotivationEmerging Wireless Communication&Automotive RadarWide-Band Challenges on Direct RF-Sampling ADC

5、 10GS/s Sampling Rate(Necessitating Interleaving&High-Speed Channel)Simple and Condition-Robust Skew CalibrationHigh Linearity Over Wide BWLow Power Consumption and Compact AreaHigh LinearityIntegration Friendly 22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI E

6、rrors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference4 of 52Review of Prior ADC Design2.25GS/s per Channel:Low TI-Factor Pre-Channel Sampler:High BW,Less Critical Instants Ali,ISSCC2012b 18GS/s8x-Time Interleaved 1300mW in 16nm2-Rank Interleaving Architecture:2-TI

7、 Sampler+Single Sub-Buffer Extra Noise,Power and NonlinearityDigital Skew Detection:Input-Dependent1122Dither12VBN1VBP1VBN2VBN1VBP1VBP2VIN1.8V1VRank 1 TI Sampler8 Interleaved2 Interleaved(3 for random.)2.25GS/sADCRank 2 Buffer22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calib

8、ration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference5 of 5212b 10GS/s16x-Time Interleaved 625mW in 5nmReview of Prior ADC DesignHierarchical Buffer:High BWMoon,VLSI22625MS/s per Channel:Big TI-Factor(16)2-Rank Buffer Architecture:Cascaded Push-Pull

9、Source Follower Extra Noise,Power and NonlinearityAuto-Correlation-Based Skew Calibration:Input-DependentVBN1VBP10.85VVINVBN1VBP10.85V625MS/sADC4 InterleavedRank 1 BufferRank 2 Buffer22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Bu

10、ffer 2024 IEEE International Solid-State Circuits Conference6 of 52Overview of This Work3GS/s per Channel:Low TI-Factor(4)Single-Rank Architecture:Linearized Buffer+4 Direct TI Low Noise,Low Power,High Linearity with Adequate BW Comprehensive Calibration of TI Errors:Global Dither Injection Based In

11、put-Independent,No Blind SkewVININJ CHACHACHAChannel3GS/s#A#B#C#DINJLSLSPP-SF1.2VSACC-cellTarget:12b 12GS/s4x-Time Interleaved 200mW in 28nm22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Ci

12、rcuits Conference7 of 52OutlineMotivationComprehensive Calibration of TI ErrorsConceptImplementationLinearized Input BufferHigh-Speed ChannelMeasurement ResultsConclusions22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IE

13、EE International Solid-State Circuits Conference8 of 522Dither Routing Mismatch112R-C MismatchS,AS,BTSTSTSRampDitherVR,AVR,B|VR,B|-|VR,A|=kt 0Detected t polarity is wrong CDACCDACCH#ACH#BVINCJ2CJ1S,AS,B Dither12R-C MismatchDither Routing Mismatch12tDitherin CH#A/#B 22.1:A 12GS/s 12b 4Time-Interleave

14、d Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference10 of 52Review of Prior Skew Detection Conventional Dither Injection BasedBlind To Mismatch Between Injection Paths(40fsrmsLuo,VLSI17)Blind To Effective Skew

15、(tSR20fs)|VR,B|-|VR,A|0Detected t polarity is wrong L VR,BVR,ADitherin CH#A/#BS,AS,BTSTSTSCDACCDACCH#ACH#BVINCJ2CJ1S,AS,B Dither12R-C MismatchDither Routing Mismatch123Signal Routing Mismatch3S,B should be here not heretSR:An effective skewVINin CH#A/#Bt22.1:A 12GS/s 12b 4Time-Interleaved Pipelined

16、ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference11 of 523Signal Routing MismatchR-C MismatchDither Routing Mismatch12CDACCDACCH#ACH#BVINCJ2CJ1S,AS,B Dither123DitherVINCDACCDACCH#ACH#BLocal Injection Versus Global Inje

17、ction Local InjectionDistributed Dither Injection:Dither Routing Mismatch R-C MismatchSeparate Dither&Signal Paths:Signal Routing Mismatch Global Injection(This Work)Unified Dither Injection:Avoid Dedicated Injection Pathsand Associated MismatchDither Distributed via Signal Routing:Signal Routing Mi

18、smatch Detected22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference12 of 52Global Injection Based Skew DetectionWith Signal Routing Mismatch(tSR)Ditherin CH#A&CH#BVD,AVD,BVD,A

19、 0+tVINin CH#A/#BDitherin CH#A/#B22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference13 of 52Global Injection Based Skew DetectionWith Signal Routing Mismatch(tSR)Ditherin CH#

20、A&CH#BVD,AVD,BVD,AVD,BWrong detected tsk polarityL S,AS,BTSTSTSDitherVINCDACCDACCH#ACH#BVR,AVR,BtSRTrim S,B till|VR,B|-|VR,A|=0,both t and tSR are compensated +tVINin CH#A/#BDitherin CH#A/#B22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized I

21、nput Buffer 2024 IEEE International Solid-State Circuits Conference14 of 52Review of Prior Skew Detection Compare With Other MethodsComprehensive Skew Calibration?Input-Independent?No Blind Skew?Global Injection Based(This Work)Conventional Injection BasedAuto-Correlation BasedAuxiliary Channel Base

22、d(No Practical for 12b 12GS/s Target)Digital Derivative Based(No Practical for 12b 12GS/s Target)22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference15 of 52S,AS,BTSTSTSRampDi

23、therVP,AVP,B|VP,A|=|VP,B|tDither PolarityModulated by PNDitherVINCDACCDACCH#ACH#BGain&Offset Mismatch Detections Analog Domain:Pulse Dither Voltage(VP,A/B)Injection Digital Domain:(1)Digital|VP,A/B|(DP,A/B)Extraction by CorrelationGain Mismatch=DP,A/DP,B(2)OA/B=Mean(+Pulse Dithered Samples of CH#A/#

24、B)Offset Mismatch=OA-OB22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference16 of 52OutlineMotivationComprehensive Calibration of TI ErrorsConceptImplementationLinearized Input

25、 BufferHigh-Speed ChannelMeasurement ResultsConclusions22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference17 of 52Comprehensive Cal.of Timing Skew Ramp DitherDP,A/B=Digital V

26、ersion of Ramp Dither;Skew Sign=Sign(DR,B-DR,A)orPNTVCDLsVCDLsVCDLsDCDLsVINCLKININJLSLSIBF SACC-cellCHACHACHAPP-SFChannel#A#B#C#DDoutMUXINJSelectionPN+or-PNGENCK GENCalibration Engineor+-GainAlign.to CH#ASignDCDLPN=+1 or-1FromCK GENDR,BDR,ACounterCorrelationVIN.CH#B.CH#APNCorrelationS1,AS1,B22.1:A 1

27、2GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference18 of 52Comprehensive Cal.of Gain&Offset Mismatch Pulse DitherDP,A/B=Digital Version of Pulse Dither;Gain Mismatch=DP,A/DP,B OA/B=M

28、ean(+Pulse Dithered Samples);Offset Mismatch=(OA-OB)orPNTVCDLsVCDLsVCDLsDCDLsVINCLKININJLSLSIBF SACC-cellCHACHACHAPP-SFChannel#A#B#C#DDoutMUXINJSelectionPN+or-PNGENCK GENCalibration EnginePN=+1 or-1DAorOA-OBDP,ADP,BRemoveDitherRemoveDitherD ADP,BOBDP,AOAPNCorrelationMean Value Corresponding to PN=+1

29、DAD AVIN.CH#B.CH#ADBD B22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference19 of 52Comprehensive Cal.of TI Errors Random Dither Type&PolarityPNTDetermines Dither Type(Ramp/Pul

30、se)PNPDetermines Dither Polarity(+/-)VCDLsVCDLsVCDLsDCDLsVINCLKININJLSLSIBF SACC-cellCHACHACHAPP-SFChannel#A#B#C#DDoutMUXINJSelectionPNP+or-CK GENCalibration EngineorPNTPNGEN Skew,gain&offset mismatchcal.run simultaneously Skew,gain&offset mismatchcal.are all input-independent No spur dither injecti

31、onfreq.(fS/125)or its multiples22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference20 of 52+R-R+P-PVINCLSVBInj.Caps(CINJs)V IN +VIN Pull-UpLSVIN+INJLSPull-DownINJGlobal Dither

32、 Injection Push-Pull Source Follower(PP-SF)Level-Shifter(LS):R-C+/-Ramp/Pulse Dither InjectionOne kind of dither at a timeInjector(INJ):Inverters&Caps22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Soli

33、d-State Circuits Conference21 of 52Global Dither Injection+RP-RP+PP-PPVIN,PCLSVBInj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBV IN,N+VIN,PPull-UpLSP-SidePull-UpLSN-SideVIN,NCKG+CKG-+/-Ramp/PulseSelectionINJPull-DownINJPull-Down+/-Ramp/Pulse SelectionVIN,P+VIN,N+22.1:A 12GS/s 12b 4Time-Interleaved Pipel

34、ined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference22 of 52Global Dither Injection+RP-RP+PP-PPVIN,PCLSVBInj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBV IN,N+VIN,PPull-UpLSP-SidePull-UpLSN-SideVIN,NCKG+CKG-+/-Ramp/Pulse

35、SelectionINJPull-DownINJPull-Down+/-Ramp/Pulse SelectionS1,BCH#BS1,DCH#DS1,CCH#CS1,ACH#AVO,NVO,PtSR,NBtSR,PAtSR,NAtSR,NCtSR,PBtSR,NDtSR,PCtSR,PD22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-Stat

36、e Circuits Conference23 of 52PerturbationVIN,N-RN+RP-RP+PP-PPVIN,PCLSVBInj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBV IN,N+RPVIN,PFeedThrough IdealPerturbatedTime-Variant Dither Magnitude 22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input

37、 Buffer 2024 IEEE International Solid-State Circuits Conference24 of 52PerturbationVIN,N-RN+RP-RP+PP-PPVIN,PCLSVBInj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBV IN,N+RPVIN,PKicking Poor Signal Integrity IdealPerturbatedTime-Variant Dither Magnitude 22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with

38、 Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference25 of 52Perturbation+RP-RP+PP-PPVIN,PCLSVBInj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBV IN,N+Kicking VIN,N-RN+RPVIN,P Perturbated Dithers&Signal Degrade SNR 22.1:A 12GS/s 12b 4Ti

39、me-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference26 of 52Perturbation Cancellation+RP-RP+PP-PPVIN,PCLSVBPerturbation Cancellation(CPCs)Inj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBVIN,PV IN,N+VIN

40、,NKicking VIN,N-RN+RPVIN,Pw/o and w/CPCs22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference27 of 52Perturbation Cancellation+RP-RP+PP-PPVIN,PCLSVBPerturbation Cancellation(CP

41、Cs)Inj.Caps(CINJs)V IN,P+RN-RN+PN-PNVIN,NCLSVBVIN,PV IN,N+VIN,NKicking VIN,N-RN+RPVIN,Pw/o and w/CPCs22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference28 of 52Simulation Res

42、ults 12GS/s,6GHz 0.95Vdiff,ppIBF Output,Noise Off Random+/-Ramp/Pulse Dither Every 5/25/125 Cycles Dither Magnitude:10mVdiff(Ramp),5mVdiff(Pulse)padmodel0.6nHbondingwiresourceimpedanceCH#ASRSTVCMIBFidealSW450fF5022.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI E

43、rrors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference29 of 52Simulation Results SNDR of Sampled Voltage Different Injection Freq.(fINJ)Dithers Removed by Digital Processing22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Error

44、s and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference30 of 52OutlineMotivationComprehensive Calibration of TI ErrorsConceptImplementationLinearized Input BufferHigh-Speed ChannelMeasurement ResultsConclusions22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Compr

45、ehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference31 of 52INJVB2VB1INJI4I3PP-SFIdeally:If VOUT,P=VIN,P then|Vgs1|=|Vgs2|=Vgs0|Vds1|VDD/2,I2=I0+I2CurrentCompensation:If I3=I2+I1I1=I0-I1,I2=I0+I2|Vgs1|=|Vgs2|=Vgs0VOUT,P=VIN,P J SACCVB3

46、VB4M3M41.1V-0.1VI3I4VIN,NPVT-Tracking BiasVB14I1I2M1M2VIN,PVOUT,PForced to be linear to VIN,PPush-Pull Source Follower Current UnbalanceWhen VIN,Pis high,I1,I2When VIN,Pis low,I1,I222.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buff

47、er 2024 IEEE International Solid-State Circuits Conference32 of 52VB1VB2INJINJPP-SF1.1V-0.1VPVT-Tracking BiasVB14I1I2M1M2VIN,PI3M3I4M4Self-AdaptiveCurrentCompensationVOUT,PVIN,NSelf-Adaptive Current Compensation(SACC)When VIN,PVCM,M3 and M4 are off22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC wi

48、th Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference33 of 52VB1VB2INJINJVB4VB3PP-SFSACC1.1V-0.1VPVT-Tracking BiasVB14I1I2M1M2VIN,PI3M3I4M4VOUT,PSelf-AdaptiveCurrentCompensationVIN,NSelf-Adaptive Current Compensation(SACC)When V

49、IN,PVCM,M3 and M4 are offWhen VIN,Pis high,M3 on,M4 off22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference34 of 52VB1VB2INJINJVB4VB3PP-SFSACC1.1V-0.1VPVT-Tracking BiasVB14I1I

50、2M1M2VIN,PI3M3I4M4Self-AdaptiveCurrentCompensationVOUT,PVIN,NSelf-Adaptive Current Compensation(SACC)When VIN,PVCM,M3 and M4 are offWhen VIN,Pis high,M3 on,M4 offWhen VIN,Pis low,M3 off,M4 on22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized

51、Input Buffer 2024 IEEE International Solid-State Circuits Conference35 of 52Linearized Input BufferI3I4I1I2SACCPP-SFVIN,PVOUT,PIdealActualIdeally:if VOUT,P=VIN,P then|Vgs1|=|Vgs2|=Vgs0|Vds1|VDD/2,I2=I0+I2Actually:KCL:I1=I2|Vgs1|Vgs0|Vgs2|Vgs0VOUT,P70dB up to 4GHzNo performance drop up to 13GS/s22.1:

52、A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference45 of 52Static Performance&Power Break-DownCalibration engine implemented off-chipInput buffer only consumes 24mW22.1:A 12GS/s 1

53、2b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference46 of 52ConvergedConvergedConvergence of Timing Skew CalibrationSkew calibration after gain mismatch calibrationfS=12GS/s,fin=5.7GHz,12.8M

54、 dithered samples per iterationCH#BD skew tunning by digitally-controlled delay lines(DCDLs)22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference47 of 52Supply Voltage&Temperat

55、ure Variations5%supply voltage variation(including references&input buffer)-40125C ambient temperatureWith background TI errors&CDRA gain calibrationsfin=335MHz,fS=12GS/sSNDR57.4dB,SFDR71.6dB22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized

56、Input Buffer 2024 IEEE International Solid-State Circuits Conference48 of 52Summary&ComparisonSlowest processFastestsingle-channel22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Con

57、ference49 of 52Summary&ComparisonLow supplyw/o swing degradationLow samplingfront-end power22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference50 of 52Summary&ComparisonLow po

58、wer,best FoMsComprehensivecalibration22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference51 of 52OutlineMotivationComprehensive Calibration of TI ErrorsConceptImplementationLi

59、nearized Input BufferHigh-Speed ChannelMeasurement ResultsConclusions22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference52 of 52ConclusionsComprehensive Calibration of TI Err

60、orsInput-Independent,No Blind SkewLinearized Input BufferLow Power,High LinearityHigh-Speed Channel3GS/s with 100ps Residue AmplificationOverall 12GS/s 12b 4 TI ADCCompetitive PerformanceHigh Energy Efficiency22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Erro

61、rs and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference53 of 52Please Scan to Rate Please Scan to Rate This PaperThis Paper22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Di

62、gital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference1 of 57A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 85dBFS HD3 Using Digital Cancellation of DAC Errors Sharvil Patil1,Asha Ganesan1,Ha

63、jime Shibata1,Victor Kozlov1,Gerry Taylor1,Qingnan Yu2,Zhao Li1,Zeynep Lulec1,Konstantinos Vasilakopoulos1,Prawal Shrestha1,Donald Paterson1,Raviteja Theertham1,Aseer Chowdhury31Analog Devices,2now with Amazon,3now with U.of Toronto22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time P

64、ipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference2 of 57Why Ultra-Low NSD and 3rd-Order DistortionfBWfBWfBWfBW0dBFSNSD160dBFS/Hz3rdorder distortion500MHzPower1WInterferersADC22.2:A 70

65、0MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference3 of 57State-of-the-Art ADCsBW GHzData points:1997 2023 ISSCC&VLSI 1BW 1WHD

66、3 80dBFS2 Shibata,ISSCC1722.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference4 of 57State-of-the-Art ADCsBW GHzData po

67、ints:1997 2023 ISSCC&VLSI 1This workHD3 85dBFSPower=0.7WBW 1WHD3 80dBFS2 Shibata,ISSCC1722.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-Sta

68、te Circuits Conference5 of 57System Constraints of DT ADCssubADCsubDACBackendCKCsampAntialiasingfilterDriverDT ADCNSDCsamp150dBFS/Hz(BW=900MHz)31.08pF164dBFS/Hz27pF14dB253 Hsieh,ISSCC23Noise,HD3,KickbackDT Amp+-22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-

69、Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference6 of 57Alternative:Continuous-Time Pipelined ADC 2+subADC+subDACCKCsamp-2 Shibata,ISSCC17AntialiasingfilterDriverBackendDT Amp22.2:A 700MHz-BW 164dBFS/Hz-S

70、mall-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference7 of 57Alternative:Continuous-Time Pipelined ADC 2+subADC+subDAC-2 Shibata,ISSCC17CT signalAnti

71、aliasingfilterDriverBackendDT Amp22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference8 of 57Alternative:Continuous-Tim

72、e Pipelined ADC 2+subADC+subDAC-2 Shibata,ISSCC17CT signalsAntialiasingfilterDriverBackendDT AmpDelay22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE Internatio

73、nal Solid-State Circuits Conference9 of 57Alternative:Continuous-Time Pipelined ADC 2+subADC-+subDACAnalogDelay2 Shibata,ISSCC17CT signalsDelayAntialiasingfilterDriverBackendCT AmpCTP22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction

74、Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference10 of 57System Benefits of CTP+subADC-+subDACAnalogDelay2 Shibata,ISSCC17BackendCT AmpCTPResistive Zin+AntialiasingSimplifies signal chain designRelaxedAntialiasingFilterRelaxedDriver

75、22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference11 of 57How do CTPs Fare?BW GHzData points:1997 2023 ISSCC&VLSI 1B

76、W 1WHD3 80dBFS2 Shibata,ISSCC17NSD dBFS/Hz22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference12 of 57Limitations of P

77、rior Low-NSD CTP+subADC-+subDACAnalogDelayCTP4 CTP stagesNSD=164dBFS/HzFive stages2.3W power2 Shibata,ISSCC17CT Amp22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 I

78、EEE International Solid-State Circuits Conference13 of 57Limitations of Prior Low-NSD CTP+subADC-+subDACAnalogDelayNon-idealities cancelled during reconstructionLimits HD3(last frontier)Process noise-like signal Passive22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC

79、with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference14 of 57Proposed ADC Architecture+subADC-+subDACAnalogDelayVCO ADCStage 2Stage 1Noise shapingNSD=164dBFS/HzThree stages0.7W powerCT Amp22.2:A 700MH

80、z-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference15 of 57Proposed ADC Architecture+subADC-+subDACAnalogDelayVCO ADCStage 2Stage

81、 1DRF with background cal.4 Shibata,ISSCC2020Digital Reconstruction Filter(DRF)CT Amp22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State

82、Circuits Conference16 of 57Proposed ADC Architecture+subADC-+subDACAnalogDelayVCO ADCStage 2Stage 1Digital Reconstruction Filter(DRF)Digital feedforward DAC Error CancellationHD3 85dBFSDEC+CT Amp22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Rec

83、onstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference17 of 57Stage Circuit Design+subADC-+subDACAnalogDelayVCO ADCStage 2Stage 1CT AmpLow NSDHigh gainImpedance scaled22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continu

84、ous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference18 of 57FLASHRDACMUX(4 Taps)Stage 1 Circuit Design1001.5Low noiseGood phase linearityPoor delay&tunability Delay tuned using

85、 MUX2 Shibata,ISSCC176-section LC lattice delay 222.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference19 of 57FLASHRDAC

86、Stage 1 Circuit Design Delay=234ps=6.4GS/s4-section delay1.522.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference20 of

87、57FLASHRDACStage 1 Circuit Design Delay=292ps=5GS/s5-section delay1.522.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Confere

88、nce21 of 57FLASHRDACStage 1 Circuit DesignFlash-DACFlash ADC(17 levels)Resistive thermometric DAC 6 Low noise with low supply Needs wideband low-Z virtual groundBiquad6 Theertham,JSSC20RDAC Unit Element22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digi

89、tal Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference22 of 57Sub-DAC Errors+subADC-+subDACAnalogDelayCT AmpBackend1()DRFNon-ideal+()22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with

90、 On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference23 of 57Sub-DAC Errors+subADC-+subDACAnalogDelay+1()DRF+Ideal()Model sub-DAC errors with block22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Contin

91、uous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference24 of 57Sub-DAC Errors+subADC-+subDACAnalogDelay+1()DRF+Sub-DAC errors appear at output HD3Analog solutions suffer from tra

92、deoffs()22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference25 of 57DAC Error Cancellation(DEC)+subADC-+subDACAnalogDe

93、lay+1()DRF+Digitally cancel via feedforward injection22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference26 of 57DAC E

94、rror Cancellation(DEC)+subADC-+subDACAnalogDelay+1()DRF+Prior work:Static errors only5 Bolatkale,ISSCC2022This work:Static&timing errors better HD322.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital C

95、ancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference27 of 57DAC Error Model+11MUEi+1122.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IE

96、EE International Solid-State Circuits Conference28 of 57DAC Error Model:Static ErrorMUEi+1+(1+,)(1+,)122.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE Internati

97、onal Solid-State Circuits Conference29 of 57DAC Error Model:Static ErrorMUEi+11Error,+,+(1+,)(1+,)22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International

98、 Solid-State Circuits Conference30 of 57DAC Error Model:Static Error+1+(1+,)(1+,),Error,+,MUEi+122.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International S

99、olid-State Circuits Conference31 of 57DAC Error Model:Timing ErrorMUEi+1122.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Con

100、ference32 of 572,DAC Error Model:Timing ErrorError approx.+2,MUEi+1Error122.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Con

101、ference33 of 57DAC Error Model:Timing Error,(1)ErrorMUEi+12,+2,Error approx.122.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits

102、 Conference34 of 57DAC Error Model,+,(1)Harmonic distortion!Need to estimate,and,MUEi+22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State

103、 Circuits Conference35 of 57Error Estimation+subADC+AnalogDelayUEiUEref-0Two of M UEs022.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State

104、 Circuits Conference36 of 57Error Estimation+UEi+ditUErefref+dit-()dit=22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Confe

105、rence37 of 57Static Error Estimation+UEi+UErefref+-(,),ditBackend+ditdit22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conf

106、erence38 of 57(,)Static Error Estimation+UEi+UErefref+-XCORRditBackend+ditditdit(,)22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Ci

107、rcuits Conference39 of 57Timing Error Estimation+UEi+UErefref+-XCORR(,)()Backend(,)dit+ditditdit22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International S

108、olid-State Circuits Conference40 of 57Putting It All Together+subADC-+AnalogDelay1()+MUEi+MDEC,ref,refInject estimated errors into DECExtract errors of all UEs22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 usi

109、ng Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference41 of 57Die Photo(16nm FinFET,3mm2)22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC

110、Errors 2024 IEEE International Solid-State Circuits Conference42 of 57FFT:No SignalAmp.dBFS/NBWFreq.MHzNSD dBFS/HzNBW=195kHzNSD over 5MHz-705MHz:163.7dBFS/Hzfs=6.4GS/s22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS

111、 HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference43 of 57DEC:One Tone(1dBFS)Amp.dBFS/NBWFreq.MHzNSD dBFS/HzDEC OFFDEC ONfs=6.4GS/sNBW=195kHzHD3:80 88dBFS22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip D

112、igital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference44 of 57DEC:Two Tone(7dBFS/Tone)Amp.dBFS/NBWFreq.MHzNSD dBFS/Hzfs=6.4GS/sNBW=195kHzIM3:86 90dBFSDEC OFFDEC ON22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW C

113、ontinuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference45 of 57HD2/HD3 Over finAmp.dBFSHD2HD3DEC OFFDEC ON8dB2dBAin=1dBFSInput Freq.MHzfs=6.4GS/s22.2:A 700MHz-BW 164dBFS/Hz-

114、Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference46 of 57Performance Over findBInput Freq.MHzDistortion falls out of bandAin=1dBFSfs=6.4GS/sDEC

115、 ON22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference47 of 57STFInput Freq.MHzdBAntialiasing 70dBDRF notchfs=6.4GS/s

116、22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 70dBInput Amp.dBFSdBfs=6.4GS/sDEC ON22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3

117、 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference49 of 57fsTunability(1dBFS Tone)Amp.dBFS/NBWFreq.MHzNSD dBFS/HzDEC OFFDEC ONHD3:84 97dBFSfs=5GS/sNBW=153kHz22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Di

118、gital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference50 of 57Comparison TableThis workISSCC 2017 2ISSCC 2020 4VLSI 2023 7ISSCC 2023 3ArchitectureCT pipelineCT pipelineCT pipelineCT IL pipelineDT IL pipelinefSGS/s6.4

119、9.08.06.421.8BW MHz70011258001000900Small-Signal NSD dBFS/Hz164164148NANALarge-Signal NSD dBFS/Hz161154147151150HD3dBFS857884634140022.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of

120、DAC Errors 2024 IEEE International Solid-State Circuits Conference51 of 57Comparison TableThis workISSCC 2017 2ISSCC 2020 4VLSI 2023 7ISSCC 2023 3ArchitectureCT pipelineCT pipelineCT pipelineCT IL pipelineDT IL pipelinefSGS/s6.49.08.06.421.8BW MHz70011258001000900Small-Signal NSD dBFS/Hz164164148NAN

121、ALarge-Signal NSD dBFS/Hz161154147151150HD3dBFS857884634140022.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference52 of

122、57Comparison TableThis workISSCC 2017 2ISSCC 2020 4VLSI 2023 7ISSCC 2023 3ArchitectureCT pipelineCT pipelineCT pipelineCT IL pipelineDT IL pipelinefSGS/s6.49.08.06.421.8BW MHz70011258001000900Small-Signal NSD dBFS/Hz164164148NANALarge-Signal NSD dBFS/Hz161154147151150HD3dBFS8578846341400*DRF power n

123、ot included DRF power included 22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference53 of 57Comparison TableThis workIS

124、SCC 2017 2ISSCC 2020 4VLSI 2023 7ISSCC 2023 3ArchitectureCT pipelineCT pipelineCT pipelineCT IL pipelineDT IL pipelinefSGS/s6.49.08.06.421.8BW MHz70011258001000900Small-Signal NSD dBFS/Hz164164148NANALarge-Signal NSD dBFS/Hz161154147151150HD3dBFS857884634140022.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-

125、NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference54 of 57What Was AchievedBW GHzData points:1997 2023 ISSCC&VLSI 1This workHD3 85dBFSPower=0.7WBW 500MHzNSD

126、dBFS/HzNSD160dBFS/Hz3rdorder distortion500MHzPower1W22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference55 of 57Conclu

127、sionCT pipelined ADC Performance:Ultra-low small-signal NSD=164dBFS/Hz HD3 85dBFS Power=703mW(including DRF+DEC)BW=700MHz at 6.4GS/s Enabling techniques:On-chip digital cancellation of static and timing DAC mismatch errors Tunable LC lattice delay Resistive sub-DAC22.2:A 700MHz-BW 164dBFS/Hz-Small-S

128、ignal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference56 of 57Acknowledgements SER design:A.Bray and R.Miller Layout:B.Banna,R.Britton,S.Brown,P.Durant,T.F

129、reeman,G.Harris,D.Hedges,B.Holford,A.Hung,E.Krommenhoek,D.Lynch,D.Martin,C.ODonnell,N.Oliver,T.Pilling,D.Pinales,J.Vanhoy,M.Williams,G.Wong,&B.Zhou Digital PnR:D.Shenoi ESD:S.Parathasarathy Laminate:A.Aucoin,R.Broughton-Blanchard,D.Rey-Losada,R.Shumovich,O.Wambu,and X.Xue Tapeout support:M.Bowers,B.

130、Chen,and M.Richards E.Alvarez Fontecilla for thoughtful discussions&E.Cooper for die photos Management:S.Aghtar,A.Boyce,P.Brown,S.Devarajan,J.Dispirito,J.Hall,R.Lourens,L.Magaldi,F.Murden,D.Robertson,and W.Taylor22.2:A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On

131、-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference57 of 57References1B.Murmann,ADCPerformanceSurvey1997-2023,Online.Available:https:/ H.Shibata et al.,A 9GS/s 1GHz-BW oversampled continuous-time pipeline

132、ADC achieving161dBFS/Hz NSD,ISSCC,Feb.2017,pp.278-279.3 S.-E.Hsieh et al.,A 1.8GHz 12b pre-sampling pipelined ADC with reference buffer and OP powerrelaxations,ISSCC,Feb.2023,pp.166-168.4 H.Shibata et al.,An 800MHz-BW VCO-based continuous-time pipelined ADC with inherentantialiasing and on-chip digi

133、tal reconstruction filter,ISSCC,Feb.2020,pp.260-262.5 M.Bolatkale et al.,A 28nm 6GHz 2b Continuous-Time ADC with 101 dBc THD and 120MHzbandwidth using digital DAC error correction,ISSCC,Feb.2022,pp.416-418.6 R.Theertham et al.,Design techniques for high-resolution continuous-time Delta-Sigma convert

134、erswith low in-band noise spectral density,IEEE JSSC,vol.55,no.9,pp.2429-2442,Sept.2020.7 R.Mittal et al.,A 6.4-GS/s 1-GHz BW continuous-time pipelined ADC with time-interleaved sub-ADC-DAC achieving 61.7-dB SNDR in 16-nm FinFET,IEEE Symp.VLSI Tech.and Circ.,2023,pp.1-2.22.2:A 700MHz-BW 164dBFS/Hz-S

135、mall-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving-85dBFS HD3 using Digital Cancellation of DAC Errors 2024 IEEE International Solid-State Circuits Conference58 of 57Please Scan to Rate Please Scan to Rate This PaperThis Paper22.3:A 76mW 40GS/s 7b Time-

136、Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference1 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input

137、 TrackingAmy Whitcombe1,Somnath Kundu2,4,Hariprasad Chandrakumar2,Abhishek Agrawal2,Thomas Brown2,Steven Callender3,Brent Carlton2,Stefano Pellerano21Intel,Santa Clara,CA;2Intel,Hillsboro,OR;3Intel,Fort Collins,CO;4now with AMD,Hillsboro,OR22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-D

138、omain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference2 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Outline Introduction ADC ImplementationTop-level ADC ArchitectureCommon Mode TrackingMerged TDC+TVC Measurement Results

139、Conclusion22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference3 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Outline Introduction ADC ImplementationTop-level A

140、DC ArchitectureCommon Mode TrackingMerged TDC+TVC Measurement Results Conclusion22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference4 of 76Distribution Statement A(Approved for Public Release,Dis

141、tribution Unlimited)MotivationTrend towards ADC/DSP-based architectures to improve data rate&reach for high-speed communication linksGrowing demand for high-speed,moderate resolution ADCs with:*Data from T.Anand,“Wireline Link Performance Survey,”Online.28 GS/s ADCs56 GS/s ADCsWireline Link Survey*L

142、ow power consumptionRobust operationLow complexityImproved speedLonger reach22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference5 of 76Distribution Statement A(Approved for Public Release,Distrib

143、ution Unlimited)High-speed ADC architectures1M1SARNConventional architecture:Time-interleaved SAR ADCSurvey of 0.5-10 GS/s,6-8b single-channel ADCsMore efficientFasterGood power efficiencyRobust operation w/well-matched capacitive DACSARB.Murmann,“ADC Performance Survey 1997-2023,”Online.Includes su

144、b-ADCs estimated from time-interleaved ADCs22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference6 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)High-speed ADC ar

145、chitectures1M1SARNConventional architecture:Time-interleaved SAR ADCSurvey of 0.5-10 GS/s,6-8b single-channel ADCsMore efficientFasterGood power efficiencyRobust operation w/well-matched capacitive DACMulti-rank samplingLimited single-channel speedSARB.Murmann,“ADC Performance Survey 1997-2023,”Onli

146、ne.Includes sub-ADCs estimated from time-interleaved ADCs22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference7 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1V

147、TCTDCHigh-speed ADC architecturesAlternate architecture:Time-interleaved time-domain ADCFast voltage-to-time converter(VTC)+time-to-digital converter(TDC)minimizes interleaving factorCompact,scaling-friendly designSurvey of 0.5-10 GS/s,6-8b single-channel ADCsMore efficientFasterTime-basedB.Murmann,

148、“ADC Performance Survey 1997-2023,”Online.Includes sub-ADCs estimated from time-interleaved ADCs22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference8 of 76Distribution Statement A(Approved for Pu

149、blic Release,Distribution Unlimited)M1VTCTDCHigh-speed ADC architecturesAlternate architecture:Time-interleaved time-domain ADCVTC0 OUT+/-VTC1 OUT+/-VTC3 OUT+/-Voltage samplesVTC2 OUT+/-V0V1V2V3t0Voltage-to-time conversionSignal encoded in edge delay differencet1t2t3Fast voltage-to-time converter(VT

150、C)+time-to-digital converter(TDC)minimizes interleaving factorCompact,scaling-friendly design22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference9 of 76Distribution Statement A(Approved for Publi

151、c Release,Distribution Unlimited)T0T1T2T3T4T5T6Thermometer to binary encoderB2:0+-+-+-+-+-+-+-tututututututuSTARTSTOPM1VTCTDCHigh-speed ADC architecturesAlternate architecture:Time-interleaved time-domain ADCRequires PVT&mismatch sensitive time-domain referencesExample 3b flash TDCFast voltage-to-ti

152、me converter(VTC)+time-to-digital converter(TDC)minimizes interleaving factorCompact,scaling-friendly design22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference10 of 76Distribution Statement A(Ap

153、proved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCHigh-speed ADC architecturesHybrid architecture:Time-interleaved voltage/time ADCRobust operation w/SAR ADCVoltage-to-time conversionTime-to-voltage conversionVoltage inputTime domain signalVoltage sample to quantize22.3:A 76mW 40GS

154、/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference11 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCHigh-speed ADC architecturesHybrid architecture:Time-int

155、erleaved voltage/time ADCEasy digital de-multiplexing of time-domain waveform with signal+clock informationVTC0 OUT+/-Digital de-multiplexingTDC0 IN+/-TDC1 IN+/-TDC2 IN+/-TDC3 IN+/-Zhu,CICC 15Robust operation w/SAR ADCVTC serves as high-speed input bufferScaling-friendly signal&clock routing22.3:A 7

156、6mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference12 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)RSTITVCCTVCVOUT VOUTtTime VoltageCTVCIVTCCVTCITVCVINM1VTC1:NTVC1NSA

157、RTDCHigh-speed ADC architecturesHybrid architecture:Time-interleaved voltage/time ADCRobust operation w/SAR ADCVTC serves as high-speed input bufferScaling-friendly signal&clock routingPVT-insensitive gain is possiblePVT-insensitive gain w/VTV conversionHao,ISSCC 23IVTCCVTCCVTCVINIVTCt Voltage TimeV

158、INVoltage TimeTime Voltage22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference13 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCHigh-speed ADC

159、 architecturesHybrid architecture:Time-interleaved voltage/time ADCSAR Logic+-N.MSBCDAC+CDAC-LSB.Coarse estimateTDC estimateCoarse TDC estimate fewer SAR cyclesWhitcombe,VLSI 22Redundancy for TDC errorsTDC assist to boost SAR speedRelaxed TDC requirementsRobust operation w/SAR ADCVTC serves as high-

160、speed input bufferScaling-friendly signal&clock routingPVT-insensitive gain is possible22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference14 of 76Distribution Statement A(Approved for Public Rel

161、ease,Distribution Unlimited)M1VTC1:NTVC1NSARTDCHigh-speed ADC architecturesHybrid architecture:Time-interleaved voltage/time ADCSAR Logic+-N.MSBCDAC+CDAC-LSB.Coarse estimateTDC estimateWhitcombe,VLSI 22Coarse TDC estimate fewer SAR cyclesDelay to relax TDC speedTDC assist to boost SAR speedRelaxed T

162、DC requirementsRobust operation w/SAR ADCVTC serves as high-speed input bufferScaling-friendly signal&clock routingPVT-insensitive gain is possible22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Confer

163、ence15 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCADC architecture in this workHybrid architecture:Time-interleaved voltage/time ADCKey objectives of this work:1.Leverage hybrid architecture to simplify interleaving implementation2.Enhance sub

164、-ADC robustness to make architecture suitable for time interleaving2.TDC assist to boost SAR speedRelaxed TDC requirementsRobust operation w/SAR ADCVTC serves as high-speed input bufferScaling-friendly signal&clock routingPVT-insensitive gain is possible22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid

165、Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference16 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Outline Introduction ADC ImplementationTop-level ADC ArchitectureCommon Mode TrackingMerged TDC+TVC Measu

166、rement Results ConclusionM1VTC1:NTVC1NSARTDC22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference17 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Time-interleave

167、d(TI)ADC floorplan requirements1M1SARNPlacing digital outputs on a single boundary simplifies system floorplanHigh-speed I/O on boundaryDSPAnalog front-endADC.Sub-ADCSub-ADCSub-ADCDigital outputsSub-ADCSub-ADCSub-ADCSub-ADCSub-ADC.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC

168、 with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference18 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)DSPAnalog front-endQ ADCI ADCTime-interleaved(TI)ADC floorplan requirements1M1SARNPlacing digital outputs on a single boundary s

169、implifies system floorplanHigh-speed I/O on boundaryScalable to multiple ADCs.Sub-ADCSub-ADCSub-ADCDigital outputsSub-ADCSub-ADCSub-ADCSub-ADCSub-ADC.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Con

170、ference19 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited).Sub-ADCSub-ADCSub-ADCDigital outputsSub-ADCSub-ADCSub-ADCSub-ADCSub-ADC.DSPAnalog front-endQ ADCI ADCTime-interleaved(TI)ADC floorplan requirements1M1SARNPlacing digital outputs on a single boundary simplifie

171、s system floorplanHigh-speed I/O on boundaryScalable to multiple ADCsLong internal interconnectHigh power buffer22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference20 of 76Distribution Statement

172、A(Approved for Public Release,Distribution Unlimited).Sub-ADCSub-ADCSub-ADCDigital outputsSub-ADCSub-ADCSub-ADCSub-ADCSub-ADC.DSPAnalog front-endQ ADCI ADCTime-interleaved(TI)ADC floorplan requirements1M1SARNPlacing digital outputs on a single boundary simplifies system floorplanHigh-speed I/O on bo

173、undaryScalable to multiple ADCsLong internal interconnectHigh power bufferSub-ADC clocks22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference21 of 76Distribution Statement A(Approved for Public Re

174、lease,Distribution Unlimited)Sub-ADCSub-ADC.Sub-ADCSub-ADCVTCVTC.Digital outputsVTCVTCM1VTC1:NTVC1NSARTDCTime-domain routing for TI-ADCTime-domain signaling allows digital signal routing with standard cell buffersLogic-level signal22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC

175、 with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference22 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCTime-domain routing for TI-ADCDifferential signaling is insensitive to routing latencySub-ADCSub-ADC.Sub-ADCS

176、ub-ADCVTCVTC.Digital outputsVTCVTCCK+CK-t22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference23 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTD

177、CTime-domain routing for TI-ADCDifferential signaling is insensitive to routing latencySub-ADCSub-ADC.Sub-ADCSub-ADCVTCVTC.Digital outputsVTCVTCCK+CK-t22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Co

178、nference24 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCTime-domain routing for TI-ADCSub-ADCSub-ADC.Sub-ADCSub-ADCVTCVTC.Digital outputsVTCVTCDifferential signaling is insensitive to routing latency VTC delays can varyCK+0CK-0CK+1CK-1Common mod

179、e delay mismatch22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference25 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)t+tOSDifferential offset must be compensate

180、d to eliminate sub-ADC mismatchM1VTC1:NTVC1NSARTDCTime-domain routing for TI-ADCSub-ADCSub-ADC.Sub-ADCSub-ADCVTCVTC.Digital outputsVTCVTCCK+0CK-0Differential delay mismatch22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International So

181、lid-State Circuits Conference26 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Overall ADC architectureUse digital nature of time-domain signal to simplify routingVTCRoutingHybrid voltage/time ADC383b+5b SAR1:4Merged TVC+3b TDCBuf.Input signal12x8x485048 TDC-assiste

182、d SAR sub-ADCs12 VTCs22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference27 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Overall ADC architectureInterleaved sa

183、mpling pulses generated from fs/2 clockVTCRoutingHybrid voltage/time ADC383b+5b SAR1:4Merged TVC+3b TDCBuf.Input signal12x8x4850Sampling clock generationS0S11fs/2 CLKfs/2 CLKS0S1S112/fs22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE Int

184、ernational Solid-State Circuits Conference28 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Off-chip foreground DCC control logic090/2Pulse gen.12x+-+-/312DCCAvg.output0.5Time-interleaved ADC clockingfs/2 CLKfs/2 clockS0S1S112/fsS2fs/12 sampling pulsesfs/4 quadratur

185、efs/12 enable signals22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference29 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)fs/4 quadratureOff-chip foreground DCC

186、 control logic090/2Pulse gen.12x+-+-/312DCCAvg.output0.5Time-interleaved ADC clockingfs/2 CLKfs/2 clockS0S1S112/fsS2fs/12 sampling pulsesQ ADCI ADCDigital signal processingAnalog front-end+clock gen./2600umTargeting system with I+Q ADCs shared clock divider22.3:A 76mW 40GS/s 7b Time-Interleaved Hybr

187、id Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference30 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)fs/2 clockfs/2 CLKOff-chip foreground DCC control logic090/2Pulse gen.12x+-+-/312DCCAvg.output0.5Time-

188、interleaved ADC clockingS0S1S112/fsS2fs/12 sampling pulsesfs/4 quadraturefs/12 enable signalsENfs/4SSampling pulse generationENfs/4VTC loadSS25 fFVIN22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conf

189、erence31 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)fs/2 clockfs/2 CLKOff-chip foreground DCC control logic090/2Pulse gen.12x+-+-/312DCCAvg.output0.5Time-interleaved ADC clockingS0S1S112/fsS2fs/12 sampling pulsesfs/4 quadraturefs/12 enable signalsENfs/4SSampling

190、 pulse generationENfs/4VTC loadSS25 fFVIN090/2Pulse gen.12x/312DCCfs/12 enable signalsS0S1S112/fsS2fs/12 sampling pulsesShallow edge rate to increase tuning range higher jitter13 ps34 fs73 fs3b6b22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 202

191、4 IEEE International Solid-State Circuits Conference32 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)fs/4 quadraturefs/2 clockfs/2 CLKOff-chip foreground DCC control logic090/2Pulse gen.12x+-+-/312DCCAvg.output0.5Time-interleaved ADC clockingS0S1S112/fsS2fs/12 samp

192、ling pulsesRing oscillator for random samplingUp to 8 ps skew from duty cycle error based on measurements of 5 die across VDD&fsampJ.Kim,JSSC 19Coarse DCC reduces fine DTC jitter by 35%4 ps local skew34 fs66 fs8 ps skew w/o DCC43 fs22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain AD

193、C with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference33 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)M1VTC1:NTVC1NSARTDCOutline Introduction ADC ImplementationTop-level ADC ArchitectureCommon Mode TrackingMerged TDC+TVC Measurem

194、ent Results Conclusion22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference34 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Voltage-to-time conversion conceptVol

195、tage inputTime-domain outputVt22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference35 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Voltage-to-time conversion co

196、nceptVoltage inputVtTime-domain outputVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationThreshold(VTH)22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference36 of 76Distribution State

197、ment A(Approved for Public Release,Distribution Unlimited)Voltage-to-time conversion conceptVoltage inputVtTime-domain outputVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationLarge time-domain output swing preferred to relax jitter impact of subsequent stagesThreshold(VTH)22.3:A 76mW

198、40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference37 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Voltage-to-time conversion limitationsVMINTime-domain outputVIN+VIN-Cro

199、ssing detectorRamp injection+SamplerVTC ImplementationDischarge time(textra)from VMINto VTHreduces speed or swingThreshold(VTH)1/fVTCtsigtextratsamptRSTVCM22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuit

200、s Conference38 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Voltage-to-time conversion limitationsVMINTime-domain outputVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationThreshold(VTH)1/fVTCtsigtextratsamptRSTVCMDischarge time(textra)from VMINto VTH

201、reduces speed or swing22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference39 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Voltage-to-time conversion limitation

202、sVMINTime-domain outputVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationCrossing detector should allow VTHto track VMINThreshold(VTH)1/fVTCtsigtextratsamptRSTVCM22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE Internation

203、al Solid-State Circuits Conference40 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Crossing detector architecturesVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationCrossing detector should allow VTHto track VMINContinuous-time comparatorInverter chai

204、nScaling friendlySelf biasingPVT-sensitive VTHDefined VTHPower hungryHigher noiseVINVTHVIN22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference41 of 76Distribution Statement A(Approved for Public

205、Release,Distribution Unlimited)Crossing detector architecturesVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationCrossing detector should allow VTHto track VMINContinuous-time comparatorInverter chainScaling friendlySelf biasingPVT-sensitive VTHDefined VTHPower hungryHigher noiseVINVTH

206、VINVTH VDD,invVDD,inv22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference42 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)VDD,invVTH,REPVTARGReplicaVINCrossing

207、detector architecturesVIN+VIN-Crossing detectorRamp injection+SamplerVTC ImplementationCrossing detector should allow VTHto track VMINInverter chainScaling friendlySelf biasingPVT-sensitive VTHVINVTH VDD,invVDD,invInverter w/VCMtrackingScaling friendlySelf biasingDefined VTH22.3:A 76mW 40GS/s 7b Tim

208、e-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference43 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Voltage-to-time converter(VTC)implementationVIN+VIN-VTARGISWING=VCM-0.5RISWINGISWING

209、 scaled to expected full-scale range22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference44 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)VIN+VDD,invVIN-RRVTH,RE

210、PVO-VO+VTARG size replica inv.SSRamp injectionVM+VM-ISWINGSVoltage-to-time converter(VTC)implementationVIN+VIN-VTARGVM+VM-22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference45 of 76Distribution

211、Statement A(Approved for Public Release,Distribution Unlimited)VIN+VIN-VTARGSVRAMPVO+/VO-Voltage-to-time converter(VTC)implementationLiu,ISSCC 22VM+VM-22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Co

212、nference46 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)SRSTVoltage-to-time converter(VTC)implementationReduce memory effectsVIN+VIN-VTARGVRAMPVO+/VO-22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE In

213、ternational Solid-State Circuits Conference47 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)1VVIN+VDD,invVIN-SVrampRRVTH,REPVO-VO+VTARG size replica inv.RSTPulse gen.SSSVM+VM-VIN+VDD,invVIN-SVM+VM-VrampRRVTH,REP25fF70fF25fFVO-VO+VTARG size replica inv.RSTPulse gen.

214、SSSWide usable VCM range w/trackingSFDR drop w/VDD,invsaturation Voltage-to-time converter(VTC)implementationVIN+VDD,invVIN-SVM+VM-VrampRRVTH,REP25fF70fF25fFVO-VO+VTARG size replica inv.RSTPulse gen.SSS22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Track

215、ing 2024 IEEE International Solid-State Circuits Conference48 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)VIN+VIN-SVM+VM-VrampVO-VO+Pulse gen.SSSVDD,inv=1VWide usable VCM range w/trackingSFDR drops if VMIN full-scale time swingCSARRSTtmaxCK-CK+CSARRSTtmaxtmaxtmax

216、22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference54 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)CSARRSTTime-to-voltage conversion operationPulse generation

217、 requires tmaxdelay full-scale time swingCSARRSTtmaxCK-CK+CSARRSTtmaxtmax22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference55 of 76Distribution Statement A(Approved for Public Release,Distribut

218、ion Unlimited)CSARRSTtmaxCSARRSTtmaxTime-to-voltage conversion operationCK-Pulse generation requires tmaxdelay full-scale time swingCK+CSARRSTtmaxtmax22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Con

219、ference56 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)CSAR+RSTtmaxCSAR-TVC+Time-to-voltage conversion operationPulse generation requires tmaxdelay full-scale time swingCK-CK+22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode In

220、put Tracking 2024 IEEE International Solid-State Circuits Conference57 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Time-to-voltage conversion operationCK-TDC sets time-domain swing tmaxneeds to match TDC rangeCK+22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Volta

221、ge/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference58 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Proposed merged TVC+TDCSolution:Merge tmaxdelay line with TDC referencestmaxdelaytmaxdelay22.3:A 76mW 40GS/s 7

222、b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference59 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Proposed merged TVC+TDCSolution:Merge tmaxdelay line with TDC referencesExtra d

223、elay+offset controlExtra delay+offset control22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference60 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)RSTRSTTDC Logi

224、cCK1+CK2+CK3+CK+CK1-CK2-CK3-CK-CK+CK-3Voltage-domain SAR.5b SAR Logic3b TDC est.32C16C8C8C4C1C32C16C8C8C4C1CVDAC+VDAC-CKD-CKD+tOS-tOS+1b redundancy for TDC error+-Proposed merged TVC+TDCAccuracy of TDC estimate affects required redundancy22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Dom

225、ain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference61 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Merged TVC+TDC reliabilityFlash TDC improves reliability with small power overhead118 uW 1 GS/s89 uW 1 GS/s3b Succ.Approx

226、.TDCThis work:3b Flash TDCMonte Carlo simulated variabilityMatching neededWhitcombe,VLSI 22Included in TVC22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference62 of 76Distribution Statement A(Appr

227、oved for Public Release,Distribution Unlimited)Outline Introduction ADC ImplementationTop-level ADC ArchitectureCommon Mode TrackingMerged TDC+TVC Measurement Results Conclusion22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE Internation

228、al Solid-State Circuits Conference63 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Bias TClock26 GHz Balun0-25GHz 20-25GHz 26 GHz BalunDC suppliesSPI adapterSignalMatched cablesADCSRAM+SPIMatched cablesDie photograph&measurement setupIntel 22FFL FinFET CMOS 8 metal

229、 layers(2 thick)RF device optionOff-chip correction algorithmsProbe landingTest equipment22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference64 of 76Distribution Statement A(Approved for Public R

230、elease,Distribution Unlimited)Measured output spectrum 40 GS/sOutput spectrum w/2 GHz inputOutput spectrum w/20 GHz inputHD2HD3HD2HD322.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference65 of 76Di

231、stribution Statement A(Approved for Public Release,Distribution Unlimited)Measured output spectrum 50 GS/sHD2HD3HD2HD3Output spectrum w/2 GHz inputOutput spectrum w/20 GHz input22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE Internation

232、al Solid-State Circuits Conference66 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Measured SNDR/SFDR vs.frequencySNDRSFDRChip#3 performance:fin=2 GHzfin=20 GHzConsistent performance&power for 5 chips22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain

233、 ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference67 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Static nonlinearityRobust flash TDC avoids missing codes to keep DNL 1 LSBWorst-case DNL:+0.75/-0.48Worst-case INL:+1.02/-0.

234、8722.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference68 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Measured sensitivity to VCMTracking allows 200 mV VCMrang

235、eMeasured with 2 GHz input tone 40 GS/s,VDD=0.85VExpected VDD,invsaturation22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference69 of 76Distribution Statement A(Approved for Public Release,Distrib

236、ution Unlimited)Measured power breakdown 40 GS/sTotal power 40 GS/s:76 mW22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference70 of 76Distribution Statement A(Approved for Public Release,Distribut

237、ion Unlimited)Comparison to state-of-the-artThis worka,bNguyenISSCC 21KullaISSCC 18Kull VLSI 18YonarVLSI 22ZhuaJSSC 23Agrawala,bISSCC 23Channel arch.TDC-assisted SARSARSARSARSARPipe.SAR TDC+SAR#Channels481286448643248Tech.22nm FinFET7nm14nm14nm4nm22nm22nmSupply(V)0.850.91.0-0.8/0.90.80.80.85/0.91.0f

238、s(GS/s)404550977232563840Resolution(b)78810877Input swing(Vpp,diff)0.5-0.650.60.80.5-ADC core power(mW)66.186.0116.030023519924012084Input buffer power(mW)10.311.314.6Excluded Excluded Excluded20SNDR low fin(dB)37.336.337.141.139.347.341.039.335.4SNDR 20GHz(dB)32.332.331.935.134.141.3c35.5c35.630.7S

239、NDR Nyq.(dB)32.230.93230.442.732.8FoMwd low fin(fJ/step)31.740.444.633.443.332.84741.954.1dFoMwd 20GHz(fJ/step)56.764.081.266.678.865.59264.1g92.8dFoMwd Nyq.(fJ/step)64.891.295.1e120.755.7f117Area(mm2)0.103h-0.150.160.0780.1070.138haChannel offset mismatch corrected off-chip.bChannel gain mismatch c

240、orrected off-chip.cEst.from SNDR vs.finplot.dPower incl.input buffer where available.efin=36 GHz.ffin=16 GHz.gfin=19 GHz.hArea incl.ref.buffers&bypass cap.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuit

241、s Conference71 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Comparison to state-of-the-artThis worka,bNguyenISSCC 21KullaISSCC 18Kull VLSI 18YonarVLSI 22ZhuaJSSC 23Agrawala,bISSCC 23Channel arch.TDC-assisted SARSARSARSARSARPipe.SAR TDC+SAR#Channels481286448643248T

242、ech.22nm FinFET7nm14nm14nm4nm22nm22nmSupply(V)0.850.91.0-0.8/0.90.80.80.85/0.91.0fs(GS/s)404550977232563840Resolution(b)78810877Input swing(Vpp,diff)0.5-0.650.60.80.5-ADC core power(mW)66.186.0116.030023519924012084Input buffer power(mW)10.311.314.6Excluded Excluded Excluded20SNDR low fin(dB)37.336.

243、337.141.139.347.341.039.335.4SNDR 20GHz(dB)32.332.331.935.134.141.3c35.5c35.630.7SNDR Nyq.(dB)32.230.93230.442.732.8FoMwd low fin(fJ/step)31.740.444.633.443.332.84741.954.1dFoMwd 20GHz(fJ/step)56.764.081.266.678.865.59264.1g92.8dFoMwd Nyq.(fJ/step)64.891.295.1e120.755.7f117Area(mm2)0.103h-0.150.160.

244、0780.1070.138haChannel offset mismatch corrected off-chip.bChannel gain mismatch corrected off-chip.cEst.from SNDR vs.finplot.dPower incl.input buffer where available.efin=36 GHz.ffin=16 GHz.gfin=19 GHz.hArea incl.ref.buffers&bypass cap.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Doma

245、in ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference72 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Comparison to state-of-the-artThis worka,bNguyenISSCC 21KullaISSCC 18Kull VLSI 18YonarVLSI 22ZhuaJSSC 23Agrawala,bISSCC 23

246、Channel arch.TDC-assisted SARSARSARSARSARPipe.SAR TDC+SAR#Channels481286448643248Tech.22nm FinFET7nm14nm14nm4nm22nm22nmSupply(V)0.850.91.0-0.8/0.90.80.80.85/0.91.0fs(GS/s)404550977232563840Resolution(b)78810877Input swing(Vpp,diff)0.5-0.650.60.80.5-ADC core power(mW)66.186.0116.030023519924012084Inp

247、ut buffer power(mW)10.311.314.6Excluded Excluded Excluded20SNDR low fin(dB)37.336.337.141.139.347.341.039.335.4SNDR 20GHz(dB)32.332.331.935.134.141.3c35.5c35.630.7SNDR Nyq.(dB)32.230.93230.442.732.8FoMwd low fin(fJ/step)31.740.444.633.443.332.84741.954.1dFoMwd 20GHz(fJ/step)56.764.081.266.678.865.59

248、264.1g92.8dFoMwd Nyq.(fJ/step)64.891.295.1e120.755.7f117Area(mm2)0.103h-0.150.160.0780.1070.138haChannel offset mismatch corrected off-chip.bChannel gain mismatch corrected off-chip.cEst.from SNDR vs.finplot.dPower incl.input buffer where available.efin=36 GHz.ffin=16 GHz.gfin=19 GHz.hArea incl.ref.

249、buffers&bypass cap.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference73 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Comparison to state-of-the-artLow absolu

250、te power 2 pJ/conversion(30 GS/s ADCsEnergy per conversionHigh-frequency FoMwThis work 0.85V0.9V1.0V1.0V0.9VThis work 0.85V22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference74 of 76Distribution

251、 Statement A(Approved for Public Release,Distribution Unlimited)Conclusion Hybrid voltage+time domain ADC simplifies time-interleaved ADC implementationTime-domain signal gives flexibility to simplify layout floorplan Techniques shown to improve sub-ADC robustnessCommon mode voltage tracking voltage

252、-to-time conversionMerged TVC+flash TDC improves DNL At 40 GS/s,consumes 76 mW and provides 32.3 dB SNDR 20 GHz,for 57 fJ/step FoMw,Nyq22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference75 of 76

253、Distribution Statement A(Approved for Public Release,Distribution Unlimited)Acknowledgements Trang Nguyen for testing support Cuong Le and Cristan Paulino for layout support Sergey Shumarayev for program supportThis research was developed with funding from the Defense Advanced Research Projects Agen

254、cy(DARPA).The views,opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S.Government.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input

255、Tracking 2024 IEEE International Solid-State Circuits Conference76 of 76Distribution Statement A(Approved for Public Release,Distribution Unlimited)Legal InformationThis presentation contains the general insights and opinions of Intel Corporation(“Intel”).The information in this presentation is prov

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259、United States and other countries.*Other names and brands may be claimed as the property of others.2024 Intel Corporation.22.3:A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking 2024 IEEE International Solid-State Circuits Conference77 of 76Distribution

260、Statement A(Approved for Public Release,Distribution Unlimited)Please Scan to Rate Please Scan to Rate This PaperThis Paper22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration

261、 2024 IEEE International Solid-State Circuits Conference1 of 62A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset CalibrationYunsong Tao,Mingyang Gu,Baoyong Chi,Yi Zhong,Lu Jie,and Nan SunTs

262、inghua University22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference2 of 62Outline Motivation Challenges and Solutions

263、 Circuit Implementation Measurement Results Conclusion22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference3 of 62Outlin

264、e Motivation Challenges and Solutions Circuit Implementation Measurement Results Conclusion22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-S

265、tate Circuits Conference4 of 62Motivation Application:wideband communicationDirect RF sampling receiversMillimeter-wave pulsed radar systems Design targetsHigh speed:4GS/sMedium resolution:6 8bLow power22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibratio

266、n and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference5 of 62Motivation Application:wideband communicationDirect RF sampling receiversMillimeter-wave pulsed radar systems Design targetsHigh speed:4GS/sMedium resolution:

267、6 8bTime-interleaved SAR ADCLow power22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference6 of 62Outline Motivation Chal

268、lenges and SolutionsTiming-Skew CalibrationSAR Speed Enhancement Circuit Implementation Measurement Results Conclusion22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024

269、 IEEE International Solid-State Circuits Conference7 of 62Outline Motivation Challenges and SolutionsTiming-Skew CalibrationSAR Speed Enhancement Circuit Implementation Measurement Results Conclusion22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration a

270、nd Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference8 of 62Challenge 1 Time-interleaved ADCHigh speed High energy efficiency Timing-skew mismatch tChannel 1Ts+t Ts t Channel 222.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR AD

271、C with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference9 of 62Challenge 1:Timing-Skew Calibration Time-interleaved ADCHigh speed High energy efficiency Timing-skew cal

272、ibrationTiming-skew mismatch tChannel 1Ts+t Ts t Channel 222.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference10 of 62P

273、rior Art Input requirementNon-zero derivative or well-defined statisticD.Stepanovic,JSSC,2013M.El-Chammas,JSSC,2011B.Razavi,JSSC,2013 R()0t V dV/dtt dV/dt22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pon

274、g Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference11 of 62Prior Art Input requirementNon-zero derivative or well-defined statisticLimited applicability Low frequency,small amplitude,non-stationary,time-variant,etc.D.Stepanovic,JSSC,2013M.El-Chammas,JSSC,2011B.Raz

275、avi,JSSC,2013 R()0t V dV/dtt dV/dt22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference12 of 62Prior Art:Clock-Injection

276、-Based Method Global clock injectionInput independent No residual skews Foreground calibration T.Miki,JSSC,2017Channel 1VinCLKrefChannel 2CLKrefCLK1CLK2t V 22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-P

277、ong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference13 of 62Prior Art:Clock-Injection-Based Method Local dithered-clock injectionInput independent Background calibration L.Luo,VLSI,2017Channel 1VinCD1CS1Channel 2CD2CS2CLKrefPN=1 22.4:A 4.8GS/s 7-ENoB Time-Interle

278、aved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference14 of 62Prior Art:Clock-Injection-Based Method Local dithered-clock injectionInput independent Backgr

279、ound calibration Large residual skews Input/clock routing mismatch Input/clock switch mismatch Injection capacitor mismatchL.Luo,VLSI,2017Channel 1VinCD1CS1Channel 2CD2CS2CLKrefPN=1 Routing MismatchSwitch MismatchCapacitor Mismatch22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Back

280、ground Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference15 of 62Prior Art:Clock-Injection-Based Method Local common-mode clock injectionInput independent Background calibration Large residual

281、skews Input routing mismatch Replica switch mismatch Common-mode voltage variationExtra spurs Time-variant input loadY.Wang,ISSCC,2023Channel 1VinCS1Channel 2CS2Common-Mode Clock Injection(fs/3)CLKrefRouting MismatchSwitch Mismatch22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Back

282、ground Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference16 of 62Prior Art:Clock-Injection-Based Method Background calibration without residual skews or spursT.Miki,JSSC,2017L.Luo,VLSI,2017Y.Wa

283、ng,ISSCC,2023TargetInput independentBackground calibrationResidual skewExtra spur22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circu

284、its Conference17 of 62Prior Art:Clock-Injection-Based MethodT.Miki,JSSC,2017L.Luo,VLSI,2017Y.Wang,ISSCC,2023TargetInput independentBackground calibrationResidual skewExtra spurInjectionLocationGlobalLocalLocalGlobalTypeClockDitherClockDitherDM/CMDifferential modeDifferential modeCommon modeDifferent

285、ial mode Background calibration without residual skews or spursGlobal dithered-clock injection in the differential mode22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 202

286、4 IEEE International Solid-State Circuits Conference18 of 62Proposed Global Dithered-Clock Injection Mismatch source Effect on calibrationRoutingInputIncluded in the calibrationClockNoSwitchInputIncluded in the calibrationClockNoReplicaNoRouting MismatchSwitch MismatchChannel 1VinCS1PN=1 Channel 2CS

287、2CLKref22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference19 of 62Proposed Dither-Based Calibration Global dithered-cl

288、ock injection in the differential modePN from PRBS generator+1+1CLKref-1-1+1PNVd,P/NCLK1CLK2Vd,refVd,2t2 Channel 1VinCS1PN=+1 or-1 Channel 2CS2Vd,PVd,NMUXCLKref22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Pi

289、ng-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference20 of 62Proposed Dither-Based Calibration Global dithered-clock injection in the differential modePN from PRBS generatorDdextraction and Doutrecovery by correlating Drawwith PNChannel 1VinCS1PN=+1 or-1 Chann

290、el 2CS2Vd,PVd,NMUXLPFDout,2PNDd,2Draw,2Dd,ref=Dd,1Variable Delay LineCLK2Timing-Skew DetectionCLKref22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE Internationa

291、l Solid-State Circuits Conference21 of 62Proposed Dither-Based Calibration Global dithered-clock injection in the differential modeInput independent Background calibration No residual skews or spurs Channel 1VinCS1PN=+1 or-1 Channel 2CS2Vd,PVd,NMUXCLKref22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC

292、 with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference22 of 62Outline Motivation Challenges and SolutionsTiming-Skew CalibrationSAR Speed Enhancement Circuit Implement

293、ation Measurement Results Conclusion22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference23 of 62Challenge 2 SAR ADCHigh

294、 energy efficiency Scaling friendly Low speed VinCDACDoutLogic22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference24 of

295、 62Challenge 2:SAR Speed Enhancement SAR ADCHigh energy efficiency Scaling friendly SAR speed enhancementLow speed VinCDACDoutLogic22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Cal

296、ibration 2024 IEEE International Solid-State Circuits Conference25 of 62Vin,ADCCDACLogicCLKSDrawCLKc2CLKc1Sampling 1 234567Prior Art:SAR ADC with Ping-Pong ComparatorsL.Kull,JSSC,2013 Comparator reset time removed from the critical path 22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Base

297、d Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference26 of 62Prior Art:SAR ADC with Ping-Pong Comparators Comparator reset time removed from the critical path Extra conversion time fo

298、r offset mismatch calibration L.Kull,JSSC,2013Vin,ADCCDACLogicCLKSDrawCLKc2CLKc1CLKRSTSampling 1 234567RSTCal.22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE In

299、ternational Solid-State Circuits Conference27 of 62V VinDoutLogicVosVresVinVoutaCDACfV VinDoutLogicVosVresVinVoutaCDACfProposed Ping-Pong Comparator Offset CalibrationNegative feedback loopSAR ADCAmplifier(a 1)ComparatorFeedback(f=1)CDACVout Vin(af 1)Dout Vin22.4:A 4.8GS/s 7-ENoB Time-Interleaved SA

300、R ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference28 of 62Proposed Ping-Pong Comparator Offset CalibrationNegative feedback loopSAR ADCAmplifier(a 1)Comparato

301、rFeedback(f=1)CDACVout Vin(af 1)Dout VinV 0(virtual ground)Vres Vos SAR ADC:an intrinsic negative feedback loopV VinDoutLogicVosVresVinVoutaCDACfV VinDoutLogicVosVresVinVoutaCDACf22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-

302、Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference29 of 62Proposed Ping-Pong Comparator Offset CalibrationL.Chen,JSSC,2017 SAR ADC:an intrinsic negative feedback loopVres Vos Last two Vres:normal distribution with comparator noiseVres7=Vr

303、es8=VosVosVres7Vres8Comparator NoiseVosVres7/Vres822.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference30 of 62Proposed

304、Ping-Pong Comparator Offset Calibration SAR ADC:an intrinsic negative feedback loopVres Vos Last two Vres:normal distribution with comparator noiseVres7=Vres8=Vos D7 D8=0L.Chen,JSSC,2017VosVres7Vres8Comparator NoiseVosVres7/Vres8D7D80.50.5D7D80.50.5VosVres7Vres8Comparator NoiseVosVres7/Vres822.4:A 4

305、.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference31 of 62 SAR ADC with ping-pong comparators2 loops sharing the same“virtual

306、 ground”Proposed Ping-Pong Comparator Offset CalibrationVinCDACDoutLogicVresVos1Vos2Loop 2Loop 1VosVres7/Vres80.50.522.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 I

307、EEE International Solid-State Circuits Conference32 of 62 SAR ADC with ping-pong comparators2 loops sharing the same“virtual ground”Distribution centers of Vres7,8(Vos2=Vos1=Vos)Vres7=Vres8=Vos D7 D8=0Proposed Ping-Pong Comparator Offset CalibrationVinCDACDoutLogicVresVos1Vos2Loop 2Loop 1VosVres7/Vr

308、es80.50.5D7D80.50.5VinCDACDoutLogicVresVos1Vos2Loop 2Loop 1VosVres7/Vres80.50.522.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuit

309、s Conference33 of 62 SAR ADC with ping-pong comparators2 loops sharing the same“virtual ground”Vres,odd Vos1(Loop 1)Vres,even Vos2(Loop 2)Proposed Ping-Pong Comparator Offset CalibrationVosVres7Vres8D7D8Vos1Vres7D7Vos2Vres8D8(Vos2 Vos1)Single ComparatorPing-Pong ComparatorsVosVres7Vres8D7D8Vos1Vres7

310、D7Vos2Vres8D8(Vos2 Vos1)Single ComparatorPing-Pong Comparators22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference34 of

311、 62 SAR ADC with ping-pong comparators2 loops sharing the same“virtual ground”Vres,odd Vos1(Loop 1)Vres,even Vos2(Loop 2)Distribution centers of Vres7,8(Vos2 Vos1)Vos1 Vres7,Vres8 Vos1)Ping-Pong ComparatorsVos2Vres7Vos1Vres8VosVres7Vres8D7D8Vos1Vres7D7Vos2Vres8D8(Vos2 Vos1)Single ComparatorPing-Pong

312、 Comparators22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference35 of 62 SAR ADC with ping-pong comparators2 loops shar

313、ing the same“virtual ground”Vres,odd Vos1(Loop 1)Vres,even Vos2(Loop 2)Distribution centers of Vres7,8(Vos2 Vos1)Vos1 Vres7,Vres8 0Proposed Ping-Pong Comparator Offset CalibrationD7D8 0.5 Vos1)Ping-Pong ComparatorsVos2Vres7Vos1Vres8VosVres7Vres8D7D8Vos1Vres7D7Vos2Vres8D8(Vos2 Vos1)Single ComparatorP

314、ing-Pong Comparators22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference36 of 62Proposed Ping-Pong Comparator Offset Ca

315、librationD7AverageD8sgnDcalSampling 1 234567RSTCal.Sampling 1 2345678Prior ArtProposed Bit-distribution-based calibrationBackground calibration Simple and fully digital 22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Back

316、ground Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference37 of 62Sampling 1 234567RSTCal.Sampling 1 234567Prior ArtProposedProposed SAR ADC with Ping-Pong Comparators Ping-pong operation with bit-distribution-based calibration Shorter conversion time No r

317、eset switch or logic 22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference38 of 62 Ping-pong operation with bit-distribu

318、tion-based calibration Shorter conversion time No reset switch or logic One extra bit of decision less quantization noise Proposed SAR ADC with Ping-Pong ComparatorsD7AverageD8sgnDcalSampling 1 234567RSTCal.Sampling 1 2345678Prior ArtProposed22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither

319、-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference39 of 62Outline Motivation Challenges and Solutions Circuit Implementation Measurement Results Conclusion22.4:A 4.8GS/s 7-ENo

320、B Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference40 of 62Vd,POverall ArchitectureDither-Injected Input BufferVinpSub-ADCCLKrefPRBS Gener

321、atorVinnVd,NDoutPhase Generator andVariable Delay LinesCLKinCLK14Vin,ADC4-to-1 MUXDraw,14Ping-Pong OS cal.TI OS,Gain,andTiming-Skew Cal.4-channel TI SAR ADC with dither-injected input buffer22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Di

322、stribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference41 of 62Prior Art:Dither-Injected Input BufferX.Pan,CICC,2023 Dither injection through a small capacitorVBN1VdDither InjectionVBN2VBP1VdVBP2VinVin,ADC22.4:A 4.8GS/s 7-ENoB Time-

323、Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference42 of 62Prior Art:Dither-Injected Input BufferVBN1VdDither InjectionBonding WireVBN2VBP1VdVBP2

324、X.Pan,CICC,2023 Dither injection through a small capacitorDither kickback to input causing ISI VinVin,ADC22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE Interna

325、tional Solid-State Circuits Conference43 of 62Simulation Comparison Sampled signal without dither injectionSNR=58.4dB0.40.81.21.622.4Frequency(GHz)-100-80-60-40-200Magnitude(dBFS)Without Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection OffSNR=58.4 dB0.40.81.21.622.4Frequency(GHz)-100-80-60

326、-40-200Magnitude(dBFS)Prior Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection=10%Full ScaleSNR=40.4 dB22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE I

327、nternational Solid-State Circuits Conference44 of 62Simulation Comparison Sampled signal after dither subtractionSNR degraded by 18dB due to ISI0.40.81.21.622.4Frequency(GHz)-100-80-60-40-200Magnitude(dBFS)Without Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection OffSNR=58.4 dB0.40.81.21.62

328、2.4Frequency(GHz)-100-80-60-40-200Magnitude(dBFS)Prior Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection=10%Full ScaleSNR=40.4 dB0.40.81.21.622.4Frequency(GHz)-100-80-60-40-200Magnitude(dBFS)Without Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection OffSNR=58.4 dB0.40.81.21.622.4Fre

329、quency(GHz)-100-80-60-40-200Magnitude(dBFS)Prior Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection=10%Full ScaleSNR=40.4 dB22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Ca

330、libration 2024 IEEE International Solid-State Circuits Conference45 of 62Proposed Dither-Injected Input Buffer Dither injection based on source follower summation24IdIdDither InjectionVin,ADCVBN1VBN2VBP1VBP2VBN1VBN2VBP1VBP2VdVin22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Backgro

331、und Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Conference46 of 62Proposed Dither-Injected Input Buffer24IdIdIsolationDither InjectionVin,ADCVBN1VBN2VBP1VBP2Bonding WireVBN1VBN2VBP1VBP2 Dither inje

332、ction based on source follower summationDither kickback isolated VdVin22.4:A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration 2024 IEEE International Solid-State Circuits Confere

333、nce47 of 62Simulation Comparison Sampled signal after dither subtractionSignal integrity maintained with dither injection0.40.81.21.622.4Frequency(GHz)-100-80-60-40-200Magnitude(dBFS)Prior Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injection=10%Full ScaleSNR=40.4 dB0.40.81.21.622.4Frequency(GHz)-100-80-60-40-200Magnitude(dBFS)Proposed Dither InjectionHD3fin=2.3 GHz,fs=4.8 GS/sDither Injectio