SESSION 25 High Concepts at High Frequencies.pdf

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1、ISSCC 2025SESSION 25High Concepts at High Frequencies25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference1 of 42A Physics-Inspir

2、ed Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution TimeEvangelos Dikopoulos,Ying-Tuan Hsu*,Luke Wormald*,Wei Tang,Zhengya Zhang,Michael P.FlynnUniversity of Michigan,EECS Dept.Email:vangelisumich.edu25.1:A Ph

3、ysics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference2 of 42Boolean Satisfiability(SAT)Find assignments to N Boolean variables XN=x1,x2,xN

4、 that satisfy a given Boolean formula:F(X)=1Clause3-SAT Single Clause ExampleF=(X89or(not X92)or X36)and Solution:X89,X92,X36=0,0,025.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time

5、2025 IEEE International Solid-State Circuits Conference3 of 42Boolean Satisfiability(SAT)3-SAT ExampleF=(X89 X92 X36)(X10 X31 X40)(X21 X65 X89)or ,not ,and Clause 1Clause 0Clause MFind assignments to N Boolean variables XN=x1,x2,xN that satisfy a given Boolean formula:F(X)=125.1:A Physics-Inspired O

6、scillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference4 of 42Applications of SATSolver01011101010SAT SolutionAICryptoEDAHealth-careComp.BioDefenseLogistics

7、25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference5 of 42Applications of SATSolver01011101010SAT SolutionAICryptoEDAHealth-car

8、eComp.BioDefenseLogistics25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference6 of 42Computational ComplexityNumber of VariablesS

9、olution Time,EnergyFast efficientsolvers are needed!25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference7 of 42ContributionsFirs

10、t-of-its-kind physics-inspired CT SAT solverDynamical system of coupled spinsMixed-signal all-to-all twin crossbar architectureRelaxation oscillator(RXO)-based spin injection25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems wi

11、th 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference8 of 42Outline Motivation and Prior Art 3-SAT SolverAccelerator ArchitectureFeedback SystemDaCTI Spin Measurement Results Comparison and Conclusion25.1:A Physics-Inspired Oscillator-Based Mixed-Signal O

12、ptimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference9 of 42Motivation:Quantum Systems Physical computation with dynamical systems Massive parallelism Continuous-time operationIBM Quan

13、tum ComputerD-Wave Quantum Annealer25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference10 of 42Motivation:Quantum Systems Large

14、power budgets(KWs)Immature technology Limited Qubit connectivityIBM Quantum ComputerD-Wave Quantum Annealer25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International

15、Solid-State Circuits Conference11 of 42=1Physics Inspired SAT Solver25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference12 of 42

16、=1Physics Inspired SAT Solver25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference13 of 42=1Physics Inspired SAT Solver25.1:A Phy

17、sics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference14 of 42Prior Art25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization En

18、gine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference15 of 42Proposed Physics-Inspired Solver25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Cla

19、use 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference16 of 42Proposed Physics-Inspired Solver25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvabil

20、ity and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference17 of 42Ground State Convergence Dynamical system naturally minimizes energy:=25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvab

21、ility and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference18 of 42Ground State Convergence Dynamical system naturally minimizes energy:=Time25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%

22、Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference19 of 42Outline 3-SAT SolverAccelerator ArchitectureFeedback SystemDaCTI Spin25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100

23、%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference20 of 42Compute Methodology25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE In

24、ternational Solid-State Circuits Conference21 of 42System Architecture25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference22 of

25、42Mixed-Signal CrossbarsDigital X-BarSpin states clausesAnalog X-BarSums clause feedbackThird-order spin interactions25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE Inte

26、rnational Solid-State Circuits Conference23 of 42Connection Cells25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference24 of 42Mix

27、ed-Signal Clause25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference25 of 42Feedback System25.1:A Physics-Inspired Oscillator-Ba

28、sed Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference26 of 42Error Detector25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Va

29、riable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference27 of 42Feedback Delay Optimization Low-power TIA Current source node pre-charge25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 5

30、0-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference28 of 42ConventionalContinuous Oscillation Dikopoulos 24RXO 1RXO 2ProposedDaCTIRXO 1RXO 2Phase ChangePhase ChangeOscillator only rotates by relative phase changeDy

31、namic CT Injection(DaCTI)25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference29 of 42Feedback Interface2-bit ADC quantizes feedb

32、ack current25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference30 of 42DaCTI SpinTwo in-oscillator convertersDynamic spin inject

33、ion25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference31 of 42DaCTI Example Waveform VDAC:relaxation threshold IDAC:integration

34、 slope25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference32 of 42Outline Measurement Results25.1:A Physics-Inspired Oscillator-

35、Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference33 of 42Chip Summary25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Va

36、riable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference34 of 42Measurement Setup SATLIB benchmark:https:/www.cs.ubc.ca/hoos/SATLIB/benchm.html 1000 50-variable 218-clause instances evaluated 100 times each25.1:A Physics-In

37、spired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference35 of 42Random Instances Solution time distribution25.1:A Physics-Inspired Oscillator-Based M

38、ixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference36 of 42Cumulative Results 1000 benchmark problems25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization E

39、ngine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference37 of 42EDP Comparison 91x improved EDP over 625.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable

40、218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference38 of 42Outline Comparison and Conclusion25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%

41、Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference39 of 42Comparison Table25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE Intern

42、ational Solid-State Circuits Conference40 of 42Conclusions22x faster and 4x lower energyLeverages physics-inspired heuristicsNo pre-processing or decompositionDaCTI reduces solution time and energyPaves the way for large-scale analog NP-complete solvers25.1:A Physics-Inspired Oscillator-Based Mixed-

43、Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference41 of 42AcknowledgementDARPA QuICC25.1:A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-

44、Variable 218-Clause 3-SAT Problems with 100%Solvability and 31.7s Solution Time 2025 IEEE International Solid-State Circuits Conference42 of 42Thank you!25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2

45、025 IEEE International Solid-State Circuits Conference1 of 401Washington University in St.Louis,St.Louis,MO2Oregon State University,Corvallis,OR3University of California,San Diego,CA 4Northeastern University,Oakland,CAA 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Ef

46、ficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOSAswin Undavalli1,Kareem Rashed2,Gert Cauwenberghs3,Shantanu Chakrabartty1,Arun Natarajan2,Aravind Nagulu1,425.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22n

47、m SOI CMOS 2025 IEEE International Solid-State Circuits Conference2 of 40 Introduction Proposed Margin-Propagation(MP)-based Analog Correlation Analog Cross Correlator Implementation Measurement Results ConclusionsOutline25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Co

48、mpute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference3 of 40MotivationTXTX-BBRXRX-BBCorr.TargetR()RadarCorr.Base-bandRXIN1IN2IN3xCode 1Out 1Communicationy(t)x(t)CorrelatorRCorrelators have wide range of applications in radar/commun

49、ication signal processing=.25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference4 of 40Application of Correlators in Code-Domain RadarLag 0Lag 1Lag 2RxT

50、xCorr.DDCorr.DCorr.PRBS gen.IFRFTxObjectRF90oCoupler0o/90oLOI/QCrossCorrelatorEstimated Range BinRxLOR=RangeT=2R/cThe reflected signals are received,down-converted,and cross-correlated across delayed copies of the template sequence.Correlators have wide range of applications in radar/communication s

51、ignal processingCode-Domain Radar SchematicMulti-lag Cross Correlation25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference5 of 40Application of Correla

52、tors in Code-Domain RadarRange=.Resolution=Tsis the template sampling rateLagsCorrelationSignal MthLagClutter Unmatched LagsThe output of multi-lag correlator exhibits a thumb-tack response with a peak associated with object round trip delay Multi-lag correlators are necessaryRange resolution,R Ts H

53、igh speed correlators are necessary Signal-to-Clutter Ratio,SCR Correlator Length,N Long N is necessary25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Confer

54、ence6 of 40Cross-Correlation:Analog vs DigitalADC overhead High PDCLarge compute lengthMulti-lag operationxxDigital Multiply-and-Accumulate(MAC)CorrelatorAnalog Correlatory(t)x(t)Analog MultiplierIntegratory(t)x(t)ADCADCRShort correlation lengthsLarge area and PDC for multi-lag operation No ADCxMang

55、al JSSC20,Wu TMTT23=.x W.PAN TCAS2425.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference7 of 40Multiplier-free CorrelationApproximate Compute-In-Memory(

56、CIM)MAC|OR/AND+ADDABS+ADDWang ISSCC22He ISSCC23Low Speeds Requires DACs and ADCs at input interfaceHigh compute efficiency xxProposed Margin-Propagation(MP)-based Analog Cross-Correlator Supports Multi-lag correlation No ADCs or DACs at I/OSupports long correlation length High compute efficiency MPy

57、(t)x(t)G-1RMPG(RMP)One-to-one mapping:G(RMP)R Supports Multi-lag correlation25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference8 of 40 Introduction Pr

58、oposed Margin-Propagation(MP)-based Analog Correlation Analog Cross Correlator Implementation Measurement Results ConclusionsOutline25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE Internationa

59、l Solid-State Circuits Conference9 of 40ReLU MP FunctionAnalog-friendly ReLU-based MP function is well-suited for low-power implementationsVinVoutVout=max(0,Vin-Vth)Realization of ReLU function-10-50510z0510ReLU(z)=+=(,)ReLU function with 0 threshold 25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-

60、Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference10 of 40ReLU MP-based Analog Correlationz+z-G-1RMPG(RMP)X+Y,-X-YMP FunctionMP FunctionX-Y,-X+YCorrelation estimated using MP functions operating on

61、additive and subtractive operands(XY)ReLU(z)-10-50510z0510Z.Xiao TCAS24MP Based CorrelatorMAC AnalogyX+Y X-Y(.)2(.)2-X.Yz+z25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-S

62、tate Circuits Conference11 of 40ReLU MP-based Analog CorrelationMultiple MP units are connected in parallel to estimate correlation between multiple samples of input signalRMPG(RMP)25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Comput

63、e Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference12 of 40ReLU MP-based Analog CorrelationReverse water-filling constraint solves for Voutfor a given set of inputs=,=Vouts.t.Vout,1,for Isink,1Vout,2,for Isink,2|x1+y1|xN+yN|xi+yi|W/L|xi+yi|W/LMP UnitsMP Units25.2:A 4GS

64、/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference13 of 40ReLU MP-based Analog CorrelationDifferential output voltage(Vout,d)estimates the correlation between

65、the input sequences=,=+|xi+yi|W/L|xi-yi|W/L+25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference14 of 40Prior Works based on Margin PropagationLow Spee

66、dHigh EfficiencyCompact AreaNot Scalable to Large NHigh SpeedModerate EfficiencyLarge Area due to Operand Gen.Scalable to Large N-xi-yiCcxi+yiV+outxiyixi+yi-xi-yixi-yi-xi+yi-xi-yiOperand GeneratorI+xiI+yiI-xiI-yiI+outCurrent Domain MPCharge Domain MP with Operand Generatorxi-xiyi-yixi+yi-xi-yixi-yi-

67、xi+yiM.Gu TCAS12K.Rashed ISSCC2425.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference15 of 40Proposed Compute Cell Using Backgate ModulationOperand Gen.

68、Using BackGateBackgate BiasP-Well/N-Well N+N+.SOI/Triple-well NMOS BackGate(Buried N-well in SOI&triple-well)enables threshold voltage tuning Operand generation is eliminated by applying input“x”to the transistor gate and the input“y”to the backgate in the SOI transistor No caps 40 x smaller area No

69、 operand power 1000 TOPS/W0.E+004.E-058.E-050.20.40.6IDS(A)Vg(V)Vb=0.8Vb=0.6Vb=0.4Vb=0.2Vb=00.360.380.40.420.440.4600.20.40.60.8Vth(V)Vbackgate(V)25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEE

70、E International Solid-State Circuits Conference16 of 40XiYi-Yi+-YiYi-Xi The four-quadrant operands with front and backgate drivewill implement margin propagation condition with:High Operating Speed High Energy Efficiency Compact four transistor layout 2.3 m 2.3 m 100 lower transistor count compared

71、to digitalmultipliers+()+()+=+/()+()+=/Proposed Compute Cell Using Backgate ModulationFour Quadrant Operands Hyper Parameters+25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Soli

72、d-State Circuits Conference17 of 40Proposed Split Source Follower Based Compute Core+()+()+=+/()+()=/MP Unit CellMP Unit CellMP Unit Cell-x(t)x(t)-y(t)y(t)RsinkXiYi-Yi-YiYi-Xi+Samples are applied to N unit cells with common source nodes making the core resemble a Split Source Follower(SSF)SSF can be

73、 scaled to large correlation length with high speeds by reducing RsinkSSF architecture is self-biased and differential resulting in stable PVT operation25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 20

74、25 IEEE International Solid-State Circuits Conference18 of 40ReLU MP-based Analog CorrelationEstimated correlation and error vs true intrinsic correlation(R)for two pseudo random inputsError in MP correlation is similar to MAC correlator Error with true correlation(R)as sequence length increases-1-0

75、.500.51-1-0.500.51Estimated CorrelationTrue Intrinsic Correlation(R)MAC-CorrelatorMP-Correlator-0.3-0.2-0.100.10.20.3-1-0.500.51Correlation ErrorTrue Intrinsic Correlation(R)MAC-CorrelatorMP-CorrelatorNc=256 25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficie

76、ncy and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference19 of 40 Introduction Proposed Margin-Propagation(MP)-based Analog Correlation Analog Cross Correlator Implementation Measurement Results ConclusionsOutline25.2:A 4GS/s Fully Analog 256x256 M

77、P-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference20 of 40256 x 256 Cross Correlator SchematicRF inputs(X,Y)are sampled on 256 differential capacitorsX is routed on horizontal pathY is

78、 routed diagonal pathMultiple lags can be realized along vertical pathThe 256 lags are readout using 4 channel with 64:1 analog MUXing.25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE Internati

79、onal Solid-State Circuits Conference21 of 40256 x 256 Cross Correlator SchematicRF inputs(X,Y)are sampled on 256 differential capacitors25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE Internat

80、ional Solid-State Circuits Conference22 of 40256 x 256 Cross Correlator SchematicRF inputs(X,Y)are sampled on 256 differential capacitorsX is routed on horizontal pathY is routed diagonal pathMultiple lags can be realized along vertical pathThe 256 lags are readout using 4 channel with 64:1 analog M

81、UXing.25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference23 of 40256 x 256 Cross Correlator SchematicRF inputs(X,Y)are sampled on 256 differential cap

82、acitorsX is routed on horizontal pathY is routed diagonal pathMultiple lags can be realized along vertical pathThe 256 lags are readout using 4 channel with 64:1 analog MUXing.25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Den

83、sity in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference24 of 40Timing Diagram of the Proposed X-Corr ICN*TsSampling Chirp 1Lag 0Lag 4Lag 8Lag 252Lag 1Lag 5Lag 9Lag 253Lag 2Lag 6Lag 10Lag 254Lag 3Lag 7Lag 11Lag 255Compute and Readout=64*TRChannel 1Channel 2Channel 3Channel 4TRNT

84、sSampling Chirp 2TimeChirp 1Readout Time of 64*TR across Four-Channel OutputsSample/Compute ControlChirp 2Sampling Time 256*TstVSample Chirp 1 Cycle through all lags using analog MUX Sample Chirp 2 .All output lags of four channels are combined for correlation across lags25.2:A 4GS/s Fully Analog 25

85、6x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference25 of 40 Introduction Proposed Margin-Propagation(MP)-based Analog Correlation Analog Cross Correlator Implementation Measureme

86、nt ResultsCross-Correlator CharacterizationCross-Correlator in a Radar System ConclusionsOutline25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference26

87、of 40Chip MicrographCross-Correlator IC implemented in 22nm SOI CMOS process.The X-corr IC includes sampling,correlation compute circuits and muxing of outputsChip occupies an area of 0.69mm0.67mm0.59 mmMP Cross CorrelatorCompute Core(256 x 256)0.59 mmClock GenerationClock GenerationOutput MUX+Resis

88、tor Bank0.69 mm0.67 mmSPI25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference27 of 40-1-0.500.51-180-135-90-450Measured CorrelationPhase()TheroticalMea

89、suredMeasurement Results:Sinusoid InputsMeasured CorrelationMeasured Correlation Error=0 =180 -0.01-0.00500.0050.01-180-135-90-450Measured Correlation ErrorPhase()_ _ =Total measured correlation error is 2=2(1)+2For periodic inputs the=0 =With sinusoidal inputs,measured correlation demonstrates 8-bi

90、t performance 25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference28 of 40-0.25-0.15-0.050.050.150.25-1-0.500.51Measured Correlation ErrorTrue Intrinsi

91、c Correlation(R)=.=.-1-0.500.51-1-0.500.51Measured CorrelationTrue Intrinsic Correlation(R)MeasuredTheoreticalMeasurement Results:Random InputsMeasured CorrelationMeasured Correlation ErrorR=1R=-1With random inputs,measured correlation follows theory/simulationsSignal processing gain,SPG=22.6 dB25.2

92、:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference29 of 40Roundtrip Delay EstimationOutput of four channels are interleaved with no post processingThe me

93、asured multi-lag correlation exhibits standard thumb-tack responseSamplingLag 0Lag 4Lag 8Lag 252Delay between X and Y matching with Lag 64SamplingOutputs at unmatched lags-0.040.010.060.11050100150200250Measured Cross-Correlation(V)X-Corr Lag(in Ts)Delay:41*TsDelay:82*TsDelay:163*TsDelay:200*TsMeasu

94、red cross-correlations across relative delays between the two input signalsMeasured Output For Channel 125.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Confe

95、rence30 of 40Signal Processing at Low SNRsOutput SCR improves across averaging chirpsImproves detection in low SNR inputsTrueFalseTrue99.20.78False0.7899.6Measured Correlation,RMPInput SNR:0dB,Averages:1 ChirpPredictedActual510152025110100SCR(dB)No.of Chirp Averages,MSCR MeasuredSCR TheoryInput SNR:

96、0dBInput SNR:-16dB Noise LimitedCorrelation length limitedSCR across chirp averages25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference31 of 40Chip-to-

97、Chip&Supply Voltage VariationProposed correlation operation is robust to chip to chip variations Proposed correlation operation is robust to supply variations X-Corr HDR across supply voltageAdopted Supply Voltage-0.0350.0150.0650.115050100150200250Measured Cross Correlations(V)(Range Bin)/TsX-Corr

98、output across chips47.55052.55557.50.40.50.60.70.8Estimated HDR(dB)Compute Core VDD(V)Chip 1Chip2Adopted Supply voltage25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State

99、 Circuits Conference32 of 40 Introduction Proposed Margin-Propagation(MP)-based Analog Correlation Analog Cross Correlator Implementation Measurement ResultsCross-Correlator CharacterizationCross-Correlator in a Radar System ConclusionsOutline25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlat

100、or with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference33 of 40X-Band Radar PrototypeMP-based cross correlator is integrated into a 10GHz code-domain radar systemThe analog cross-correlator acts as the core proc

101、essing unit of the radar system X-Corr Radar SystemObjectPRBS gen.1GHzIFRFTxObjectRF90o Coupler0o/90o LOI/QX-Corr PCBEstimated Range BinRx10 GHz LOR=RangeT=2R/cPRBSTemplate25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density

102、 in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference34 of 40I and Q Phase MeasurementX-corrs in the I and Q phase align closely with the digital MAC based correlatorThe I and Q-phase correlations can be used for velocity estimationMeasured I-Phase Correlations Using X-Corr IC an

103、d 12b-digitizer MACMeasured Q-Phase Correlations Using X-Corr IC and 12b-digitizer MAC05010015020025000.250.50.75105101520253035(Range Bin)/TsI-Phase CorrelationDistance(m)X-Corr_I12-b_Digitizer_MAC_I05010015020025000.250.50.75105101520253035(Range Bin)/TsQ-Phase CorrelationDistance(m)X-Corr_Q12-b_D

104、igitizer_MAC_Q25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference35 of 4000.250.50.75102468Measured Cross Correlation,RMPRange(m)Object at 3.35mObject

105、 at 3.39m357911357911Measured Range(m)Range(m)12-b Digitizer MACX-Corr measured00.250.50.751010203040Measured Cross Correlation,RMPRange(m)Object at 3.15mObject at 3.3mRange and Resolution MeasurementThe detected range closely matches with a digitizer+MAC based radar systemThe radar resolution match

106、es with the theoretical resolutionR=0.0375mR=0.15mRange MeasurementResolution Measurement 1GS/sResolution Measurement 4GS/s25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-S

107、tate Circuits Conference36 of 40Performance Summary and ComparisonThe proposed correlator achieves superior efficiency and compute density compared to prior correlatorsPerformance Compared to State-of-the-Art Analog Correlators/Cross-Correlators25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correl

108、ator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference37 of 40Performance Summary and ComparisonAchieves superior efficiency and comparable compute density with respect to prior digital and analog matrix mult

109、ipliersPerformance Compared to State-of-the-Art Analog and Digital Matrix Multipliers25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference38 of 40 Intro

110、duction Proposed Margin-Propagation(MP)-based Analog Correlation Analog Cross Correlator Implementation Measurement Results ConclusionsOutline25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Compute Density in 22nm SOI CMOS 2025 IEEE In

111、ternational Solid-State Circuits Conference39 of 40Conclusions We presented an area and power efficient 4-transitor based compute cell using backgate modulation Proposed SSF architecture is PVT robust and can be scaled to large correlation length and high speeds Proposed cross-correlator achieved 25

112、6 correlation length,multi-lag correlations at 4GS/s,1000TOPS/W and 1.3TOPS/mm2 Cross-correlator IC has been integrated with COTS code-domain radar for system feasibility demonstration25.2:A 4GS/s Fully Analog 256x256 MP-Based Cross-Correlator with 1000 TOPS/W Compute Efficiency and 1.3 TOPS/mm2 Com

113、pute Density in 22nm SOI CMOS 2025 IEEE International Solid-State Circuits Conference40 of 40AcknowledgmentsThis work was supported by the DARPA MAX program,award no.FA8650-23-2-7309,NSF CNS 2128535 and NSF CNS FuSE2-2425444Authors thank GlobalFoundries University MPW program for fabrication support

114、Authors thank Tabor Electronics for equipment supportAuthors thank Dr.James Wilson(DARPA),Dr.Bryan Jacobs(DARPA),and Dr.Tony Quach(AFRL)for their valuable feedbackAuthors thank Gopabandhu Hota from the University of California,San Diego for the process and layout support.Authors thank Nagulu Lab mem

115、bers for valuable discussion and support25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference1 of 76AI-enabled Design Space

116、Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz Jonathan Zhou*1,Emir Ali Karahan*1,Sherif Ghozzy1,Zheng Liu2,Hossein Jalili1,Kaushik Sengupta11Princeton University,Princeton,NJ2Texas Instruments,Dallas,T

117、X25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference2 of 76Current Method of Design of RFICsZ.Liu,E.A.Karahan,K.Sengupta,A

118、 3691 GHz Broadband Beamforming Transmitter Architecture With Phase Error Between 1.2o2.8ofor Joint Communication and Sensing.IEEE Transactions on Microwave Theory and Techniques.2023 Oct 25.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inv

119、erse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference3 of 76Current Method of Design of RFICsPAL1W1L2W2W3L4W4L5W5L6W6PALibrary of EM/Circuit Templates25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Rein

120、forcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference4 of 76Current Method of Design of RFICsIterative Design Process Months to years to design a RFIC.10s to 100s of million of dollars.Pre-fixed topology lim

121、its the design space.PAL1W1L2W2W3L4W4L5W5L6W6PALibrary of EM/Circuit TemplatesPackagingAntennaSchematicEM PassivesEM+SchematicLayout25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-12

122、0 GHz 2025 IEEE International Solid-State Circuits Conference5 of 76Current Method of Design of RFICsIterative Design Process Months to years to design a RFIC.10s to 100s of million of dollars.Pre-fixed topology limits the design space.CharacterizeDesignOptimizeRepeatInnovateIterative Design Process

123、PackagingAntennaSchematicEM PassivesEM+SchematicLayout25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference6 of 76Nobel Priz

124、e in 2024 on AI for Science Protein structures were predicted from amino acid sequences.AI can be used to learn complex structures and generate new designs in that space.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstr

125、ating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference7 of 76AI-enabled RFIC Design:Fast and New Design Space DiscoveryAI engineSpecificationsPDK(s)+PackagingDesign+Layout Rapid Designs(months/years to days/weeks).Invents new topologies beyond human intui

126、tion/knowledge.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference8 of 76OutlineDesign Space for an AI-enabled RFICFramewo

127、rk of the AI-enabled Design ProcessReinforcement Learning+Inverse DesignDesign Examples and Measurement ResultsConclusion25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025

128、IEEE International Solid-State Circuits Conference9 of 76OutlineDesign Space for an AI-enabled RFICFramework of the AI-enabled Design ProcessReinforcement Learning+Inverse DesignDesign Examples and Measurement ResultsConclusion25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs

129、 with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference10 of 76RFIC Design Space(Topology+Circuits+Layout)RFIC performance25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs wit

130、h Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference11 of 76RFIC Design Space(Topology+Circuits+Layout)RFIC performanceCircuit TopologyCircuit Parameters25.3:AI-enabled Design Space Discovery and End-

131、to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference12 of 76RFIC Design Space(Topology+Circuits+Layout)RFIC performanceCircuit TopologyActive CellsCircuit Parameters25.3:

132、AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference13 of 76RFIC Design Space(Topology+Circuits+Layout)RFIC performanceCircuit T

133、opologyActive CellsCircuit Parameters25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference14 of 76RFIC Design Space(Topology

134、+Circuits+Layout)RFIC performanceCircuit TopologyActive CellsCircuit ParametersActive Cells25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State

135、 Circuits Conference15 of 76RFIC Design Space(Topology+Circuits+Layout)RFIC performanceCircuit TopologyActive CellsCircuit ParametersW,LVbias2Vbias1VbiasW,LActive CellsLWR#Gain Stage;#Combiner.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and I

136、nverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference16 of 76Circuit Topology Sub-SpaceActive CellsCircuit Topology25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Me

137、thods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference17 of 76Circuit Topology Sub-SpaceCircuit TopologyActive CellsCombiningStages,Combining etc#Stages,#combiningAsymmetrical(eg Doherty)25.3:AI-enabled Design Space Discovery and End-to-end

138、Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference18 of 76Circuit Topology Sub-SpaceCircuit TopologyActive CellsCombiningStages,Combining etc#Stages,#combiningAsymmetrical(eg

139、Doherty)Electromagnetic PassivesWilkinson,transformer,t-line matching networks,25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Co

140、nference19 of 76Circuit Topology Sub-SpaceCircuit TopologyActive CellsCombiningStages,Combining etc#Stages,#combiningAsymmetrical(eg Doherty)Electromagnetic PassivesWilkinson,transformer,t-line matching networks,PA active devices(output,drivers)CE,CB,CE stack,CB stack,cascode25.3:AI-enabled Design S

141、pace Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference20 of 76Circuit Parameters Sub-SpaceCircuit ParametersActive CellsCombiningStages,Combining etc

142、#Stages,#combiningAsymmetrical(eg Doherty)Electromagnetic PassivesWilkinson,transformer,t-line matching networks,PA active devices(output,drivers)CE,CB,CE stack,CB stack,cascode25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods D

143、emonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference21 of 76Universalization of Electromagnetic Passivess31s21s11sN1S-parametersInverse Inverse designdesignQuadrature hybrid0.71j V-0.71V1 VInOut0.71ej V0.71ej V1 V Given S-parameter of a generaliz

144、ed multi-port network,inverse design tries to find the optimal structure.Creates a generalized EM synthesis paradigm with arbitrary S-parameters,overcoming limitations of pre-chosen templates.T-linematchingHybridCombiner/SplitterSee:Karahan,JSSC 2023,Karahan,Nat.Comm.202425.3:AI-enabled Design Space

145、 Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference22 of 76Universalization of RF circuitsPAPAPAPASynthesized RF/mmWave ICSpecificationss11s2230 GHz10

146、0 GHzs21PAE PSAT30 GHz100 GHzAM-PM PSAT All RF/mmWave ICs can be represented as a combination of active/inverse designed passive devices.The AI engine needs to figure out the optimal active/passive architecture and parameters.The constraints such as stability,breakdown,symmetry,DC biasing,can also b

147、e taken into considerations.AI25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference23 of 76OutlineDesign Space for an AI-ena

148、bled RFICFramework of the AI-enabled Design ProcessReinforcement Learning+Inverse DesignDesign Examples and Measurement ResultsConclusion25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between

149、30-120 GHz 2025 IEEE International Solid-State Circuits Conference24 of 76Traditional PA Design from Specifications to LayoutPinfrequencyPoutPAES22frequencyACLRPoutPAES2125.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstr

150、ating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference25 of 76Proposed AI-enabled PA Design from Specifications to LayoutPinfrequencyPoutPAES22frequencyACLRPoutPAES21PA_gen.py25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with R

151、einforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference26 of 76Proposed AI-enabled PA Design from Specifications to LayoutStateRewardsActionsDeep Reinforcement Learning(Optimal PA Arch.,PA/driver circuits)P

152、infrequencyPoutPAES22frequencyACLRPoutPAES21Deep reinforcement learning and AI-enabled Inverse synthesis for end-to-end RFIC synthesis(in the non-intuitive design space)PA_gen.pyW/L1 R2C2C1R1W/L2 ZoutZinPA Architecture(stages,combining etc)Constituent circuits(Driver,PA)25.3:AI-enabled Design Space

153、Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference27 of 76Proposed AI-enabled PA Design from Specifications to LayoutAI-enabled Inverse Synthesis of M

154、ulti-port EMInput SplitterOutput CombinersInter-stage MatchingStateRewardsActionsDeep Reinforcement Learning(Optimal PA Arch.,PA/driver circuits)PinfrequencyPoutPAES22frequencyACLRPoutPAES21Deep reinforcement learning and AI-enabled Inverse synthesis for end-to-end RFIC synthesis(in the non-intuitiv

155、e design space)PA_gen.pyW/L1 R2C2C1R1W/L2 ZoutZinPA Architecture(stages,combining etc)Constituent circuits(Driver,PA)25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE

156、 International Solid-State Circuits Conference28 of 76Proposed AI-enabled PA Design from Specifications to LayoutAI-enabled Inverse Synthesis of Multi-port EMInput SplitterOutput CombinersInter-stage MatchingStateRewardsActionsDeep Reinforcement Learning(Optimal PA Arch.,PA/driver circuits)End-to-en

157、d AI-enabled RFIC Synthesis PinfrequencyPoutPAES22frequencyACLRPoutPAES21Deep reinforcement learning and AI-enabled Inverse synthesis for end-to-end RFIC synthesis(in the non-intuitive design space)PA_gen.pyW/L1 R2C2C1R1W/L2 ZoutZinPA Architecture(stages,combining etc)Constituent circuits(Driver,PA)

158、25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference29 of 76Specifications to AI-enabled Layout:Summary of the Design Space

159、 we CoverPA Cells/Driver Cells/ParametersClass of OperationPA active devices&Classes of Operation(CE,CB,CE stack,CB stack)25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025

160、 IEEE International Solid-State Circuits Conference30 of 76Specifications to AI-enabled Layout:Summary of the Design Space we CoverPA Cells/Driver Cells/ParametersClass of OperationArchitecture(Number of Stages,Combining/Not,how many combining paths)Matching Networks and Combiners/SplittersPA active

161、 devices an Classes of Operation(CE,CB,CE stack,CB stack)Stages,Combining etc#Stages,#combiningAsymmetrical(eg Doherty)Combining25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GH

162、z 2025 IEEE International Solid-State Circuits Conference31 of 76OutlineDesign Space for an AI-enabled RFICFramework of the AI-enabled Design ProcessReinforcement Learning+Inverse DesignDesign Examples and Measurement ResultsConclusion25.3:AI-enabled Design Space Discovery and End-to-end Synthesis f

163、or RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference32 of 76Reinforcement Learning for Topology,Circuit Optimization and Impedance optimizationAgent MDP models sequential decision problems

164、 much like human designer Environment gives“feedback”to agent,which decides optimal next actions25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-

165、State Circuits Conference33 of 76Reinforcement Learning for Topology,Circuit Optimization and Impedance optimizationAgentEnvironment MDP models sequential decision problems much like human designer Environment gives“feedback”to agent,which decides optimal next actionsState,Rewardst,rtActionatTraject

166、ory:=(s0,a0,sT+1)25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference34 of 76Reinforcement Learning for Topology,Circuit Op

167、timization and Impedance optimizationAgentEnvironment MDP models sequential decision problems much like human designer Environment gives“feedback”to agent,which decides optimal next actionsState,Rewardst,rtActionatReward signal(rt):Trajectory:=(s0,a0,sT+1)TopologyParametersPAEGainPsatS-Param25.3:AI-

168、enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference35 of 76Zout,Dr1Zin,Dr1Zout,Dr2Zin,Dr2Zout,PAZin,PAZout,Dr1Zin,Dr1Zout,Dr2Zin,D

169、r2Zout,PAZin,PA(N+1)port(N+1)port50 50 M stagesN combinerTo capture power transfer between stages(not synthesized)Optimal impedances for inverse synthesisDesigning the Layout-Aware Design Space:Topology,Parameter and S-matrix Optimization25.3:AI-enabled Design Space Discovery and End-to-end Synthesi

170、s for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference36 of 76STATE=Cell1,Cell2,.CellM,#Gain,#Combiner;Captures PA architecture,Driver/PA topologies,Optimal impedances,and Device paramete

171、r values REWARD=PA perf-Target perf Designing the Layout-Aware Design Space:Topology,Parameter and S-matrix Optimization25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 I

172、EEE International Solid-State Circuits Conference37 of 76STATE=Cell1,Cell2,.CellM,#Gain,#Combiner;Captures PA architecture,Driver/PA topologies,Optimal impedances,and Device parameter values REWARD=PA perf-Target perf SS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,

173、Le2,Zin,Zout,Biasing Perf=S11,S21,.AM-AM,AM-PM,PAE,.CellM=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topologyDesigning the Layout-Aware Design Space:Topology,Parameter and S-matrix Optimization25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learnin

174、g and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference38 of 76SS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout Perf=S11,S21,.AM-AM,AM-PM,PAE,.Cell1=Trans,SS,Perf,CE/CB/StackCE/CB/

175、Stack=decides cell topologySS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout Perf=S11,S21,.AM-AM,AM-PM,PAE,.Celli=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topologySTATE=Cell1,Cell2,.CellM,#Gain,#Combiner;Captures PA architecture,Driver/PA topolog

176、ies,Optimal impedances,and Device parameter values REWARD=PA perf-Target perf SS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout,Biasing Perf=S11,S21,.AM-AM,AM-PM,PAE,.CellM=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topologyDesigning the Layout-Awa

177、re Design Space:Topology,Parameter and S-matrix Optimization25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference39 of 76SS(

178、Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout Perf=S11,S21,.AM-AM,AM-PM,PAE,.Cell1=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topologySS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout Perf=S11,S21,.AM-A

179、M,AM-PM,PAE,.Celli=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topologySTATE=Cell1,Cell2,.CellM,#Gain,#Combiner;Captures PA architecture,Driver/PA topologies,Optimal impedances,and Device parameter values REWARD=PA perf-Target perf SS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStac

180、k/no stackTrans=Le1,Le2,Zin,Zout,Biasing Perf=S11,S21,.AM-AM,AM-PM,PAE,.CellM=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topology#Gain=M=Number of gain stages#Combiner=N=Number of combiner pathsPA architecture statesDesigning the Layout-Aware Design Space:Topology,Parameter and S-matrix Optim

181、ization25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference40 of 76SS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/

182、CBStack/no stackTrans=Le1,Le2,Zin,Zout Perf=S11,S21,.AM-AM,AM-PM,PAE,.Cell1=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topologySS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout Perf=S11,S21,.AM-AM,AM-PM,PAE,.Celli=Trans,SS,Perf,CE/CB/StackCE/CB/Sta

183、ck=decides cell topologySTATE=Cell1,Cell2,.CellM,#Gain,#Combiner;Captures PA architecture,Driver/PA topologies,Optimal impedances,and Device parameter values REWARD=PA perf-Target perf SS(Small signal)=gm,Vth,ic,Le1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackTrans=Le1,Le2,Zin,Zout,Biasing Perf=S11,S21

184、,.AM-AM,AM-PM,PAE,.CellM=Trans,SS,Perf,CE/CB/StackCE/CB/Stack=decides cell topology#Gain=M=Number of gain stages#Combiner=N=Number of combiner pathsPA architecture statesRewardsPinfPoutPAES22S11fACLRPsatPAEDesigning the Layout-Aware Design Space:Topology,Parameter and S-matrix Optimization25.3:AI-en

185、abled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference41 of 76Deep Reinforcement Learning for Architecture and Circuit Topology Synthes

186、isLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuit

187、s Conference42 of 76Deep Reinforcement Learning for Architecture and Circuit Topology SynthesisLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState Action=Le1,Le2,Zin,Zout,RL Policy DeepNeural Network Le1-2 um+2 umprobability Le1 Le2 ZinTopologyCB stackCE stackTop25.3:AI

188、-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference43 of 76Deep Reinforcement Learning for Architecture and Circuit Topology Synt

189、hesisLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState Action=Le1,Le2,Zin,Zout,RL Policy DeepNeural Network Le1-2 um+2 umprobability Le1 Le2 ZinPA Architecture:Optimal combining,Optimal#Gain StagesOptimal PA/Driver topologies and parameters#Combiner4321Episodes324#Gai

190、n StagesEpisodesEg:2-stage with 2-way combiner(for target specs)RewardsW/L1 R2C2C1R1W/L2 ZoutZinOpt:CB DriverL1Driver L2Zin,Driver,optZout,Driver,optLe1Le2ZoutZinZoutZinPA cellEpsiodesOpt:CE StackLe2Driver cellsLe1Opt:CE StackEpsiodesTopologyCB stackCE stackTop25.3:AI-enabled Design Space Discovery

191、and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference44 of 76Deep Reinforcement Learning for Architecture and Circuit Topology SynthesisLe1 Lb R2C2C1R1Le2 ZoutZinC

192、E/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState Action=Le1,Le2,Zin,Zout,RL Policy DeepNeural Network Le1-2 um+2 umprobability Le1 Le2 ZinPA Architecture:Optimal combining,Optimal#Gain StagesOptimal PA/Driver topologies and parameters#Combiner4321Episodes324#Gain StagesEpisodesEg:2-stage with

193、2-way combiner(for target specs)RewardsW/L1 R2C2C1R1W/L2 ZoutZinOpt:CB DriverL1Driver L2Zin,Driver,optZout,Driver,optLe1Le2ZoutZinZoutZinPA cellEpsiodesOpt:CE StackLe2Driver cellsLe1Opt:CE StackEpsiodesAI-enabled Inverse Design for all EMs s3131s s2121s s1111s sN1N1 Real&Real&ImagImag Parts of Parts

194、 of N N-Port ParametersPort ParametersInverse Inverse designdesignDesired S-parameters of all EM structures(Zin,Zout,.)Evaluate rewardsTopologyCB stackCE stackTop25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mm

195、Wave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference45 of 76Deep Reinforcement Learning for Architecture and Circuit Topology SynthesisLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState Action=Le1,Le2,Zin,Zout,RL Policy DeepNeural

196、 Network Le1-2 um+2 umprobability Le1 Le2 ZinPA Architecture:Optimal combining,Optimal#Gain StagesOptimal PA/Driver topologies and parameters#Combiner4321Episodes324#Gain StagesEpisodesEg:2-stage with 2-way combiner(for target specs)RewardsW/L1 R2C2C1R1W/L2 ZoutZinOpt:CB DriverL1Driver L2Zin,Driver,

197、optZout,Driver,optLe1Le2ZoutZinZoutZinPA cellEpsiodesOpt:CE StackLe2Driver cellsLe1Opt:CE StackEpsiodesAI-enabled Inverse Design for all EMs s3131s s2121s s1111s sN1N1 Real&Real&ImagImag Parts of Parts of N N-Port ParametersPort ParametersInverse Inverse designdesignDesired S-parameters of all EM st

198、ructures(Zin,Zout,.)Evaluate rewardsTopologyCB stackCE stackTop25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference46 of 76

199、Inverse Design of Electromagnetic StructuresGiven the S-parameters,inverse design finds the optimal geometry in few minutes with a deep-CNN based forward model with no EM simulations.Predicted Predicted S S-parametersparametersN N-port port GeometryGeometryOptimizationForward AI Model s31s21s11sN1Ta

200、rget S-parametersSee:Karahan,JSSC 2023,Karahan,Nat.Comm.202425.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference47 of 76Gen

201、erative AI with Diffusion Models for EM synthesis Generative ProcessMetalPortShorting ViaU-NetTarget S-parametersGenerative AI using Diffusion models(such as DALL-E)can also be employed to synthesize EM structures with target S-parameters.See:Y.Guo,E.A.Karahan,et.al,IMS-2025(accepted for publication

202、)25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference48 of 76Multi-port EM Synthesis60 60 GHz Splitter with Quadrature Phas

203、eGHz Splitter with Quadrature Phaseeff/6.5400 m2828-75 75 GHz Splitter with GHz Splitter with 0 0 PhasePhase400 mSee:Karahan,JSSC 2023,Karahan,Nat.Comm.2024mmWave DiplexermmWave Diplexer70 70 GHz Notch FilterGHz Notch Filter500 m300 m25.3:AI-enabled Design Space Discovery and End-to-end Synthesis fo

204、r RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference49 of 76Passive Synthesis for mmWave PA Design For PA design we require both 2-port and multi-port EM structures for matching and power c

205、ombining.Passive and active losses are captured into simulations.PAPAPAPACo-optimizeImpedance SeenInsertion LossDC BiasingCo-optimizePhase/amplitude balanceInsertion LossDC BiasingGmaxvsDevice SizePassive Insertion Loss25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Re

206、inforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference50 of 76Training Time and Synthesis Time*400 CPU Cores+192 CPU Cores*Within the design space in which it was trained 25.3:AI-enabled Design Space Discov

207、ery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference51 of 76Training Time and Synthesis Time*400 CPU Cores+192 CPU Cores*Within the design space in which it w

208、as trained 25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference52 of 76Training Time and Synthesis Time*400 CPU Cores+192 C

209、PU Cores*Within the design space in which it was trained 25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference53 of 76Deep R

210、einforcement Learning for Architecture and Circuit Topology Synthesis:FrameworkLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState Action=Le1,Le2,Zin,Zout,RL Policy DeepNeural Network Le1-2 um+2 umprobability Le1 Le2 ZinPA Architecture:Optimal combining,Optimal#Gain Sta

211、gesOptimal PA/Driver topologies and parameters#Combiner4321Episodes324#Gain StagesEpisodesEg:2-stage with 2-way combiner(for target specs)RewardsW/L1 R2C2C1R1W/L2 ZoutZinOpt:CB DriverL1Driver L2Zin,Driver,optZout,Driver,optLe1Le2ZoutZinZoutZinPA cellEpsiodesOpt:CE StackLe2Driver cellsLe1Opt:CE Stack

212、EpsiodesAI-enabled Inverse Design for all EMs s3131s s2121s s1111s sN1N1 Real&Real&ImagImag Parts of Parts of N N-Port ParametersPort ParametersInverse Inverse designdesignDesired S-parameters of all EM structures(Zin,Zout,.)Evaluate rewardsLayout-Aware Circuit Topology SynthesisInverse EM Synthesis

213、Deep RL for Topology/Parameter/EM Optimization25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference54 of 76Deep Reinforcemen

214、t Learning for Architecture and Circuit Topology Synthesis:FrameworkLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBLe1 Lb R2C2C1R1Le2 ZoutZinCE/CBStack/no stackState Action=Le1,Le2,Zin,Zout,RL Policy DeepNeural Network Le1-2 um+2 umprobability Le1 Le2 ZinPA Architecture:Optimal combining,Optimal#Gain StagesOptimal

215、PA/Driver topologies and parameters#Combiner4321Episodes324#Gain StagesEpisodesEg:2-stage with 2-way combiner(for target specs)RewardsW/L1 R2C2C1R1W/L2 ZoutZinOpt:CB DriverL1Driver L2Zin,Driver,optZout,Driver,optLe1Le2ZoutZinZoutZinPA cellEpsiodesOpt:CE StackLe2Driver cellsLe1Opt:CE StackEpsiodesAI-

216、enabled Inverse Design for all EMs s3131s s2121s s1111s sN1N1 Real&Real&ImagImag Parts of Parts of N N-Port ParametersPort ParametersInverse Inverse designdesignDesired S-parameters of all EM structures(Zin,Zout,.)Evaluate rewardsLayout-Aware Circuit Topology SynthesisInverse EM SynthesisDeep RL for

217、 Topology/Parameter/EM OptimizationTogether,this leads to Specifications to RFIC Layout25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Cir

218、cuits Conference55 of 76OutlineDesign Space for an AI-enabled RFICAI algorithms for Active-Passive Co-designReinforcement Learning+Inverse DesignDesign Examples and Measurement ResultsConclusion25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and

219、Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference56 of 76Example:7dB Gain,13dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with

220、 Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference57 of 76Example:7dB Gain,13dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBmSimulation Curves25.3:AI-enabled Design Space Disc

221、overy and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference58 of 76Example:7dB Gain,13dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBmSimul

222、ation CurvesMatching I/O Impedances25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference59 of 76Example:7dB Gain,13dBm PsatP

223、A at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBmSimulation CurvesMatching I/O ImpedancesTopology+Real Passives25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2

224、025 IEEE International Solid-State Circuits Conference60 of 76Example:7dB Gain,13dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBmSimulation CurvesMatching I/O ImpedancesTopology+Real PassivesStack Cap./Ind.+Bias Values25.3:AI-enabled Design Space Discovery and End-to-end Synt

225、hesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference61 of 76Example:7dB Gain,13dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBmSimulation CurvesMatching I/O

226、ImpedancesTopology+Real PassivesStack Cap./Ind.+Bias ValuesDevice Sizes25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference

227、62 of 76Example:7dB Gain,13dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE7dBPsat13dBmSpecResultPAE%31%Pgain Peak PAE7.4dBPsat14dBm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs b

228、etween 30-120 GHz 2025 IEEE International Solid-State Circuits Conference63 of 76Example:18dB Gain,14dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE18dBPsat14dBmSpecResultPAE%30.2%Pgain Peak PAE18.5dBPsat14dBm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with

229、 Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference64 of 76Example:18dB Gain,17dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE27%Pgain Peak PAE18dBPsat17dBmSpecResultPAE%30.2%Pgain Peak PAE17.2dBPsat17dBm

230、25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference65 of 76Example:14dB Gain,22dBm PsatPA at 40GHz(Layout+EM)SpecTargetPAE

231、27%Pgain Peak PAE14dBPsat22dBmSpecResultPAE%27.5%Pgain Peak PAE14.1dBPsat22dBm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Con

232、ference66 of 76Distribution of Designs at 40GHz Model learns large design range,with high efficiency.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International S

233、olid-State Circuits Conference67 of 76Distribution of Designs at 40GHz PAE decreases slightly with Psatdue to large layout devices.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120

234、 GHz 2025 IEEE International Solid-State Circuits Conference68 of 76Synthesized&Measured Chips48m48m48mL=94m,Z0=70 RFinRFoutVCC2VB1VB2VB35.9+j13.1(110 GHz)VCC1=1.6 V25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating

235、 mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference69 of 76Synthesized&Measured Chips2x6mRFin400 m400 mRFout2x6m4x8m4x8mVcc=1VVbe=-0.85VVbe=-0.85VVcc=1VVbe=-0.85 VVbe=-0.85 VVcc=1.25VVcc=1.25VVbe=-0.85V25.3:AI-enabled Design Space Discovery and End-to-end S

236、ynthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference70 of 76110GHz Measurement Results S21S11S22Sim.Meas.102 GHz120 GHz111 GHz 105-115GHz S21,3dB,100-120GHz Psat,3dBbandwidth Gai

237、n:12.9dB,PAE:9.4%,Psat:12.6dBm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference71 of 76110GHz Measurement Results Modula

238、tion6Gpbs-64 QAMPout,avg:7.1dBmPAEavg:3%EVM:-25.76dB 107GHz 115GHz 110GHz6Gpbs-64 QAMPout,avg:5.89dBmPAEavg:2.44%EVM:-26.23dB 6Gpbs-64 QAMPout,avg:5.05dBmPAEavg:1.9%EVM:-26.75dB 5Gpbs-32 QAMPout,avg:7.78dBmPAEavg:3.6%EVM:-25.93dB5Gpbs-32 QAMPout,avg:6.51dBmPAEavg:2.72%EVM:-24.48dB5Gpbs-32 QAMPout,av

239、g:5.65dBmPAEavg:2.16%EVM:-26.33dB0.95mm0.25mm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference72 of 7634-70GHz Measureme

240、nt Results 47-67GHz S21,3dB,34-70GHz Psat,3dBbandwidth Gain:15dB,PAE:11-26%,Psat:18.5-21.2dBm0.82mm1.07mm25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE Internation

241、al Solid-State Circuits Conference73 of 76Comparison 34-70 GHz Wideband PA Power,efficiency,gain are competitive with SOTA First end-to-end algorithmically designed PA25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrati

242、ng mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference74 of 76Comparison 110 GHz D-Band PA Synthesis free from fixed templates,comparable to the SOTA25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inv

243、erse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference75 of 76ConclusionFirst hybrid Human/AI method using Reinforcement learning and inverse design for RF/mmWave/sub-THz demonstrating end-to-end synthesis.Architecture+Circuits+EM co-

244、optimization for end-to-end design process.Demonstrated with broadband mmWave and sub-THz PA.AI-enabled design avoids long iterative processes,dramatically reduces design time&cost,and enhances productivity.25.3:AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement

245、Learning and Inverse Methods Demonstrating mmWave/sub-THz PAs between 30-120 GHz 2025 IEEE International Solid-State Circuits Conference76 of 76A New Word of AI-enabled RFICsJ.Zhou et,al,“AI-enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Met

246、hods Demonstrating mmWave/sub-THz PAs between 30-120 GHz”IEEE ISSCC 2025.E.A.Karahan,Z.Liu,A.Gupta,Z.Shao,J.Zhou,U.K.Khankhoje and K.Sengupta,Deep-learning Enabled Generalized Inverse Design of Multi-Port Radio-frequency and Sub-Terahertz Passives and Integrated Circuits,“Nature Comm(2024).The visio

247、n for future RFICs from blocks to systems could be one with AI-enabled assistants:Reducing design time,and discovering new topologies.Acknowledge ARO,AFOSR,ONR for funding.GlobalFoundries for chip fabrication25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ

248、 Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference1 of 34A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHzJ.Moody*,T.Liebsch*,P.Finnegan,S.Lepkowski,R.Costanzo,M.Hirabayashi,M.Jordan,T.Forbes,C.No

249、rdquistSandia National Laboratories,Albuquerque,NM25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference2 of 34Outline Need for high-Z non-disruptive probing Design considerati

250、ons for microprobes Electrical design RFIC Sense amplifier Design Mechanical system design Probe fabrication Measurements Comparison with prior art Die photo25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE Internatio

251、nal Solid-State Circuits Conference3 of 34Applications for non-disruptive probing25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference4 of 34Applications for non-disruptive pr

252、obingAggressorVictimFreq.DomainNo DC20GHzSpec.An.WidebandSignal Integrity and Cross-talk Debug25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference5 of 34Applications for non-

253、disruptive probingFreq.DomainLow DC Content1V signalsFreq.40GHzNarrowbandPCBAntenna substrate5G/6G RF Interface debugXOPLLTRXTRXTRXTRXTime and Freq.DomainPower system/bus debugTD/FDDC Component1V signalsFreq.1V signalsFreq.40GHzNarrowbandPCBAntenna substrate5G/6G RF Interface debugXOPLLTRXTRXTRXTRXT

254、ime and Freq.Domain25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference7 of 34Advances in non-invasive probingPicoprobe 35 GGB:Single point of contact26GHz cutoff10:1 Atten U

255、ndefined impedance in ground return High levels of inductive distortion High attenuation25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference8 of 34Advances in non-invasive pr

256、obingPicoprobe 35 GGB:Single point of contact26GHz cutoff10:1 Atten Multi contact defines ground return well Millimeter scale pitch for PCB level debugKeysight infiniimax:Flexible PCB Int.50GHz cutoff5:1 Atten25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Sit

257、u Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference9 of 34Advances in non-invasive probingPicoprobe 35 GGB:Single point of contact26GHz cutoff10:1 Atten Heterogeneous integration enables micron scale pitch Low attenuation maximizes SNR Designed for tightly integra

258、ted systems debugKeysight infiniimax:Flexible PCB Int.50GHz cutoff5:1 AttenThis work:Micromachined substrate(10um pitch)50GHz cutoff1:1 Atten25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State

259、Circuits Conference10 of 34Micromachine probe system RFICTipDecapSMPS-mini CoaxRFICTip Len LinDecapZ0=50DC+CTRLDC+CTRL300m handle15m probe thicknessFPC-DC Bias25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE Internat

260、ional Solid-State Circuits Conference11 of 34Probe Tip Electrical Considerations Probe tip forms inductance proportional to length Inductance and Cin form zero in Z11 Die Thickness/sin()VTHRe(Zin)0GM GM0VINDCVTHRe(Zin)0on=CC/ILeak GM=GM0VinDCVTH25-4:A Micromachined Heterogeneously Integrated Active-

261、Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference16 of 34DC Coupled Amplifier InputINIPVFBVIPVINVOPVONVIPCS InputSF Input+-ILeakon=CC/ILeak Complementary input with current mode feedbackSample&HoldComp.InputCurrent Mode FBVFBV

262、inVinVINDC0ID NonlinVINDC0ID Nonlin25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference17 of 34DC Coupled Amplifier InputINIPVFBVIPVINVOPVONVIPCS InputSF Input+-ILeakon=CC/IL

263、eak Complementary input with current mode feedbackSample&HoldComp.InputCurrent Mode FBVFBVinVinVINDC0ID NonlinVINDC0ID NonlinVINDC0ID Nonlin25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State C

264、ircuits Conference18 of 34Single Ended DC Coupled Amplifier Design Single ended implementation for GSG probe inputs25fFRF In1p1001001pActive Bias-TVDD=0.4 to 2.0VPeaking NetworkVSS=-1.6 to 0RF Out RF TermRF TermOutput BufferComp.Folded CascodeCLCFBCoCoIPMOSINMOS25-4:A Micromachined Heterogeneously I

265、ntegrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference19 of 34Differential DC Coupled Amplifier Design Fully differential implementation for GSSG probe inputs25fFRF In+25fF10fActive Bias-TVDD=0.4 to 2.0VPeaking Net

266、workVSS=-1.6 to 0RF Out+Output BufferComp.Folded CascodeCLCFBCoCoIPMOSINMOS10fRF Out-RF In-25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference20 of 34Core OP-Amp Design(Inpu

267、t)Input sized for 50fF CinEqual sized feedback FETs for unity gain FBBias for minimum NFMIN=150uA/umACBDBACD50fFPeak NetRF OutRF IN33 170 56 25 33 33 33 56 170 200 200 25 DC Offset Correction25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements fro

268、m DC to 50GHz 2025 IEEE International Solid-State Circuits Conference21 of 34ACBDBACD50fFPeak NetRF OutRF IN33 170 56 25 33 33 33 56 170 200 200 25 DC Offset CorrectionCore OP-Amp Design(Input)Minimum L in stackLow L drops AVOL50GHz RF BW Measured across multiple supplies 25-4:A Micromachined Hetero

269、geneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference24 of 34Measurement setup and S2P AWG/Scope for time domain measurements,VNA for Freq Tested on commercial RF probe station DUT is meandered RF throu

270、gh line Fabricated on same wafer run as probe substrate Standard GSG-100um probes used for RF-IODUT substrateDUT substrateH-Z1m coax1m coax1m coaxGSG-100GSG-100-probe25GHz/64GS AWG32GHz Oscope25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements fr

271、om DC to 50GHz 2025 IEEE International Solid-State Circuits Conference25 of 34RF S-Parameter measurements Measuring RF Signal into port 1 out of port 2 and port 3(Probe)Minor disruption 5010.753 12 WuDist.Rin=50No-17.21200.85568 11 ShifmanADC Buff.NR(HighZ)Yes1.64.00029.710 Kim Opt.RxRin=50Yes730.29

272、103DC CompensationInput voltageCurrentNANoNoNoTechnology45nm PD-SOI55nm250nmSiGe65nm CMOS10nm CMOS120nm SiGeDC Input range(V)-.9 to 1.4VNRNR0 to 1.05VNRNR(HighZ)NR1 to 2VComparison to prior ultra-wideband RF amplifiers25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disrupti

273、ve In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference28 of 34Probe Comparison with Prior Art 3 CrippsActiveNRNeedle4NoCOTSNRNo GND-6V to 6V2 GGB IndActiveCin=50fFNeedle26.520dBCOTSNo GNDTypeThis work1 KeysightImpedanceActiveCin=90fFActive48f/1k 5 Bauwens Pa

274、ssive50Probe Pitch(m)15/25/50500+5Amp.BW(GHz)5052220Tip Atten.(dB)1dB14dB404mV1mV-25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference29 of 34Probe Comparison with Prior Art

275、3 CrippsActiveNRNeedle4NoCOTSNRNo GND-6V to 6V2 GGB IndActiveCin=50fFNeedle26.520dBCOTSNo GNDTypeThis work1 KeysightImpedanceActiveCin=90fFActive48f/1k 5 Bauwens Passive50Probe Pitch(m)15/25/50500+5Amp.BW(GHz)5052220Tip Atten.(dB)1dB14dB404mV1mV-25-4:A Micromachined Heterogeneously Integrated Active

276、-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference30 of 34Die photos(RFIC)CMOS active area 650um25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IE

277、EE International Solid-State Circuits Conference31 of 34Die photos(Probe Substrate)Probe tip 10um pitch Tip Length 25um Overall substrate area 25mm225-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid

278、-State Circuits Conference32 of 34Die photos(Assembled System)3D printed Housing 1inX1in Ribbon cable connectors Mounts on standard probe stations25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-S

279、tate Circuits Conference33 of 34ConclusionsMicron scale probe developed with many applications in debugging complex microsystemsElectronic and Multiphysics must be considered when designing probe systemPresenting 10um pitch fully integrated probe system capable of detecting GHz class signals with mi

280、nimal disruption25-4:A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz 2025 IEEE International Solid-State Circuits Conference34 of 34Acknowledgements The authors would like to thank DARPA for funding this work This research was dev

281、eloped with funding from the Defense Advanced Research Projects Agency(DARPA).The views,opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S.Government.Approved for public relea

282、se,distribution Unlimited25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference1 of 32A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measure

283、ment in 28nm CMOSGuangdong Wu*1,Yuanliang Li*1,Bingyi Ye*1,2,Fangzhu Li1,Xin Liu1,Haowei Niu1,Ruixu Wang1,Dunshan Yu1,Weixin Gai1,3*Equally-Credited Authors(ECAs)1Peking University,Beijing,China,2East China Normal University,Shanghai,China,3Beijing Advanced Innovation Center for Integrated Circuits,

284、Beijing,China 25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference2 of 32Outline Motivation Overall Architecture Transmitter Sampler Measurement Result Comparison&Conclusion25.5:A

285、 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference3 of 32Outline Motivation25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in

286、28nm CMOS 2025 IEEE International Solid-State Circuits Conference4 of 32Channel Density Soars Rapidly Number of ports in switches continuously increases Electrical channel(Cable and PCB)density is rising20052010201520202025Year020406080100Number of Ports/Rack Unit10G Ethernet40G Ethernet100G Etherne

287、t400G EthernetInfiniBand25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference5 of 32Traditional Desktop Instruments Face DilemmasPowerSizeCostScalabilityDensityAccuracyS11S21S12S22

288、Vector Network AnalyzerTDR/TDT Sampling Head with OsciloscopeProposed ICA ICA25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference6 of 32Integrating Instrument:The Way Forward Each

289、 ICA Includes a transmitter and a sampler Support bi-directional TDR&TDT measurement Off-Chip Quantization&ProcessingIncidentWaveViReflectedWaveVrDUTTransmittedWaveVtOff-Chip Quantization&ProcessingICA1FEPTXSETSR ICA2TXSampler TXSampler25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for H

290、igh-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference7 of 32Challenge:High-frequency SNR Power decreases rapidly with increasing frequency Poor SNR at high frequency limits measurement bandwidthIncidentWaveViReflectedWaveVrDUTVtICA1TXSampler Tr

291、ansmittedWaveTime(ns)Frequency(GHz)Power(dBm)010203040-60-40-2000.10.20.30.40.500.51Amplitude(V)Step StimulusNoise Floor25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference8 of 32

292、Our Solutions:Patterned-Step Stimulus Combines periodic signals(f1)with step signalsTime(ns)Frequency(GHz)Power(dBm)010203040-60-40-20-38-50SinglePatternedf100.10.20.30.40.500.51Amplitude(V)Single Step vs.Patterned StepSinglePatterned Enhance the power in the frequency band around f125.5:A 99.5mW/po

293、rt DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference9 of 32Our Solutions:Patterned-Step Stimulus Adjust the power distribution by modify the pattern from 0101 to 001001 Move the energy peak from

294、f1to 2/3 f1Time(ns)00.10.50.51010101 vs.001001001010101001001001Amplitude(V)00.20.30.4Frequency(GHz)010203040-60-400101012/3f1f1001001001Power(dBm)25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State

295、 Circuits Conference10 of 32Outline Overall Architecture25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference11 of 32Overall ArchitectureTXSampler32Control&Pattern Gen.SER4Retimer4

296、4DFFDFFDFFDFFCML DriverBUFBUF32:4SAH4CKOUTCKIN(28GHz)OUTINOUTCKSCMLDIV2SETSCLK Gen.CMLDIV28242CML2CMOSDividersCLK Gate4Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pseudo-Differential Input/Output Clock-Gated 4:1 MUX Sequential Equivalent Time Sampling(SETS)25.5:A

297、99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference12 of 32Outline Transmitter25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in

298、 28nm CMOS 2025 IEEE International Solid-State Circuits Conference13 of 32TX ArchitectureTX32Control&Pattern Gen.SER4Retimer44DFFDFFDFFDFFCML Driver32:4CKIN(28GHz)INOUTCMLDIV28242CML2CMOSDividersCLK Gate4Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.Pulse Gen.25.5:A 99.5mW/po

299、rt DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference14 of 32Traditional Pulse Generator based 4:1 MUX Switching of the differential pairs leads to ripples Ripples superimposed on the echo cause e

300、rrorCK0CK90PGPGDI0DI0VOUTDO0PGPGDI90DI90DO90PGPGDI180DO180PGPGDI270DO270DI180DI270DO0PG-based 4:1 MUXDO180DO270DO90CK180CK270VOUTOUTPUT WITH RIPPLE55.055.15.155.2Time(ns)48mVCK0CK90CK180CK27025.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 2

301、8nm CMOS 2025 IEEE International Solid-State Circuits Conference15 of 32Clock-Gated 4:1 MUX C1M1M2TG1INV1C1BM3M4TG2INV2I_CK180I_CK0CK0CK180CK90CK270I_CK270I_CK90PGPGDI0DI0VOUTDO0PGPGDI90DI90DO90PGPGDI180DO180PGPGDI270DO270ABDI180DI270DO0PG-based 4:1 MUXCLK GateDO180DO270DO90 Add CLK Gate to pause an

302、d recover the four-phase clock Strictly synchronized C1 and C1B Signals.25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference16 of 324:1 MUX with Clock-Gated Ripples are eliminated

303、 since clock is halt Error is significantly reduced to below 2%without ripples00.050.10.150.2Time(ns)0%5%10%15%20%Impedancew/CLK Gatew/o CLK GateError010203040Frequency(GHz)0%50%100%Return Lossw/CLK Gatew/o CLK GateErrorw/o CLK GateVOUTOUTPUT WITH RIPPLE55.055.15.155.2Time(ns)48mVCK0CK90CK180CK27055

304、.055.15.155.2Time(ns)w/CLK GateOUTPUT WITHOUT RIPPLE7.1uV25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference17 of 32Outline Sampler25.5:A 99.5mW/port DC-to-40GHz Integrated Chann

305、el Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference18 of 32Sampler ArchitectureT=period of sampled signalT+t=period of sampling clock1/t=equivalent sample rateSETS&Signal ReconstructiontT+t1234567TSignalRec.tPeriodic inputSam

306、pling clockSequential Equivalent Time Sample(SETS)25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference19 of 32SETS Clock Generator 14GHz 7-bit Phase Interpolator provides t=558fs

307、Equivalent sample rate=1.792THz The PI update at 1/256 clock frequency,which reduces the random noise because the signal is oversampled and averaged Clock boosters for leakage reductionCKSCKOUTCKFPICLK BSTR25124422214GHzCML2CMOS7256CKACNTRDIfeedback path25.5:A 99.5mW/port DC-to-40GHz Integrated Chan

308、nel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference20 of 32Sample and hold Sampling capacitor C1 is only 14.7fF for high bandwidth Miller capacitance C2 reduces charge injection errors Channel leakage leads to large hold err

309、orsCKCKBVCMC1C2VINVIPVONVOPSHPSmallSampling CapacitorBUFM1M4M3AM225.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference21 of 32Clock boosterMN1MP1CCKIN=GNDCK=GNDMP3VDDB=600mVMN2MP2V

310、2V1Charging PhaseMN1MP1CCK=VDD+VDDBMP3VDDB=600mVMN2MP2V2V1CKIN=VDDBoosting phase The clock booster generates a high voltage sample clock with 10ps rising edge(10%-90%).No reliability issues VDDVDDBCKINCK25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Meas

311、urement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference22 of 32Simulated SAH waveformsThe hold error of SAH is reduced from 40mV to 34V with clock boostersCKCKBVCMC1C2VINVIPVONVOPSHPSmallSampling CapacitorBUFM1M4M3AM200.751.50.60.851.1Voltage(V)Voltage(V)SHSCKVIP480mVw/o CLK Boo

312、sterw/CLK Booster10203040500Time(ns)0.60.851.1Voltage(V)SHP192327313515Time(ns)0.930.971.01Voltage(V)40mV25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference23 of 32Outline Measur

313、ement Result25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference24 of 32TXSAH SETS CLK Gen.TXBlocksSampler0.0593Area(mm2)0.0085CLK Gate4:1 MUX220m439m226mPort3Port4Port1Port2Sampl

314、er40mChip Micrograph28nm CMOSChip Area:6mm2Four test ports(Two pseudo-differential pairs)per chipPower Consumption:398mWSupport Multi-Chip Collaborative Testing25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE Internationa

315、l Solid-State Circuits Conference25 of 32Measurement SetupICA2ICA1ADCGSGSGProbe28GHzClockGSGSGProbe28GHzClockICA1ICA2PCDUTLogic AnalyzerGSGSGProbeGSGSGProbeADCADCLogic Analyzer28GHz ClockR&S SMA100BRF Signal GeneratorBalunPowerDivider Conduct TDR and TDT measurement with two ICAs25.5:A 99.5mW/port D

316、C-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference26 of 32Impedance MeasurementCable1PCable1NCable2PCable2NPCB Trace PPCB Trace NCable3PCable3NDevice Under Test0%05101520Time(ns)2%4%3.4%405060Singl

317、e-ended ImpedanceGold Ref.ICAImpedance(ohm)Average Error=0.83%Error05101520Time(ns)0%2%4%3.8%Impedance(ohm)80100120Differential ImpedanceGold Ref.ICAAverage Error=1.03%ErrorCable1PCable2PPCB Trace PCable3PDevice Under Test25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Si

318、gnal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference27 of 32Differential S-Parameter MeasurementSparameter(dB)-40-30-20-100SDD22&SDD12Gold Ref.SDD12ICA SDD12Gold Ref.SDD22ICA SDD220510152025303540Frequency(GHz)Sparameter(dB)-40-30-20-100SDD11&SDD21Gold Ref.

319、SDD21ICA SDD21Gold Ref.SDD11ICA SDD110510152025303540Frequency(GHz)Frequency Band(GHz)010102020303040SDD211.16%1.48%2.28%4.37%SDD121.48%2.74%3.84%5.91%Average Error25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE Internat

320、ional Solid-State Circuits Conference28 of 32Single-End S-Parameter MeasurementFrequency Band(GHz)010102020303040S212.69%1.53%2.93%6.27%S121.93%1.45%1.64%4.13%Average ErrorSparameter(dB)-40-30-20-100S11&S21Gold Ref.S21ICA S21Gold Ref.S11ICA S110510152025303540Frequency(GHz)Sparameter(dB)-40-30-20-10

321、0S22&S12Gold Ref.S12ICA S12Gold Ref.S22ICA S220510152025303540Frequency(GHz)25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference29 of 32Outline Comparison&Conclusion25.5:A 99.5mW/

322、port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference30 of 32Comparison with state-of-the-artsTechnologyFrequency(GHz)PortsRise Time(20%80%,ps)TX Jitter(fs,rms)TX Noise(mV,rms)Sampler Noise(mV,r

323、ms)Area/Port(mm2)Power/Port(mW)Dynamic Range(dB)Frequency Sweep180nm SiGe BiCMOST-MTT *4322N/AN/A-894044-77Internal180nm SiGe BiCMOST-MTT 20*0.01262N/AN/A-0.93201293External*28nm CMOSThis Work04049.11170.980.810.40299.530-40Not Required*Integrated VNA*Integrated VNA Front End*No internal stimulusOpe

324、rational DomainFrequencyFrequencyTime25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference31 of 32Conclusion A 4-port integrated channel analyzer for SI measurement is verified in

325、28nm CMOS technology The analyzer exhibits an average measurement error below 6.5%from DC to 40GHz with a DUT IL of 20.04dB28GHz.The TX utilizes a clock-gated 4:1 MUX with a patterned step technique to reduce the ripple and improve the SNR of the sampled signal PI-based SETS clock generator provides

326、 an equivalent sample rate of 1.792THz with low power The sample-and-hold circuit with clock boosters reduces the hold errors 25.5:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS 2025 IEEE International Solid-State Circuits Conference32 of 32Thank you for your attention!