SESSION 7 - Ultra-High-Speed Wireline.pdf

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1、ISSCC 2024SESSION 7Ultra-High-Speed Wireline7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference1 of 46A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm

2、 FinFETJ.Q.Wang1,A.Tan1,A.Iyer1,A.Fan2,A.Farhoodfar1,B.Alnabulsi3,B.Smith3,C.Loi4,C.R.Ho1,D.Cartina5,J.Riani1,J.Casanova1,K.Raviprakash1,L.Patra1,L.Wang1,M.Bachu1,S.Ray1,S.Chong4,S.Dallaire3,T.Nguyen1,T-F.Wu2,V.Giridharan1,V.Gurumoorthy1,X.Ding4,Y.Yin1,Z.Sun4,S.Jantzi2,L.Tse11Marvell,Santa Clara,CA,

3、2Marvell,Irvine,CA,3Marvell,Ottawa,Canada,4Marvell,Singapore,Singapore5Marvell,Burnaby,Canada7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference2 of 46Outline Motivation Transmitter Architectur

4、e Receiver Architecture Measurement Results Comparison and Conclusion7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference3 of 46Data CenterOptical ModulesCampus Switch/RoutersT3 SwitchT1/T2 Swit

5、chTORServerTraditional data center7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference4 of 46Data Center Evolution with AICampus Switch/RoutersT3 SwitchT1/T2 SwitchTORServerData center with AITr

6、aditional data centerAI SwitchAI compute nodesHigh bandwidth opticsAI compute interconnect opticsAI Inference ServerAI Training ClusterDemand Expansion7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits C

7、onference5 of 46BW Requirements are Exponential024681012141618202020 2021 2022 2023 2024 2025 2026 2027DC Capex CAGR:11%DC BW CAGR:51%Growth FactorSource:Marvell estimates based on industry analyst forecastsOptical(IMDD-PAM4)Pluggable Modules200G/Bandwidth and Capex GrowthAnnual Units Consumed1x2x3x

8、7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference6 of 46Optical Module OverviewODSPOpticsDriverTIADACHOST SERDESTXDTXADCRXDRX7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Dir

9、ect-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference7 of 46Optical Module OverviewODSPOpticsDriverTIADACHOST SERDESTXDTXADCRXDRXFocus of this talk7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE I

10、nternational Solid-State Circuits Conference8 of 46Design ChallengesPowerPerformanceModule Power Breakdown28G55GDoubling BWReducing RJ200fs,rms100fs,rms7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits

11、Conference9 of 46Outline Motivation Transmitter Architecture Receiver Architecture Measurement Results Comparison and Conclusion7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference10 of 46TX Arc

12、hitecture Performance Focus DAC+linear driver CAL ADC for skew loop 1 PLL per TX CKGENDCC+Skew correction Timing margin calDetection with PDAdjustment with LS PITX PLLCKGEN32:11128 x 8b Data LSPI/22 x 4UIPDCAL ADCSerializer2:14:1 DAC2-stage Linear Driver4 x 4UI8 x 8UI7.1:A 2.69pJ/b 212Gb/s DSP-Based

13、 PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference11 of 46TX Architecture Power Focus Adaptive voltage scaling(AVS)Two AVS domains Adapted in backgroundTX PLLCKGEN32:11128 x 8b Data LSPI/22 x 4UIPDCAL ADCSerializer2:14:1 DAC

14、2-stage Linear Driver4 x 4UI8 x 8UIData AVSClock AVS7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference12 of 46TX Frontend Architecture for 200G TXDACDACDACChoi,ISSCC21Kim,ISSCC21This WorkDirec

15、t DACDAC+1-stage driverDAC+2-stage driverDAC size DAC loadingPower3x3x7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference13 of 46TX Frontend DAC Unit Cell double stack structure+cascodeVBCK1CK2

16、CK2BDDAC Unit CellDIVdmpCK1CK2CK2BDDIDAC Timing Diagram1UIIoutIoutD0D1D1D2D2D17.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference14 of 46TX Frontend DAC Unit Cell NMOS cascode:swing control PMO

17、S switch:faster turn off,reduce ISIVBCK1CK2CK2BDDAC Unit CellDIVdmpCK1CK2CK2BDDIDAC Timing Diagram1UIIoutIoutD0D1D1D2D2D17.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference15 of 46TX Frontend D

18、AC Unit Cell D pre-charged DI through NAND gateVBCK1CK2CK2BDDAC Unit CellDIVdmpCK1CK2CK2BDDIDAC Timing Diagram1UIIoutIoutD0D1D1D2D2D17.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference16 of 46T

19、X Frontend DAC Unit Cell CK1 rising edge:DAC turned onVBCK1CK2CK2BDDAC Unit CellDIVdmpCK1CK2CK2BDDIDAC Timing Diagram1UIIoutIoutD0D1D1D2D2D17.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference17

20、 of 46TX Frontend DAC Unit Cell CK2 rising edge:reset DI-DAC turned off CK2B falling edge:DAC turned offVBCK1CK2CK2BDDAC Unit CellDIVdmpCK1CK2CK2BDDIDAC Timing Diagram1UIIoutIoutD0D1D1D2D2D17.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IE

21、EE International Solid-State Circuits Conference18 of 467b DACCK*3D0PD0N887b DACSlice0Slice1Slice2Slice3VCMFB1VCMFB2VrefVonVopTX Front end Overview4:1 DACPre-DriverDriver7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Sol

22、id-State Circuits Conference19 of 467b DACCK*3D0PD0N887b DACSlice0Slice1Slice2Slice3VCMFB1VCMFB2VrefVonVopTX Front end 4:1 DAC 2b therm+5b binary Common mode control7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-St

23、ate Circuits Conference20 of 467b DACCK*3D0PD0N887b DACSlice0Slice1Slice2Slice3VCMFB1VCMFB2VrefVonVopTX Front end Pre-Driver Flipped voltage follower(FVF)7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuit

24、s Conference21 of 467b DACCK*3D0PD0N887b DACSlice0Slice1Slice2Slice3VCMFB1VCMFB2VrefVonVopTX Front end Driver Push-pull architecture AC coupling on PMOS side7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circ

25、uits Conference22 of 46Outline Motivation Transmitter Architecture Receiver Architecture Measurement Results Comparison and Conclusion7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference23 of 46

26、RX Architecture Off-chip TIA Short channel NO RX CTLE needed BW Control is important Many optical impairments Requires DSP-based RXTIATERM8xSAR128 x 7b Data BUF1BUF2TAH2 x 4UIPulseGen12.5%16AFEx16RX PLL16 x 16UIVGACKGENDSP(FFE,DFE,RC,MLSD)7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optica

27、l Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference24 of 46RX Architecture Performance FocusTERM8xSAR128 x 7b Data BUF1BUF2TAH2 x 4UIPulseGen12.5%16AFEx16RX PLL16 x 16UIVGACKGEN BW control in AFE VGA drives 16 TAH(2UI)2-rank time interleaving 1 PLL per R

28、X CKGEN:phase gen and clock skew compensation PulseGen:2UI track pulse7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference25 of 46RX Architecture Power Focus Two AVS domains Adapted in backgroun

29、dTERM8xSAR128 x 7b Data BUF1BUF2TAH2 x 4UIPulseGen12.5%16AFEx16RX PLL16 x 16UIVGACKGENData AVSClock AVS7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference26 of 46RX AFE OverviewTERMBuffer1VGATo

30、 TAHRXPRXN7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference27 of 46RX AFE TerminationTo TAHRXPRXN Integrated AC coupling7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-D

31、etect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference28 of 46RX AFE Buffer1To TAHRXPRXN Input cap neutralization to reduce Miller cap BW extension with capacitor degeneration7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in

32、5nm FinFET 2024 IEEE International Solid-State Circuits Conference29 of 46RX AFE VGATo TAHRXPRXN Improved linearity with parallel PMOS switches Input AC coupling for optimal common mode7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE In

33、ternational Solid-State Circuits Conference30 of 46To TAHRXPRXNRX AFE BW Control Inductor shorting switches in active stages7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference31 of 46Outline Mo

34、tivation Transmitter Architecture Receiver Architecture Measurement Results Comparison and Conclusion7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference32 of 46Die Photo 4 lanes of RX+TX RX ana

35、log(w/PLL)0.72mm2 TX analog(w/PLL)0.64mm27.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference33 of 46TX Measurement:Random Jitter FSWP50 1100 clock pattern RJ=72fs,rms 2M 2ndorder CDR 1kHz to 13

36、.28GHz7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference34 of 46TX Measurement:212Gbps PAM4 PAM4 106Gbaud De-embedded to die bump PRBS13 Swing=817mV RLM 0.99 BW 55GHz7.1:A 2.69pJ/b 212Gb/s DSP

37、-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference35 of 46RX Measurement:Magnitude Response High BW setting55GHz BWFor low optical input power Low BW setting30GHz BWFor high optical input power7.1:A 2.69pJ/b 212Gb/s DS

38、P-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference36 of 46RX Measurement:SNDR SNDR 36dB DC SNDR 30dB 40GHzDominated by residue timing spur and RJ7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-De

39、tect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference37 of 46RX Measurement:Histogram-3-113025210215220Count PRBS test with BERT Pre-FEC BER 55GHz signal bandwidth Transceiver analog power efficiency of 2.69pJ/b is achieved7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Trans

40、ceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference45 of 46Acknowledgement The authors would like to thank the entire development team of this project for their dedication and support.Special thanks go to validation team for valuable mea

41、surement support.7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference46 of 46References1 Z.Guo et al.,A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with 50dBChannel Loss in 5nm FinFET,I

42、SSCC,pp.116-118,Feb.2022.2 H.Park et al.,A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switchin 5nm FinFET,ISSCC,pp.110-112,Feb.2023.3 J.Kim et al.,A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nmCMOS,ISSCC,pp.126-128,Feb.2021.4 M.Choi et al.,An Output-Bandwidth-Optimi

43、zed 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS,ISSCC,pp.128-130,Feb.2021.5 Y.Segal et al.,A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation,ISSCC,pp.114-116,Feb.2022.6 B.Ye,G.Wu,W.Gai,K.Sheng and Y.He,A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE wi

44、th Low-Frequency Equalization in 28nm CMOS,ISSCC,pp.112-114,Feb.2023.7.1:A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET 2024 IEEE International Solid-State Circuits Conference47 of 46Please Scan to Rate This Paper7.2:A 224Gb/s sub-pJ/b PAM-4 and PA

45、M-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference1 of 56A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFETMarco Cusmai,Noam Familia1,Elad Kuperberg1,Mohammad Nashash1,Dovid Gottesman1,Daljeet Kumar2,Zvi Marcus1,Yeshayahu Horwitz1,Sagi

46、 Zalcman1,Jihwan Kim3,Sandipan Kundu3,Ilia Radashkevich1,Yoav Segal1,Dror Lazar1,Udi Virobnik1,Mike Peng Li4,Ariel Cohen11Intel,Jerusalem,Israel,2Intel,Bangalore,India,3Intel,Hillsboro,OR,4Intel,San Jose,CA7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE Internati

47、onal Solid-State Circuits Conference2 of 56Outline Motivation Architecture Circuit implementation MeasurementsJitter on clock patternsPRBS eye diagrams and compliance tests Performance summary7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-Sta

48、te Circuits Conference3 of 56Motivation Need higher data-rate to improve energy efficiency7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference4 of 56Key Challenges 224Gb/s TX and RX demonstrated in prev.ISSCC 1 23.3pJ/b co

49、mbined energy efficiency(TX=1.9pJ/b,RX=1.4pJ/b)Improve performance,focusing on power efficiencyMuch better energy efficiency(pJ/b)compared to 100Gb/sCompetitive power for legacy standards Evolving ecosystem requires a flexible designDifferent modulations and legacy standards support Compliant to IEE

50、E802.23ckScaling specifications from 56Gbaud for 224Gb/s Ready for volume manufacturingImplementing test featuresRobust against SOC supply noise7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference5 of 56Key Challenges 224G

51、b/s TX and RX demonstrated in prev.ISSCC 1 23.3pJ/b combined energy efficiency(TX=1.9pJ/b,RX=1.4pJ/b)Improve performance,focusing on power efficiencyMuch better energy efficiency(pJ/b)compared to 100Gb/sCompetitive power for legacy standards Evolving ecosystem requires a flexible designDifferent mod

52、ulations and legacy standards support Compliant to IEEE802.23ckScaling specifications from 56Gbaud for 224Gb/s Ready for volume manufacturingImplementing test featuresRobust against SOC supply noise7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Sol

53、id-State Circuits Conference6 of 56Key Challenges 224Gb/s TX and RX demonstrated in prev.ISSCC 1 23.3pJ/b combined energy efficiency(TX=1.9pJ/b,RX=1.4pJ/b)Improve performance,focusing on power efficiencyMuch better energy efficiency(pJ/b)compared to 100Gb/sCompetitive power for legacy standards Evol

54、ving ecosystem requires a flexible designDifferent modulations and legacy standards support Compliant to IEEE802.23ckScaling specifications from 56Gbaud for 224Gb/s Ready for volume manufacturingImplementing test featuresRobust against SOC supply noise7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based

55、 Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference7 of 56Key Challenges 224Gb/s TX and RX demonstrated in prev.ISSCC 1 23.3pJ/b combined energy efficiency(TX=1.9pJ/b,RX=1.4pJ/b)Improve performance,focusing on power efficiencyMuch better energy efficiency(pJ/b)compared

56、 to 100Gb/sCompetitive power for legacy standards Evolving ecosystem requires a flexible designDifferent modulations and legacy standards support Compliant to IEEE 802.3ckScaling specifications from 56Gbaud Ready for volume manufacturingImplementing test featuresRobust against SOC supply noise7.2:A

57、224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference8 of 56Key Challenges 224Gb/s TX and RX demonstrated in prev.ISSCC 1 23.3pJ/b combined energy efficiency(TX=1.9pJ/b,RX=1.4pJ/b)Improve performance,focusing on power efficiencyM

58、uch better energy efficiency(pJ/b)compared to 100Gb/sCompetitive power for legacy standards Evolving ecosystem requires a flexible designDifferent modulations and legacy standards support Compliant to IEEE 802.3ckScaling specifications from 56Gbaud Ready for volume manufacturingImplementing test fea

59、turesRobust against SOC supply noise7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference9 of 56Outline Motivation Architecture Circuit implementation MeasurementsJitter on clock patternsPRBS eye diagrams and compliance tes

60、ts Performance summary7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference10 of 56Transmitter architectural choices FlexibilityDAC-based transmitter with quarter rate clockingSupporting NRZ,PAM-4 and PAM-6Local lane PLL wi

61、th intra-lane optional clock distribution Power efficiencyTargeting sub pJ/b for TX+PLL(2x better than previous art)2Single stage output driverLow voltage serializer with single re-timer Ready for productionCalibrations with on-chip sensing on output pads onlyRegulated power supply from on-chip LDOs

62、 for jitter sensitive blocksInternal loopback support to local lane RX7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference11 of 56Transmitter architectural choices FlexibilityDAC-based transmitter with quarter rate clockin

63、gSupporting NRZ,PAM-4 and PAM-6Local lane PLL with intra-lane optional clock distribution Power efficiencyTargeting sub pJ/b for TX+PLL(2x better than previous art)2Single stage output driverLow voltage serializer with single re-timer Ready for productionCalibrations with on-chip sensing on output p

64、ads onlyRegulated power supply from on-chip LDOs for jitter sensitive blocksInternal loopback support to local lane RX7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference12 of 56Transmitter architectural choices Flexibilit

65、yDAC-based transmitter with quarter rate clockingSupporting NRZ,PAM-4 and PAM-6Local lane PLL with intra-lane optional clock distribution Power efficiencyTargeting sub pJ/b for TX+PLL(2x better than previous art)2Single stage output driverLow voltage serializer with single re-timer Ready for product

66、ionCalibrations with on-chip sensing on output pads onlyRegulated power supply from on-chip LDOs for jitter sensitive blocksInternal loopback support to local lane RX7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference13 o

67、f 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 2

68、24Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference14 of 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to dr

69、iver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference15 of 56Transmitter architectureOn-chip 28GHz LC P

70、LLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Tran

71、smitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference16 of 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timingDriver replicaFor temperature track

72、ing2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference17 of 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented D

73、AC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International

74、Solid-State Circuits Conference18 of 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane recei

75、verFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference19 of 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI

76、+Phase detectorFor serializer to driver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference20 of 56Transmi

77、tter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timingDriver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-

78、pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference21 of 56Transmitter architectureOn-chip 28GHz LC PLLInductorless I/Q generation7-bit segmented DAC1-stage CML driver9-Tap FFE64:4 serializerPI+Phase detectorFor serializer to driver timing

79、Driver replicaFor temperature tracking2 bits internal loopbackTo local lane receiverFor pre-packaging testing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference22 of 56Outline Motivation Architecture Circuit implementatio

80、n MeasurementsJitter on clock patternsPRBS eye diagrams and compliance tests Performance summary7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference23 of 56Clocking:LC-DCO Complementary class B oscillatorSelected for good

81、area/performance tradeoff Running at 28GHz for PAM-4 224Gb/s Running at 22.4GHz for PAM-6 224Gb/sRequiring 25%coarse tuning range Tail 2f0 LC filters To improve phase noise and supply noise rejection7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International So

82、lid-State Circuits Conference24 of 56Clocking:LF/HF Clock Path High Frequency path for 200+Gb/s Low Frequency path,based on quadrature dividers Option to use same lane or remote lane PLL7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Cir

83、cuits Conference25 of 56Clocking:LF/HF Clock Path High Frequency path for 200+Gb/s Low Frequency path,based on quadrature dividers Option to use same lane or remote lane PLL7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Confere

84、nce26 of 56Clocking:LF/HF Clock Path High Frequency path for 200+Gb/s Low Frequency path,based on quadrature dividers Option to use same lane or remote lane PLL7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference27 of 56Cl

85、ocking:LF/HF Clock Path High Frequency path for 200+Gb/s Low Frequency path,based on quadrature dividers Option to use same lane or remote lane PLL7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference28 of 56Clocking:I/Q Ge

86、neration Delay line based,used only in full rate mode I/Q(1UI)delay controlled by load capacitors and vccdlvccdlgenerated by finely tuned 1.2V LDO Supported tuning range from 20GHz to 30GHz Temperature tracking with vccdlonly 7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET

87、 2024 IEEE International Solid-State Circuits Conference29 of 56Clocking:Phase Control Fine control on each of the 8 rising/falling clock edgesThrough DCC and load capacitors tuning Series-shunt peaking on output buffer for noise filtering 2Shunt inductor used only in full speed mode 7.2:A 224Gb/s s

88、ub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference30 of 56Clocking:Phase Control Fine control on each of the 8 rising/falling clock edgesThrough DCC and load capacitors tuning Series-shunt peaking on output buffer for noise filtering 2

89、Shunt inductor used only in full speed mode 7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference31 of 56Datapath:FFE and 64:8 serializerNRZ/PAM mapping and equalization64UI mapped to 64UI x 7b 9 sliding FFE taps64:8 serial

90、izerRunning on low voltage digital supply3b to 7b Binary to Thermometer decoderWithout retiming to save power7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference32 of 56Datapath:8:4 serializerChallenging timing between 8:4

91、 to 4:1Power supplies mismatched1UI delay to avoid additional re-timerPhase detector(PD)on replica datapathTurned on periodically for voltage/temp.trackingPhase Interpolator(PI)Setting optimal timing on serializers interface7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2

92、024 IEEE International Solid-State Circuits Conference33 of 56Datapath:8:4 serializerChallenging timing between 8:4 to 4:1Power supplies mismatched1UI delay to avoid additional re-timerPhase detector(PD)on replica datapathTurned on periodically for voltage/temp.trackingPhase Interpolator(PI)Setting

93、optimal timing on serializers interface7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference34 of 56Datapath:8:4 serializerChallenging timing between 8:4 to 4:1Power supplies mismatched1UI delay to avoid additional re-timer

94、Phase detector(PD)on replica datapathTurned on periodically for voltage/temp.trackingPhase Interpolator(PI)Setting optimal timing on serializers interface7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference35 of 56Datapath

95、:8:4 serializerChallenging timing between 8:4 to 4:1Power supplies mismatched1UI delay to avoid additional re-timerPhase detector(PD)on replica datapathTurned on periodically for voltage/temp.trackingPhase Interpolator(PI)Setting optimal timing on serializers interface7.2:A 224Gb/s sub-pJ/b PAM-4 an

96、d PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference36 of 56 Quadrature clocks used to generate 1UI pulseNo pulse generated if corresponding data is high Supplied by 0.9V LDO,trimmed for best pulse widthOutput driver:Pulse generator7.2:A 224Gb/s sub-pJ/

97、b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference37 of 56Output driver:DAC slice Pulse generator drives the 4:1 serializer without pre-driverImproving power,linearity and jitter amplification Pseudo-differential driver with weighted current

98、 source 67.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference38 of 56Output driver:DAC sliceUndriven node when long string of“1”s is transmittedNode will reach Vcs-Vth to barely turn on current sourceVoltage will sharply d

99、rop when data starts to toggleParasitic capacitance needs to be low enough to not cause ISIUndriven nodelong string of“1”s7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference39 of 56Output driver:DAC array7 thermo+4 binary

100、 weighted slices make the whole DACAll slices outputs shorted to drive matching networkSame Vcsbiasing for all slicesCreated by analog loop on driver replica,calibrated for target output swing7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-Sta

101、te Circuits Conference40 of 56Output driver:matching network 7thorder inductive network with trimmable terminationShunt inductor for bandwidth extensionT-coil with ESD diodes on central tap7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State

102、Circuits Conference41 of 56Outline Motivation Architecture Circuit implementation MeasurementsJitter on clock patternsPRBS eye diagrams and compliance tests Performance summary7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conf

103、erence42 of 56Die photo and package technology Two possible escape routes:C4 bump to On Package Connector(OPC)Better insertion loss performanceC4 bump to Ball Grid Array(BGA)DieConnectorPCB121OPC2BGAConnectorCoax.Package7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024

104、IEEE International Solid-State Circuits Conference43 of 56Package and matching network performance7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference44 of 56Clock patterns(High frequency path)56GHz clock pattern89.6GHz sc

105、ope BW4MHz 1storder CDR RJ=62fs28GHz clock patternPhase noise analyzer(R&S FSWP50)-99dBc/Hz 1MHz offset from carrier21.2GHz to 30.0GHz PLL tuning range7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference45 of 56Eye diagram

106、s measurement setupPackaged die and PCBOPC+6inch Coax+DC blockReal-time oscilloscope256GS/s Keysight UXR1104AChannel de-embedded80%of baud-rate scope BWNo scope equalizationOn-chip FFE activeSet to maximize vertical eye openingQPRBS-13 patternEye opening for BER=1e-47.2:A 224Gb/s sub-pJ/b PAM-4 and

107、PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference46 of 56IEEE 802.3ck TX specificationsAll measured on Q-PRBS13 pattern12 different PAM-4 transitionsSNDR 32.5dBLinearity and noise without ISIRLM 0.95PAM-4 levels separationJRMS 23mUI(210fs 224Gb/s)Uncor

108、related jitter RMSJ3u03 106mUI(950fs 224Gb/s)Uncorrelated jitter BER=10-3Only 0-3 transition due to oscilloscope noiseEOJ Drivers undriven node not an issuePRBS7,NRZ 112Gb/sPRBS31,NRZ 112Gb/s7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-Stat

109、e Circuits Conference52 of 56Outline Motivation Architecture Circuit implementation MeasurementsPRBS eye diagrams and compliance testsJitter on clock patternsSpectrum of sinewave Performance summary7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Sol

110、id-State Circuits Conference53 of 56Performance comparison7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference54 of 56Performance comparison7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IE

111、EE International Solid-State Circuits Conference55 of 56Summary Presented a 224Gb/s TX in 3nm FinFET technology Supports both PAM-4 and PAM-6 at 224Gb/s Achieved analog energy efficiency,including PLL:0.92pJ/b at 224Gb/s PAM-40.61pJ/b at 224Gb/s PAM-61.00pJ/b at 112Gb/s PAM-4 TX occupies 0.15mm2,inc

112、luding PLL Meeting all 802.3ck specs scaled to 112Gbaud7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference56 of 56References1 J.Kim et al.,A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS”ISSCC,pp.126-128

113、,Feb 2021.2 Y.Segal et al.,A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation ISSCC,pp.114-116,Feb.2022.3 H.Park et al.,A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET,ISSCC,pp.5-7,Feb 2023.4 Z.Guo et al.,A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Re

114、ach Transceiver with 50dB Channel Loss in 5nm FinFET,ISSCC,pp.116-118,Feb 2022.5 B.Zhang et al.,A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology,ISSCC pp.5-7,Feb 2023.6 Z.Toprak-Deniz et al.,6.6 A 128Gb/s 1.3pJ/b

115、PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS,ISSCC,pp.122-124,Feb 2019.7.2:A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET 2024 IEEE International Solid-State Circuits Conference57 of 56Please Scan to Rate This Paper 2024 IEEE International Solid-State Circuits

116、 ConferenceA 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS Dirk Pfaff1,Muhammad Nummer1,Noman Hai2,Peter Xia2,Kai Ge Yang2,Mohammad-Mahdi Mohsenpour1,Marc-Andre LaCroix1,Babak Zamanlooy3,Tom Eeckelaert1,Dmitry Petrov1,Mostafa Haroun1,Carson Dick2,Alif Zaman1,Haitao Mei1,Shahab Moa

117、zzeni1,Tahseen Shakir1,Carlos Carvalho1,Howard Huang1,Pratibha Kumari1,Ralph Mason1,Fahmida Brishty2,Ifrah Jaffri21Synopsys,Ottawa,Canada 2Synopsys,Mississauga,Canada 3Synopsys,Markham,Canada 7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS1 of 52 2024 IEEE International Solid-

118、State Circuits ConferenceOutline Transceiver Architecture Custom Circuit Implementation Clock Synthesis and Conditioning Receiver:Analog Frontend,Analog to Digital Converter Transmitter Measurement Results Transceiver Operation Bit-Error-Rate Gain from Advanced DSP 224Gb/s Measurement Results for a

119、40dB Channel Conclusions7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS2 of 52 2024 IEEE International Solid-State Circuits ConferenceTransceiver ArchitectureTLTX CCUDSPSERRX CCU ADCCDRAFEDSPCMURXTXXTALDACRXdataTXdatato lanes2,3,4TL Shared clock multiplier unit AFE/ADC/DSP rec

120、eive path DSP/SER/DAC transmit path 1/8 rate clock 8 phase recovered clock 8 phase transmit clock Preserved from 112Gb/s:New concepts:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS3 of 52 2024 IEEE International Solid-State Circuits ConferenceTransceiver ArchitectureTLTX CCUD

121、SPSERRX CCU ADCCDRAFEDSPCMURXTXXTALDACRXdataTXdatato lanes2,3,4TLWhy 1/8 rate clock:Elimination of 28GHz clock saves power Passive,inductor free clock distributionBut 8 phase clock system increases complexity Handled by TX/RX Clock Conditioner Units(CCUs)28GHz 14GHz7.3:A 224Gb/s 3pJ/b 40dB Insertion

122、 Loss Transceiver in 3nm FinFET CMOS4 of 52 2024 IEEE International Solid-State Circuits ConferenceTransceiver ArchitectureTLTX CCUDSPSERRX CCU ADCCDRAFEDSPCMURXTXXTALDACRXdataTXdatato lanes2,3,4TLChallenging analog circuity environment:56GHz Nyquist frequency Clock jitter:sub 100fs Clock phase accu

123、racy:100fs Limitations of connectors,interconnect worsen SIRemedy comes partially from advanced DSP:Maximum likelihood sequence detection(MLSD)7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS5 of 52 2024 IEEE International Solid-State Circuits ConferenceDLFPDPSDRIFT CORRDIV 1.5

124、XTALCLKDLFPDPSDRIFT CORRXTALDLFPDPSDRIFT CORRDIV 1.5XTALCLKDLFPDPSDRIFT CORRXTAL12.7GHz 10%10.4GHz 10%Full octave frequency achieved by Divide by 1.5 range extension7GHz 14GHz Dual oscillator with+/-10%tuning range LC tank:Q 10Clock Synthesis7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm

125、 FinFET CMOS6 of 52 2024 IEEE International Solid-State Circuits ConferenceDLFPDPSDRIFT CORRDIV 1.5XTALCLKDLFPDPSDRIFT CORRXTALClock Synthesis Fine resolution Digitally Controlled Oscillator(DCO)All Digital Bang-Bang PLL with minimum quantization jitter500kHz/LSB500kHz/LSB7.3:A 224Gb/s 3pJ/b 40dB In

126、sertion Loss Transceiver in 3nm FinFET CMOS7 of 52 2024 IEEE International Solid-State Circuits ConferenceDLFPDPSDRIFT CORRDIV 1.5XTALCLKDLFPDPSDRIFT CORRXTALClock Synthesis Digital background drift correctionMaintains phase locking over-40C to 125C temperature range(without need for re-calibration)

127、650MHz650MHz7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS8 of 52 2024 IEEE International Solid-State Circuits ConferenceClock Conditioning Wideband locking suppresses ring oscillator jitter Removes clock buffer chain high frequency jitter28Octal clock:8-stage injection locke

128、d ring oscillator:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS9 of 52 2024 IEEE International Solid-State Circuits ConferenceClock ConditioningTX Clock Conditioner Unit:2DACDACDACTDC88To TXTDCPhase ShifterILOFrom PLL DAC controlled ILO free-running frequency DAC controlled

129、Phase Shifting Buffer set positive/negative clock edges individually Clock phase calibration circuits:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS10 of 52 2024 IEEE International Solid-State Circuits ConferenceClock ConditioningTX Clock Conditioner Unit:2DACDACDACTDC88To TX

130、TDCPhase ShifterILOFrom PLL Time To Digital Converters(TDC)measure phase error at ILO and Phase Shifting Buffer outputs Digital background servo loops maintain phase accuracy7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS11 of 52 2024 IEEE International Solid-State Circuits Co

131、nferenceClock ConditioningRX Clock Conditioner Unit:DACDACDACTDCXTDC82844222ILOPhase ShifterPhase RotatorDACDACDACTDC88TDCPhase ShifterILOTo ADCFrom PLLidentical to the TX CCU10-bit phase rotator:1/128 UI recovered clock resolution Second ILO with Phase Shifting Buffers ensure high PR linearity7.3:A

132、 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS12 of 52 2024 IEEE International Solid-State Circuits ConferenceClock ConditioningVnVpOperationAdvance clockDelay clock.Increase DC.Decrease DCPhase Shifting Buffer:VDDDACDACinoutVnVpSigma Delta ModulatorC10:0VnVp11-bit Sigma Delta Mod

133、ulator DAC7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS13 of 52 2024 IEEE International Solid-State Circuits ConferenceClock ConditioningTime to Digital Converter(TDC)measurement principle:1.Over-sampling of 1/8-rate clock phases by auxiliary clock2.Post-sampling logic ident

134、ifies R2R and F2F events3.Event countingIncrement R2R counterIncrement F2F counterCK8EARLYCK8LATEAuxiliary Clock7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS14 of 52 2024 IEEE International Solid-State Circuits ConferenceClock ConditioningTime to Digital Converter(TDC)implem

135、entation:samplinglogiccountingCK8EARLYCK8LATEENAsync.OSCF2FR2R24-bit Cntr24-bit Cntr Asynchronous auxiliary clock enables low speed sub-sampling 7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS15 of 52 2024 IEEE International Solid-State Circuits ConferenceClock Measurements1/8

136、 rate clock phase noise:Full rate TX clock:90fs rms jitter(1kHz 100MHz)55fs rms jitter with 4MHz CDR7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS16 of 52 2024 IEEE International Solid-State Circuits ConferenceClock Measurements12fsrms Jitter vs.Temperature:Phase shifting buf

137、fer delay:Stable PLL jitter over fulltemperature range 14fs average step size 10ps delay range7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS17 of 52 2024 IEEE International Solid-State Circuits ConferenceTransmitterPrincipal Architecture:7-bit DAC 64 symbol wide data port 8:1

138、 data MUXAdvantages:Flexible modulation/equalization1.75GHz max.core clock1/8 rate clock lower powerDIVCK87:0D647:063:0D89:07:0TXRTTVTTgm7b DAC8:164:87.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS18 of 52 2024 IEEE International Solid-State Circuits ConferenceDIVCK87:0D647:06

139、3:0D89:07:0TXRTTVTTgm7b DAC8:164:8TransmitterKey parameters determining the eye quality:Output bandwidth:Group delay variation:Also critical:8:1 MUX Pulse ShrinkageTermination network Clock phase accuracy:TDC based calibration7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS19 o

140、f 52 2024 IEEE International Solid-State Circuits ConferenceTransmitterCK8SETCK8RESETD8p Pulse generator:Generates unit interval wide data pulse from 1/8 rate clock Turn on(off):Positive(negative)edge of set(reset)clock Full rail to rail pulse amplitude CK8SETCK8RESETD8p Current source driver contro

141、lled by pulse generator VBCK8SETCK8RESETD8p7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS20 of 52 2024 IEEE International Solid-State Circuits ConferenceTransmitter 8 pulse generator instances form 8:1 MUX BW limitation at OUTVBVBVBVBVBVBVBVBRTTVTTOUT8 CS implementationD81 CK

142、81D82 CK82D83 CK83D84 CK84D85 CK85D86 CK86D87 CK87p0p1p2p3p4p5p6p7D80 CK800 1 2 3 4 5 6 77.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS21 of 52 2024 IEEE International Solid-State Circuits ConferenceVBVBVBVBRTTOUTVTTQuadruple CS implementationTransmitter BW limitation at swit

143、ch nodeRTTVTTOUTVBSingle CS implementation Sufficient BW at all full rate nodes7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS22 of 52 2024 IEEE International Solid-State Circuits Conference1641530274147263OUTD83D82D87D86D80D81D84D85P0P1P2P3P4P5P6P7CK8.630730CK8.CK8.CK8.053041

144、74116152CK8.30405CK8.CK8.CK8.VBVBTransmitter8:1 MUX with D8 re-timer logic Quadruple current source(CS)Dynamic logic pulse generator(8 MOS)Data retiming by dynamic latches(4 MOS)1641530274147263OUTD83D82D87D86D80D81D84D85P0P1P2P3P4P5P6P7CK8.630730CK8.CK8.CK8.05304174116152CK8.30405CK8.CK8.CK8.VBVBRT

145、MUXDRVx7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS23 of 52 2024 IEEE International Solid-State Circuits ConferenceRTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12RTMUXDRV12RTMUXDRV8RTMUXDRV8RTMUXDRV12RTMUXDRV12SE-DAC,14 slicesoutTransmitter 14-slice 7-bit DAC Optimized for b

146、andwidth and power consumption Drive strength spread limited to 12 Driver segmentation:1x,2x,4x,8x(3),12x(8)7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS24 of 52 2024 IEEE International Solid-State Circuits ConferenceTransmitterRTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12R

147、TMUXDRV12RTMUXDRV8RTMUXDRV8RTMUXDRV12RTMUXDRV122:12:12:12:12:12:12:12:14:14:14:14:14:14:14:14:1I/FDECD647:063:0SE-DAC,14 slicesout Static CMOS Serializer:Interface Decoder 4:1 MUX,2:1 MUX Dual T-Coil output terminationRTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12RTMUXDRV12RTMUXDRV8RTMUXDRV8RTMUXDRV

148、12RTMUXDRV122:12:12:12:12:12:12:12:1RTTVTTTXP4:14:14:14:14:14:14:14:1I/FDECD647:063:0SE-DAC,14 slicesField Solver Simulation80GHz-3dB Bandwidth1psGroup delay variation-12dBReturn loss7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS25 of 52 2024 IEEE International Solid-State Ci

149、rcuits ConferenceRTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12RTMUXDRV12RTMUXDRV8RTMUXDRV8RTMUXDRV12RTMUXDRV122:12:12:12:12:12:12:12:1RTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12RTMUXDRV12RTMUXDRV8RTMUXDRV8RTMUXDRV12RTMUXDRV122:12:12:12:12:12:12:12:1RTTVTTTXNDACNRTTVTTTXP4:14:14:14:14:14:14:14:1I

150、/FDECD647:063:0SE-DAC,14 slicesTransmitter Differential signaling by symmetrical half-circuits7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS26 of 52 2024 IEEE International Solid-State Circuits ConferenceRTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12RTMUXDRV12RTMUXDRV8RTMUXDR

151、V8RTMUXDRV12RTMUXDRV122:12:12:12:12:12:12:12:1RTRTRTRTMUXDRV8MUXDRV4MUXDRV2MUXDRV1RTMUXDRV12RTMUXDRV12RTMUXDRV8RTMUXDRV8RTMUXDRV12RTMUXDRV122:12:12:12:12:12:12:12:1RTTVTTTXNDACNRTTVTTTXP4:14:14:14:14:14:14:14:1I/FDECD647:063:0CK87:0CK64PRDIV 4DIV 2CCULDOVBGENCK16SE-DAC,14 slicesTransmitter Clocking

152、system:CK87:0,CK16,CK64 Phase rotator(PR)Voltage regulator(LDO)Bias generator(VB GEN)7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS27 of 52 2024 IEEE International Solid-State Circuits ConferenceTransmitter Measurements224Gb/sRLM=0.992Vswing=960mVdiffpp106.25Gb/s56Gb/s 4MHz C

153、DR BW(Sampling Scope)No TX FFE 5.5dB test fixture loss removed7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS28 of 52 2024 IEEE International Solid-State Circuits ConferenceTransmitter MeasurementsDNL=+/-0.2 LSBINL=+/-0.5 LSBDifferential NonlinearityIntegral Nonlinearity7.3:A

154、224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS29 of 52 2024 IEEE International Solid-State Circuits ConferenceRXPRXN ADCCTLE1CTLE2 VGATERMD796:0D786:0D006:0Analog FrontendReceiverAnalog/Mixed Signal RX section:80 parallel outputs Dxx6:0 Direct I/F to DSP Termination(TERM)Continuous

155、 Time Linear Equalizer(CTLE)Variable Gain Amplifier(VGA)7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS30 of 52 2024 IEEE International Solid-State Circuits ConferenceRXPRXN ADCCTLE1CTLE2 VGATERMRXDSPS791:0S781:0S001:0Receiver RX DSP converts signal samples into PAM4 symbolsDx

156、x6:0=-64,+63 Sxx1:0=-3,-1,+1,+3 Main DSP functions:(signal path)ADC gain and offset correction Feedforward Equalization(adaptive)Decision Feedback Equalization(adaptive)Maximum Likelihood Sequence Detection7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS31 of 52 2024 IEEE Inter

157、national Solid-State Circuits ConferenceRXPRXN ADCCTLE1CTLE2 VGATERMRXDSPRX CCUCCU ControlRecovered ClockS791:0S781:0S001:0PLL CLKReceiver Main DSP functions:(clock path)Mueller-Muller Clock Data Recovery Skew Error Correction7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS32 o

158、f 52 2024 IEEE International Solid-State Circuits ConferenceReceiverDSPRX CCU80 180 90 45 10 x SAR10 x SAR10 x SAR10 x SARAFE10 x SAR10 x SAR10 x SAR10 x SAR270 225 135 315 SARCLKRank 1Rank 2112-Gb/s Time Interleaved Analog-to-Digital Converter:2 rank data converter topology 10-way signal interleave

159、r 80 7-bit Successive Approximation Register(SAR)8-way signal interleaver 14GHz samplers 4 input buffers eliminate charge sharing between samplers7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS33 of 52 2024 IEEE International Solid-State Circuits ConferenceReceiver1C1C2C2C4C4C

160、8C8C16C 16C32C 32C1C1C2C2C4C4C8C8C16C 16C32C 32CTrack&HoldCompAsync.LogicSAR_CLKCOMP_CLKVINDOUT6:0 Top plate sampling Binary weighted capacitor DAC Asynchronous switching logic Balanced switching Constant common mode Strong-ARM comparator1.4Gs/s Successive Approximation Register(SAR)7.3:A 224Gb/s 3p

161、J/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS34 of 52 2024 IEEE International Solid-State Circuits ConferenceRTTESDRXNCTLE1ESDRXPReceiver T-coil provides excellent return loss T-coil extends bandwidth from RX bump to CTLE inputT-Coil Termination:RXPRXNCTLE1CTLE2 VGATERM Combined ESD and CTL

162、E capacitance restrict signal bandwidth7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS35 of 52 2024 IEEE International Solid-State Circuits ConferenceRTTESDRXNCTLE1ESDRXPReceiverSolution:Isolate ESD from CTLE by additional T-coilDual T-Coil Termination:RXPRXNCTLE1CTLE2 VGATERM

163、 BW determined by CTLE aloneField Solver Simulation:78GHz-3dB Bandwidth-9dBReturn loss0.9dBPassband ripple7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS36 of 52 2024 IEEE International Solid-State Circuits ConferenceReceiverQfZfPfresAHFAMFADCRXPRXNCTLE1CTLE2 VGATERMOUTINgm1gm

164、d1gm1gmd1kLLPassive series peaking:Inverter gain stage Transformer coupled output Conjugate complex pole pair Q factor determines peaking gain11mDCmdgAg=HFDCAQ A=7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS37 of 52 2024 IEEE International Solid-State Circuits ConferenceRece

165、iverOUTINgm1gmd1gm2gmd2gm1gmd1gm2gmd2CCkLLCCQ21mmggRXPRXNCTLE1CTLE2 VGATERM AC coupled gain stage introduces zero/pole pair Medium frequency gain Wideband peaking:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS38 of 52 2024 IEEE International Solid-State Circuits ConferenceRec

166、eiverQfZfPfresAHFAMFADCRQOUTINgm1gmd1gm2gmd2gm1gmd1gm2gmd2CCRQRQkLLCCRXPRXNCTLE1CTLE2 VGATERM Transmission gate RQ reduces Q factor(peaking gain)Programmable peaking gain:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS39 of 52 2024 IEEE International Solid-State Circuits Confe

167、renceReceiverOUTINgm1gmd1gm2gmd2gm1gmd1gm2gmd2CCRCRQRQkLLRCCCQfZfPfresAHFAMFADCRQRCRXPRXNCTLE1CTLE2 VGATERM Transmission gate RC increases DC gainProgrammable DC gain:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS40 of 52 2024 IEEE International Solid-State Circuits Conferenc

168、eReceiverOUTINgm1gmd1gm2gmd2gm1gmd1gm2gmd2CCRCRQRQkLLRCCCgmd2QfZfPfresAHFAMFADCRQRCRXPRXNCTLE1CTLE2 VGATERMProgrammable zero/pole:Diode impedance sets zero/pole frequency7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS41 of 52 2024 IEEE International Solid-State Circuits Confer

169、enceReceiverMeasured VGA Gain20dB6dBMeasured CTLE1+CTLE2 Responsewith fixed VGA gainwith fixed CTLE boost7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS42 of 52 2024 IEEE International Solid-State Circuits ConferenceReceiverENOB=5.5bit 1.2GHzENOB=4.0bit 50GHzAFE/ADC sine wave

170、test at 112GS/s:SNR=36.5dBSNDR=35.0dBSNR=26.5dBSNDR=25.5dB7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS43 of 52 2024 IEEE International Solid-State Circuits ConferenceReceiverDNL=+/-0.2 LSBINL=+/-0.6 LSBAFE/ADC Linearity Test:Differential NonlinearityIntegral Nonlinearity7.3

171、:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS44 of 52 2024 IEEE International Solid-State Circuits ConferenceReceive EqualizationAFEADCGainOffsetFFEV(t)sDFEnsMLSDnDFEMLSDEqualization Methods:1.44-tap FFE+1-tap DFE2.44-tap FFE+Full State MLSD3.44-tap FFE+Reduced State MLSDChanne

172、l:1.212.5Gb/s at 36dB IL2.224Gb/s at 40dB IL7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS45 of 52 2024 IEEE International Solid-State Circuits ConferenceReceive EqualizationAFEADCGainOffsetFFEV(t)sDFEnsMLSDnDFEMLSD 1+D partial FFE response:BERDFERS MLSDFS MLSD01BER vs :7.3:A

173、 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS46 of 52 2024 IEEE International Solid-State Circuits ConferenceReceive EqualizationAFEADCGainOffsetFFEV(t)sDFEnsMLSDnDFEMLSD+3+1-1-3sMLSD-3 sMLSD-2 sMLSD-1 sMLSD0 Viterbi Algorithm+3+1-1-3sMLSD-3 sMLSD-2 sMLSD-1 sMLSD0+3+1-1-3sMLSD-3

174、sMLSD-2 sMLSD-1 sMLSD0 Preselection of most likely transitionsFull State MLSD:Reduced State MLSD:7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS47 of 52 2024 IEEE International Solid-State Circuits ConferenceReceiver Bit Error Rate MeasurementsDFERS MLSDFS MLSD2.4E-051.8E-061.

175、0E-067.5E-051.4E-051.0E-06212.5Gb/s36dB IL224Gb/s40dB IL MLSD improves BER24x to 75x24x75x FS MLSD lowers BER to 1E-6 at 224Gb/s with 40dB IL channel 7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS48 of 52 2024 IEEE International Solid-State Circuits ConferenceTest Chip Summar

176、yTechnology3nmAreaTX:0.1mm2RX:0.22mm2DSP:0.18mm2Lane0.5mm2PowerTX:1pJ/bitRX:2pJ/bitAnalog3pJ/bitSupplies0.75V1.1V1.5V7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS49 of 52 2024 IEEE International Solid-State Circuits ConferenceVisit the Live Demo!7.3:A 224Gb/s 3pJ/b 40dB Inse

177、rtion Loss Transceiver in 3nm FinFET CMOS50 of 52 2024 IEEE International Solid-State Circuits ConferenceConclusions Presented a 224Gb/s transceiver in 3nm FinFET Combines low power consumption and excellent signal equalization3pJ/bit analog energy efficiency1e-6 BER at 40dB IL Achieved by advances

178、in both analog and digital1/8 rate clocking,inverter based AFEMaximum Likelihood Sequence Detection7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS51 of 52 2024 IEEE International Solid-State Circuits ConferenceThe following Synopsys teams have contributed to this work:Physical

179、 Design TeamDigital Design TeamDigital Verification TeamSystem GroupValidation Team112Gb/s Analog Team7.3:A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS52 of 52 2024 IEEE International Solid-State Circuits ConferencePlease Scan to Rate This Paper 2024 IEEE International Solid-Sta

180、te Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 1 of 30A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and 74.2dBc Reference Spur Yunbo Huang1,Yong Chen1,Zunso

181、ng Yang2,Rui P.Martins1,3,Pui-In Mak11-University of Macau,Macau,China2-Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China3-Instituto Superior Tecnico/University of Lisboa,Lisbon,Portugal 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Rin

182、g-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 2 of 30MotivationProposed Dual-Path Ping-Pong Sampling PLLMeasurement ResultsConclusionsOutline 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-P

183、ong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 3 of 30Ring-Oscillator-Based PLL Compact footprint and wide frequency tuning range Inherent multi-phase generation and frequency-pulling resilience Inferior phase noise and high flicker-noise corner Large reference spur due to wid

184、e loop bandwidth or periodical injection-80-70-60-50-40REF Spur(dBc)02004006008001000RMS Jitter(fs)Xu,ISSCC22TargetLee,JSSC18Lee,ISSCC20Kong,JSSC16ILCMPLLMDLLKim,ISSSC22Yang,ISSCC19Bae,JSSC16Park,JSSC22Kim,JSSC17Nagam,JSSC18Kang,JSSC22Megawer,JSSC19Yang,JSSC19Elkholy,JSSC19Khashaba,JSSC20Prior RO-ba

185、sed Integer-N Clock GeneratorsDemand on Multiple PLLs in High-Speed WirelineB.Zand,ISSCC22H.Park,ISSCC23 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 4 of 30Type-I Sa

186、mpling PLL High PD gain and wide bandwidth Effective noise suppression of in-band and VCO Only proportional path Insufficient flicker-noise suppression Charge sharing between CS1and CS2induces pole Degraded phase marginLimitations of State-of-the-Art TopologiesCK1VS1CK2XOREF Buf.fREF NSampling CLK G

187、eneratorXOR+MSSFCK1CK2CS1CS2VS2ROXORfOUTL.Kong,JSSC16 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 5 of 30XOPulse Gen.fREFROfOUTLimitations of State-of-the-Art Topolo

188、gies High RO PN suppression through the phase-realignment mechanism Imperfect alignment timing Sensitive jitter and spur performance Limited multiplication factor(N)Injection-Locked Clock Multiplier(ILCM)R.Xu,ISSCC22 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ri

189、ng-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 6 of 30Limitations of State-of-the-Art Topologies High RO PN suppression through the phase-realignment mechanism Larger N than ILCM due to edge-switching Time required for edge switching limits the maximu

190、m frequencyMultiplying Delay Locked Loop(MDLL)XOREF Buf.fREF01PDROfOUT.SelectLogicLF NS.Yang,JSSC19 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 7 of 30Limitations of

191、 State-of-the-Art Topologies Multiplied REF frequency via multiphase combining Extended loop bandwidth Digital background calibration required Convergence time of 1msXOfREFMultiPhase Gen.EdgeCombinerPhase ErrorCalibratorREF MultiplierPLLfOUTMfREFA.Khashaba,JSSC20PLL with Reference(REF)Multiplier 202

192、4 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 8 of 30XOREF Buf.fREFSSPDfOUT.CP+LFVCDLPLLZ.Huang,ISSCC16Limitations of State-of-the-Art TopologiesAdditional RO PN filterin

193、g outside the main PLL loop Relieve BW-stability trade-off Power-consuming VCO-frequency VCDLArea-penalty of additional SS-DLL filterPLL with Cascaded Closed-Loop DLL 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring

194、 220.3fsrms Jitter and 74.2dBc Reference Spur 9 of 30XOREF Buf.fREFfOUTSS-PLLNCBNoise ExtractionLimitations of State-of-the-Art TopologiesPLL with Open-Loop Feedforward PN CancellationAdditional RO PN filtering outside the main PLL loop Relieve BW-stability trade-off Power-consuming VCO-frequency no

195、ise cancelling block(NCB)Sensitive open-loop noise cancellation Off-chip gain calibration requiredS.S.Nagam,JSSC18 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 10 of

196、30Proposed Dual-Path Ping-Pong Sampling PLLPing-pong sampling Implicit REF frequency doubling Larger loop BW and PMP-pathUGBVREFGMCII-pathVSVDIV(2fREF)CK1CK2VS1VS2Ping-Pong Sampling PD(PP-SPD)CK3CK3Slope Generator NROXOREF BUFfREFSampling CLK GeneratorCK1CK2CK3 VS updates at 2fREF UGB to eliminate c

197、harge sharing Fully use rising and falling edges of REFCS1CS2CU 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 11 of 30Proposed Dual-Path Ping-Pong Sampling PLLHigh KPD

198、+I/P Dual Path in-band and 1/f noise suppression Low RMS JitterP-pathUGBVREFGMCII-pathVSVDIV(2fREF)CK1CK2VS1VS2Ping-Pong Sampling PD(PP-SPD)CK3CK3Slope Generator NROXOREF BUFfREFSampling CLK GeneratorCK1CK2CK3 Dual path to further suppress 1/f noise High KPD to suppress in-band noise CS1CS2CU 2024 I

199、EEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 12 of 301.Master-Slave Sampling PD2.Ping-Pong Sampling PD3.Ping-Pong Sampling PD with UGB InsertedUGBCK1CK2CK3CK3CS1VIVOCS2CS1C

200、K1CK2CK3CK3CS1VIVOCS2CS1CK1CK2CS1VOVICS2Evolution of PP-SPDVDIVCK2VS(2fREF)(2fREF)TREF CK1VS1VS2CK3TREF/2 Timing DiagramVS1VS2VSVSis updated at 2fREFrate equivalently 2fREFsamplingCS2contains the varactor arrays inserting UGB to eliminate charge sharing 2024 IEEE International Solid-State Circuits C

201、onference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 13 of 30Evolution of PP-SPDSimulated PAC Response(CS1=2CS2)00.20.40.60.81/REF-120-80-400Phase(Degree)-20-100Magnitude(dB)00.20.40.60.81/REFPing-pong sampling with UGB

202、extends the BW of the equivalent sampling filterThe little gain loss is due to finite gain of UGB Can be compensated by high KPD1.Master-Slave Sampling PD2.Ping-Pong Sampling PD3.Ping-Pong Sampling PD with UGB InsertedUGBCK1CK2CK3CK3CS1VIVOCS2CS1CK1CK2CK3CK3CS1VIVOCS2CS1CK1CK2CS1VOVICS2 2024 IEEE In

203、ternational Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 14 of 30Comparison with Prior Double-Edge Sampling Prior Double-Edge Sampling Y.Zhao,JSSC22Proposed Ping-Pong Sampling This WorkSchem

204、aticTiming DiagramSample and Hold DelayTREF/2TREFDouble Edge LeverageUtilize rising and falling edges of the reference clock to sample 2fREF feedback signalUtilize feedback clock to sample the rising and falling edges of the reference clockSampling Stage12CK1C1CK1C2CK3C3C4CK2VRVS1VS2(fREF)VS updates

205、 at 2fREF CK1C1CK3C2CK2VRCK3VSVS1VS2(2fREF)VRTREF0CK3CK1CK2VRCK3CK1TREF0CK2 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 15 of 30Top Architecture and Circuit DetailsR

206、ODual PathMain S-PLL LoopP-pathMMDUGB-AMPRe-Sampling and Edge Correction Loop(ECL)ECL-AMPVREFGM-AMPCII-pathXOREF BUFfREFVSVDIV(2fREF)VREFCK1CK1CK2CK2VS1VS2PP-SPDCK3CK3CK1CK2CK3CK3CK3CK3Sampling Clock GeneratorT-Shape SWT-Shape SWCK1CK2CK3Slope GeneratorCK3CK3DQRetimerCUCS1CS2CRS1CRS2CECL 2024 IEEE I

207、nternational Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 16 of 30Noise of amplifiers are suppressed by high KPDTwo separate sets of varactors array for I/P-pathGM-AMPECL-AMPUGB-AMPVIPVINVBV

208、OVDDVIPVINVBVOVDDVBRzCzVIPVINVBVOVDDDifferential ROSW2:0SW2:0SW2:0CVPCVPCVICVIVCPVCICVPCVPCVICVIVCPVCICVPCVPCVICVIVCPVCIP-PathI-PathTop Architecture and Circuit Details 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scori

209、ng 220.3fsrms Jitter and 74.2dBc Reference Spur 17 of 30Imperfect Sampling Timing VDIV(2fREF)VSTREF TREF/2 VDIV(2fREF)VSTREF TREF/2 TCK1-CK2=TREF/2 TCK1-CK2 TREF/2 The average value of VSis about VREF(typically VDD/2)due to the I-pathVSis toggling when TCK1-CK2deviates from TREF/2 Loop BW and jitter

210、 degradationVSVDIV(2fREF)VREFCK1CK1CK2CK2VS1VS2PP-SPDCK3CK3CK1CK2CK3CK3CK3CK3T-Shape SWT-Shape SWCS1CS2 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 18 of 30Operation

211、 Principle of ECLTunable REF BufferSampling CLK GeneratorEdge Delay TuningScaled assistant branch to finely adjust the transition thresholdThe falling edges of CK1and CK2inherit the falling and rising edges of CK0.20.30.40.50.60.70.8VECL(V)0.450.50.55Edge Delay(TREF)ECL Locking PointTT 27C SS 80C FF

212、-40C t1 t1 t2 CKCK2CK1CK3TREF/2 t1 t1 t2 CKS2DCK1CK1S2DCK2CK2S2DCK3CK3CKVECLAMPXOfREFCK3CK3CRS1CRS2CECLVRS1VRS2Upon Locking Status:VS=VRS1=VRS2 VS 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter a

213、nd 74.2dBc Reference Spur 19 of 30Settling Behavior of ECL2fREFupdated VSis re-sampled and then comparedVSconverges after the settling of the ECL and main PLL loop VS=VRS1=VRS2CKVECLAMPXOfREFCK3CK3CRS1CRS2CECLVRS1VRS2Upon Locking Status:VS=VRS1=VRS2 VS00.20.40.60.8Voltage(V)VS00.511.522.533.5Time(s)

214、2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 20 of 30Settling Behavior of ECLVECLdynamically aligns edge delay by adjusting the threshold of REF bufferPing-pong sampl

215、ing edge delay is TREF/2 after locked00.511.522.533.5Time(s)00.20.40.60.8Fast LockingVoltage(V)VECLCKVECLAMPXOfREFCK3CK3CRS1CRS2CECLVRS1VRS2Upon Locking Status:VS=VRS1=VRS2 VS 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PL

216、L Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 21 of 30Chip Photo with Power BreakdownDGFA250m 130m ECBRO13.1UGB-Amp+GM-Amp+LFs 0.83Divider+Slope Buffer1.13PP-SPD0ECL-Amp+LF0.12Sampling CLK GeneratorTotal16.47Power Consumption(mW)ABCDEFREF Buffer1.29G65nm CMOSActiveArea:0.027mm2 2024 IEEE In

217、ternational Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 22 of 30Measured Phase Noise 6.6GHz(fREF=100MHz)fPLL,OUT=6.6GHzRMS Jitter=220.3fs(1k-100MHz)98.26dBc/Hz1kHz109.11dBc/Hz10kHz118.37dBc

218、/Hz100kHz118.93dBc/Hz1MHz10k100k10M1M100MOffset Frequency(Hz)1k-100Phase Noise(dBc/Hz)-110-120-130-140-90fBW 35MHzSufficient PM119.78dBc/Hz10MHzFree Running ROs PNWide loop bandwidth of 35MHz with no PN peaking sufficient loop PM 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2

219、5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 23 of 30Measured Phase Noise 6.6GHz(fREF=100MHz)Measured phase noise when turning-OFF the ECL Degraded BW and jitterThe control voltage VS is togglingDegraded KPD and loop bandwidthECL OFF:34

220、2.5fsECL ON:220.3fsLarge spur 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 24 of 30Measured RMS Jitter across Frequency Range5.566.577.58Frequency(GHz)200220240260Jit

221、ter(fs)Chip1Chip2Chip3Across the whole tuning range for three chips,RMS jitter is consistently 250fsIntegration Range:1k-100MHz 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Referenc

222、e Spur 25 of 30Measured Spectrum 6.6GHz(fREF=100MHz)Decent REF spur under large loop BWfPLL,OUT=6.6GHzfREF=100MHz74.17dBc 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur

223、 26 of 30Measured Spectrum 6.6GHz(fREF=100MHz)16.29dBcRapid-deteriorated SpurfPLL,OUT=6.6GHzfREF=100MHzThe control voltage VS is togglingECL OFFMeasured spectrum when turning-OFF the ECL Degraded BW and spur 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscill

224、ator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 27 of 30Measured REF Spur across Frequency RangeAcross the whole tuning range for three chips,REF spur is consistently 67dBc-80-70-60REF Spur(dBc)5.566.577.58Frequency(GHz)Chip1Chip2Chip3 2024 IEEE International S

225、olid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 28 of 30Performance Comparison with the State-of-the-ArtsThis WorkJSSC22 S.ParkISSCC22 R.XuISSCC20Y.LeeISSCC20H.H.TingJSSC18S.S.NagamCMOS Process(

226、nm)656565654065PLL ArchitectureAnalog S-PLLwith PP-SPDPower GatingILCMILCMwith IPSDigital PLLAnalog SS-PLLAnalog SS-PLL with FFNCSupply Voltage(V)11.211.20.91.2fREF(MHz)10012050120-1232149.15fPLL,OUT(GHz)6.6(5.6-7.8)8.16(7.68-8.52)2.5(2.1-2.7)7.68(7.68-7.872)5.252.36Multiplication Factor(N)66(56-78)

227、68(64-71)50(42-54)642548Tuning Range(%)33.310.425NANANAPower(mW)16.4714.31.236.489.015.86Core Area(mm2)0.0270.1020.0210.0750.160.022REF Spur fREF(dBc)74.2557960.5NA55.2Integrated Jitter(fsRMS)(Integrated Range)220.3(1k-100MHz)97(1k-100MHz)819(10k-40MHz)373(1k-100MHz)1950(50k-10MHz)630(1k-100MHz)PN10

228、0kHz(dBc/Hz)#118.4118.3103.2116.391.8111.1PN1MHz(dBc/Hz)#118.9126.8103.1117.793.7110.1FOM*241.0248.7240.8240.5224.6236.3FOMN*259.2267254.8258.5248.6253.1 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms J

229、itter and 74.2dBc Reference Spur 29 of 30ConclusionsAwide-loop-BW dual-path RO-based PLL is presented:Ping-pong sampling phase detector(PP-SPD)to mitigate the limitation of the loop BW Edge correction loop(ECL)to effectively align the two sampling edges Simultaneously improve integrated jitter and R

230、EF spur PLL prototyped in 65nm CMOS:Balanced jitter-spur performance:Low jitter(250fsrms)and low spur(70dBc)Compact area:0.027mm2 State-of-the-art FOM:241dB-80-70-60-50-40Reference Spur(dBc)02004006008001000This WorkBetterRMS Jitter(fs)ISSCC22JSSC18ISSCC20ISSCC19JSSC16JSSC16JSSC22JSSC17JSSC19JSSC19

231、JSSC18JSSC22JSSC19 JSSC20ISSSC22ILCMPLLMDLL 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc Reference Spur 30 of 30Acknowledgments Multi-Year Research Grant of University of Macau(MYRG

232、 of UM)Macao Science and Technology Development Fund(FDCT)High-Frequency High-Speed Wireless/Wireline(HFHS-W2)Research Group in IME,UM 2024 IEEE International Solid-State Circuits Conference7.4:A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and 74.2dBc R

233、eference Spur 31 of 30Please Scan to Rate This Paper7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference1 of 43A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 80

234、0GbE/1.6TbEXiongshi Luo1,Xuewei You1,Zhenghao Li1,Hamed Mosalam1,Dongfan Xu1,Taiyang Fan1,Hongchang Qiao1,Wentao Zhou1,Hongzhi Wu1,Liping Zhong1,Patrick Yin Chiang2,Quan Pan11Southern University of Science and Technology,Shenzhen,China 2Fudan University,Shanghai,China 7.5:A 224Gb/s/wire Single-Ended

235、 PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference2 of 43Outlinen Motivationn Overall Architecturen Transmitter Front-Endn Receiver Front-Endn Measurement Resultsn Conclusion7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver F

236、ront-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference3 of 43MotivationSource:OIF-FD-CEI-224GnExponential traffic growth demands a high date rate of 224Gb/s/lane7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 8

237、00GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference4 of 43MotivationTypical long-reach scenarios with 310m distanceRack to rackChassis to chassisnHeavy insertion loss,P/N skew,impedance discontinuity FPGA/ASICLRCopper CableCopper trace/cableLRTXRXTXRXFPGA/ASICCopper trace/cable7.5:A

238、 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference5 of 43MotivationSource:OIF-FD-CEI-224G7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE

239、 International Solid-State Circuits Conference6 of 43MotivationSource:OIF-FD-CEI-224GnChallenging to find an LR scheme with low power,high density and low latency7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State C

240、ircuits Conference7 of 43MotivationnDSP-based differential signaling LR schemes are powerful and robust but come with heavy power and hardware overheadnA promising cost-efficient scheme is a low-power XSR/VSR SerDes or retimer+single-ended transceiver front-end,supporting high-density,high-equalizat

241、ion-efficiency,and low-latency LR linksDifferential Transmission LineTXSingle-Ended Transmission LineTransceiver Front-EndXSR/VSRSerDesLane-0Lane-NTXProposed SchemeLane-0Lane-NLane-0Lane-NConventional SchemeXSR/VSRSerDesLRSerDesLRSerDesLane-0Lane-NRXDSP-based7.5:A 224Gb/s/wire Single-Ended PAM-4 Tra

242、nsceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference8 of 43Outlinen Motivationn Overall Architecturen Transmitter Front-Endn Receiver Front-Endn Measurement Resultsn Conclusion7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End w

243、ith 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference9 of 43Overall Architecturen4-lane DC-coupled SE analog TRX front-end supporting 4x224 Gb/s50 ccccOUTI2C&BiasFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC CoupledZ=90 cccccccc+-+-+-+-TXHF&MFLFccc

244、cccccccccccccccccccccS2D ConverterFeedforward CTLE90OBccccVGAINREGCMFB0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&BiasREG+-+-50 X4INPINNOUTPOUTN7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits

245、Conference10 of 43Overall Architecturen90 differential termination to match 90 differential channel in favor of better insertion loss and return loss OIF-FD-CEI-224G-01.050 ccccOUTI2C&BiasFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC CoupledZ=90 cccccccc+-+-+-+-TXHF&MFLFccccccccccccccccccc

246、cccccS2D ConverterFeedforward CTLE90OBccccVGAINREGCMFB0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&BiasREG+-+-50 INPINNOUTPOUTN7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference11 of 43

247、Overall Architecture50 ccccOUTI2C&BiasFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC CoupledZ=90 cccccccc+-+-+-+-TXHF&MFLFccccccccccccccccccccccccS2D ConverterFeedforward CTLE90OBccccVGAINREGCMFB0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&BiasREG+-+-50 INPINNOUTPOUTNnDC-couped D2S

248、-S2D conversion avoids the use of on-chip/off-chip DC block,supporting for high-density applications7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference12 of 43Overall Architecture50 ccccOUTI2C&Bi

249、asFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC CoupledZ=90 cccccccc+-+-+-+-TXHF&MFLFccccccccccccccccccccccccS2D ConverterFeedforward CTLE90OBccccVGAINREGCMFB0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&BiasREG+-+-50 INPINNOUTPOUTNnTX compensates 2/3 IL7.5:A 224Gb/s/wire Single-En

250、ded PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference13 of 43Overall Architecture50 ccccOUTI2C&BiasFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC CoupledZ=90 cccccccc+-+-+-+-TXHF&MFLFccccccccccccccccccccccccS2D Conve

251、rterFeedforward CTLE90OBccccVGAINREGCMFB0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&BiasREG+-+-50 INPINNOUTPOUTNnMost amplification is performed by RX due to the swing and linearity limitation of SE TX output7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization

252、 for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference14 of 43Outlinen Motivationn Overall Architecturen Transmitter Front-Endn Receiver Front-Endn Measurement Resultsn Conclusion7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE

253、2024 IEEE International Solid-State Circuits Conference15 of 43Transmitter Front-EndnAttenuator-based 90 termination nFeedforward full-band(LF/MF/HF)pre-emphasis amplifiernGroup delay and bandwidth optimized D2S driver50 ccccOUTINPINNI2C&BiasFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC Co

254、upledZ=90 cccccccc+-+-+-+-TXHF&MFLFREG+-+-7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference16 of 43Transmitter Front-EndnAttenuator-based 90 termination nFeedforward full-band(LF/MF/HF)pre-emph

255、asis amplifiernGroup delay and bandwidth optimized D2S driver50 ccccOUTINPINNI2C&BiasFeedforward Pre-EmphasisD2S DriverODTccReplica 50 REGDC CoupledZ=90 cccccccc+-+-+-+-TXHF&MFLFREG+-+-7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE Inte

256、rnational Solid-State Circuits Conference17 of 43D2S DrivernReplica Rterm_RX supports DC coupling to RX nThe regulator is employed to avoid power noise coupling to the single-ended TX output24mAReplica 50RC Network6mA6mA6mA6mA from RXREGGDGDGDINOUTBW Extension&Gain Control7.5:A 224Gb/s/wire Single-E

257、nded PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference18 of 43D2S DrivernReplica Rterm_RX supports DC coupling to RX nThe regulator is employed to avoid power noise coupling to the single-ended TX outputnShunt peaking and emi

258、tter degeneration are used for bandwidth enhancement24mAReplica 50RC Network6mA6mA6mA6mA from RXREGGDGDGDINOUTBW Extension&Gain Control7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference19 of 43D

259、2S DrivernReplica Rterm_RX supports DC coupling to RX nThe regulator is employed to avoid power noise coupling to the single-ended TX outputnShunt peaking and emitter degeneration are used for bandwidth enhancementnRC network with output loading provides a falling GD,achieving GDV mitigation with ri

260、sing GD of peaking enhanced driver,thus indicating a better eye height and eye width24mAReplica 50RC Network6mA6mA6mA6mA from RXREGGDGDGDINOUTBW Extension&Gain Control7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-St

261、ate Circuits Conference20 of 43D2S Driver204060801.52.02.53.03.5Group delay(ps)Freq(GHz)w/o RC network w/RC networkGDV=0.54psGDV=1.23ps020406080-12-10-8-6-4-2Gain(dB)Freq(GHz)w/RC network w/o RC networkf-3dB=60GHzf-3dB=69GHz0D2S Gain ResponseD2S GD Response Bessel2.832.762.90W/o RC NetworkButterwort

262、h 2.832.742.92ttV0.3UI0.13Vpp0.4UI0.34UI0.37UI0.4UI0.38UI0.13Vpp0.15Vpp0.18Vpp0.2Vpp0.17Vpp224Gb/s D2S Eye DiagramsW/RC Network24mAReplica 50RC Network6mA6mA6mA6mA from RXREGGDGDGDINOUTBW Extension&Gain Control7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800

263、GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference21 of 43Outlinen Motivationn Overall Architecturen Transmitter Front-Endn Receiver Front-Endn Measurement Resultsn Conclusion7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEE

264、E International Solid-State Circuits Conference22 of 43ccccccccccccccccccccccccS2D ConverterFeedforward CTLE90OBccccVGAINOUTPOUTNREGgmCMFB0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&Bias50 Receiver Front-EndnPower noise compression techniquesnCascade feedforward full-band(LF/MF/HF)equalize

265、rs with shunt and series peakingnA degeneration-based high-linearity VGA to adjust the swing for different equalization values7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference23 of 43Receiver F

266、ront-EndnPower noise compression techniquesnCascade feedforward full-band(LF/MF/HF)equalizers with shunt and series peakingnA degeneration-based high-linearity VGA to adjust the swing for different equalization valuesccccccccccccccccccccccccS2D ConverterFeedforward CTLE90OBccccVGAINOUTPOUTNREGgmCMFB

267、0dBDegeneration+-+-+-+-+-+-+-+-+-+-ccRX HF LF MFHFI2C&Bias50 7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference24 of 43S2D ConverternPseudo-differential stage with LCB features a high CMRR,indic

268、ating a decent choice of S2D amplifiernCooperated with asymmetric inductors,GD and gain mismatch is significantly eliminated204060800-1.0-0.50.00.51.01.52.0 GD mismatch w/LCB&Asym.IND GD mismatch w/o LCB&Asym.INDFreq(GHz)Gain(dB)Gain mismatch w/LCB&Asym.INDGain mismatch w/o LCB&Asym.IND-4-20Group de

269、lay(ps)Simulated S2D Gain&GD ResponseL1L2VOPVONAsym.Inductor:L2 L1 RTermVINIBPBC:Power Bounce CancellerCMFBEAREGREGREGLCB:Low-capacitance BiasingVOPVONReplica 507.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Ci

270、rcuits Conference25 of 43S2D ConverternRegulators and replica 50 support a high PSRRnCMFB is required to avoid the eye lean issue caused by the DC offset101000-70-60-50-40-30-20PSRR(dB)Freq(GHz)w/replica 50 w/o replica 507dB56GHzSimulated S2D PSRRW/DC offsetW/o DC offsetL1L2VOPVONAsym.Inductor:L2 L1

271、 RTermVINIBPBC:Power Bounce CancellerCMFBEAREGREGREGLCB:Low-capacitance BiasingVOPVONReplica 507.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference26 of 43S2D ConverternPBC is employed to support

272、the bounce elimination caused by the single-ended signalnLPF and UGOP are employed to generate a reference voltage for PBC11020-35-30-25-20-15Sss11(dB)Freq(GHz)w/o PBC w/PBC0.30.40.50.60.71E-121E-101E-81E-61E-4BERSample(UI)w/o PBC w/PBC3dB2GHz0.17UI0.19UI12%improvementMeasured TRX 112Gb/s NRZ BERMea

273、sured RX Sss11L1L2VOPVONAsym.Inductor:L2 L1 RTermVINIBPBC:Power Bounce CancellerCMFBEAREGREGREGLCB:Low-capacitance BiasingVOPVONReplica 507.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference27 of

274、43High-speed equalizernThe feedforward CTLE topology supports moving the large-area LF path away from the critical HF part in the layout,ensuring the HF equalization up to 56GHznWell-modelled on-chip wiring inductor is used to resonate with the dominant capacitance in the IN/OUT nodeINHFAuxiliaryLF

275、PathOUTCritical Non-critical IND.IND.Non-dominant Cap.Dominant cap.Dominant cap.Inductive output impedanceIsolationCompact core7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference28 of 43Outlinen

276、Motivationn Overall Architecturen Transmitter Front-Endn Receiver Front-Endn Measurement Resultsn Conclusion7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference29 of 43Measurement Setup Probe Stat

277、ionKeysight 8050APCTX DUTDC PowerDC PowerProbe StationKeysight 1046AKeysight M5247B&N5292ARX DUTTX SideRX Side7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference30 of 43Measurement SetupKeysight

278、M8050AKeysight M1046AEvaluation BoardDC Power6V6V6VEvaluation BoardTXRXPCILDUTDUTTX-sideRX-sideSGSGSGGSGSGSDC Power6V6V6VILPGHead2-4m Coaxial CableKeysight M5247B&N5292ADe-embeddedDe-embedded7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEE

279、E International Solid-State Circuits Conference31 of 43Transceiver Front-End Die photosD2S DRV48.2%Pre-emphasis38.5%Others13.3%VGA19.1%CTLE35.8%S2D26.8%OB12.7%Others 5.6%3.2mm3.2mm0.76mm0.84mmTXRXLane0Lane1Lane2Lane3Lane0Lane1Lane2Lane3I2CI2CTotal Power:154mWPower Efficiency:0.69pJ/bTotal Power:312m

280、WPower Efficiency:1.39pJ/bREGREG0.45mm0.3mm0.3mm0.6mmD2SPEODTD2SPEODTD2SPEODTD2SPEODTS2DCTLEVGAOBS2DCTLEVGAOBS2DCTLEVGAOBS2DCTLEVGAOBTXRXnFabricated in SiGe 130nm technology7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International So

281、lid-State Circuits Conference32 of 43Measurement ResultsnS-parameters of TRX with channel 1(-16 dB loss at 56 GHz),channel 2 (-22 dB loss at 56GHz),and channel 3(-29 dB loss at 56 GHz)020406080-40-30-20-100S-parameters(dB)Freq(GHz)16dB-loss channel 22dB-loss channel 29dB-loss channel020406080-20-15-

282、10-50S-parameters(dB)Freq(GHz)TRX w/16dB IL TRX w/22dB IL TRX w/29dB ILf-3dB=68GHzf-3dB=63GHzf-3dB=65GHz7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference33 of 43Measurement ResultsnEye diagrams

283、 of TRX with channel 1-3(IL before TX input and RX output is de-embedded)W/8-tap FFEW/8-tap FFEW/8-tap FFEW/29dB IL56GHz40mV1.49 psPRBS-15 112Gb/s NRZW/22dB IL56GHz40mV1.49 psPRBS-15 112Gb/s NRZW/16dB IL56GHz40mV1.49 psPRBS-15 112Gb/s NRZ7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End wi

284、th 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference34 of 43Measurement ResultsnFor PAM-4 case,8-tap scope FFE is used to cope with the uneven frequency responseW/8-tap FFEW/8-tap FFEW/8-tap FFEW/29dB IL56GHzPRBS-15 224Gb/s PAM430mV1.49 psW/22dB IL56GHzw/8-t

285、ap scope FFEW/16dB IL56GHzPRBS-15 224Gb/s PAM450mV1.49 psw/8-tap scope FFEPRBS-15 224Gb/s PAM440mV1.49 psw/8-tap scope FFEPRBS-15 224Gb/s PAM4PRBS-15 224Gb/s PAM4PRBS-15 224Gb/s PAM430mV1.49 ps50mV1.49 ps40mV1.49 ps16dB29dBEqualizer linearity limitationEqualization capacity limitationGood range7.5:A

286、 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference35 of 43Measurement ResultsnBER of TRX with channel 1-3(IL before TX input and RX output is de-embedded)0.30.40.50.60.71E-121E-101E-81E-61E-40.011BER

287、Sample(UI)112Gb/s NRZ w/16dB IL 112Gb/s NRZ w/22dB IL 112Gb/s NRZ w/29dB IL0.30.40.50.60.71E-121E-101E-81E-61E-40.011BERSample(UI)224Gb/s PAM4 w/16dB IL&FFE 224Gb/s PAM4 w/22dB IL&FFE 224Gb/s PAM4 w/29dB IL&FFEW/8-tap FFE7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalizat

288、ion for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference36 of 43Measurement ResultsnEye diagrams and BER of RX with/without LF&MF EQ at a loss of 16 dB PRBS-15 112Gb/s NRZW/LF&MF EQ60mV1.49 psPRBS-15 112Gb/s NRZW/o LF&MF EQ60mV1.49 ps0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91E-121E-10

289、1E-081E-061E-041E-021E+00Sample(UI)BER w/LF&MF EQ w/o LF&MF EQ7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference37 of 43Measurement ResultsnFEXT of TX/RX -35dB0204060 67-80-70-60-50-40-30FEXT(dB

290、)Freq(GHz)TX FEXT RX FEXT7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference38 of 43Approximative LR scenario nAn approximative LR scenario using the proposed transceiver front-end incorporated w

291、ith DSP algorithmsSignalGeneratorTXRXDFE35dB-loss Channel DSP AlgorithmBER Test224Gb/sPAM4FFE Vol MLSEp DSP algorithms:FFE:Feed Forward Equalization DFE:Decision Feedback Equalization Vol:Volterra MLSE:Maximum Likelihood Sequency Estimation7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End

292、with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference39 of 43Simulated ResultsnSimulated BER using measured waveform date with DSP algorithms ABCD1E-131E-121E-111E-41E-31E-2BERTRX with 35dB-loss ChannelFFE MLSEBBER TestAVol MLSECDFE MLSEDBER TestBER TestBER

293、 TestMeasuredWaveform Date7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference40 of 43Outlinen Motivationn Overall Architecturen Transmitter Front-Endn Receiver Front-Endn Measurement Resultsn Con

294、clusion7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference41 of 43ConclusionISSCC 2021ISSCC 2023JSSC2023ISSCC 2021ISSCC 2022This workTechnologyFinFET7nmFinFET4nmFinFET5nmFinFET7nmFinFET5nmSiGe 13

295、0nmSignalingSESESEDiff.Diff.SEDate Rate(Gb/s/wire)403250.46112224Loss(dB)Nyquist820GHz416GHZ5.425.2GHz728GHz1856GHz*2956GHzArchitectureAnalogAnalogAnalogAnalog+DigitalAnalog+DigitalAnalogModulationNRZNRZNRZPAM-4PAM-4PAM-4ApplicationMCMInterposerInterposerMCMCable+PCBCableEqualizationCTLEDFENACTLE+FF

296、ECTLE+FFECTLEActive Area Per Lane(mm2)0.661.40.003*0.167*0.34*0.315Power Efficiency(pJ/bit)1.70.440.2971.49*1.41*2.08FoM=Power Eff./Loss(pJ/bit/dB)0.210.110.0550.210.80.07*Analog only,exclude DSP*RX only,exclude DSP*Estimated from chip micrograph7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Fron

297、t-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference42 of 43ConclusionnAn analog single-ended transceiver front-end supporting 224Gb/s per lane is presented lIt features S2D and D2S conversion,power-efficient analog equalizers,and VGAlIt can compensa

298、te a maximum 29dB56GHz channel losslIt consumes 466mW and occupies 0.315mm2 per lane in 130nm SiGe technologylIt supports 800G/1.6Tbps throughput over 4/8 lanes at 224GbpslIt indicates the proposed long-reach scheme is promising according to the simulated results of an approximative LR scenario with

299、 DSP algorithms7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE International Solid-State Circuits Conference43 of 43Thank You!7.5:A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE 2024 IEEE

300、International Solid-State Circuits Conference44 of 43Please Scan to Rate This Paper7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference1 of 37A 112Gb/s/pin Single-Ended Crosstalk-Cancellatio

301、n Transceiver with 31dB Loss Compensation in 28nm CMOSLiping Zhong,Hongzhi Wu,Yangyi Zhang,Xuxu Cheng,Weitao Wu,Catherine Wang,Xiongshi Luo,Taiyang Fan,Dongfan Xu,Quan PanSouthern University of Science and Technology,Shenzhen,China7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver wit

302、h 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference2 of 37Outlinen Motivationn TransmitterlArchitecturelReconfigurable crosstalk-cancellation(XTC)n ReceiverlArchitecturelMismatch-mitigation Gm-TIA S2Dl4-tap FFE with multiphase clock techniquen Measurement Re

303、sultsn Conclusions7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference3 of 37Outlinen Motivationn TransmitterlArchitecturelReconfigurable crosstalk-cancellation(XTC)n ReceiverlArchitecturelM

304、ismatch-mitigation Gm-TIA S2Dl4-tap FFE with multiphase clock techniquen Measurement Resultsn Conclusions7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference4 of 37Trendsn Per-lane data rate

305、 has doubled every 3-4 yearsn More stringent requirements are placed on passive partsn Power-hungry DSP solutions not suitable for VSR/MR applicationsSource:ISSCC Wireline Trends 20227.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE

306、International Solid-State Circuits Conference5 of 37Single-ended Schemen It halves the links bandwidth requirementn It doubles the data throughput and pin utilization efficiencyData rate=224 Gb/s/Diff.pinTotal throughput:448 Gwith CrosstalkDieCH1CH4d112 Gb/s112 Gb/sConventional LinksSE MIMO LinksBW=

307、40 GHz(Cables,Connectors,Packages)BW=40 GHz(Cables,Connectors,Packages)Data rate=112 Gb/s/Diff.pinTotal throughput:224 Gw/o Crosstalks=8 mil,d=40 mils=8 mil,d=40 milsPin Efficiency:1Pin Efficiency:0.5DieCH1CH2sd112 Gb/s112 Gb/sCH2112 Gb/sCH3112 Gb/sVIN1VIN2VIN3VIN4VIN1VIN2Source:ISSCC Wireline Trend

308、s 20227.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference6 of 37Single-ended Schemen Single-ended links exhibit heavy crosstalk noise,particularly for the backplane scenarios with connector

309、sn Single-ended circuits suffer from more noise(CM,SSN)SerDesTXSerDesRXConnectorConnectorCrosstalkMicrostrip-lineStrip-lineSerDesTXSerDesRXConnectorConnectorCrosstalkMicrostrip-lineStrip-lineCable7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CM

310、OS 2024 IEEE International Solid-State Circuits Conference7 of 37Outlinen Motivationn TransmitterlArchitecturelReconfigurable crosstalk-cancellation(XTC)n ReceiverlArchitecturelMismatch-mitigation Gm-TIA S2Dl4-tap FFE with multiphase clock techniquen Measurement Resultsn Conclusions7.6:A 112Gb/s/pin

311、 Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference8 of 37Transmitter Architecturen Quarter-rate mixed-signal architecturen On-chip pattern programmer+mode&polarity switch for reconfigurable XTC(light cross

312、talk)n 4-tap FFE+pseudo-differential CML driver+-RetimerFFEGenerator8:4 MUXPulseGeneratorOn-chip Pattern ProgrammerDIV2DCC&QECModeSwitch4:1 MUX&DRV.X4X2Data Path+-S2DDIV2VCDLMSBLSBOn-chip Lane-0Clock PathCKINCKIPRtermRtermRtermRterm48T-coilT-coilRdummy44228On-chip Lane-1VCDL4TXOUT7.6:A 112Gb/s/pin S

313、ingle-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference9 of 37Scheme of Reconfigurable XTCn XTC signal is generated at the low-speed node for low costn Reconfigurable XTC is controlled by polarity control switchX

314、4Data PathSwitchData Signal(Lane-0)Data Signal(Lane-0)Data Signal(Lane-1)Data Singal(Lane-1)8:4Re-timerData PathLane-0Lane-1VCDLCK4_IN4On-chip Pattern ProgrammerMSBLSBDataXTDataXT4:1 MUX&DRV.44XTC_Main Path OUTXTC_Post Path DIVCK_DataCK_XTC_PCK_XTC_MT Tuning Range:0-9psData SingalXTC SingalOutput Si

315、gnal2PolarityControl7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference10 of 37Scheme of Reconfigurable XTCn TX-FIR technique is employed for XTCX4Data PathSwitchData Signal(Lane-0)Data Sig

316、nal(Lane-0)Data Signal(Lane-1)Data Singal(Lane-1)8:4Re-timerData PathLane-0Lane-1VCDLCK4_IN4On-chip Pattern ProgrammerMSBLSBDataXTDataXT4:1 MUX&DRV.44XTC_Main Path OUTXTC_Post Path DIVCK_DataCK_XTC_PCK_XTC_MT Tuning Range:0-9psData SingalXTC SingalOutput Signal2PolarityControlData_Main OUTXTC_Post O

317、UTXTC_Main OUTXTC OUT TX OUT TTTTTTEven ModeXTC Superposition Mode XTCOdd ModeXTC Examples of inductive XTC,implement capacitive XTC by controlling signal polarityTiming Diagram7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE Intern

318、ational Solid-State Circuits Conference11 of 37Outlinen Motivationn TransmitterlArchitecturelReconfigurable crosstalk-cancellation(XTC)n ReceiverlArchitecturelMismatch-mitigation Gm-TIA S2Dl4-tap FFE with multiphase clock techniquen Measurement Resultsn Conclusions7.6:A 112Gb/s/pin Single-Ended Cros

319、stalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference12 of 37Receiver Architecturen Quarter-rate mixed-signal architecture for low powern MIMO-XTC scheme for XTC(heavy crosstalk)n Mismatch-mitigation Gm-TIA S2D for low noise a

320、nd low mismatchn 4-tap RX-FFE with multiphase clock technique for high-speed422VREFPRBSChecker&ControlVINVIPVINVIPS/H1-1 2 RZ-to-NRZ&DecoderI-Path QQBIBRterm+-CTLE+-VGA+-XTC+-S2D4-tap S/H RX-FFEFrom Lane-1DIV2DCC&QECDIV2VCDL44VCDLDCC&QEC888On-chip Lane-0CKINOUTClock PathAFE4 To Pre-tapVCDL4CK4CK4_De

321、layOBSEL.SEL.CK8CKIP2RtermRtermOn-chip Lane-1RXIN+-S2DAggressor Signal HPFLPFData Signal DMUXDeserializer7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference13 of 37Conventional S2D CML S2Dn

322、 Gain and phase mismatchn Limited BWn High PSRRVbVDDVinVonVop7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference14 of 37Conventional S2D CML S2DInverter-based S2Dn Gain and phase mismatchn

323、Limited BWn High PSRRn Phase mismatchn High BWn Low PSRRVDDVinVopVonVbVDDVinVonVop7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference15 of 37Proposed Mismatch-mitigation Gm-TIA S2D(1/2)n Lo

324、w Gain mismatch Low Freq.n Moderate BWn High PSRRConventionalOptimizedVbVinVoutpVoutnVbVinWeak PathStrong PathStrong PathWeak Path+-TIA+-GmLow-Mismatch Gm-TIA S2D1ISS1ISS1:1M7M8M2M1M5M6M3M4GainVo+Vo-GainVo+Vo-Vo-Vo+7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Comp

325、ensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference16 of 37Proposed Mismatch-mitigation Gm-TIA S2D(2/2)n Low Gain mismatch LF&HFn High BWn High PSRRProposedOptimizedVbVinVoutpVoutnVbVin+-TIA+-GmLow-Mismatch Gm-TIA S2D1ISS1ISS1:1M7M8M2M1M5M6M3M4R1R2GainVo+Vo-GainVo+Vo-Vo-Vo+

326、7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference17 of 37Comparison with Conventional S2Ds CML S2DInverter-based S2DSimulated Gain and Phase Mismatch Performance Proposed Gm-TIA S2D020406

327、0-15-10-50 Von VopFrequence(GHz)Amplitude(dB)05101520 Group Delay(ps)0.1dB Mismatch(060GHz)0.5ps at 28GHz0204060-15-10-50 Von VopFrequence(GHz)Amplitude(dB)05101520 Group Delay(ps)3dB DC Mismatch2dB HF Mismatch(wo/DC)1.3ps at 28GHz0204060-20-15-10-50 Von VopFrequence(GHz)Amplitude(dB)05101520 Group

328、Delay(ps)0.7dB DC Mismatch0.2dB HF Mismatch2.5ps at 28GHz7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference18 of 37Comparison with Conventional S2Ds CML S2DInverter-based S2DSimulated Powe

329、r Supply rejection Ratio PerformanceProposed Gm-TIA S2D 43dB(080GHz)28dB(080GHz)45dB(080GHz)020406080-60-55-50-45-40-35-30-25PSRR(dB)Frequency(GHz)INV.S2D 020406080-60-55-50-45-40-35-30-25PSRR(dB)Frequency(GHz)CML S2D 020406080-65-60-55-50-45-40-35-30-25-20PSRR(dB)Frequency(GHz)Proposed S2D7.6:A 112

330、Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference19 of 374-tap FFE with Multi-Phase Clock technique(1/5)nCKQ&CKQB in passive S/H introduce an additional 1-UI hold timenThis design enables at most

331、3 tap RX-FFEH.Li,et.al,ISSCC,2021hphnVBVBVipCKICKIBDCKQBCKQBCKQCKQVoutnVoutpCKIBConventional FFEVaopVaonVponVpop FFE tapsActive S/HSummerPassive S/HVinD-1D0D1D2D3CKICKQCKIBCKQBCKIBDVao-IVpo-IVpo-QVout-ICKQBDCKIDCKQDVpo-IBVpo-QBD4h0Vao-Qh-1h1h-1h27.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation

332、Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference20 of 374-tap FFE with Multi-Phase Clock technique(2/5)n CKQBD&CKQD further increase the hold timen Post-tap2(h2)data error and ISI occur in the summer nodeD-1D0D1D2D3CKICKQBCKIBCKQCKIBDCKQBDC

333、KIDCKQDD4h0h-1h1h2h-1ErrorVao-IVpo-IVpo-QVout-IVpo-IBVpo-QBVao-QhphnVBVBVipCKICKIBDCKQBDCKQBDCKQDCKIVoutnVoutpCKQImprove FFEVaopVaonVponVpop FFE tapsActive S/HSummerPassive S/HVin7.6:A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference21 of 374-tap FFE with Multi-Phase Clock technique(3/5)nCKQ