SESSION 26 Wireless Transmitters and Front-Ends.pdf

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1、ISSCC 2025SESSION 26Wireless Transmitters and Front-Ends26.1:A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOS 2025 IEEE International Solid-State Circuits Conference1 of 36A 24 GHz Direct Digital Transmitter Using Mu

2、ltiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOSSoumya Mahapatra1,Mostafa Ayesh1,Ce Yang1,Mayank Palaria1,Shiyu Su1,2,Aoyang Zhang3and Mike Shuo-Wei Chen11University of Southern California,Los Angeles,CA2University of Waterloo,Waterloo,Canada3Tsinghua Univers

3、ity,Beijing,China26.1:A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOS 2025 IEEE International Solid-State Circuits Conference2 of 36Outline Motivation Proposed Multiphase SHS TXBandwidth and Efficiency EnhancementPh

4、ase-shifted SH LO DividerIntegration with Dual-rate Hybrid DAC System ImplementationMultiphase SHS LO GenerationRF Power-DAC and Matching Network Measurement Results Conclusion26.1:A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM

5、 in 65nm CMOS 2025 IEEE International Solid-State Circuits Conference3 of 36Challenges in High-Performance TXModern wireless systems demand TX capable of high data rates,high efficiency and high linearity(or low EVM)Existing TXarchitecturesIdealTX architectureTrade-offEnvelopeEfficiency(%)Data Rate(

6、Gb/s)Data Rate(Gb/s)EVM(dB)Existing TXarchitecturesIdealTX architectureTrade-offEnvelope26.1:A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOS 2025 IEEE International Solid-State Circuits Conference4 of 36Existing TX

7、Architectures-IDigital Polar TransmitterDigital Quadrature Transmitter High PA efficiency No IQ sum loss Low data rate BW expansion Poor linearity/EVM Low PA efficiency 3dB IQ sum loss High data rate No BW expansion Moderate linearity/EVM90 180 270 0 ABBBBCORDICPhase ModulatorIBBQBBDAC+PALOTXO/P 0-3

8、60 LOQuad GenQBBTXO/PCh.ICh.QIQDAC+PAIBB26.1:A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOS 2025 IEEE International Solid-State Circuits Conference5 of 36Existing TX Architectures-IIDigital Multiphase TransmitterAn

9、alog Quadrature Transmitter Medium to high PA efficiency High data rate Moderate linearity/EVM Low PA efficiency High data rate Better linearity/EVMYuan,JSSC 17IBBQuad GenI-DACQ-DACLOTXO/PIQI-MixerQ-MixerQBBPA90 180 270 0 315 225 135 45 MPGenTXO/PCh.BCh.AIBBMP Dec.QBBMP Dec.ABDAC+PALO26.1:A 24GHz Di

10、rect Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOS 2025 IEEE International Solid-State Circuits Conference6 of 36TX Benchmarks across ArchitecturesState-of-the-art PA/TX published in ISSCC,JSSC,VLSI(2015-2024)00.511.522.53Data R

11、ate(Gb/s)5101520253035Average PAE(%)Average PAE vs.Data RateDigital PolarDigital QuadratureDigital MultiphaseAnalog Quadrature?mm-Wave(20GHz)RF(20GHz)RF(20.3%Data Rate1.2-3.2 Gb/sEVM3Gb/s),high average efficiency(20%)and low in-band EVM(1)InterpolatorPolyphaseFilterIBB/QBBfs=M*fBB=fLO/2EncoderfLO/2I

12、up/QupDfLO=2*fs=2M*fBBWideband DPAfLO3fLO/2PowerDesired Signal2*fLOFreq.DOutput ReplicasSinc FunctionA single DPA for wideband coverageStill need high-speed digital processingfLO/2Conventional Polyphase ArchitectureLLJ J Polyphase architecture to better enhance the sampling rate to fs=fLO/2 Sampling

13、 replicas are pushed farther away,but still appear at fLO+n*fLO/2 High-speed digital processing results in high power consumption and difficulty in physical implementation 2025 IEEE International Solid-State Circuits Conference9 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint

14、-Digital-Analog Interpolation and Filtering in 28nm CMOSProposed Wideband Replicas-Rejection DTX(2/2)Proposed Wideband DTX Using Joint-Digital-Analog Interpolation and FilteringfBBPolyphaseFilterIBB/QBBEncoderDelay IntegrationCLK fBBfs=M*fBB=fLO/2Proposed Polyphase ArchitectureEncoderEfLO/2Iup/QupfL

15、O/2fLO/2fLO=2*fsAnalog Interpolation Wideband DPAfLO3fLO/2PowerDesired Signal2*fLOFreq.EAnalog Interpolation&FilteringReplicas-Free Solution!Effectively reduced digital frequencyHybrid digital-analog replicas rejectionJ J J J Optimized polyphase architecture:low speed for high-frequency sampling Joi

16、nt digital-analog interpolation and filtering:effective suppression of sampling replicas Analog interpolation wideband DPA:single channel for wideband coverage 2025 IEEE International Solid-State Circuits Conference10 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-An

17、alog Interpolation and Filtering in 28nm CMOS Background Proposed Joint-Digital-Analog Replicas-Rejection Digital Transmitter Implementation Details Measurement Results ConclusionsOutline 2025 IEEE International Solid-State Circuits Conference11 of 3426.2:A Wideband Replicas-Rejection Digital Transm

18、itter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSProposed Digital Polyphase Interpolation Filter(1/3)P0(z4)P1(z4)P2(z4)z-1P3(z4)z-1z-1+x(n)y(m)Lower speed operation:Reduce power consumptionImprove circuit realizabilityH(zM)Mx(n)y(m)v2(m)P0(z4)P1(z4)P2(z4)P3(z4)z-1z-1z-14444x(

19、n)fLO/8y(m)fLO/2P0(z)P1(z)P2(z)P3(z)z-1z-1z-14444x(n)fLO/8y(m)fLO/2CLK fLO/2CLKfLO/8CLK fLO/2H(z)Mx(n)y(m)v1(n)Optimization:swap the order of interpolation and filteringFiltering then InterpolationInterpolation then FilteringTransposeSwap order 2025 IEEE International Solid-State Circuits Conference

20、12 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSProposed Digital Polyphase Interpolation Filter(2/3)P0(z)P1(z)P2(z)P3(z)x(n)fLO/8z-3z-2z-1+y(m)Delay Freq.=fLO/2fLO/2S5S1S2S3S4A1C1C2C3C4SummingS6S7y(m)A2A3A4B1B2B3B4P0(z

21、)P1(z)P2(z)P3(z)z-1z-1z-14444x(n)fLO/8y(m)fLO/2CLKfLO/8CLK fLO/2 Timing difference of 1/(fLO/2)Summing to increase data rate No extra fitting circuitsDelay IntegrationSimplify structure&Reduce power consumption 2025 IEEE International Solid-State Circuits Conference13 of 3426.2:A Wideband Replicas-R

22、ejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSProposed Digital Polyphase Interpolation Filter(3/3)806040200-20-40-60-80-100-600-400-2000200400600Power(dBm)Frequency(MHz)Effective filtering of sampling replicasBW:160MHzfs:320MHz 2000150010005000-500-1

23、000-1500-20003.43.453.53.553.63.6510-5DataTime(s)InputOutput 4x digital interpolation High fitting accuracyOutput Spectrum Sim.Time-Domain Sim.60dBc 2025 IEEE International Solid-State Circuits Conference14 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interp

24、olation and Filtering in 28nm CMOSAnalog Linear Interpolation&Filtering(1/4)fLO3fLO/2PowerDesired Signal2*fLOFreq.Output ReplicasSinc FunctionfLO3fLO/2PowerDesired Signal2*fLOFreq.Analog Interpolation&FilteringReplicas-Free Solution!DFFDFFIDelay_ICLK fLOI_OUTDPABB Output Signal:IupfLO/2Analog Linear

25、 Interpolation Architecture2-stage triggerAlignmentDelaySynthesisConventional DPAAnalog interpolation DPACLK fLOI fLO/2Delay_II_OUT fLOData rate increases&signal interpolationdelay then add 2025 IEEE International Solid-State Circuits Conference15 of 3426.2:A Wideband Replicas-Rejection Digital Tran

26、smitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSAnalog Linear Interpolation&Filtering(2/4)DFFDFFIDelay_ICLK fLOI_OUTDPABB Output Signal:IupfLO/2DataTimeD1D2D3D4D52/fLODataTimeD1D2D3D4D5b1b2b3b41/fLOAnalog Linear Interpolation Architecture2-stage triggerAlignmentDelaySynthe

27、sisConventional DPAAnalog Interpolation DPACLK fLOI fLO/2Delay_II_OUT fLOData rate increases&signal interpolationdelay then addinterpolation&power synthesis 2025 IEEE International Solid-State Circuits Conference16 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analo

28、g Interpolation and Filtering in 28nm CMOSAnalog Linear Interpolation&Filtering(3/4)BW(MHz)10204080160fs(MHz)160160160320640r=fs/fBW168444Interpolation Factor88842 If only analog linear InterpolationFrequencyfsAmplitude(dBm)0-10-20-30-40-50-60-7001234567810MHz 820MHz 840MHz 880MHz 4160MHz 2Nearest r

29、eplicas rejectionReplicas Rejection(dBc)20dBcThe smaller r value&the larger BW,the worse replicas rejectionIf only analog linear interpolation,replicas rejection for high BW does not meet the mask requirements!Analog filters are needed to associate with the analog interpolation to further suppress t

30、he replicas for wideband application 2025 IEEE International Solid-State Circuits Conference17 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSAnalog Linear Interpolation&Filtering(4/4)z-3z-2p0p1p2p3y(k)fLO/2z-1z-1K1K2K3O

31、utinK1=K3z-1z-1z-1fLO/2fLOFilter for Analog InterpolationDelay IntegrationPre-filter806040200-20-40-60-80-100-1-0.5010.5Power(dBm)Frequency(GHz)Original coefficientsModified coefficientsAcceptable slight deteriorationOriginalModifiedSim.Spectrum after FilteringFreq.Normalized to fLO/20.20.40.60.80-2

32、00-40-60Normalized Gain(dB)OriginalK1=K3=0.25K2=0.5Filter ResponseModified1Coefficient OptimizationSimple shifts lower cost!How to realize analog filter for analog interpolation?Difficult in the analog domain due to accuracy limitation&complexity Advance to digital domain due to flexibility&low cost

33、How to optimize in digital domain?K1=K3=0.25&K2=0.5:simple shift operations Acceptable slight deterioration in exchange for significant reduction in cost and complexity 2025 IEEE International Solid-State Circuits Conference18 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-D

34、igital-Analog Interpolation and Filtering in 28nm CMOSAnalog Linear Interpolation DPA with Cell-Sharing Two quadrature identical half_DPAswith opposite clock to realize analog linear interpolationAnalog Linear Interpolation DPA 12-bit:6-bit MSB&6-bit LSB 8 hybrid groups&a binary group Hybrid group:7

35、 thermo-coded cells(T6-0)+3 binary cells(1 Bit5&2 Bit4)Wideband DPA with Dohertytechnique,cell-sharing and compact SCT for efficiency enhancementJ.Li,ISSCC 2023 2025 IEEE International Solid-State Circuits Conference19 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-A

36、nalog Interpolation and Filtering in 28nm CMOSOverall DTX ArchitectureZ-1P0(z)P1(z)P2(z)P3(z)Configurable Sampling Architecture4-phase ArchitectureGAIN_CTRLIBB/QBBSPI2S-to-PFIRFilterP0(z)P1(z)P2(z)P3(z)Z-1Z-1Delay IntegrationPre-FilterGain AdjustmentMUX/2/2/2fLO/2fLO/4fLO/8 UP_CTRLfLOK1K2Proposed DT

37、X Using Joint-Digital-Analog Interpolation and FilteringOn-ChipRFoutz-1z-1Analog Interpolation Quadrature DPA/22fLO4-phase LOs(4-phase)Digital Baseband Signal Processing(DBSP)Swapping the order of interpolation and filtering to reduce power consumption Analog interpolation techniques in DPA to furth

38、er suppress sampling replicas Wideband application:joint digital-analog interpolation and filtering techniques&wideband quadrature DPA 2025 IEEE International Solid-State Circuits Conference20 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Fi

39、ltering in 28nm CMOSDTX Floorplan with DBSP under XFMR Coils Q1+Q1-PA_OUTI1+I1-EncoderI1 Q1I2-I2+Q2-Q2+EncoderQ2 I2LOIPLOINLOQPLOQNLOsLOsLOsLOsDPA1DPA2DPA3DPA4Transformer Coils:M9&APGND Shielding:M7Digital Cells:M1-M6Ground shielding wires perpendicular to XFMR coils 90Digital baseband circuit under

40、 XFMR for compact area&better alignment 2025 IEEE International Solid-State Circuits Conference21 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOS Background Proposed Joint-Digital-Analog Replicas-Rejection Digital Transm

41、itter Implementation Details Measurement Results ConclusionsOutline 2025 IEEE International Solid-State Circuits Conference22 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSChip Photo&Measurement Setup 28nm CMOS technolo

42、gy Core area:0.88mm2 Power supplies:1.1V SE(system efficiency)=Pout/Pdc(all blocks)DTX PCBFPGARF Signal GeneratorPower SupplySpectrumanalyzer20dB AttenuatorSPI ConfigI/QUARTPCSPI ConfigI/Q180-deg CouplerRFOUTLONLOPFMC InterfaceFMC Interface 2025 IEEE International Solid-State Circuits Conference23 o

43、f 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSMeasured DTX CW Performance DTX peak output power and system efficiency vs frequency0510152025303540Peak System Efficiency(%)2.02.42.83.23.64.04.44.85.2101520253035404550 Pea

44、k System Efficiency Peak Output PowerFrequency(GHz)Peak Output Power(dBm)Peak Pout=27.8dBmPeak SE=30.4%2.6GHzPeak Pout=27.3dBmPeak SE=30.5%3.6GHz3dB RF BW:2.1-5.1GHzPeak Pout=24.8dBmPeak SE=14.9%5.1GHz 3dB RF BW：2.1-5.1GHz 27.8dBm,30.4%SE2.6GHz;27.3dBm,30.5%SE3.6GHz;24.8dBm,14.9%SE5.1GHz 2025 IEEE I

45、nternational Solid-State Circuits Conference24 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSMeasured DTX CW Performance Output power and SE contours in the first quadrant 2025 IEEE International Solid-State Circuits Co

46、nference25 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOS fLO=2.6GHz:AM-AM 0.4dB,AM-PM 32dB 2025 IEEE International Solid-State Circuits Conference27 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joi

47、nt-Digital-Analog Interpolation and Filtering in 28nm CMOSMeasured Wi-Fi 40MHz 64QAM 2.56GHz(2/2)Farout spectrum of WiFi 40MHz 2.56GHz3fLO/2 2fLO 5fLO/23fLO 7fLO/24fLO Sampling Replicas43dBc2nd Harmonic3rd HarmonicSinc(fLO,BW)Replicas rejection 43dBc 8dBc improvement compared to the ideal digital up

48、-sampling with fs=fLO/2 Other spurs limited by the Sinc function of fLOand BW as well as LO harmonics 2025 IEEE International Solid-State Circuits Conference28 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSMeasured Wi-F

49、i 80MHz 256QAM 3.84GHz(1/2)Wi-Fi 80MHz 256QAM 3.84GHz(w/DPD):Pavg=17.5dBm SE=10.3%EVM=-29.5dB Dynamic power range 33dB-20-15-10-505101520-20-1001020Measured DTX performance of WiFi 80MHz at 3.84GHz DTX System Efficiency EVMAverage Output Power(dBm)DTX System Efficiency(%)-40-30-20-100EVM(dB)Pavg=17.

50、5dBmSEavg=10.3%EVM=-29.5dBPavg=15.1dBmEVM=-29.8dBWiFi 80MHz 3.84GHz 2025 IEEE International Solid-State Circuits Conference29 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSMeasured Wi-Fi 80MHz 256QAM 3.84GHz(2/2)Replica

51、s rejection 42dBc 9dBc improvement compared to the ideal digital up-sampling with fs=fLO/2(even with high BW,high QAM mod.and high LO freq.)Other spurs limited by the Sinc function of fLOand BW as well as LO harmonicsFarout spectrum of WiFi 80MHz 3.84GHz3fLO/2 2fLO 5fLO/23fLO Sampling Replicas42dBc2

52、nd Harmonic3rd HarmonicSinc(fLO,BW)2025 IEEE International Solid-State Circuits Conference30 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOSMeasured DTX Modulation Power Consumption The power consumption of DBSP accounts

53、 for 42dBc wideband replicas rejection Wide frequency coverage of 2.1-5.1GHz Peak Pout of 27.8dBm with 30.4%SE Only 0.88mm2core size with a single 1.1V supply 2025 IEEE International Solid-State Circuits Conference34 of 3426.2:A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Ana

54、log Interpolation and Filtering in 28nm CMOSAcknowledgements We would like to thank the State Key Laboratory of Integrated Chips and Systems at Fudan University for testing supports.We would like to thank group members of Fudan WiCAS lab for technical discussions and supports.This work was supported

55、 by the National Natural Science Foundation of China under Grant 62322105.26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference1 of 48Crystal-less Frequency-Modul

56、ation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power ConnectivityYi Shen,Boxuan Chang,Chien-Wei Tseng,Yunfan Wang,Qirui Zhang,Zichen Fan,Zhen Feng,Rahul Narashimha,Andrea Bejarano-Carbo,Hun-Seok Kim,David BlaauwUniversity of Michigan,Ann Arbor,MI26.3:Crystal-less

57、 Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference2 of 48 Introduction Prior and Proposed Work Operation Principles Hardware Implementation DetailsLow-power Neural Engine Encod

58、erHigh-efficiency Analog Front-endMeasurement ResultsConclusionOutline26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference3 of 48Introduction:Wireless Connectivi

59、ty in IoTSmart HomeInventory TrackingIndustrial AutomationAgricultureAutomotive&TransportHealthcare&Medical26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference4

60、of 48Low-power IoT Connectivity System Asymmetric Resources for Up vs.Down Link Limited Energy and Power for Up Link26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Con

61、ference5 of 48Low-power IoT Connectivity System Previous Solution:Non-coherent Frequency Modulation Simplified Design Reduced Cost Lower Power Consumption.26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE

62、 International Solid-State Circuits Conference6 of 48Prior WorkXTAL-Less AFEAFE w/PLL Direct Modulation26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference7 of 4

63、8Prior WorkXTAL-Less AFEAFE w/PLL Direct Modulation26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference8 of 48Recent XTAL-Less AFE Approaches#1:MEMS Device asDCO

64、 Inductor#2:Clock Recovery/Calibration from RXLow PowerNot MonolithicHigher CostLow Phase Noise&DriftPower OverheadRequire Active RX PathB.Wiser,VLSI,2019K.Tang,JSSC,2023F.Maksimovic,VLSI,2019A.Alghaihab,ISSCC,202026.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven

65、 Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference9 of 48Channel Coding(Conv.Code,Polar,.)Modulation(GFSK,CSS,.)TX DataDigital Baseband(DBB)ArchitectureAnalog Front-end(AFE).IoT NodePADCODigital Baseband in Low-power IoTConventional Coding and M

66、odulation Process:Independent coding and modulation A Small Number of Discrete Symbols in Modulation Separate Digital Baseband Design from AFE=Room for Optimization26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity

67、2025 IEEE International Solid-State Circuits Conference10 of 48Proposed NN-driven XTAL-less TX System:Neural-FM28nm Neural-FM TX IC Joint Coding and Modulation with Deep Neural Network(DNN)Simple XTAL-less AFE and BB CLK generation Hardware Impairments are Modeled in DNN Training26.3:Crystal-less Fr

68、equency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference11 of 48Design Challenges:#1 Free-run.LO Impairments Challenges:Excessive Center Frequency Offset(CFO)&Phase Noise26.3:Crystal-le

69、ss Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference12 of 48Design Challenges:#1 Free-run.LO Impairments Challenges:Excessive Center Frequency Offset(CFO)&Phase Noise Proposed

70、Solution:DNN Model trained with LO Impairments Tolerate Phase Noise/CFO/Circuit Block to Reduce the Temperature Drift26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Co

71、nference13 of 48Design Challenges:#2 Neural Network Complexity Challenges:DNN Computation=Power/Efficiency Costs 26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Confer

72、ence14 of 48Design Challenges:#2 Neural Network Complexity Challenges:DNN Computation=Power/Efficiency Costs Proposed Solution:Low-power Neural Engine in Digital BB Highly Efficient DNN Computation26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and C

73、oding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference15 of 48Benefit of the Proposed Neural-FM Joint Coding and Modulation:DNN-Based Integration of Channel Coding and Modulation Optimized Symbol for Enhanced Communication Quality26.3:Crystal-less Frequency-Modulati

74、on Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference16 of 48Benefit of the Proposed Neural-FM Joint Coding and Modulation:DNN-Based Integration of Channel Coding and Modulation Optimized Symbol for

75、 Enhanced Communication QualityUnder the Same TX Power:BER Superior to Conventional Individual Coding&Modulation 26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Confer

76、ence17 of 48 Introduction Prior and Proposed Work Operation Principles Hardware Implementation DetailsLow-power Neural Engine EncoderHigh-efficiency Analog Front-endMeasurement ResultsConclusionOutline26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation a

77、nd Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference18 of 48Neural-FM Network Model&Training End-to-end(TX-RX)Training with AWGN+AFE Impairments Round-robin Training:Train encoder with a fixed decoderTrain decoder with a fixed encoderIterate until convergesTra

78、nsmitterReceiver26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference19 of 48Neural-FM Operation PrinciplesNN-based DBBXTAL-less AFE26.3:Crystal-less Frequency-Mo

79、dulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference20 of 48XTAL-less AFENeural-FM Operation Principles Encoding TX Data Packet1.Get N-bit TX data bit as a packet(N=128 in this work)2.Encoded

80、 by a 3-layer Bi-directional Recurrent Neural Network(RNN)NN-based DBBTX Bit/Last ActivationTo NextNNLayer26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference21

81、of 48XTAL-less AFENeural-FM Operation Principles Symbol Mapping3.Map RNN output to freq.samples by Fully-connected Layer4.Filter the NN output to improve spectrum efficiencyNN-based DBB26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Lo

82、w-Power Connectivity 2025 IEEE International Solid-State Circuits Conference22 of 48XTAL-less AFEDigital FIRZ-1a1a2anZ-1.Neural-FM Operation Principles Symbol Mapping3.Map RNN output to freq.samples by Fully-connected Layer4.Filter the NN output to improve spectrum efficiencyNN-based DBBFM Symbol af

83、ter FIRFCLDCO26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference23 of 48fc=2.4GHzBLEMaskpfnfBB SignalDCO2.4GHzRF SignalXTAL-less AFENeural-FM Operation Principl

84、es TX Signal Synthesis5.DCO w/6-bit Fine SCA generate signal 2.4GHz ISM band6.PA amplifies DCO output and transmit via antennaNN-based DBB26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International So

85、lid-State Circuits Conference24 of 48 Introduction Prior and Proposed Work Operation Principles Hardware Implementation DetailsLow-power Neural Engine EncoderHigh-efficiency Analog Front-endMeasurement ResultsConclusionOutline26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Ne

86、twork-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference25 of 481.Hardware-Algorithm Co-optimization26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 202

87、5 IEEE International Solid-State Circuits Conference26 of 481.Hardware-Algorithm Co-optimization Quantization-aware Training of DNN Model Reduce weights and activations to 6bit fix-point Negligible effective-SNR degradation with 6bit arithmetic 32.9%lower power consumption compared to 8bit precision

88、.*Equ.Rx Power Loss BER=10-4*DBB+AFE power to achieve the same BER performance26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference27 of 482.Weight Stationary PE&

89、Dual-Rail Buffer26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference28 of 482.Weight Stationary PE&Dual-Rail Buffer Weight Stationary PE in GRU Cell Pre-loading

90、weight to on-chip low-leakage local registers Eliminating memory accesses and delay during RNN inference26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference29 of

91、 482.Weight Stationary PE&Dual-Rail Buffer Weight Stationary PE in GRU Cell Pre-loading weight to on-chip low-leakage local registers Eliminating memory accesses and delay during RNN inference Dual-Supply-Rail Layer Buffer De-couple SRAM and logic circuits,allow sub-Vthoperation w/o MEM failure26.3:

92、Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference30 of 483.Low-power NE Encoder Performance 0.72mW active power for encoding a 0.5 Mbps data stream Peak efficiency

93、=13.86 TOPs/W Less significant power overhead compare to AFE26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference31 of 48 Introduction Prior and Proposed Work Ope

94、ration Principles Hardware Implementation DetailsLow-power Neural Engine EncoderHigh-efficiency Analog Front-endMeasurement ResultsConclusionOutline26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE Intern

95、ational Solid-State Circuits Conference32 of 481.DCO Fine-step SCA Design 6bit Parallel-Series SCA Unit caps are diluted by parallelingCap CL+Trim Cap Achieve 15.6kHz/step in 1MHz BWMeasurement of fine SCA op.(2.4GHz by chirp)Measurement of DCOPhase Noise 2.4GHz26.3:Crystal-less Frequency-Modulation

96、 Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference33 of 482.DCO Temperature Compensation Low-power Coarse Compensation Keep drift w/i algorithm limit(600kHz)Reuses the bias circuit for CTAT voltage

97、 Use varactor nonlinearity to mitigatesecond-order effect in DCO driftMeasurement of DCO Temperature Compensation 26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Confe

98、rence34 of 483.PA Dead-zone Driver Class-D PA w/Dead Zone Driver for Higher Efficiency Alleviate power stage switching loss 9.6%drain efficiency improvement w/driver overhead includedW.-H.Yu,TCSA-I,2017Class-DPA26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Mo

99、dulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference35 of 48 Introduction Prior and Proposed Work Operation Principles Hardware Implementation DetailsLow-power Neural Engine EncoderHigh-efficiency Analog Front-endMeasurement ResultsConclusionOutline2

100、6.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference36 of 48Chip Photograph&Power Breakdown 28nm CMOS Core Area:1.23mm2 DBB:0.98mm2 AFE:0.19mm2 SCAN:0.06mm2 Tx Ac

101、tive Power=4.86mW 1.05V for PA 0.67V for DCO&SRAM Core 0.48V for DBB Logic Core26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference37 of 48Measurement:Neural-FM

102、Signal Spectrum Measurement:Spectrum utilization is comparable to GFSK defined in BLE W/i BLE spectrum mask Instantaneous FrequencyMeasurement of Same Packet:Neural-FM Convolutional Coded GFSK(BLE Coded)26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation

103、 and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference38 of 48Measurement:BER/PER Test Setup Neural-FM IC vs.GFSK from USRP:GFSK TX:USRP w/high-performance PLL Same RX FE Same Channel:Fix+TunableAttenuator(Assume AWGN)26.3:Crystal-less Frequency-Modulation Tra

104、nsmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference39 of 48Measurement:BER/PER(N=128bit)Neural-FM outperforms GFSK w/Conv.Coded(BLE Coded)and GFSK w/Polar Code(more advanced coding)in both BER and PER(N

105、=128bit)Compare to uncoded/conv.-coded/polar-coded GFSK:Gain at 0.1%BER:10.0/4.4/3.6dBGain at 1%PER:10.4/4.4/2.0dB26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Confe

106、rence40 of 48Measurement:BER/PER(N=128bit)Neural-FM outperforms GFSK w/Conv.Coded(BLE Coded)and GFSK w/Polar Code(more advanced coding)in both BER and PER(N=128bit)Compare to uncoded/conv.-coded/polar-coded GFSK:Gain at 0.1%BER:10.0/4.4/3.6dBGain at 1%PER:10.4/4.4/2.0dBAchieved by NN Modelw/o Post-f

107、ab Fine-tuning26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference41 of 48Measurement:CFO Tolerance The NN-encoded packets can tolerate CFO form-900kHz to+600kHz

108、with a BER increase of 20%(PRX=-104dBm,BER 0.1%)Enough to cover the CFO residue of AFE temperature compensation:CFO 600kHz,in a range from-20C to 80CCFO Tolerance MeasurementAchieved by NN Modelw/o Post-fab Fine-tuning26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Dr

109、iven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference42 of 48Comparison Table:Coding&Modulation Schemes26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025

110、IEEE International Solid-State Circuits Conference43 of 48Comparison Table:Coding&Modulation Schemes26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference44 of 48C

111、omparison Table:TX System26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference45 of 48Comparison Table:TX System26.3:Crystal-less Frequency-Modulation Transmitter

112、 IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference46 of 48Comparison Table:TX System26.3:Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Co

113、nnectivity 2025 IEEE International Solid-State Circuits Conference47 of 48Conclusion A Low-power TX System:DNN-based joint channel-coding and modulationSub-VthNeural Engine as DBB with high computation efficiencyXTAL-less AFE with simplified complexity Similar/Superior TX Power Efficiency:TX Eff.=41

114、.1%,including the overhead of NE Resiliency to Freq.Drift and Phase Noise of the Free-run.DCO:CFO tolerance+/-600kHz,system robust across-20 to 80C Significant Reduction on RX Power for Same Error Rate:4.4dB gain compared to GFSK w/conv.coding(BLE Coded)26.3:Crystal-less Frequency-Modulation Transmi

115、tter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity 2025 IEEE International Solid-State Circuits Conference48 of 48Thank You for Listening26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area

116、1 of 42 2025 IEEE International Solid-State Circuits ConferenceA 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2AreaXiaohan Zhang*,Ruizhe Wang*,Qiang Zhou*,Hao Guo,Chuan Shi and Taiyun ChiRice University,Houston,TX*Equally credited au

117、thors(ECA)26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area2 of 42 2025 IEEE International Solid-State Circuits ConferenceOutline Introduction of 28GHz Front-End Module Circuit Innovations TX Mode Operation RX Mode Operation

118、Measurement Results Conclusion26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area3 of 42 2025 IEEE International Solid-State Circuits ConferenceFront-End Module(FEM)IntroductionKey considerations for FEM:TX Pout,efficiency,and

119、linearity RX NF SizePALNAPoutNFFEM#1.BeamformerT/R SWPALNAPoutNFFEM#NT/R SW26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area4 of 42 2025 IEEE International Solid-State Circuits ConferenceX.Tang,TMTT21Compact area(0.2mm2)Linea

120、r Class-AB PA PAEavg 10%(PAPR of 5G NR OFDM 10dB)Existing 28GHz FEMs 26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area5 of 42 2025 IEEE International Solid-State Circuits ConferenceCompact area(0.154mm2)Havent been integrated

121、 to fully functional FEME.Liu,ISSCC24Two-way Doherty PASymmetric Doherty PA(PAP=PAM)Efficiency enhancement up to 6dB backoff26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area6 of 42 2025 IEEE International Solid-State Circuits

122、 ConferenceX.Zhang,ISSCC24Efficiency enhancement at deeper back-off(10-12dB)Size(0.81mm2)OK for base stations,but not the best candidate for UEMulti-way Doherty PA26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area7 of 42 2025

123、IEEE International Solid-State Circuits ConferenceSymmetric Doherty PA Efficiency enhancement limited to 6dB back-offLarge area(0.86mm2Including PA,LNA,and SW)C.Elgaard,JSSC2428GHz FEMs with Doherty PA26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power

124、Amplifier and 0.22mm2Area8 of 42 2025 IEEE International Solid-State Circuits ConferenceDesign Motivation 28GHz FEM with a compact core area Efficiency enhancement for 5G OFDM Competitive TX Poutand RX NF 26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Po

125、wer Amplifier and 0.22mm2Area9 of 42 2025 IEEE International Solid-State Circuits ConferenceOutline Introduction of the Front-End Module Circuit Innovations TX Mode Operation RX Mode Operation Measurement Results Conclusion26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asy

126、mmetric Doherty Power Amplifier and 0.22mm2Area10 of 42 2025 IEEE International Solid-State Circuits ConferenceCircuit Innovation#1:Asymmetric DohertyTwo-way asymmetric Doherty(PAP=2 PAM)Efficiency enhancement up to 9.5dB back-offPAEavgof asymmetric=1.22 PAEavgof symmetricRANTPAMPAP Doherty Combiner

127、26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area11 of 42 2025 IEEE International Solid-State Circuits ConferenceCircuit Innovation#1:Doherty PA Size Reduction N-way Doherty typically requires N TXFs at the output network Inn

128、ovation:Two-way asymmetric Doherty in one TXFRANTPAMPAPk11n1TXF1k2n2TXF2S.Hu,JSSC19RANTPAMPAPk11n1LPPhysical transformerCP2CP1X.Zhang,ISSCC2426.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area12 of 42 2025 IEEE International So

129、lid-State Circuits ConferenceCircuit Innovation#2:Co-Designed TX-RX NetworkCo-designed TX-RX network with embedded T/R SWShared LPbetween TX and RX compact area(0.22mm2)26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area13 of 4

130、2 2025 IEEE International Solid-State Circuits ConferenceOutline Introduction of the Front-End Module Circuit Innovations TX Mode Operation RX Mode Operation Measurement Results Conclusion26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and

131、 0.22mm2Area14 of 42 2025 IEEE International Solid-State Circuits ConferenceTX Mode OperationSW1and SW2both turned onLPis part of PA output matching network26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area15 of 42 2025 IEEE I

132、nternational Solid-State Circuits ConferencePA Output Matching Network SynthesisStep 1:Insert ideal transformerTlineRANTPAMPAPZ0R0LPROPT,MROPT,PTransform RANT to R0Asymmetric Doherty(ROPT,P ROPT,M)TlineRANTPAMPAPk=11n1LPIdeal transformerZ026.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module

133、Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area16 of 42 2025 IEEE International Solid-State Circuits ConferencePA Output Matching Network SynthesisStep 2:Replace 90 transmission line with CLC networkRANTPAMPAPk=11n1Z0LPCLCTlineRANTPAMPAPk=11n1LPIdeal transformerZ026.4:A 24-to-29GHz C

134、ompact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area17 of 42 2025 IEEE International Solid-State Circuits ConferencePA Output Matching Network SynthesisStep 3:Swap shunt inductor&capacitor in orangeRANTPAMPAPk=11n1Z0LPCLCRANTPAMPAPk=11n1Z0LP26.4:A

135、24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area18 of 42 2025 IEEE International Solid-State Circuits ConferencePA Output Matching Network SynthesisStep 4:Components(in purple)consolidate into physical transformer RANTPAMPAPk=11n1Z

136、0LPPAMPAPk11n1LPPhysical transformerCP2CP126.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area19 of 42 2025 IEEE International Solid-State Circuits ConferencePA Output Matching Network SynthesisStep 5:single-ended schematic is c

137、onverted into differentialPAMPAPk11n1LPPhysical transformerCP2CP1RANTPAMPAPk11n1CDEVCDEVLPTXF126.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area20 of 42 2025 IEEE International Solid-State Circuits ConferencePA Output Matching

138、 AdvantagesArbitrary impedance transformation ratio from RANTto ROPT,M&ROPT,PRANTk11n1CDEVCDEVLP/2LP/2PAMPAPCS1CS1SW1SW1SW2TXF1ROPT,MROPT,PAsymmetric Doherty(ROPT,P-10-10.0 -6.319.64.3a-12.3a14.2a82a19.5a2.8a-19.2ac48a-9.8c3.119.310-15.0c-20c-18.5 -15.6-22.2a-28.8a-19.4IP1dB(dBm)RX Mode26.4:A 24-to-

139、29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2Area41 of 42 2025 IEEE International Solid-State Circuits ConferenceConclusionThe highest PSAT,OP1dB,PAEP1dB,and PAE9.5dB,BO in the TX modeA significant PAEavgenhancement of 1.5 in 5G NR OFDM t

140、estsA competitive NFA comparable area to FEMs adopting linear Class-AB PAsKey techniques to achieve these performances:Two-way asymmetric Doherty PACo-design with the PA output and LNA input matching with T/R switch26.4:A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric

141、Doherty Power Amplifier and 0.22mm2Area42 of 42 2025 IEEE International Solid-State Circuits ConferenceAcknowledgmentGlobalFoundries for chip fabricationKeysight for measurement equipment supportMembers of the Rice Integrated Systems and Electromagnetics(RISE)Lab for insightful technical discussions

142、Thank You26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference1 of 30A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOSBotao Yang1,Nayu Li2,Yiwei Liu1,Hang Lu1,Huiyan Gao1,Shao

143、gangWang1,Jingwen Xu1,Xuanyu He1,Na Yan3,Qun Jane Gu4,ChunyiSong2,Zhiwei Xu11Zhejiang University,Zhoushan,China,2Donghai Laboratory,Zhoushan,China,3Fudan University,Shanghai,China,4Georgia Institute of Technology,Atlanta,GA26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in

144、 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference2 of 30Outline Motivation Transceiver Front-end Architecture Load Capacitance Cancellation Network(LCCN)Measurement Results Conclusions26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE

145、 International Solid-State Circuits Conference3 of 30Outline Motivation Transceiver Front-end Architecture Load Capacitance Cancellation Network(LCCN)Measurement Results Conclusions26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-

146、State Circuits Conference4 of 30Motivation 17.7-29.5 GHz：Enable 5G/SATCOM fusion communication.Conventional TRXs cannot fulfill these needs at the same time.33GHz25n2572921n258 n261SATCOM UplinkSATCOM DownlinkTDDFDDWideband Low Noise RXWideband High-efficiency TXIsolation Between TX/RXConflict26.5:A

147、 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference5 of 30Prior Arts26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference6

148、 of 30Load Capacitance Cancellation Network（LCCN）TX Loss:0.18-0.22dBRX Loss:0.18-0.3dB Isolation Wideband 02468101214152025303540Noisre Figure(dB)Frequency(GHz)PA Parasitic Cap.IncreaseCPA=870fF(Actual Value)Noise degenaration at 25GHz2.52.93.33.74.14.54006008001000Noisre Figure(dB)Parasitic Capacit

149、or(fF)Without LCCNActual LCCNIdeal LCCNNF Decoupled From Parasitic Cap.NF increaseto 8dBNF+0.05dBFrequency:25GHz26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference7 of 30Outline Motivation Transceiver Front-

150、end Architecture Load Capacitance Cancellation Network(LCCN)Measurement Results Conclusions26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference8 of 30GSGVBLNA2LCVBLNA3VBPA2VBPA4IONLNAIOPLNAVBLNA11.1VM18M17VGP

151、A4VBPA3VBPA1Cn3M12M11Cn4Cn7M16M15Cn8M22M21VGPA41.1VVINPAVIPPA2.0VLSLSM20M19M23M24M25M261.8VM27M28Cn10Cn9VGLNA1M29M30Cn12Cn11M1-860n/240M3-460n/120M5-1660n/60PA transistorsM23-2660n/144M27-3060n/96LNA transistorsC2-Way 4-Stage Voltage-CombinePower Amplifier3-Stage LNA1.1VCGVGPA1VBPA2VBPA3VBPA1Cn2M10C

152、n1Cn6M13M14Cn51.1VCGVGPA1M1M2M6M5M8M7M3M4-+M91.8V1.1V1.1V-+SPINVG-1V/1.5VTransceiver Front-end Architecture26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference9 of 30Outline Motivation Transceiver Front-end A

153、rchitecture Load Capacitance Cancellation Network(LCCN)Measurement Results Conclusions26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference10 of 30GSGVBLNA2LCVBLNA3IONLNAIOPLNAVBLNA10VLSLSM23M24M25M261.8VM27M2

154、8Cn10Cn9VGLNA1M29M30Cn12Cn11M1-860n/240M3-460n/120M5-1660n/60PA transistorsM23-2660n/144M27-3060n/96LNA transistorsC2-Way 4-Stage Voltage-CombinePower Amplifier3-Stage LNA1.8V1.5VSPINVG1.5VVBLNA1Transceiver Front-end Architecture(RX)26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dB

155、m OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference11 of 30LCCN Design(RX)LCCN can be modeled by inductance and coupling effects.Load Capacitance Cancelation NetworkLNACPARX-MODEPA OFF870fFL1=140pHL2=130pHPAPA26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2

156、dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference12 of 30LCCN Design(RX)The opposite coupling coefficients completely cancelled.Load Capacitance Cancelation NetworkLNACPARX-MODEPA OFF870fFL1=140pHL2=130pHPAPAK=0.3K=-0.3Signal DirectionKtotal 0LCCN Theoretical ModelL1L22

157、6.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference13 of 30LCCN Design(RX)The effects of the other coils are added to the practical model.Load Capacitance Cancelation NetworkLNACPARX-MODEPA OFF870fFL1=140pHL2

158、=130pHPAPALCCN Practical ModelLcenterLsupplyInputOutputLinK=K+K1CPAL1=L1+LinL2=L2+LcenterK126.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference14 of 30LCCN Design(RX)Simplification of the model by the transfo

159、rmer T-model.LNA impedance is no longer interfered by PA coil parasitic.L1-ML2-MCPACPAL2+ML1+MShort-circuited Parasitic NetworkK=-1M-MM-MK=1zOutputInputZ=0L2-MCPACPAL2+MM-MLsupply(Large)InputOutputL1-ML1+MZ=0M=M=1 212K LLKL LTransformer for LCCNLNA Input Impedance:PA Load Capacitance is Completely C

160、anceledInputOutputL1-M+L1+M26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference15 of 30GSGVBPA2VBPA4IONLNAIOPLNAVBLNA11.1VM18M17VGPA4VBPA3VBPA1Cn3M12M11Cn4Cn7M16M15Cn8M22M21VGPA41.1VVINPAVIPPA2.0VM20M19M1-860

161、n/240M3-460n/120M5-1660n/60PA transistorsM23-2660n/144M27-3060n/96LNA transistors2-Way 4-Stage Voltage-CombinePower Amplifier3-Stage LNA1.1VCGVGPA1VBPA2VBPA3VBPA1Cn2M10Cn1Cn6M13M14Cn51.1VCGVGPA1M1M2M6M5M8M7M3M4-+M91.1V1.1V-+SPINVG-1V-1V0VTransceiver Front-end Architecture(TX)26.5:A 17.7-29.5 GHz Tra

162、nsceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference16 of 30LCCN Design(TX)Regulated gate capacitance guarantees transistor reliability.Load Capacitance Cancellation NetworkLNATX-MODELNA OFFPAPAPACGVD22.01.8VD11.00.6VG10.30.8VG21.30

163、.126.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference17 of 30048121620232425262728-15-10-505101520PAE(%)Gain(dB)Output Power(dBm)With NVGWithout NVGXGain/Power degenarationLarge Signal(12dBm)23GHz048121620-2

164、5-15-551525-39-30-21-12-3PAE(%)Output Power(dBm)Input Power(dBm)XWith NVGWithout NVGOP1dB:17.119.8dBmPAEOP1dB:11.618.9%23GHzLCCN Design(TX)Power leakage to the LNA is limited.The output power and PAE of the PA is greatly improved.26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm O

165、P1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference18 of 30Load Capacitance Cancellation NetworkLNATX-MODELNA OFFPAPA0VLNA coil in TX MODE-1VCoupling LCCN Design(TX)Negative voltage of LNA switch provided by NVG26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2d

166、Bm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference19 of 30PA Wideband Load-pull With/Without LNA circle Output Power PAEwo.LNA w.LNA17.7GHz 29.5GHzLCCN Design(TX)LNA switch is reliably turned off with limited voltage swing.LNA has limited effect on PA load-pull impedance.

167、26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference20 of 300V-1VNegative Voltage Generator CLK+CLK-R-C FilterOSCILLATORCLK+CLK-LNA coil in TX MODELCCN Design(TX)Negative voltage of LNA switch provided by NVG

168、26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference21 of 30Outline Motivation Transceiver Front-end Architecture Load Capacitance Cancellation Network(LCCN)Measurement Results Conclusions26.5:A 17.7-29.5 GHz

169、 Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference22 of 301338m1458mT/R SwitchPA1-3PA1-3PA4LNASPINegative Voltage Genarator1180m900mDie Micrograph65-nm CMOS process26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 2

170、0.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference23 of 30Measurement Results LNANF:3.3-5dB;S11-10dB at 17.7-29.5 GHz PAS22-9.5dB at 17.7-29.5 GHz-30-20-10010203040152025303540S Parameters(dB)Frequency(GHz)Meas.-Sim.S21S22S11-10-5051015-40-30-20-1001020304015202530354

171、0Noise Figure(dB)S Parameters(dB)Frequency(GHz)Meas.-Sim.S21S11S22NF26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference24 of 300510152025131517192123251820222426283032PAEOP1dB(%)OP1dB(dBm)Frequency(GHz)OP1dB

172、=20.2dBm PAEOP1dB=20.56%24GHz20-31.5 GHzOP1dB:16.7-20.2dBm PAEOP1dB:14-20.56%0510152025131517192123251820222426283032PAEMAX(%)Psat(dBm)Frequency(GHz)Psat=20.5dBm PAEOP1dB=21.8%24GHz20-31.5 GHzPsat:17.04-20.56dBm PAEMAX:14.3-21.8%Measurement Results Psat=20.5 dBm at 24 GHz,with PAEMAX=21.8%OP1dB=20.2

173、 dBm at 24 GHz,with PAEOP1dB=20.6%26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference25 of 30Measurement Results 2021-2024 Published silicon-based TRX or front-ends26.5:A 17.7-29.5 GHz Transceiver Front-end

174、with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference26 of 3026.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference27 of 30Outline Motivation Transceiver Front-en

175、d Architecture Load Capacitance Cancellation Network(LCCN)Measurement Results Conclusions26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference28 of 30ConclusionProposed Load Capacitance Cancellation Network(LC

176、CN)LCCNs cancellation of PA parasitics allow LNA to achieve NF as low as 3.3 dBLCCN combined with NVG allow PA to achieve up to 20.2 dBm OP1dBThe chip has been implemented in 65nm CMOS.The chip has been successfully tested.26.5:A 17.7-29.5 GHz Transceiver Front-end with 3.3dB NF and 20.2dBm OP1dB in 65-nm CMOS 2025 IEEE International Solid-State Circuits Conference29 of 30Acknowledgements This work was supported in part by the National Key Research and Development Program of China under Grant 2023YFB4403302,and in part by the Science Foundation of Donghai Laboratory under Grant DH-L23ZY001.