HotChips_MCP_for_Wireless_Application_Intel.pdf

1、HOTCHIPS 2022Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF ApplicationsSergey ShumarayevAllen ChanTim HoangProgrammable Solution Group(PSG)CTO OfficeRobert KellerTexas InstrumentsIntel ConfidentialDepartment or Event Name2Outlines5G Use Cases and Massive MIMO Typical Base

2、StationMotivationDARPA CHIPS ProgramBuilding BlocksGrowing AIB-Based Chiplet PortfolioChiplet Connection with EMIB and AIBChiplet IntegrationAFE Chiplet Design FeaturesHeterogeneous Integration AdvantagesCHIPS Phase 2 Platform Hardware OverviewEnabling Massive MIMOEnabling Radar SystemEnabling Next

3、Generation SystemsConclusionIntel ConfidentialDepartment or Event Name35G Use Cases and Massive MIMO Base Station5G Use CasesDiagram of typical base station with massive MIMO channelsBandwidth/Power?JESD 204BBW308GbpsChannels26 12.5GbspPower25WLatency135 Frame ClkBoard ComplexityHighWorkload executi

4、on time?Intel ConfidentialDepartment or Event NameMotivation4Gordon E.MooreMoores Law paper“It may prove to be more economical to build large systems out of smaller functions,which are separately packaged and interconnected.”Intel ConfidentialDepartment or Event Name5DARPA CHIPS ProgramCHIPS program

5、 seeks to establish a new paradigm in IP reuse.The vision of CHIPS is an ecosystem of discrete modular,reusable IP blocks,which can be assembled into a system using existing and emerging integration technologies.Successful assembly of chiplets of various sizes into a heterogeneously integrated syste

6、m resulting in:Shorter design developmentLower-risk design integrationLower-cost design implementationSystem power reductionBoard area complexity reductionBoard design simplificationDARPA MTO,CHIPSIntel ConfidentialDepartment or Event Name6At https:/ Using chiplets from different process nodes and f

7、oundries(including GF,TSMC and Intel)as building blocks to create more complex systems demonstrates effectiveness of heterogeneous integration Employing Advanced Interface Bus(AIB)and Intel EMIB technology,chiplet concept was successfully demonstrated in CHIPS Phase 1 with 64 Gsps data converters In

8、 CHIPS Phase 2,chiplet concept is proven for repeatability with a TI analog front end(AFE)with up to 16TX16RX4FB at 12Gsps and 4Gsps for DAC and ADC respectively AIB Public Specification and Hardware Open Source available to download via GithubSee datasheet for workloads and configurations.Results m

9、ay vary.Chiplets as Building BlocksIntel ConfidentialDepartment or Event Name7Growing AIB-Based Chiplet PortfolioTechnology&Foundry AgnosticAt https:/ 2 FPGA families 6 SERDES chiplets 3 Data converter chiplets 3 Optical chiplets 2 ASIC compute chiplets 5 Defense Industrial Base(DIB)partners and chi

10、pletsIntel ConfidentialDepartment or Event Name8 ADC/DAC Machine Learning Memory Processors Adjacent IP Your IdeasChiplet Connection with EMIB and AIB Platform for innovation through ecosystem Explore new business models and technology partnershipsAIBAIBEMIBMicrobump pitch 55umFlip-Chip Pitch 100umI

11、ntel Embedded Multi-Die Interconnect Bridge(EMIB)Chiplet Library Advanced Packaging TechnologyAdvanced Interface Bus(AIB)Intel ConfidentialDepartment or Event Name9Chiplet IntegrationDiscrete component platformIntegrate AFE into FPGA platformSubstrate signaldrawingSubstrate physical design8T8R2AUX A

12、FE floorplanIntel ConfidentialDepartment or Event Name10TI AFEChiplet Design FeaturesConfiguration:8T8R2AUXMAX sample rate:DACs:12GSPS/ADCs:4GSPSRF Bandwidth 7 GHzDigital Features RX DDC:dual DDC with complex decimationAUX DDC:dual DDC with complex decimation TX DUC:dual DUC with complex interpolati

13、onClocking Options:internal PLL for TX and RXinternal PLL for TX and external clock for RXexternal clock for TX and RXInterface:Die to Die:16 AIB channels,16b TX/16b RX,2GbpsSee datasheet for workloads and configurations.Results may vary.Intel ConfidentialDepartment or Event Name11Chiplet Integratio

14、n PlatformResultsA.4 chiplets on 3 process nodes from 2 foundriesB.AIB-enabled Analog Front End(AFE)chiplet from Texas InstrumentsC.AIB 1.0 IP with 55m microbumpsCharacterization platformIntegration advantagesHeterogeneous Integration AdvantagesIntel ConfidentialDepartment or Event Name12Board Manag

15、ement ControllerOCP OpenBMC FormfactorPower Sequencing(PMBus)FPGA ConfigurationTelemetry(P,I,V,T)I2C/SPI ControllerUART/Ethernet/USB/JTAGQSPI Flash RF Clock BoardClock Gen and SyncTI LMK04828(Low Noise PLL)Low noise LDOCommunication Ports Ethernet USB 2.0 High SpeedCHIPS Phase 2 Platform Hardware Ov

16、erviewPower Supply Network In-Rush Current Controller FPGA Supplies AFE SuppliesRF Frontend Passive Matching Network BALUN RF Connectors/CablesCHIPS P2 Multi-Chip Package FPGA fabric die 1x 56G XVER 2x TI AFEIntel ConfidentialDepartment or Event Name13Board Management ControllerOCP OpenBMC Formfacto

17、rPower Sequencing(PMBus)FPGA ConfigurationTelemetry(P,I,V,T)I2C/SPI ControllerUART/Ethernet/USB/JTAGQSPI Flash RF Clock BoardClock Gen and SyncTI LMK04828(Low Noise PLL)Low noise LDOCommunication Ports Ethernet USB 2.0 High SpeedRF Frontend Passive Matching Network BALUN RF Connectors/CablesCHIPS Ph

18、ase 2 Platform Hardware OverviewPower Supply Network In-Rush Current Controller FPGA Supplies AFE SuppliesCHIPS P2 Multi-Chip Package FPGA fabric die 1x 56G XVER 2x TI AFEIntel ConfidentialDepartment or Event Name14JESD 204BAIBBW308Gbps256 GbpsChannels26 12.5Gbsp16 AIB Ch x 2GbpsPower25W0.512WLatenc

19、y135 Frame Clk6 Frame ClkBoard ComplexityHighLowEnabling Massive MIMO2x Bandwidth10 x in interface reduction power5G Use Casesmultiple workload execution time improvementDiagram of proposed base station with FPGA HW accelerationIntel ConfidentialDepartment or Event Name15FPGA increases Digital Beamf

20、orming Capabilities8T8R2AUX TI ChipletDACs:12GSPSADCs:4GSPS Multi Chip Package from CHIPS Phase 2 enables next gen Radar and 5G Comm SystemAir and Missile Defense Radar(AMDR)upgradeto US Navy ships with increased search volume in the same amount of search timeExamples of other applicationsLower Tier

21、 Air and Missile Defense Radar(LTAMDS)Enterprise Air Surveillance RadarEnabling Radar SystemsIntel ConfidentialDepartment or Event Name16RF Receiver:4GSPS ADC Decimation x4 at DDC Nyquist Zone Sampling Data is forwarded to FPGA via AIB for FFT calculationRF Transmitter:12GSPS DAC Interpolation x16 a

22、t DUC Carrier Frequency at 3.5Ghz NCO data from FPGA to DUC via AIBCHIPS technology in partnership with Texas Instruments AFE technology enables next generation RF systems,e.g.in our demonstration by combining AI and full FPGA HW/SW stack,we created a powerful modulation classification capabilityCHI

23、PS Technology Enables Next Generation SystemsStratix 10 FabricAIBAFEADCDACDDCDUCAIBLinkLayerEgressBufferHost Interface LogicSW FFTCapture BufferHW FFTAcceleration EngineIntel ConfidentialDepartment or Event Name17ConclusionIntel and Texas Instruments have successfully developed CHIPS Phase 2 fully f

24、unctional state-of-the-art MCP.Breath of technology coverage spans from commercial to military,aerospace and government markets.We achieved programs objectives of creating and integrating complex heterogeneous system at a fraction of development time and cost without compromising performance.Increas

25、ed bandwidth improvementReduction of interface powerEase of board design constraintsImproved system performance/latencyReduced system SWAP17Intel ConfidentialDepartment or Event NameReady to win?Visit bit.ly/HotWings22 and match Intel speakers to their talks for a chance to win an Intel NUC Mini PC

26、and other prizes.Intel at Hot Chips Intel ConfidentialDepartment or Event NameNotices&DisclaimersIntel technologies may require enabled hardware,software or service activation.No product or component can be absolutely secure.Your costs and results may vary.Intel Corporation.Intel,the Intel logo,and other Intel marks are trademarks of Intel Corporation or its subsidiaries.Other names and brands may be claimed as the property of others.