15-d3s3-2-SiFive_Discovering the RVV C intrinsics API v1.0_eop Chen.pdf

1、2023 SiFiveDiscovering the RVV C intrinsicsAPI v1.0eopChenKitoCheng2023 SiFive2CreditsThe development of RVV intrinsics owes a great debt to Nick Knight,Craig Topper,and Roger Ferrer Ibez for their valuable comments and reviews.2023 SiFive3AbstractIntroductionAvailability and usageTest macro and hea

2、der inclusionCurrent status of support in the upstream compiler toolchainControl to the vector extension programming modelOverviewExplicit(non-overloaded)intrinsicsImplicit(overloaded)intrinsicsOther variantsCurrent status and planning2023 SiFive4Availability and usageCurrent status of support in th

3、e upstream compiler toolchainLLVMLLVM 16 0 supports the v0.11 intrinsicsLack the tuple-type segment load/store,the floating-point rounding mode intrinsics,and the fixed-point rounding mode intrinsics.LLVM 17 1 supports the v0.12 intrinsicsExpecting no more change to the specification and identical t

4、o what is in v1.0GCCThe next GCC release(GCC 14)2 is expected to support v1.00 https:/releases.llvm.org/16.0.0/tools/clang/docs/ReleaseNotes.html1 https:/ https:/gcc.gnu.org/releases.html2023 SiFive5Availability and usageTest macro and header file inclusionUsers can check the compiler support throug

5、h the testing macro _riscv_v_intrinsic.Please include to access the RISC-V vector intrinsics.#ifdef _riscv_v_intrinsic#include#endif/*_riscv_v_intrinsic*/2023 SiFive6Control to the vector extension programming model Overview-Starting from the vsetvl configuration(1)Decision on the level of abstracti

6、on Starting from the essential instruction in the vector extension2023 SiFive7Control to the vector extension programming model Overview-Starting from the vsetvl configuration(2)Decision on the level of abstraction Starting from the essential instruction in the vector extensionIntrinsics brings asse

7、mbly instruction control to the C language level,taking care of tedious jobs likeInstruction schedulingRegister allocationvsetvl configurationRounding mode(frm and vxrm)configuration2023 SiFive8Control to the vector extension programming model Overview-Type systemEncodesData typeElement widthLength

8、multiplierIntrinsic types are likevfloat16m4_tvint32m1_tvuint8m8_t2023 SiFive9Control to the vector extension programming model Explicit(non-overloaded)intrinsics(1)EncodesData typeElement widthLength multiplierIntrinsic types are likevfloat16m4_tvint32m1_tvuint8m8_t2023 SiFive10Control to the vecto

9、r extension programming model Explicit(non-overloaded)intrinsics(2)2023 SiFive11Control to the vector extension programming model Explicit(non-overloaded)intrinsics(3)General naming convention is_riscv_V_INSTRUCTION_MNEMONIC_OPERAND_MNEMONIC_RETURN_TYPE_ROUND_MODE_POLICY(.)Example:vint32m1_t _riscv_

10、vadd_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl);vint32m1_t _riscv_vadd_vv_i32m1_tum(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,size_t vl);2023 SiFive12Control to the vector extension programming model Explicit(non-overloaded)intrinsics(4)General naming convention is_ris

11、cv_V_INSTRUCTION_MNEMONIC_OPERAND_MNEMONIC_RETURN_TYPE_ROUND_MODE_POLICY(.)Example:vfloat32m2_t _riscv_vfadd_vf_f32m2 (vfloat32m2_t op1,float32_t op2,size_t vl);vfloat32m8_t _riscv_vfadd_vf_f32m8_rm (vfloat32m8_t op1,float32_t op2,unsigned int frm,size_t vl);vfloat32m8_t _riscv_vfadd_vf_f32m8_rm_tum

12、u(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,float32_t op2,unsigned int frm,size_t vl);For exceptions,please checkout the intrinsics specification.2023 SiFive13Control to the vector extension programming model Implicit(overloaded)intrinsics(1)Main intention:Provide type agnostic interface

13、 to usersGeneral naming convention is_riscv_V_INSTRUCTION_MNEMONIC_OPERAND_MNEMONIC_RETURN_TYPE_ROUND_MODE_POLICY(.)Example:vint32m1_t _riscv_vadd(vint32m1_t op1,vint32m1_t op2,size_t vl);vint32m2_t _riscv_vadd(vint32m2_t op1,vint32m2_t op2,size_t vl);2023 SiFive14Control to the vector extension pro

14、gramming model Implicit(overloaded)intrinsics(2)vint8m2_t foo(vint8m1_t op1,vint8m1_t op2,vint8m1_t op3,vint8m1_t op4,vint8m1_t op5,vint8m1_t op6,vint8m1_t op7,vint8m1_t op8,size_t vl)vint8m1_t op12=_riscv_vadd(op1,op2,vl);vint8m1_t op34=_riscv_vadd(op3,op4,vl);vint8m2_t op1234=_riscv_vset_v_i8m1_i8

15、m2(op1234,0,op12);op1234=_riscv_vset_v_i8m1_i8m2(op1234,1,op34);vint8m1_t op56=_riscv_vadd(op5,op6,vl);vint8m1_t op78=_riscv_vadd(op7,op8,vl);vint8m2_t op5678=_riscv_vset_v_i8m1_i8m2(op5678,0,op56);op5678=_riscv_vset_v_i8m1_i8m2(op1234,1,op78);return _riscv_vadd(op1234,op5678,vl);foo:#foo.cfi_startp

16、roc#%bb.0:#%entryvsetvli zero,a0,e8,m1,ta,mavadd.vv v8,v8,v9vadd.vv v9,v10,v11vadd.vv v10,v14,v15vmv2r.v v12,v8vmv.v.v v13,v10vsetvli zero,a0,e8,m2,ta,mavadd.vv v8,v8,v12ret.Lfunc_end0:.size foo,.Lfunc_end0-foo.cfi_endproc#-End functionDue to limitation of the C language,the overloaded intrinsics do

17、es not cover 100%of the RVV instructions.For more detail please checkout the intrinsics specification.2023 SiFive15Control to the vector extension programming model Other variantsOther variants allows users to control the vector programming model like:Masked variants to control vmvfloat32m2_t _riscv

18、_vfadd_vf_f32m2_m (vbool16_t mask,vfloat32m2_t op1,float32_t op2,size_t vl);Policy variants to control vta and vmavfloat32m2_t _riscv_vfadd_vv_f32m2_tumu (vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1 vfloat32m2_t op2,size_t vl);Rounding mode variants to control frm and vxrmvfloat32m2_t _ri

19、scv_vfadd_vv_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1 vfloat32m2_t op2,unsigned int frm,size_t vl);2023 SiFive16Current status and planningCurrent status:Under first round of internal review among RVI Tech ChairsFuture planningC+templatesException handling intrinsics for fflag and vxsatPick up intrinsics of other vector extensionsVector cryptoNon Temporal Local HintBF16Feel free to checkout riscv-non-isa/rvv-intrinsic-doc for the latest draft specification.https:/ future of Empowering