王瀟-從Linux優化角度探索RISCV性能與兼容性的平衡.pdf

1、Explore the Balance between Perf and Compatibility in RISCV Linux Legal Notices and DisclaimersStatements in this document that refer to future plans or expectations are forward-looking statements.These statements are based on current expectations and involve many risks and uncertainties that could

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4、 that are in development and usage may change over time.No license(express or implied,by estoppel or otherwise)to any intellectual property rights is granted by this document.Intel Corporation.Intel,the Intel logo,and other Intel marks are trademarks of Intel Corporation or its subsidiaries.Other na

5、mes and brands may be claimed as the property of others.This document contains information on products and/or processes in development.Agenda Intro of riscv modularized ISA design Challenge of Linux lib optimization on riscvALTERNATIVE:A dynamic code patching design riscv lib optimization status fut

6、ure work Address the user level SW compatibility glibc ifunc binary translation A new BT mode Summary3RISCV modularized ISA design A shared general RISC ISA(i+m+a+f+d)Enough for Linux with csr+ifence Then,free customization according to your taste!Open vs fragmentation4The challenges posted to Linux

7、 lib optimization Different segments prefer different customizations Compute intensive workload like Vector extension,Matrix,etc IO intensive workload prioritize Cache management,etc Micro architecture diversity makes SW perf tuning harder Linux kernels forward and backward compatibility Allow advan

8、ced ISA extensions to accelerate the widely used APIs Latest kernel build should still be able to run on old/simple riscv implementation Build once,run everywhere5api consumerx-extx-extension supported?legacyNYx-extcall backeitherlegacynopnop or jumpjumpx-extlegacyretretinsn streamacceleration with

9、x-extraise minimum execution requirementcallextra condition check for every callfunction pointer adds another layer of abstractionconflict with inlinedynamic binary patching,with very small overhead(1 insn)patch just onceOptions6Text SectionSubSectionSubSectionAlternative Section_alt_start_alt_endal

10、ternative.oold insnsfunc to be patchednew insnsalt entryLeverage the ALTERNATIVE mechanismstatic _always_inline unsigned long _arch_hweight64(_u64 w)#ifdef CONFIG_RISCV_ISA_ZBB asm_goto(ALTERNATIVE(j%llegacy,nop,0,RISCV_ISA_EXT_ZBB,1):legacy);asm(.option pushn .option arch,+zbbn cpop%0,%0n .option p

11、opn :+r(w):);return w;legacy:#endif return _sw_hweight64(w);alternative run at boot time and module load offset fix is needed when jump is new code ALTERNATIVE_2 allows further patching7Status and future work Linux RISCV Lib optimization status B-ext based bitops optimization,hweight(),CRC,str*V-ext

12、 based memory copy,etc micro arch based checksum Future work Address multi acceleration choices Monitor the expansion of.alternative section Profile based buildRVA20RVA22RVA238How about the compatibility for user level SW?glibcs ifunc developer aware,hard to scale binary translation static BT,perfor

13、mant but not flexible dynamic BT,performance overhead deployment challenge in-kernel emulation layer native performance for HW supported instructions dynamic switch in/out transparent to user9 A lot of SW optimization SW optimization opportunities for RISCV,modularized ISA requires extra effort to keep compatibilitykeep compatibility.BT innovation could help HW build a standard ISA interface standard ISA interface to user SW,in a more deployabledeployable and transparenttransparent way.Takeaways10Thanks!