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1、ISSCC2025Forum4HighlightsofData-ConverterR&DinthePast5Years:AComprehensiveOverviewISSCC 2025 Forum 4Highlights of Data-Converter R&D in the Past 5 Years:A Comprehensive OverviewInternational Solid State Circuit ConferenceFebruary 20th,2025Start of presentations at 8:15 amISSCC 2025-Forum 4:Introduct
2、ion1 of 4 2025 IEEE International Solid-State Circuits ConferenceOrganizers:Hajime Shibata,Analog Devices,Toronto,CanadaLucien Breems,NXP Semiconductors,Eindhoven,The NetherlandsCo-Organizers:Pieter Harpe,Eindhoven University of Technology,Eindhoven,The NetherlandsIl-Min Yi,Gwangju Institute of Scie
3、nce and Technology,Gwangju,KoreaShiyu Su,University of Waterloo,Waterloo,CanadaChampions:Kostas Doris,NXP Semiconductors,Eindhoven,The NetherlandsMatteo Bassi,Infineon Technologies,Villach,AustriaModerator:Matt Straayer,Infineon Technologies,Andover,MAOrganizing Committee2 of 4ISSCC 2025-Forum 4:Int
4、roduction 2025 IEEE International Solid-State Circuits ConferenceDuring the Forum:8 Talks+panel session1 Breakfast,2 Coffee Breaks&1 Lunch Break40-minute talk followed by 5 minutes Q&A for each presenterPlease silence your mobile devicesPlease complete your speaker evaluations.Help us improve ISSCC.
5、After the Forum:Forum presentations will be available as downloadable PDFs and streaming videos(not downloadable)to the registered forum attendees only The material will not appear in IEEE Xplore or the conference digestGeneral Information3 of 4ISSCC 2025-Forum 4:Introduction 2025 IEEE International
6、 Solid-State Circuits ConferenceAgenda4 of 4ISSCC 2025-Forum 4:IntroductionStartTitleSpeakerAffiliation8:00 AMBreakfast8:15 AMIntroductionHajime ShibataAnalog Devices8:25 AMAD Converter Figures of Merit:From a Meaningful Metric to a Design DisasterBram NautaUniversity of Twente9:10 AMHigh-Speed ADCs
7、 for 100Gb/s+Wireline TransceiversHeng ZhangBroadcom9:55 AMBreak10:10 AMDevelopments and Challenges in High-Speed Continuous-Time ADCs for Wideband Wireless CommunicationsSharvil PatilAnalog Devices10:55 AMHigh-Speed DAC Architectures and Techniques Towards High Dynamic Range,Bandwidth and Output Po
8、werMike Shuo-Wei ChenUniversity of Southern California11:40 AM High-Performance Noise-Shaping ADCsMuhammed Bolatkale NXP Semiconductors12:25 PM Lunch1:40 PMHighlights of Power-Efficient ADCsYoungcheol ChaeYonsei University2:25 PMExtending ADC Performance Through TDC-Assisted Quantization in Multiple
9、 Dimensions Minglei ZhangUniversity of Macau3:10 PMBreak3:25 PMHigh-Performance Discrete-Time Amplifiers Utilizing Time-Varying Settling ProcessesLinxiao ShenPeking University4:10 PMPanel Discussions:Data Converter R&D for the Next 5 YearsMatt StraayerInfineon Technologies4:55 PMClosing RemarksLucie
10、n BreemsNXP Semiconductors 2025 IEEE International Solid-State Circuits Conference4 of 4AD CONVERTER FIGURES OF MERIT:from a Meaningful Metric to a Design DisasterBram NautaUniversity of Twente,Enschede,The Netherlands 2025 IEEE International Solid-State Circuits Conference1 of 49Fundamental limits
11、of power dissipationAnalog/Digital ConversionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsOutline 2025 IEEE International Solid-State Circuits Conference2 of 49=DD DDDD=Smin=D 8k min=8k S=DDIf1 E.A.Vittoz,1990.=S2 22kFundamental limits of p
12、ower dissipation 2025 IEEE International Solid-State Circuits Conference3 of 4922nm3nm1m10m0.5nmDigital CMOS NxN bit multiplier:Power/BW W/GHz or fJSignal to Noise Ratio dBPower/Bandwidth per polemin=8k min=8k 1 E.A.Vittoz,1990.SNR 30dB:pure analog wins 2025 IEEE International Solid-State Circuits C
13、onference4 of 49?Power/BW W/GHz or fJSignal to Noise Ratio dBPower/Bandwidth per pole 2025 IEEE International Solid-State Circuits Conference5 of 49P x 2(+3dB)SNR x 2(+3dB)scale W=2WLRC2WL2CR2 2025 IEEE International Solid-State Circuits Conference6 of 49Power/BW W/GHz or fJSignal to Noise Ratio dBP
14、ower/Bandwidth per pole 2025 IEEE International Solid-State Circuits Conference7 of 49Fundamental limits of power dissipationAnalog/Digital ConversionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsOutline 2025 IEEE International Solid-State C
15、ircuits Conference8 of 49Successive Approximation ADCNoise 2025 IEEE International Solid-State Circuits Conference9 of 49Sigma Delta ModulatoractiveintegratorpassivefilterNoise 2025 IEEE International Solid-State Circuits Conference10 of 49Fundamental limits of power dissipationAnalog/Digital Conver
16、sionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsOutline 2025 IEEE International Solid-State Circuits Conference11 of 49Empirical Metric 2every doubling of fsamplegives 1 effective bit lessmain cause:aperture jitter normalized to powerworks
17、 best for Nyquist converters,not being noise-limitedIf power is set by CV2,then technology scaling benefitWalden FoM=2 2originally this used to be fsample 2025 IEEE International Solid-State Circuits Conference12 of 49SNR based 3Indeed fits with Vittoz:Does NOT benefit from technology scalingBenefit
18、s from“mature”technologies thanks to high VoltagesSchreier FoMS=dB+10 10=min=8k 2025 IEEE International Solid-State Circuits Conference13 of 49Scheier FoM,best caseS,max=10 10(8)=195dBS=dB+10 10Vittozmin=8k f=BWSNR=SNDR(no distortion)2025 IEEE International Solid-State Circuits Conference14 of 49Pow
19、er/BW W/GHz or fJSignal to Noise Ratio dBPower/Bandwidth per poleS=185dBPublished ADCs:Already very close to fundamental limit of VittozS,max=10 10(8)=195dB 2025 IEEE International Solid-State Circuits Conference15 of 49Power of input driverhuge output swinglow distortionlow ohmic load Power of refe
20、rence generatorlow noisevery fast recovery BWPower of clock driverlow jitterBut what is missing?2025 IEEE International Solid-State Circuits Conference16 of 49Fundamental limit Driver powerSAR ADC:In reality much more power needed!min,driver=DDS 8k 2025 IEEE International Solid-State Circuits Confer
21、ence17 of 49Fundamental limit Driver powermin,driver=(1)DDS 8k ADC:In reality much more power needed!2025 IEEE International Solid-State Circuits Conference18 of 49Power/BW W/GHz or fJSignal to Noise Ratio dBPower/Bandwidth per poleS=Vddonly discharge caps inside the ADCless charge from the supplybu
22、t taken from the input driveruse Matlab/DSP to fix all errors,except noiseand ignore that poweror just make a digital sinewave generator;-)just detect amplitude,frequency and phase Figure of Merits a design disaster 2025 IEEE International Solid-State Circuits Conference20 of 49How to get a zero FoM
23、?just turn off your ADCHow to get a negative FoM?dont use a supply voltage as power source,but just as referenceuse the clock signal as power source for the ADCand create a negative supply currentBut whats the point of doing this?Figure of Merits a design disaster 2025 IEEE International Solid-State
24、 Circuits Conference21 of 49Fundamental limits of power dissipationAnalog/Digital ConversionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsOutline 2025 IEEE International Solid-State Circuits Conference22 of 49LOLNAClassical RF Front end mill
25、i Wattsmicro Watts full supply swing 2025 IEEE International Solid-State Circuits Conference23 of 49LOLNAPassive Mixer-First RF Front endMore linear,but still milli Wattsmicro Watts full supply swingN-path circuits 2025 IEEE International Solid-State Circuits Conference24 of 49Power/BW W/GHz or fJSi
26、gnal to Noise Ratio dBPower/Bandwidth per poleS=185dBADC:ADC+Driver+Ref.+40dBSOTA Passive Mixer-First RF Front end3 Zanten ISSCC24*Only baseband Ipath,3 poles.2025 IEEE International Solid-State Circuits Conference25 of 49LOLNAAmplifiers:Noise+Linearity challengenoiselinearitylinearity 2025 IEEE Int
27、ernational Solid-State Circuits Conference26 of 49input stageoutput stageBaseband LNA noise challengeweak inversion,shot noiseBrick wall noise filtercount only this currenttail=8(k)2n2 q 2025 IEEE International Solid-State Circuits Conference27 of 49micro Wattsmilli WattsLOLNAThe easy life for the A
28、DCtail=8(k)2n2 q full supply swing+more power!2025 IEEE International Solid-State Circuits Conference28 of 49Successive Approximation ADC is too easy may have quite high noise no linearity neededIDD?2025 IEEE International Solid-State Circuits Conference29 of 49Fundamental limits of power dissipatio
29、nAnalog/Digital ConversionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsOutline 2025 IEEE International Solid-State Circuits Conference30 of 49Comparatorpreamp6 Bindra,JSSC18latchVDDVDD 2025 IEEE International Solid-State Circuits Conference
30、31 of 49Comparatorpreamplatch6 Bindra,JSSC18Vc+Vc-2025 IEEE International Solid-State Circuits Conference32 of 49Comparator What about noise?preampVc+Vc-weak inversion,shot noiseDD=4(k)2n2 qcharge per clock cycle,count electronsduring dischargec2n,Di,2=electr,p33 of 49clock=2 tail=8(k)2n2 q DD=4(k)2
31、n2 qDD=8(k)2n2 q=ItailDD=clockBut:only 1 bit,NyquistIDDt001/fclockCLK=resetNeed oversamplingQDDIDDQDDsame area,same chargesame power!2025 IEEE International Solid-State Circuits Conference34 of 49Comparator oversamplingBWfclock2reference designPower=P0OSR=2:2x oversamplefclockBW2Power=2xP0digital fi
32、lterImpedance scale W=1=12fclock2BW=power neutralPower=P0Power=P0 2025 IEEE International Solid-State Circuits Conference35 of 49Amplifier versus Oversampled Comparator-Need large linear output swing-Drive next analog input+not linear+has easy load to driveIDDnoise set by#electrons passed through in
33、put transistor per 1/BWtail=8(k)2n2 q DD=8(k)2n2 q=5 Nauta,ISSCC24 2025 IEEE International Solid-State Circuits Conference36 of 49Fundamental limits of power dissipationAnalog/Digital ConversionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsO
34、utline 2025 IEEE International Solid-State Circuits Conference37 of 49good FoMlow noisehigh linearityhigh gainHigh risk,No GainLow-Swing,Low Noise ADClow noise5 Nauta,ISSCC24 2025 IEEE International Solid-State Circuits Conference38 of 49Bad FoMmin=8k min=DDS 8k “A”times worse FoM is totally fine at
35、 system levelfair=dB+10 10+10 10low noiseVS=VDDA 2025 IEEE International Solid-State Circuits Conference39 of 49Small swing SAR ADC,w/o active linear gainHigh power,but less than a linear pre-amplifier before the ADC would otherwise needMakes input window smallsmall input swing,no linear pre-amplifi
36、er 2025 IEEE International Solid-State Circuits Conference40 of 49Small swing ADC,w/o active linear gainHigh power,but less than a linear pre-amplifierbefore the ADC would otherwise needMakes input window smallsmall input swing,no linear pre-amplifier 2025 IEEE International Solid-State Circuits Con
37、ference41 of 49min=8k No need for factor“A”worseSmall swing ADC still close to fund power limitpassive filterfull swing DAClow-noisecomparator 2025 IEEE International Solid-State Circuits Conference42 of 49LOLNAPassive Mixer-First RF Front endN-path circuits 2025 IEEE International Solid-State Circu
38、its Conference44 of 49Capacitive Stacking in Mixer-First RF FEUse bottom plate switches instead of top plate switchesStack capacitor voltages from opposing phases to yield 2x voltage gain(6dB)3x voltage gain is also possible.9 Purushothaman JSSC22VINR90 C0 C270 C180 CVA1+-+-VB180CB180 VA18 Purushoth
39、aman JSSC20 2025 IEEE International Solid-State Circuits Conference45 of 49Some form ofRF Impedance up-transformationLow noise,low swing ADC(with bad FoM)A receiver without active linear gain?No LNA,but LNADCSome form of capacitor-stackingN-path circuitspassive voltage gain,filtering&downconversion5
40、 Nauta,ISSCC24 2025 IEEE International Solid-State Circuits Conference46 of 49Fundamental limits of power dissipationAnalog/Digital ConversionFigures of MeritThe“need”for analog pre-processingComparator v.s.amplifierNo more linear gain!ConclusionsOutline 2025 IEEE International Solid-State Circuits
41、Conference47 of 49 Focus on FoM has created unpractical ADCs But analog preprocessing burns the power ADCs have a too-easy life Lets try something else:Conclusionshigh risk,no gain!2025 IEEE International Solid-State Circuits Conference48 of 491 Vittoz,E.A.Future of analog in the VLSI environment.in
42、 IEEE International Symposium on Circuits and Systems.1990.2 R.H.Walden,“Analog-to-digital converter survey and analysis,in IEEE Journal on Selected Areas in Communications,vol.17,no.4,pp.539-550,April 1999.3 R.Schreier and G.Temes,Understanding Delta-Sigma Converters,New York:Wiley,2005.4 S van Zan
43、ten,et al.,”5.5 A Stacking Mixer-First Receiver Achieving 20dBm Adjacent-Channel IIP3 Consuming less than 25mW”ISSCC 20245 B.Nauta,“Racing Down the Slopes of Moores Law”Keynote ISSCC 20246 Bindra,H.S.,et al.,A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.IEEE Journa
44、l of Solid-State Circuits,2018.53(7):p.1902-912.7 M.Tohidian,I.Madadi,and R.B.Staszewski,“Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter,”IEEE JournalofSolid State Circuits,vol.49,no.11,pp.25752587,2014.8 Purushothaman,V.K.,et al.,A Fully Passive RF Front End With 13-d
45、B Gain Exploi5ng Implicit Capaci5ve Stacking in a Bofom-Plate N-Path Filter/Mixer.IEEE Journal of Solid-State Circuits,2020.55(5):p.1139-1150.9 Purushothaman,V.K.,et al.,Low-Power High-Linearity Mixer-First Receiver Using mplicit Capaci5ve Stacking With 3 Voltage Gain.IEEE Journal of Solid-State Cir
46、cuits,2022.57(1):p.245-259.References 2025 IEEE International Solid-State Circuits Conference49 of 49 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 ForumsHigh-speed ADCs for 100Gbps+Wireline TransceiversHeng Zhang1 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid
47、-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based vs.ADC-basedADC requirementsHow to build a 100Gbps+ADC-based Wireline Receiver High BW Linear Front-EndMassive Interleaving StructurePower/Area efficient Sub-ADCLow Jitte
48、r Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link2 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid-State Circuits ConferenceHigh Speed Wireline EverywhereISSCC 2025-Forum 4.2:3 of 565G/6G infrastructuresHyperscale Data Center for AI/ML/CloudAll connec
49、ted&ever-increasing TrafficHeng ZhangMetro Data Center Interconnect 2025 IEEE International Solid-State Circuits ConferenceData Center InterconnectISSCC 2025-Forum 4.2:4 of 56Heng Zhang High Speed Wireline Links:2nd Highest Power&Cost in AI ClusterSource:https:/ 2025 IEEE International Solid-State C
50、ircuits ConferenceIncreasing Need for BandwidthISSCC 2025-Forum 4.2:5 of 56Heng ZhangData Center market transitioning to AI/ML:Ethernet(Backend)&InfiniBand source:www.ethernetalliance.org 2025 IEEE International Solid-State Circuits ConferenceIncreasing Need for BandwidthHeng ZhangISSCC 2025-Forum 4
51、.2:6 of 56source:www.ethernetalliance.orgData Center switch:AI/ML Port Speeds&Serdes ShipmentsBW increases every two years 2025 IEEE International Solid-State Circuits Conference Both electrical and optical systems are trending away from simple NRZ signaling for higher speed links Linear Front-end c
52、ircuits and very high-speed ADCs are requiredIncreasingly Complex ModulationHeng ZhangISSCC 2025-Forum 4.2:7 of 56ModulationBits/SymbolBandwidthNRZ11 PAM4212PAMNlog2N1log2NDP-QPSK414DP-QAM6412112DP-QAMN2xlog2N12x log2NIMDDCoherentNRZPAM4QPSKQAM64 2025 IEEE International Solid-State Circuits Conferen
53、ceCoherent ApplicationISSCC 2025-Forum 4.2:8 of 56Heng ZhangSampling rate=Data rate x OSR x System-overhead/bit-per-symbolCoherent transceiver achieves much longer transmission distance and higher throughput compared to IMDDEnabling spectrally efficient modulation formatsRelieving bandwidth limitati
54、on of both electrical and optical channelsLeveraging the power from much more advanced DSP 2025 IEEE International Solid-State Circuits ConferenceEthernet and Optical link:Marching Towards Terabits9 of 562014199019921994199619982000200220042006200820102012MegabitsTerabits10BASE-T10 MB100BASE-T100 MB
55、1000BASE-T1 GB10GBT/40GE10 GB100GE4x25 GB2x50GBOC482.5 GBOC19210 GBOC76840 GBOTU4/LH100 GBCoherent100 GBEthernetOptical Transport201820162020Coherent200 GBCoherent600 GB200GE4x50GB 202420222026Coherent1.2T GBCoherent1.6TBGigabits400GE4x100GB Coherent800 GB800GE4x200GB 8x100GB 100Gbps+ADC-based Trans
56、ceiver inthis presentationHeng ZhangISSCC 2025-Forum 4.2:1.6TE8x200GB 2028Coherent2.4TB 2025 IEEE International Solid-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based vs.ADC-basedADC requirementsHow to build a 100Gbps+AD
57、C-based Wireline Receiver High BW Linear Front-EndMassive Interleaving StructurePower/Area efficient Sub-ADCLow Jitter Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link10 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid-State Circuits ConferenceAnalog tr
58、ansceiverPros:Power/area efficient for 25Gbps&below NRZ transceiversCons:does not scale well with process;sensitive to PVT;Extremely challenging DFE timing for higher rate PAMn applicationsAnalog vs.ADC based Wireline TransceiverISSCC 2025-Forum 4.2:11 of 56Heng ZhangAnalog Serdes Before/At 56GbpsAD
59、C/DSP basedAt/After 56Gbps,100Gbps+RX inRX inDSPADC-based transceiverScales well with process;less sensitive to PVT;Enables massive signal processing in digital domain,and digital correction for channel&circuit impairmentsBetter power efficiency for 100Gbps+LR applications 2025 IEEE International So
60、lid-State Circuits ConferenceAnalog Serdes Challenges for LR PAM4ISSCC 2025-Forum 4.2:12 of 56Frans,CICC 2019For 100Gbps+LR application,multiple taps of FFE and DFE are neededDesign ChallengesAll the buffers/summer stages preceding Slicer must have good BW and high linearityDFE timing:Slicer require
61、s very good sensitivity,and large input swingADC-based solution is advantageous at 56Gbps,and becomes the dominant architecture choice for 100Gbps and beyondHeng Zhang 2025 IEEE International Solid-State Circuits ConferenceAnalog Serdes becomes very complicated for 100Gbps+LR applicationsAnalog Serd
62、es for LR PAM4ISSCC 2025-Forum 4.2:13 of 56112Gbps:Quarter rate;3tap FFE+18 tap DFE56Gbps:Half rate;14tap DFEKocaman,ISSCC 2022Zhang,ISSCC 2023Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceDatapath:Linear signal processingPre-conditioning to release DSP complexityLarge Analog ban
63、dwidth while driving larger backend loading from TI-ADCInterleaver optimizationClock path:Low jitterMulti-phase generationAccurate Clkphase alignmentDSPADC calibration;EQ adaptation,CDR,etc.ADC-based Wireline ReceiverISSCC 2025-Forum 4.2:14 of 56Heng ZhangData PathClk Path 2025 IEEE International So
64、lid-State Circuits ConferenceTime-interleave SAR ADCs with 6-8bit resolution satisfied the requirements by wireline communicationsAchieves very high speedGood power efficiency:no power-hungry amplifier;low VDD;scales well with processState-of-Art High-Speed ADCsISSCC 2025-Forum 4.2:15 of 56ADC for 1
65、00Gbps+wireline transceiversB.Murmann:1997-2024Heng Zhang 2025 IEEE International Solid-State Circuits ConferencePAM4 LR application is pushing the forefront for AFE PreEQ capability:1530dBNyquistStringent Power&Area requirements:increased port density,crosstalk issue,etc.7bit ADC with Time-interlea
66、ved SAR architectureADC-based 100Gb/s+PAM4 TransceiversISSCC 2025-Forum 4.2:16 of 56DesignM.LaCroix ISSCC2021C.LiuCICC 2025Z.Guo ISSCC2022H.Park ISSCC2023J.Wang ISSCC2024D.PfaffISSCC 2024Process7nm CMOS7nm CMOS5nm CMOS5nm CMOS5nm CMOS3nm CMOSData rate116Gb/s112.5Gb/s112Gb/s112.5Gb/s212Gb/s224Gb/sADC
67、 architecture7bit TI-SAR7bit TI-SAR7bit TI-SAR7bit TI-SAR7bit TI-SAR7bit TI-SARMax sample rate58GS/s56GS/s56GS/s56GS/s106GS/s112GS/sAFE Pre-EQ22dB2224GHz16dB28GHz18dB30dB20GHzN/A20dB50GHzEQ in DSP25 TAP FFE+2 TAP DFE24 TAP FFE+1 TAPDFE+MLSD30 TAP FFE+1 TAP DFE32 TAP FFE+1 TAP DFE44Tap FFE+1Tap DFE+M
68、LSD24 TAP FFE+1 TAPDFE+MLSDRX SNDRN/A36dBDC33dB28G36dB DC 35dB DC28dB 28G36dBDC30dB40G31dBDC26dB50GBER Loss1e-545dB3e-8 42dB1e-9 40dB7e-6 48dB1e-12*1e-6 40dBRX Power/lane 223mW177mW141mWN/A288mW448mWPower efficiency1.9pJ/b1.57pJ/b1.3pJ/bN/A1.36pJ/b2pJ/b*optical channelHeng Zhang 2025 IEEE Internatio
69、nal Solid-State Circuits ConferenceFour Streams of Data Carried by a Single-LightFour Synchronized ADC&DAC at Electrical/Optical InterfaceGenerate and capture four streams of analog signals that are carried by the same light in DP-QAM formatRequired precise phase alignment between XI,XQ,YI,and YQ ch
70、annels to extract the phase information in coherent transmissionSupport flexible modulation,data rate and transmission range ADC-Based Coherent Optical TransceiverISSCC 2025-Forum 4.2:17 of 56Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceCoherent application pushes the forefront
71、for ADC sampling rate&Datapath BWMust be reliable:e.g.difficult to replace submarine devices in long-haul application8bit ADC;up to 200Gsps sampling rateADC-based 100Gb/s+Coherent TransceiversISSCC 2025-Forum 4.2:18 of 56DesignJ.Cao ISSCC17G.Li ISSCC24R.L.Nguyen ISSCC21R.L.Nguyen ISSCC24Process20nm
72、CMOS16nm CMOS7nm CMOS5nm CMOSData rate100Gbps(DP-QPSK)600Gbps(DP-QAM64)400Gbps(DP-QAM16)800GbpsADC Architecture8bit TI SAR8bit TI SAR8bit TI SAR8bit TI SARMax Sample Rate4x 69GS/s4x 105GS/s4x 97GS/s4x 200GS/sRX BW 20GHz40GHz40GHz50GHzRX SNDR 39.7dB DC32.5dB 19G42.8dB DC39.2dB 20.9G41.1dB DC35.1dB 19
73、.4G41.5dB DC36.1dB 21GPower/laneRX:950mWRX:698mWRX:311mW(no VGA)RX:400mWFOMh,sf(dB)138.119G148.020.9G147.019.4G150.121GHeng Zhang=+1010(2)2025 IEEE International Solid-State Circuits ConferenceHigher analog bandwidthE.g.112Gbps224Gbps requires doubling the RX bandwidth(assuming the same PAM4 modulat
74、ion to maintain backward compatibility)More demanding signal equalizationAFE preEQ+powerful DSPHigher sampling rate and Larger#of sub-ADCs AFE needs to drive bigger loadingLower clock jitter and circuit noiseBetter power efficiencyInnovative circuit techniques in both the Data path and Clock path is
75、 a mustPaths to Achieve Higher Data RateISSCC 2025-Forum 4.2:19 of 56Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based vs.ADC-basedADC requirementsHow to build a 100Gbps+ADC-based
76、Wireline Receiver High BW Linear Front-EndMassive Interleaving StructurePower/Area efficient Sub-ADCLow Jitter Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link20 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid-State Circuits ConferenceRX Frontend:Block
77、s&FunctionsISSCC 2025-Forum 4.2:21 of 56VGA:Programmable broadband gain;keeping ADC input to the required portion of full scale;with various RX input amplitudesHeng ZhangTermination:Provide broadband matching to the channel characteristic impedance;minimizing signal reflections that are difficult to
78、 equalize.CTLE:Shapes the equivalent channel to have a well-controlled PMR to relax both the ADC and DSP design specifications.2025 IEEE International Solid-State Circuits ConferenceHigh BWAFE bandwidth and ADC sampling rates are continuously pushed to the edge of thetechnology limits.Doubling the d
79、ata rate requires 2x BW(with same PAM4 modulation for backwardcompatibility);E.g.112Gbps224Gbps,AFE BW requirement from 28GHz 56GHzPeakingAnalog Pre-EQ provides a good match for the channel TF to minimize the ADC input ISI.This relaxes the required ADC resolution&subsequent digital equalization.Driv
80、abilityTo push sampling speed well beyond 50GS/s,very large ADC parallelization is needed,translating into big loading for the front end.Linearity&NoiseHigher BW lower noise power spectral densityMore complex modulation scheme better linearity requiredRX Frontend:Design MetricsISSCC 2025-Forum 4.2:2
81、2 of 56Heng Zhang 2025 IEEE International Solid-State Circuits Conference Distributed input matching network to isolate the capacitance from Pad,ESD,1st-stage CTLE,and Rterm Inductor size chosen to ensure Characteristic impedance Rterm Input impedance preserved up to high frequenciesRX Frontend:Term
82、inationISSCC 2025-Forum 4.2:23 of 56Kiran,VLSI 21Heng ZhangPtaff,ISSCC 24 2025 IEEE International Solid-State Circuits ConferenceTransimpedance gain stage-based LEQ with on-chip inductor feedback have been widely used in state-of-art designs since 2014Output current from the input diffpair is fed to
83、 the TIA stagesTIA amplifier is configured by single-stage inverter-based circuitTail current to maintain the DC biasVery effective to provide peaking,with good bandwidth,small noise/distortion,efficient power and areaCompared to multi-stages of CMLRX Frontend:Gm+TIAISSCC 2025-Forum 4.2:24 of 56Kimu
84、ra,JSSC14Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceComplementary stage doubles the transconductance for a given biasing current lower noise and smaller power;Inductive peaking+source degeneration to shape the frequency responseRX Frontend:Complimentary/Inverter-basedISSCC 202
85、5-Forum 4.2:25 of 56Khairi JSSC 23Heng ZhangPtaff,ISSCC 24Removed tail current sources Diode-connected inverter used as loadHigh-freq.peaking:by coupling the signal to next-stage input through transformerLower freq.peaking:by signal coupling of gm2/gmd2 gain stage+parallel Rc&Cc 2025 IEEE Internatio
86、nal Solid-State Circuits ConferenceCML-based VGAAdjust signal swingReject input CM rippleLarge BandwidthTcoil for BW extensionDistortion cancellation Two differential pairs connected in opposite polarityCancel distortion without reducing gain significantlyCancellation Relies on Ratios of Devices;Ins
87、ensitive to PVTRX Frontend:Linearity ImprovementISSCC 2025-Forum 4.2:26 of 56IbiasVin+Vin-Vout+Vout-gm1gm2Rs2Rs1I01I02Li,ISSCC 24Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based v
88、s.ADC-basedADC requirementsHow to build a 100Gbps+ADC-based Wireline Receiver High BW Linear Front-EndMassive Interleaving StructurePower/Area efficient Sub-ADCLow Jitter Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link27 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE In
89、ternational Solid-State Circuits ConferenceDominant architecture for High-speed ADC-DSP based wireline receiversReduces#of critical Clock phases&total cap presented to inputAFE drives R1x Buf1;Each Buf1 drives R2x Buf2;Each Buf2 drives Rsx Sub-ADCTotal#of Interleave:N=R1xR2xRs Sub-ADC speed:Fs/N#of
90、critical Sampling Clk phases:R1 x R2 THA sampling speed:Fs/(R1xR2)Two-Rank Time-Interleaving:MotivationISSCC 2025-Forum 4.2:28 of 56Heng Zhangfrom AFERank2 BufferRank1 BufferR1R2Rs 2025 IEEE International Solid-State Circuits ConferenceTwo-Rank Time-Interleaving:Design MetricsHeng ZhangISSCC 2025-Fo
91、rum 4.2:29 of 56Kumar,ISSCC 2023How to pick interleaving factors(R1,R2,Rs)to achieve an“optimal”design?A“Divide-and-conquer”problemPower&Area:determined by both Sub-ADC&InterleaverTheres”Optimal”Sub-ADC speed for specific resolution&processSpeed,BW,Timing skew/BW mismatch:determined by InterleaverKr
92、upnik JSSC 2020Khairi ISSCC 2022 2025 IEEE International Solid-State Circuits ConferenceHeng ZhangISSCC 2025-Forum 4.2:30 of 56Two-Rank Time-Interleaving:OptimizationDatarate,Modulation scheme,OSRSampling rate Fs,ResolutionOptimal Sub-ADC speedInterleaving factor NVDD,ProcessDetermine R1&Design Buf1
93、BW&Noise BudgetDetermine R2&Design Buf2Smaller(R1xR2)fewer#of critical clkphases&better clk matchingLarger(R1xR2)longer track window,easier settlingSmaller R1better BW&NoiseRs=N/(R1xR2)StartAre BW,Noise,THD,Settling,Power OK?EndYesNo 2025 IEEE International Solid-State Circuits ConferenceA High inte
94、rleaving factor of tens to hundreds is necessaryN1:2N facilitate symmetric signal routing&clk phase generationTheres”Optimal”Sub-ADC speed for specific resolution&processTwo-Rank Time-Interleaving:ExamplesISSCC 2025-Forum 4.2:31 of 56Wang,ISSCC 24Pfaff,ISSCC 24Li,ISSCC 24Nguyen,ISSCC 24Process5nm CM
95、OS3nm CMOS16nm CMOS5nm CMOSArchitecture7bit TI-SAR7bit TI-SAR8bit TI-SAR8bit TI-SARSampling rate(Fs)106GS/s112GS/s105GS/s200GS/sRX Bandwidth55GHz50GHz40GHz50GHzR11681616R28101216THA Sampling Speed6.625G14G6.56G12.5GSub-ADC Speed 828M1.4G547M781M#of SAR12880192256SNDR36dBDC30dB40G31dBDC25.5dB50G42.8d
96、BDC39.2dB20.9G41.5dBDC36.1dB21GRX Power288mW448mW698mW400mWFOMS,hf(dB)*142.640G136.550G148.020.9G150.120GHeng Zhang=+1010(2)2025 IEEE International Solid-State Circuits ConferenceFour buffers at rank1 to minimize channel-to-channel coupling.TH1 clocking ensures that within any of the four groups of
97、1 switches,only one switch will be conducting at a time.Two-Rank Time-interleaving:ExamplesISSCC 2025-Forum 4.2:32 of 56Li,ISSCC 24ck12ck8ck4VGA 4SSFBUFSkew Cali.16CK_4Tfrom PLLSAR0,0SAR0,1SAR0,11Token&Clock Gen.SAR0,10.SAR0,011 Retimerckbckckbckck0,0ck0,1ck0,10ck0,11ck0SAR4,011 RetimerSAR8,011 Reti
98、merSAR12,011 RetimerClock and Global TokenSAR1/5/9/13,111SAR2/6/10/14,111SAR3/7/11/15,111ck1/5/9/13ck2/6/10/14ck3/7/11/1516Global Retimer4SAR0/4/8/12,111Rank1Rank212L0,L4,L8,L12L1,L5,L9,L13L2,L6,L10,L14L3,L7,L11,L15Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceRank1 Clock16 of 1
99、clocks are 1/FSapart;alignment controlled by timing-skew calibration loop4 samplers driven by the same buffer1 are 4/FSapart and non-overlapping;The use of 25%duty-cycle clocks reduces the buffer1 loadingRank1&Rank2 Clock alignment is critical,e.g.ensure non-overlap between 1&2Two-Rank Time-interlea
100、ving:ExamplesISSCC 2025-Forum 4.2:33 of 561L21L31L41L81L121L15.1L11L0.THDriven By the same Buffer1Rank1 Clock Rank1&Rank2 Clock relationshipHeng ZhangTHTHHTHTTH12,02,12,7.11Li,ISSCC 24 2025 IEEE International Solid-State Circuits ConferenceRank1 Clk:Fast path;Critical sampling edge w minimize jitter
101、&skew;“A”“B”Rank2 Clk:Slow path;“A”“C”Two paths delay difference varies over PVTdegrading alignment“Aligner”circuit added to adjust Rank2 Clk position to ensure optimal alignment over PVTA calibration loop controls alignment to provide proper delayRank1&Rank2 Timing AlignmentISSCC 2025-Forum 4.2:34
102、of 56LaCroix,ISSCC21Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based vs.ADC-basedADC requirementsHow to build a 100Gbps+ADC-based Wireline Receiver High BW Linear Front-EndMassive
103、 Interleaving StructurePower/Area efficient Sub-ADCLow Jitter Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link35 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid-State Circuits ConferencePower&Area efficiency drives Sub-ADC design in Massive Time-interl
104、eaveSAR is the dominant choice for high-speed wirelineCompact layout area:reduces parasitic propagated to the front end thus enables high BWThe most power efficient ADCs:driven by both process scaling&design innovationsSAR Power reduction:Block levelComparatorPre-amp techniques DACSplit cap;Custom M
105、oM Cap LayoutSAR LogicAsynchronousSAR Power reduction:Architecture levelMulti-comparator structureAnalog Adaptive Voltage Scaling(A-AVS)*p.s.Techniques picked here are proven for wireline application 68bit,500M1.4Gsps Sub-ADCSub-ADC:Design MetricsISSCC 2025-Forum 4.2:36 of 56Heng Zhang 2025 IEEE Int
106、ernational Solid-State Circuits ConferenceSAR Power Reduction:ComparatorHeng ZhangISSCC 2025-Forum 4.2:37 of 56Double tail Feed-backward(DTFB)Bheemisetti,JSSC 2024 StrongArm:baseline comparator design;simple&widely usedDouble tail:higher gain,lower noise and offsetDTFB:further increasing gain and sp
107、eed,with lower noise simultaneouslyDouble tailElzakker,ISSCC 2008 StrongArmKobayashi,VLSI 1992 2025 IEEE International Solid-State Circuits ConferenceDifferential Top-plate SamplingBetter SNR than bottom-plate samplingBody effect neglecgible in advanced processcharge injection is linearSplit Capacit
108、or Array DAC37%lower switching energy than conventional,with slightly faster speedMaintain constant common-mode during conversion ensure comparator working at optimal regionSAR Power Reduction:DACHeng ZhangISSCC 2025-Forum 4.2:38 of 56Frans,CICC 2019Ginsburg,JSSC 2007 2025 IEEE International Solid-S
109、tate Circuits ConferenceTwo-comparator SARMSB decisions use coarse comparator(high noise/low power)to save energyLSB decisions use fine comparator(low noise)to ensure conversion accuracyLoop-unrolled SAR#of comparator used=#of conversion bitsMemory-less schedule reduces power and critical path laten
110、cySAR Power Reduction:Multi-ComparatorISSCC 2025-Forum 4.2:39 of 56Loop-unrolled SAR Bheemisetti,JSSC 2024Heng ZhangTwo-comparator SARGiannini,ISSCC 2008 2025 IEEE International Solid-State Circuits ConferenceSAR Power Reduction:Analog AVSISSCC 2025-Forum 4.2:40 of 56Sub-ADCs are powered from a dyna
111、mically controlled power supplyAverage conversion time for each asynchronous SAR sub-ADC is measured and used to inform upon optimal power supply conditionsMeasure of the conversion speed from bits 6 to 1Average of many samplesRepresented by CONV_MON duty cycle(a voltage)LaCroix,ISSCC 19 Heng Zhang
112、2025 IEEE International Solid-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based vs.ADC-basedADC requirementsHow to build a 100Gbps+ADC-based Wireline Receiver High BW Linear Front-EndMassive Interleaving StructurePower/Ar
113、ea efficient Sub-ADCLow Jitter Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link41 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid-State Circuits ConferenceMulti-phase Generation with desired dutycycleE.g.25%for 1 to ensure non-overlap if Buf1 driving 4
114、x Buf2Critical Sample edgeUltra-Low JitterVery accurate phase matchingRX Clocking:Design MetricISSCC 2025-Forum 4.2:42 of 56Heng ZhangRank1&2 Clock AlignmentData PathClk PathCritical Sample edge 2025 IEEE International Solid-State Circuits Conference Clock jitter sets the envelope for ADC high-frequ
115、ency ENOB hence the link BER For given jitter:10 x increase in Fin20dB drop in SNDR State-of-art:50fsRX Clocking:Low Jitter ISSCC 2025-Forum 4.2:43 of 56Heng ZhangB.Murmann:1997-2024ADC for 100Gbps+wireline transceivers 2025 IEEE International Solid-State Circuits ConferenceMulti-Phase GenerationISS
116、CC 2025-Forum 4.2:44 of 56Heng ZhangRX&TX architecture designPerformance,Power&Area budgetPLL&Global Clkdistribution Freq.Input freq.Output freq.Divider,Super-harmonic ILO,etcInput freq.=Output freq.DLL,PI Polyphase Filter,1stharmonic ILO,etcInput freq.Output freq.MDLL,Sub-harmonic ILO,etc 2025 IEEE
117、 International Solid-State Circuits ConferenceMulti-phase Generation using DividerHeng ZhangISSCC 2025-Forum 4.2:45 of 56Wang,ISSCC 2024VGA directly driving 16 TAH switches,i.e.AFE merged with Rank1 Buffer2UI pulse width&16UI clock period12.5%dutycycle for 1RX PLL sends differential 4UI clock to IQG
118、EN through clock distributionDivider takes 4-phase 4UI clock input to generate 16 phases of 16UI clocksDelay line adjusts the 16 clock phases to compensate for systematic&random clock-skewA pulse generator uses 2 clock phases 2UI apart to generate the 12.5%duty cycle for 1 2025 IEEE International So
119、lid-State Circuits ConferenceILO1 delivers 8 clock phases to the ADCILO2 generates 8 clock phases to a 7-bit PI which interpolates between two ILO2 clock phases spaced 45degree part.Clock can be continuously shifted with a resolution of 1/128 UI,required for RX CDRMulti-GHz injection locking bandwid
120、th of the ILO rejects majority of PLL phase noiseMulti-Phase Generation using ILOISSCC 2025-Forum 4.2:46 of 56Ptaff,ISSCC 24Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceSkew CorrectionISSCC 2025-Forum 4.2:47 of 56Cao,ISSCC 17 Popular solution:measure errors in digital domain,and
121、 compensate via adjustable delay lines Heng ZhangPtaff,ISSCC 24 2025 IEEE International Solid-State Circuits ConferenceOutlineHigh speed Wireline Links:Trends and ApplicationsADC-based Transceiver architecturesAnalog-based vs.ADC-basedADC requirementsHow to build a 100Gbps+ADC-based Wireline Receive
122、r RX Front-EndMassive Interleaving StructureUnit ADCLow Jitter Multiphase ClockingRecent developments:600Gbps ADC-based Coherent Optical link48 of 56Heng ZhangISSCC 2025-Forum 4.2:2025 IEEE International Solid-State Circuits ConferenceIntegrated Variable Gain Amplifier192 SAR Time-Interleaved by 2-S
123、tage T/H105GSps 8bit ADC for 600Gbps CoherentHeng ZhangISSCC 2025-Forum 4.2:49 of 56ck12ck8ck4VGA 4SSFBUFSkew Cali.16CK_4Tfrom PLLSAR0,0SAR0,1SAR0,11Token&Clock Gen.SAR0,10.SAR0,011 Retimerckbckckbckck0,0ck0,1ck0,10ck0,11ck0SAR4,011 RetimerSAR8,011 RetimerSAR12,011 RetimerClock and Global TokenSAR1/
124、5/9/13,111SAR2/6/10/14,111SAR3/7/11/15,111ck1/5/9/13ck2/6/10/14ck3/7/11/1516Global Retimer4SAR0/4/8/12,111Li,ISSCC 2024 2025 IEEE International Solid-State Circuits ConferenceData Path BandwidthHeng ZhangISSCC 2025-Forum 4.2:50 of 56Measure the loading of ADCInputBufferS/HVGAADC-3dB Bandwidth 40GHzL
125、i,ISSCC 2024 2025 IEEE International Solid-State Circuits ConferenceSFDR 50.7dBInterleaving Spur 6bit up to 25GHzADC ENOB and SpectrumISSCC 2025-Forum 4.2:51 of 56Heng ZhangLi,ISSCC 2024 2025 IEEE International Solid-State Circuits ConferenceRMS Jitter 10K-100MHz=51.4fsCritical to SNDR of high-speed
126、 ADC/DACClock JitterISSCC 2025-Forum 4.2:52 of 56RMS Jitter 10kHz-100MHzHeng ZhangLi,ISSCC 2024 2025 IEEE International Solid-State Circuits ConferenceFlexible Modulation Format and Data RateDP-QAM64 enabled by ADC/DAC with excellent SNDROptical Loopback ConstellationsISSCC 2025-Forum 4.2:53 of 5640
127、0Gbps DP-QAM16600Gbps DP-QAM64200Gbps DP-QPSKHeng ZhangLi,ISSCC 2024 2025 IEEE International Solid-State Circuits ConferenceADC-based Transceivers are the dominate architecture at 100Gbps+,especially for long reach applications with PAM-N modulationOptical Coherent applications are pushing the foref
128、ront for BW and speed:1.6Tbps(per color per fiber)Higher analog bandwidth,lower clock jitter,and more demanding equalization are the main circuit challenges for higher data rateState-of-Art circuit techniques in the data path and clock path are presentedHigh BW Linear Front-EndMassive Interleaving S
129、tructurePower/Area efficient Sub-ADCLow Jitter Multiphase ClockingWireline community is working hard to enable the AI/ML and other emerging applications in the near futureSummaryISSCC 2025-Forum 4.2:54 of 56Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceKey ReferencesThe Future of
130、 Electrical Signaling”,Technology Exploration Forum,Oct.22-23,2024,www.ethernetalliance.orgB.Murmann,“ADC Performance Survey 1997-2024,”https:/ Latest High-Speed Wireline Serdes Technology”,CICC 2024,Educational Session ES3-1Y.Frans,“ADC-based Wireline Transceiver”,CICC 2019,Educational Session ES3-
131、3K.Zheng,“System-Driven Circuit Design for ADC-Based Wireline Data Links”,Ph.D.Dissertation,Stanford University,2018N.Kocaman et al.,“An 182mW 1-60Gbps Configurable PAM4/NRZ Transceiver for High-Density IOs in 7-nm FinFET Technology”,ISSCC 2022,paper 6.4.B.Zhang et al.,“A 112Gb/s Serial Link Transce
132、iver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in7nm FinFET Technology”,ISSCC 2023,paper 6.1.D.Cui et al.,A 320mW 32Gb/s 8b ADC-Based PAM-4 Analog Front-End with Programmable Gain Control and Analog Peaking in 28nmCMOS,ISSCC 2016,paper 3.2.M.LaCroix et al.,“A 60Gb/
133、s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at32dB Loss”,ISSCC 2019,paper 6.2.M.LaCroix et al.,“A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and52dB in PAM-2”,ISSCC 2021,paper 8.4.Kiran et al.
134、,“A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS”,VLSI 2021,C21-1A.Khairi et al.,“A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long ReachChannels”,ISSCC 2022,paper 6.1.Z.Guo et al.,“A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach
135、 Transceiver with 50dB Channel Loss in 5nm FinFET”,ISSCC 2022,paper 6.2.H.Park et al.,“A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET”,ISSCC 2023,paper 6.2.J.Wang et al.,“A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5n
136、m FinFET”,ISSCC 2024,paper 7.1.ISSCC 2025-Forum 4.2:55 of 56Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceD.Pfaff et al.,“A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS”,ISSCC 2024,paper 7.3.C.Liu et al.,“An 800GbE PAM-4 PHY transceiver that supports 42dB copp
137、er and direct-drive optical applications in 7nm”,CICC 2025J.Cao et al.,”A Transmitter and Receiver for 100Gb/s Coherent Networks with Integrated 4x64GS/s 8bit ADCs and DACs in 20nmCMOS,ISSCC 2017,paper 29.2.R.L.Nguyen et al,“A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and
138、Sub-35fJ/conv-step for400Gb/s Coherent Optical Applications in 7nm FinFET”,ISSCC 2021,paper 8.6.G.Li et al.,A 600Gb/s DP-QAM64 Coherent Optical Transceiver Front-End with 4x105GS/s 8b ADC/DAC in 16nm CMOS,ISSCC2024,paper 18.1.R.L.Nguyen et al,“A 200GS/s 8b 20fJ/c-s Receiver with 60GHz AFE Bandwidth
139、for 800Gb/s Optical Coherent Communications in5nm FinFET”,ISSCC 2024,paper 18.4.H.Kimura et al.,“A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision FeedbackEqualizer in 28 nm CMOS”,JSSC,Dec.2014,pp.3091-3103.S.Kumar,“A 750mW 24GS/s 12b Time-Interleaved ADC
140、for Direct RF Sampling in Modern Wireless Systems”,ISSCC 2023,paper17.4.T.Kobayashi,“A Current-mode Latch Sense Amplifier and a Static Power Saving Input Buffer for Low-power Architecture”,VLSI 1992,pp 28-29.M.Elzakker et al.,“A 1.9W 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC”,ISSCC 2
141、008,paper 12.4.C.Bheemisetti et al.,“A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a224-Gb/s SerDes Receiver”,JSSC 2024,early accessX.Tang et al.,“Low-Power SAR ADC Design:Overview and Survey of State-of-the-Art Techniques”,TCAS I,June 2022,pp.224
142、9-2262B.P.Ginsburg et al.,“500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC”,JSSC,Apr.2007,pp.739-747.Key ReferencesISSCC 2025-Forum 4.2:56 of 56Heng Zhang 2025 IEEE International Solid-State Circuits ConferenceDevelopments and Challenges in High-Speed Continuous-Time ADCs for Wideban
143、d Wireless CommunicationsSharvil PatilISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications1 of 49 2025 IEEE International Solid-State Circuits ConferenceEvolution of Wireless Basestations(BTS)1G2G3G4G5G(FR1)Onset of Deployment198019
144、90200020102018No.of Tx/Rx ChannelsFDD1/21/21/22/24/4TDD-8/88/864/64Max RF Freq GHz1.01.02.12.64.0Data Rate Mbps 0.00240.00642100200Signal BW MHz0.030.2520100Transceiver BW MHzN/A0.2020200400Chuang 2022 1Bandwidth(BW)Spectrum availabilityCarrier aggregationChannel#Spectrum availabilitymMIMO,Beamformi
145、ng2 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceReceiver(Rx)ArchitecturesDSPDirect RFFlexibleFreq planningPowerFootprintCostLNAXADCZero-IF(This talk)Simplified fil
146、teringPowerIntegrationCostGood for multichannelLNAXADC0/90LO3 of 49DSPADCISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceAD9371 ADRV9009 ADRV9026 ADRV9040Process technology
147、 nm65652816Release year2014201620182021Number of Rx Channels2248Rx Bandwidth MHz100200200400ADI Zero-IF TRx for Wireless BTSChuang 2022 1Channel#BandwidthNeed ADCs with:Increasing BWLow power/channel4 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideba
148、nd wireless communications 2025 IEEE International Solid-State Circuits ConferenceGoal:Provide clean spectrum with low powerADC Specifications for Zero-IF RXfBWfInterferersSignalNoiseDistortionBWADC5 of 49SpecValueNSD dBFS/Hz150SFDR dB 80BW MHz20 400PowerLow(ADC dominates)(I or Q channel)ISSCC 2025-
149、Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceADC Architecture for Zero-IF RXAD9371 ADRV9009 ADRV9026 ADRV9040Process technology nm65652816Release year2014201620182021Number of Rx C
150、hannels2248Rx Bandwidth MHz100200200400Continuous-Time(CT)Delta-Sigma(DS)ADCCT Pipelined(CTP)ADCCT benefits+Higher BW(This Talk)6 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits
151、 ConferenceOutlineMotivationBasestation Radio NeedsLimitations of Continuous-Time Delta-Sigma(CT DS)ADCsTechnology Disruption:Continuous-Time PipeliningArchitectural EvolutionWhats Next?7 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless c
152、ommunications 2025 IEEE International Solid-State Circuits ConferenceWhy CT DS ADC?Higher BW&lower power than DT DSEasy to drive Resistive input impedanceRelaxed AA filter(AAF)Implicit anti-aliasing+subADC-+subDACCT Loop FilterINOUTIn-band gain 1dBBW MHzFOM=NSD 10 log10(P)1 10 50 100 500 1000 150155
153、160165170175180185DT DSCT DSMurmann 28 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceSystem Benefits of CT ApproachNSD=150dBFS/HzNSD=150dBFS/HzPTOT=10mW(FOM=170dB)NS
154、D=155dBFS/Hz for each block(0dB gain)P=33mW for each(FOM=170dB)PTOT=100mWCT DS ADCs excel in fully-integrated wireless RX 33mW33mW33mW10mWFOM=NSD 10 log10(P)Slide courtesy:Hajime Shibata9 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless c
155、ommunications 2025 IEEE International Solid-State Circuits Conference1 10 50 100 500 1000 150155160165170175180185DT DSCT DSBW Limitations of CT DS ADCsdBBW MHzFOM=NSD 10 log10(P)BW 500 MHzFeedback requires oversampling for stabilityBW 500 MHz Fs 20 GHz Power10 of 49+subADC-+subDACCT Loop FilterINOU
156、TIn-band gain 1ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceOutlineMotivationBasestation Radio NeedsLimitations of CT DS ADCsTechnology Disruption:Continuous-Time Pipeli
157、ningArchitectural EvolutionWhats Next?11 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferencePushing BWBWSystem PowerDT DSCT DSDT PipeCT Pipe?FeedbackFeedforward12 of 49IS
158、SCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceDT PipelinesubADCsubDACBackendCKCsampDriverDT ADCNoise,HD3,KickbackDT Amp13 of 49AAF+-+ISSCC 2025-Forum 4.3:Developments and c
159、hallenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCT PipeliningsubADCCKCsampDriverBackendDT Amp14 of 49AAFsubDAC+-+ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband w
160、ireless communications 2025 IEEE International Solid-State Circuits ConferenceCT PipeliningsubADCCT signalDriverBackendDT Amp15 of 49AAFsubDAC+-+ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-Stat
161、e Circuits ConferenceCT PipeliningsubADCCT signalsDriverBackendDT AmpDelay16 of 49AAFsubDAC+-+ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCT PipeliningsubADCCT signalsD
162、elayDriverBackendCT AmpCTP17 of 49AAFsubDAC+-+AnalogDelayISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communicationsShibata,ISSCC 2017 3 2025 IEEE International Solid-State Circuits ConferenceDigital Reconstruction Filter(DRF)+subADC-+AAFD
163、riverCTP1()+()Multi-tap filter 4 Combines stage outputs Needs calibrationDRF18 of 494 Pavan,TCAS-II 2021AnalogDelaysubDACISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP
164、 Benefits+subADC-+DriverCTP1()+()DRFNo feedback Higher BW than CT DS19 of 49AAFAnalogDelaysubDACISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits Conference1 10 50 100 500 1000 1501551
165、60165170175180185DT DSCT DSCTPCTPs Achieve BW 500 MHzdBBW MHz10 dB/dec.FOM=NSD 10 log10(P)Murmann 220 of 49CTPISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceSystem Benefit
166、s+subADC-+subDACAnalogDelayBackendCT AmpCTPResistive ZinLike a CT DS ADCRelaxedDriverAAF21 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceSystem Benefits+subADC-+Back
167、endCT AmpCTPIs antialiasing filter relaxed too?Need ADC signal transfer function(STF)22 of 49RelaxedDriversubDACAnalogDelayISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceC
168、TP Signal Transfer Function(STF)xsubADC+subADCAnalog delayCT amp()()DRFADC output()subDAC23 of 49+1/()+ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP Signal Transfer F
169、unction(STF)1/()+()()+subADCsubDACsubADC24 of 49xsubADC()()ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP Signal Transfer Function(STF)1/()+()1/()()+subADCsubDACsubADC
170、25 of 49xsubADC()()1110ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP Signal Transfer Function(STF)1/()+26 of 49xsubADC()()ADC outputISSCC 2025-Forum 4.3:Developments
171、and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP Signal Transfer Function(STF)()()1/()()()subADCsubDACsubADC27 of 49xADC outputISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-ti
172、me ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits Conference=()CTP Signal Transfer Function(STF)()()ADC output1/()()()subADCsubDACsubADC28 of 49x02020400123456Freq GHzdBFsBWCT AAFSampling+aliasingAlias suppression5 Basavaraj,TCAS-II 2022ISSCC 2025-Forum 4.3:De
173、velopments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP Signal Transfer Function(STF)()()1/()()()CTP offers implicit AAFLike a CT DSsubADCsubDACsubADC29 of 49x=()ADC outputCT AAFSampling+aliasingAlia
174、s suppressionISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP System Benefits+subADC-+subDACAnalogDelayBackendCT AmpCTPEnables energy-efficient Rx BW than a CT DSRelaxed
175、DriverRelaxed AAF30 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceAliasFsOverload Near Fs+subADC-+CTPLimits blocker level near Fs31 of 49BlockerOverloadNRZfffffsubDA
176、CAnalogDelayRelaxedDriverRelaxed AAFISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceOutlineMotivationBasestation Radio NeedsLimitations of CT DS ADCsTechnology Disruption:C
177、ontinuous-Time PipeliningArchitectural EvolutionWhats Next?32 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCTP ADCs1 10 50 100 500 1000 150155160165170175180185DT D
178、SCT DSCTPdBBW MHz10 dB/dec.FOM=NSD 10 log10(P)31067Murmann 233 of 49CTPISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceFirst Fully CT Pipelined ADC 35 stages,=200 Fs=9 GHzB
179、W=1125 MHz34 of 49Shibata,ISSCC 2017 3ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceFirst Fully CT Pipelined ADC 3Shibata,ISSCC 2017 3NBW=824kHzA=0dBFSA=80dBFSAmplitude d
180、BFS/NBWNSD dBFS/HzFrequency MHz1125MHz BW(10 to 1135MHz)164dBFS/Hz ave.NSD156dBFS/Hz ave.NSDfin=1130MHzSTF5 stages,=200 Fs=9 GHzBW=1125 MHzNSD=164 dBFS/HzPower=2.3 WOff-chip DRF40 dB alias rejection35 of 49FsBWISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wi
181、deband wireless communications 2025 IEEE International Solid-State Circuits ConferenceImproving Power&Integration 617-level6.4GS/sVCO ADCADCinputADCoutputClockinput2nd-order LPF:fC 800MHzDC gain:7DRFShibata,ISSCC 2020 636 of 492 stagesOn-chip DRF,=800 ISSCC 2025-Forum 4.3:Developments and challenges
182、 in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceImproving Power&Integration 62 stagesOn-chip DRF,=800 Fs=8 GHzBW=800 MHzNSD=148 dBFS/HzPower=230 mWNBW=146kHzSmall-signal average NSD:148dBFS/Hz800MHz BW40 dB alias rejecti
183、on37 of 49Shibata,ISSCC 2020 6ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceImproving Bandwidth38 of 49+-+subDACDelayCT AmpVCOADCCKCKCKDigital Reconstruction FilterOutput
184、 FsInputSub-ADC-sub-DAC hand-off limits Fs and BWsub-ADCsub-DACISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceImproving BandwidthSub-ADC-sub-DAC hand-off limits Fs and BWI
185、nterleave sub-ADC-sub-DAC 7-8Mittal,VLSI 2023 739 of 49VCOADCCKDigital Reconstruction FilterOutput FsPavan,JSSC 2024 8Manivannan,TCAS-I 2022 9+-+subDACDelayCT AmpCKCKCKCKInputsub-ADCsub-DACISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless commu
186、nicationsVCOADC 2025 IEEE International Solid-State Circuits ConferenceImproving Bandwidth 7Sub-ADC-sub-DAC hand-off limits Fs and BWInterleave sub-ADC-sub-DAC 7-8Fs=6.4 GHz(CK rate)BW=1000 MHz,=400 40 of 49+-+subDACDelayCT AmpVCOADCCKCKCKCKCKDigital Reconstruction FilterOutput FsInputMittal,VLSI 20
187、23 7sub-ADCsub-DACISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceImproving Bandwidth 7Sub-ADC-sub-DAC hand-off limits Fs and BWInterleave sub-ADC-sub-DACFs=6.4 GHz(CK rate
188、)BW=1000 MHz,=400 NSD=151 dBFS/HzPower=240 mW41 of 4940 dB alias rejection02004006008001000Frequency MHz-70-60-50-40-30-20-100STF dBSignal transfer function-20 dBFS tone near FCLK -3 dBFS tone near FCLK02004006008001000Frequency MHz-100-80-60-40-200Signal Amplitude dBFS/NBWMittal,VLSI 2023 7ISSCC 20
189、25-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceImproving Distortion 10 Sub-DAC static&timing mismatch Distortion Digital DAC error cancellation(DEC)Error estimationFeedforward dig
190、ital cancellation+subADC-+subDACAnalogDelayVCO ADCStage 2Stage 1Digital Reconstruction Filter(DRF)DEC+CT Amp42 of 49Patil,ISSCC 2024 10ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits
191、 ConferenceImproving Distortion 10Fs=6.4 GHzBW=700 MHzIM3 90 dBFSNSD=164 dBFS/Hz,=200 Power=703 mWPatil,ISSCC 2024 10Amplitude dBFS/NBWNSD dBFS/HzFrequency MHzNBW=195 kHzDECONDECOFF7978IM2dBFS9086IM3dBFSDEC OFFDEC ON700 MHz BWfs=6.4 GS/s0100 200 300400 500 600 700 800 900 100012913413914414915415916
192、4169204060801001200Single-Tone Input Frequency MHzdBInput Amplitude:6 dBFS 67 MHzGenerator power left unchanged&input frequency sweptAntialiasing 70 dBNotch from DRFfilter responseSTF10002000300040005000600070001040608090020305070043 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-spee
193、d continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceOutlineMotivationBasestation Radio NeedsLimitations of CT DS ADCsTechnology Disruption:Continuous-Time PipeliningArchitectural EvolutionWhats Next?44 of 49ISSCC 2025-Forum 4.3:Developme
194、nts and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits Conference1 10 50 100 500 1000 10000150155160165170175180185DT DSCT DSCTPFurther BW Extension?dBBW MHz10 dB/dec.FOM=NSD 10 log10(P)Interleaving?Scaling?Murmann 245
195、of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceInterleaving46 of 49+-+subDACFspathInputFull-BWCT pathBW GHz psDelayTD=1.5/FspathpsBWGHzEffective FsGHzInterleaving Fac
196、torFs of one pathFspathGHz15015011011015075220120300150220210600150440410TDIncrease interleaving factor=Delay of one sub-ADC-sub-DAC pathChallenging to implement analog delay as BW rises!Need disruptive delay architecture!ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time
197、 ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceCT DS in wide BW Zero-IF RXCT benefits:Relaxed AAF and driver System powerChallenging to BWDisruptive technology:CT Pipelined ADCCT benefits+BWArchitectural improvements Power:Short CTPDRF Integration B
198、W:Interleaving Distortion:DAC error cancellationLots of scope to further innovate!Conclusions47 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceKey References1 K.Chuan
199、g et al.,Radio Challenges,Architectures,and Design Considerations for Wireless Infrastructure:Creating the Core Technologies That Connect People Around the World,in IEEE Microwave Magazine,vol.23,no.12,pp.42-59,Dec.2022.2 B.Murmann,ADC Performance Survey 1997-2024,Online.Available:https:/ H.Shibata
200、et al.,“A 9GS/s 1GHz-BW Oversampled Continuous-Time Pipeline ADC Achieving-161dBFS/Hz NSD,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2017,pp.278279.4 S.Pavan and H.Shibata,Continuous-time pipelined analog-to-digital converters:A mini-tutorial,in IEEE TCAS-II,vol.68,no.3,pp.810
201、-815,March 2021.5 N.Basavaraj et al.,“Simplified simulation and measurement of the signal transfer function of a continuous-time pipelined analog-to-digital converter,”IEEE TCAS-II,vol.69,no.10,pp.39933997,Oct.2022.6 H.Shibata et al.,“An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inheren
202、t Anti-Aliasing and On-Chip Digital Reconstruction Filter,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2020,pp.260262.7 R.Mittal et al.,“A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET,”in Proc.IEEE Symp.
203、VLSI Circuits,Jun.2023,pp.12.8 S.Pavan et al.,Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining,in IEEE Journal of Solid-State Circuits,vol.59,no.1,pp.268-281,Jan.20249 S.Manivannan and S.Pavan,“Improved multistage continuous-time pipelined analog-to-digital converters
204、and the implicit decimation property,”IEEE TCAS-I,vol.69,no.8,pp.31023113,Aug.2022.48 of 49ISSCC 2025-Forum 4.3:Developments and challenges in high-speed continuous-time ADCs for wideband wireless communications 2025 IEEE International Solid-State Circuits ConferenceKey References10 S.Patil et al.,“
205、A 700MHz-BW 164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 100 GOPS/mW!2025 IEEE International Solid-State Circuits Conference4 of 48Mike Shuo-Wei ChenDAC is BottleneckISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towa
206、rds High Dynamic Range,Bandwidth and Output Power A good DAC is really costly!Wideband AWG instrument often consumes 100s Watts with expensive III-V technology.Keysight:256GS/s,8bit DAC220W!Tektronix:12GS/s,10bit DAC450W!PA$400,000?$100,000 2025 IEEE International Solid-State Circuits Conference5 of
207、 48Mike Shuo-Wei ChenState-of-the-art DACs(ISSCC,VLSI,JSSC)ISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power 2025 IEEE International Solid-State Circuits Conference6 of 48Mike Shuo-Wei ChenNemeses of DAC Design.ISSCC 2025-Forum 4.4
208、:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power Tang et aI.,JSSC 2011907030SFDRdBc50IIIIIISample rate/Signal frequencyAmplitude ErrorTiming ErrorFinite ImpedanceImage courtesy of internetDAC designers daily life 2025 IEEE International Solid-State C
209、ircuits Conference7 of 48Mike Shuo-Wei ChenCurrent steering or charge-redistribution DAC dominates the high speed operationAchieve higher speed(10GS/s)by more time interleaving,just like ADCs.Calibration for Time-Interleaved DACs non-idealities,e.g.gain,offset,timing skews.Time interleaving dynamic
210、element matching(DEM)Inter-channel adaptive filteringCalibration for Single-channel DAC non-idealitiesTiming mismatch compensation(TMC)Bounded INL calibrationDAC architecture explorationTrend Over Past 5+YearsISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range
211、,Bandwidth and Output Power 2025 IEEE International Solid-State Circuits Conference8 of 48Mike Shuo-Wei ChenTI-DAC Non-idealities CalibrationISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power Time-interleaving DEM(T-DEM)TI-DAC Calib
212、ration w/Adaptive FiltersISSCC 2023 Tseng,MediaTekISSCC 2024 Ahmad,Marvell 2025 IEEE International Solid-State Circuits Conference9 of 48Mike Shuo-Wei ChenSingle DAC Non-idealities CalibrationISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Ou
213、tput Power Bounded INL Calibration&thermometer DEM to reduce voltage/timing errorsISSCC 2018 Lin BroadcomVLSI 2022 Koo SamsungCode-dependent Timing Mismatch Compensation 2025 IEEE International Solid-State Circuits Conference10 of 48Mike Shuo-Wei ChenBetter DAC Architecture?ISSCC 2025-Forum 4.4:High
214、-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power 907030SFDR(dB)Speed(S/s)1M10M1G10G50Delta-Sigma DACNyquist DAC100M100GAny potential architecture that will enable new operation regime?i.e.GHz bandwidth,with 100 dB dynamic range 2025 IEEE International Sol
215、id-State Circuits Conference11 of 48Mike Shuo-Wei ChenConventional DAC ArchitecturesISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power IoutThermometer DecoderDigitalInputMSBLSBDigitalInputIoutSmall Step Size Multiple Current Cells L
216、arge Step Size Single Current CellNyquist DAC:Delta-Sigma DAC:Segmented 2025 IEEE International Solid-State Circuits Conference12 of 48Mike Shuo-Wei ChenCombine the best of the two worldsISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output
217、Power-TimingError-AmplitudeError-AsymmetricRise/Fall Time-Incomplete Settling Large Current Cell Array Large Step Size Less Current Cells Smaller Step Size 2025 IEEE International Solid-State Circuits Conference13 of 48Mike Shuo-Wei ChenDual-Rate Hybrid DACISSCC 2025-Forum 4.4:High-Speed DAC Archite
218、ctures and Techniques towards High Dynamic Range,Bandwidth and Output Power IoutThermometer DecoderDigitalInputMSBLSB Power delivered MSB Path,and LSB path lowers the noise floor Minimal analog complexity and technology friendly 2025 IEEE International Solid-State Circuits Conference14 of 48Mike Shu
219、o-Wei ChenTradeoff CurvesISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power 93%of energy is distributed to Nyquist path,i.e.Nyquist.2025 IEEE International Solid-State Circuits Conference15 of 48Mike Shuo-Wei ChenConcept of Pre-dist
220、ortionISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power Pre-distortionHarmonics due to current cell mismatches 2025 IEEE International Solid-State Circuits Conference16 of 48Mike Shuo-Wei Chen assisted Pre-distortionISSCC 2025-Foru
221、m 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power IoutThermometer DecoderDigitalInputMSBLSB AnalogDigital Assisted Pre-distortion+From analog to digital Leverage fine LSB path of dual-rate hybrid DAC 2025 IEEE International Solid-State Circuits C
222、onference17 of 48Mike Shuo-Wei ChenPre-distortionISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power With calibration,MSB is relaxed from 0.1%to 2.5%the area saves more than 200 times to satisfy SFDR 86dB86dB 2025 IEEE International
223、Solid-State Circuits Conference18 of 48Mike Shuo-Wei ChenDual-Rate Hybrid DAC Block DiagramISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power MSB 4b12bPre-distortionLSB 8b15b15b Digital InputThermometer Decoder4b8GS/sAnalogDigitalDW
224、AUnitaryDAC+MUX&LatchArray15b1GS/s4b 8 Channels Interpolator12bBinaryDACx1x2x4x8x8x8x82G_I8G4G2G_Q1GPhase RotatorsCML Divider4GPhase DetectorClock Generator4 bits1ns step 4 bits MSB1nsDelta Sigma ModulationDifferential Hybrid DAC Output timekkk1Gkk+1kkkk+1k+1k+1Feedback ErrorPipelineOverflowPipeline
225、 2025 IEEE International Solid-State Circuits Conference19 of 48Mike Shuo-Wei ChenFirst Silicon PrototypeISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power Digital Core1.27mm1.53mmCSLatch ClockMUXTechnology65nm CMOSSupplyAnalog:1V/2
226、.5V16mADigital:1VBest SFDR91dBPower8GS/sDigital Core(including DDS):165mWWorst SFDR75.6dBAnalog Core:163mWResolution12 bitsClock Gen:104mWBW 77dBSFDR420MHzTotal Die SizeNyquist Path:1GHzActive AreaDSM Path:8GHzS.Su,T.Tsai,P.Sharma,M.S.W.Chen,“A 12-bit Hybrid DAC with 8GS/s Unrolled Pipeline Delta-Si
227、gma Modulator achieving 75dB SFDR over 500MHz in 65nm CMOS,”IEEE VLSI and(Invited)JSSC 2014.2025 IEEE International Solid-State Circuits Conference20 of 48Mike Shuo-Wei ChenMeasured SFDR in bandISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and
228、Output Power Output Spectrum with low frequency inputSDFR dominated by HD2RF attenuation is enabledSecond harmonic dominates 2025 IEEE International Solid-State Circuits Conference21 of 48Mike Shuo-Wei ChenMeasured SFDR NyquistISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards
229、High Dynamic Range,Bandwidth and Output Power Output Spectrum with high frequency input=.=.Second harmonic dominates 2025 IEEE International Solid-State Circuits Conference22 of 48Mike Shuo-Wei ChenState-of-the-art CMOS(GS/s)DACISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards
230、 High Dynamic Range,Bandwidth and Output Power This work:12-bit Hybrid DAC 8GS/sISSCC20131.6GS/sISSCC201121.25GS/sISSCC200911.6GS/sISSCC201233GS/sISSCC20056500MS/sISSCC200912.9GS/s 2025 IEEE International Solid-State Circuits Conference23 of 48Mike Shuo-Wei ChenTurn into bandpass operation?ISSCC 202
231、5-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power 2025 IEEE International Solid-State Circuits Conference24 of 48Mike Shuo-Wei ChenBandpass Hybrid DACISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Rang
232、e,Bandwidth and Output Power LSBMSBThermometer DecoderLUnaryDACBinaryDACL/Nyquist PathDelta-Sigma Path0FrequencyMag.Tunable bandpass DSM Single/Dual-rate modesMax Fout=6GHzFos=12GHzAnalog OutputTunable 2025 IEEE International Solid-State Circuits Conference25 of 48Mike Shuo-Wei ChenFrequency Operati
233、on ModesISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power 0=1=0=1=0MagnitudeBand B Band C Band DBand AFdsmDC0.5Fs0.5Fdsm0.75Fdsm0.25FdsmCh1Ch16Ch2Ch3Ch4Ch5Ch6Ch7Ch8Ch9Ch10Ch11Ch12Ch13Ch14Ch15Chopping modeChannel 2&15Channel 7&10Pip
234、elinedSuccessive2nd/3rdorderBP-DSM8 Channels(13b)(4b)MUX&LatchesInn+7Inn+1InnOut1.5GS/s(Fdsm)12GS/s(Fs)Effective sample rate of DSM is 12GHz(8 parallel DSM)A tunable DSM design allows 64 available channelsConditionally support carrier aggregations 2025 IEEE International Solid-State Circuits Confere
235、nce26 of 48Mike Shuo-Wei ChenChip MicrographISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power 2.5mm2mmLVDS RxTest Signal Gen.BP-DSMSPICS ArrayLatchesSerializeCLK Gen.Area mm2Power mWDigital1.611510Analog0.1250MUX(2%)Latch(4%)CS(3%)
236、CLK(3%)Digital(88%)Area DistributionS.Su and M.S.-W.Chen,“A 16-bit 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving 210 Phases(10 b)Peak Mode PBO Mode90 180 270 0 0 30 60 90 315 225 135 45 15 45 75 105 PBO=peak/3Discrete FixedLO Phases 8 Phases(3 bits)Peak Mode PB
237、O ModePolar SHSMulti-phase SHSIncrease signal bandwidth 2025 IEEE International Solid-State Circuits Conference46 of 48Mike Shuo-Wei ChenCombining Dual-rate Hybrid DACISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power HybridDACMP-SH
238、SLUTAM SHS MP I(t)CKFBWFs/2w/HDAC Noise shapingLowerIn-band EVMFreqMag Thermo.DecoderPre-DistortionDigitalInput+10b3b MSB7b LSB8b3b Binary7b UnaryDual RateHybridDACMP-SHSDecoderControl AMControl SHSControl MPBB I-DataCK Channel-AMP-SHS Decoder w/HDAC Channel-BBB Q-DataMP-SHS Decoder w/HDACB_selFB_se
239、lBctrl,MSBBctrl,LSBA_selFA_selActrl,MSBActrl,LSBSignal1st-OrderDSM1st-OrderDSMH(z)DigitalFilter+1-1 MASH7be1nv2n1b+2b1b+2bMASHOUT1b1b+7bxnOOB noise filtered by Matching NW10b noise6b noise1b w/o HDACv1n26.1:S.Mahapatra,et.al.,“A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching
240、 PA Achieving 3.2Gb/s Data Rate and-30.8dB EVM in 65nm CMOS”ISSCC 2025Increase dynamic range 2025 IEEE International Solid-State Circuits Conference47 of 48Mike Shuo-Wei ChenConclusionISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Pow
241、er Current-steering and Capacitor DAC are common choices for high-speed implementation.Dual-rate hybrid DAC allows high dynamic range with lowpass and bandpass operation.Multi-phase Sub-harmonic switching enhances backoffefficiency with high output power and bandwidth When combined a high-speed DAC
242、towards high dynamic range+bandwidth+output power 2025 IEEE International Solid-State Circuits Conference48 of 48Mike Shuo-Wei ChenAcknowledgementISSCC 2025-Forum 4.4:High-Speed DAC Architectures and Techniques towards High Dynamic Range,Bandwidth and Output Power Prof.Shiyu Su,Prof.Aoyang Zhang for
243、 their past PhD work Soumya Mahapatra for his ongoing PhD work 2025 IEEE International Solid-State Circuits Conference1 of 63NXP SemiconductorsDelft University of TechnologyMuhammed BolatkaleHigh-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference2 of 63Introductio
244、nFundamentals of Noise-ShapingBrief overview of ADC SurveyHighlights of Noise Shaping ADCsCase studiesDelta-sigma ADCsADC architectures employing NS-SAR ADCsConclusionsOutlineMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Confe
245、rence3 of 63Reflecting the PastMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs Modulator Modulator High-order NTF MASH Sampling rate increases New DSM architectures DAC Calibration Wide band M Noise-shaping SAR Zoom ADC Error shaping tech.InceptionStability TheoryCMOS eraS
246、ystem Optimizationref:S.R.Norsworthy et.al.,Delta-sigma data converters:theory,design,and simulation.Wiley,1997.2025 IEEE International Solid-State Circuits Conference4 of 63 ADCFSVinX(nTs)ErrorNTFFS=OSR*2*BWNTF=(1-z-1)nError:Qnoise,mismatch,gain,.AAFCal.&Dec.Y(nTnq)A noise shaping ADC must be overs
247、ampledQn limits resolution and higher-order noise-shaping improves SQNRDefinition of Noise-shapingMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs0.0010.010.10.5Freq./Fs(-)-60-50-40-30-20-1001020NTF(dB)1st order2nd order40dB/dec20dB/decOBG 2025 IEEE International Solid-Stat
248、e Circuits Conference5 of 63System OptimizationMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsRadar,lidar,biomedicalLarge number of ADCsBest KPI(Linearity,Power/Area)Audio,radio,wireless,IoT,MCUWideband,Multi-mode ADCs Best KPI(Linearity,Power/Area)ADC ADC Multi-ModeWideba
249、ndBandpass FmixLNALNALNACTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTCTSensor Array(Bio,Lidar)MiMo System(Radar,Wireless)ADC ArraySensor/AntennaSize few m to mm 2025 IEEE International Solid-State Circuits Conference6 of 63ADC SurveyMuhammed BolatkaleISSCC 2025-Forum 4.5 High-perfor
250、mance Noise-shaping ADCsMain take away:Power efficiency is saturatingScope:BW20KHz&with noise-shaping techniques=2.5dBref:B.Murmann,ADC Performance Survey 1997-2024,Online.Available:https:/ 2025 IEEE International Solid-State Circuits Conference7 of 63Noise Shaping ADCs(2020-2024)Muhammed BolatkaleI
251、SSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsMain ArchitecturesScope:NS-SAR:Single stage,PipelineDSM:Single stage,MASHVCO-ADC is excluded.2025 IEEE International Solid-State Circuits Conference8 of 63Power efficiency(2020-2024)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-s
252、haping ADCsWhat is calibrated:OffsetDAC mismatch(R&C)Mismatch error shapingDEM,DWA,CLA,TDWAIntegrator Gain&lossResidue Amplifier gainGain error shapingTransfer functionsVCO non-linearityNegative-gmS.Li VLSI241-bit DSMX.He ISSCC24Pipelined NS-SARY.Lyu VLSI20Pipelined NS-SARC.Y.Lee,ISSCC22Multi-bit DT
253、-DSM w/DWA 2025 IEEE International Solid-State Circuits Conference9 of 63CT-DSM demonstrated highest level of system integration(LNA+ADC)BW exceeding 100MHz for single loop,350MHz for MASH modulators ctdsm1,4Bandpass modulators with Fcenterranging from 200MHz to 2.4GHz ctdsm2,5DAC calibration achiev
254、ing better than ctdsm1-31/f noise cancellation techniques at GHz sampling rates ctdsm2ADC architectures with a Noise-Shaping SAR quantizerHybrid ADC architectures d1-d8 Noise-shaping SAR convertersBW extended till 200MHz with OSR of 4 s1Pipeline and TI architectures to increase BW s1-7Dynamic amplif
255、iers,Mismatch&Gain error shaping techniques s4,6,17,18Higher order NTFs(i.e:up to 5thorder)s9,10,13,15Experiments on 1storder CT-NS-SAR ADC s12Highlights Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference10 of 63Case Stu
256、diesMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference11 of 63CT Delta-sigma ADCsWide-band Continuous-time Delta Sigma ADCHigh-pass NTF based bandpass Delta-Sigma ADC1/f noise reduction at GHz sampling ratesExtending ban
257、dwidth of CT Delta-sigma ADCADC architectures employing noise-shaping SAR architecturesContinuous-Time Zoom ADC employing a Noise-shaping SAR ADCCT M with a True TIME-interleaved NS QuantizerTI-Pipe-SAR ADC with a Residue Integrating AmplifierCase StudiesMuhammed BolatkaleISSCC 2025-Forum 4.5 High-p
258、erformance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference12 of 63High Performance Noise-Shaping ADCsMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsctds-4ctds-1ctdsm-5ctds-2 2025 IEEE International Solid-State Circuits Conference13 of 63WIDE-BAND
259、 CT ADC WITH DIGITAL DAC ERROR CORRECTIONCase Study:CTDSM-1Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference14 of 63A mixer-less receiverFixed-frequency PLLRobust against interferersGlobal FM receiverApplication(Broadca
260、st FM Radio)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsSingle-tone blocker Multi-tone blockerWanted ChannelFM Radio:76MHz 108 MHz 2025 IEEE International Solid-State Circuits Conference15 of 63ArchitectureMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-sh
261、aping ADCss1+s2+s3+s4+f1 f2 f3 f4 f5 d1 c1 c2 c3+d3 DACADCDAC2+z-0.5PRBS11+psINPUTFs/9DMUXDEECcorrected&decimatedoutput9b17b Fs/9PRBSgenFsD2:0Barrel shifterFsDS2:0Fs3b3bArchitecture28nm CMOSFs=6GHzBW=120MHz2b TI RTO R-DACBackground cal.(Static)2b Flash QuantizerBackground cal.(Static)4th order CT fi
262、lterInverter-basedStability(c1-c4)STF design(f1-f5)ELD comp.(DAC2)Power=109mWArea=0.13mm2 2025 IEEE International Solid-State Circuits Conference16 of 633 level quantizer exampleDAC errors accumulated&send to programmable DAC correction()After calibration convergence,Y is free of DAC mismatch errorD
263、AC Error Estimation and Compensation Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsMismatch Estimation0.5CF 21-1+D1c 2+D2c 2-D2co -D1co LFQ3lvl1-1+FSPNVinT1T2D1D2D1f (1+)D2f -(1-)Y Vin+NTF*LPF*EQ 2025 IEEE International Solid-State Circuits Conference17 of 63Validation re
264、sults(THD)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs0102030405060708090100110120Frequency(MHz)-120-100-80-60-40-200Amplitude(dB)HD2 improvedby 25.4dBHD3 improvedby 21.4dBHD2HD30dB=0.51VpeakHD2=-102.5dBcHD3=-106.5dBcCal.OFFCal.ONSignalsource noise 2025 IEEE Internation
265、al Solid-State Circuits Conference18 of 63Validation results(IMx)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference19 of 631/F NOISE IN CONTINUOUS-TIME M AT GHZ SAMPLING RATESCase study:CTDS-3Muhammed BolatkaleISSCC 2025
266、-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference20 of 63ArchitectureMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCss1+s2+s3+s4+f1 f2 f3 f4 f5 d1 c1 c2 c3+d3 DACADCDAC2+z-0.5PRBS11+psINPUTFs/9DMUXDEECcorrected&decimatedo
267、utput9b17b Fs/9PRBSgenFsD2:0Barrel shifterFsDS2:0Fs3b3bArchitecture28nm CMOSFs=6GHz3GHz Chopper(w1)BW=120MHz2b TI RTO R-DACBackground cal.(Static)2b Flash QuantizerBackground cal.(Static)4th order CT filterStability(c1-c4)STF design(f1-f5)ELD comp.(DAC2)Power=115mWArea=0.15mm2Fchop 2025 IEEE Interna
268、tional Solid-State Circuits Conference21 of 63Simulated input referred noise from first integrator Flicker noise corner 9MHz Chopping the input stage at fs/2&fs Reduced flicker noise but increased thermal noise Effective chopping rate should be fs/6First Integrator-ChoppingMuhammed BolatkaleISSCC 20
269、25-Forum 4.5 High-performance Noise-shaping ADCsSimulated Input Noise1stIntegratorP.Cenci,ESSCIRC 2023 2025 IEEE International Solid-State Circuits Conference22 of 63Mulit-frequency and Multi-path ChoppingMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs3GHz1GHzFs/26Fs/26 3-
270、path input stage 1/3 of parasitic cap SW at every chopping edge CLK edges align with fs/2 Sampling of Q-noise at fs Mismatch b/w 3-paths Folding of Q-noise frommultiples of fs/13 The number of times error occurs due to Q-noise sampling is much smaller 2025 IEEE International Solid-State Circuits Con
271、ference23 of 631/f noise corner frequency 9MHzChopping SpectrumMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference24 of 631/f noise corner frequency=400kHz&Thermal noise floor increases by 3dB Chopping SpectrumMuhammed Bo
272、latkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference25 of 63 1/f noise corner freq.=350kHz,SFDR is 113.4dBFS due to mismatch bw pathsChopping SpectrumMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEE
273、E International Solid-State Circuits Conference26 of 63 SFDR of 122dBFS in 150kHz 120MHz BWChopping SpectrumMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference27 of 63Validation(IMx)Muhammed BolatkaleISSCC 2025-Forum 4.5
274、High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference28 of 63HIGH-PASS NTF BASED CT BANDPASS ADCCase study:CTDSM-2Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference29 of 63Power opti
275、mization from antenna to bits.Application specific ADC architecture.Application(Broadcast DAB Radio)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsCTDSM-2:Bajoria,ESSERC24 2025 IEEE International Solid-State Circuits Conference30 of 63For a low-IF Fs/30,Highpass based NTF
276、achieves the same SQNRMore robust over PVT and easily switched to lower frequency modes(e.g.FM)NTF Choice-IIMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference31 of 63DAC3 for 1.5b dither+tone signal injection5-bit capaci
277、tor bank tuning of(C1-C4 capacitors)ArchitectureMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsCTDSM-2:Bajoria,ESSERC24Simplified block diagram.Input signal feedforward coefficients are omitted.2025 IEEE International Solid-State Circuits Conference32 of 63Validation Resul
278、t(Calibration)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs1.61.822.22.42.6Frequency Hz108-115-110-105-100-95-90-85Signal power dBOutput SpectrumDrift due to temperature change(145C)After re-calibration0510152025Iteration#2425262728Capacitor codeLoopfilter CalibrationInt
279、egrator 1Integrator 2Integrator 3Integrator 4DAB bandwidth 2025 IEEE International Solid-State Circuits Conference33 of 63Validation Result(IMx)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference34 of 631-1-1 FILTERING CT
280、 MASH MCase study:CTDS-4Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference35 of 63SQNR=75dB in 360MHz BW Sampled at 5GHz,40nm CMOS1ststage RC integrator,Gm-C in Stages 2&3 with Interstage Gain(G=3),DAC2ELD,DAC3&DAC4 IDAC
281、(integration)+CDAC(ELD compensation).1-1-1 Filtering MASH ArchitectureMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsINAPFV1OUT11SDAC1DAC2ADC1LPFV2OUT2DAC3ADC2Gm2GOUT3DAC4ADC3Gm3GV33bFlash3bFlash3bFlash3bCurrent SteeringStage-1Stage-2Stage-3 2025 IEEE International Solid-S
282、tate Circuits Conference36 of 631-1-1 Filtering MASH ArchitectureMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsINAPFOUT11SDAC1DAC2ADC1LPFAPF(R-RC)equalizes delay from DAC1 td1=1.5Ts(ELD+ZOH delay)LPF(RC)cancels signal from DAC2(td2=ELD=Ts)&ADC1 samples IN directly30dB sig
283、nal suppression at OSR=7V1 2025 IEEE International Solid-State Circuits Conference37 of 63Validation(HDx)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference38 of 63Highlights of CT DS ADCsMuhammed BolatkaleISSCC 2025-Foru
284、m 4.5 High-performance Noise-shaping ADCsHighlightWideband Low FcenterMulti-freq ChoppingUltra Wideband Low Noise RFReferenceCTDSM-1CTDSM-2CTDSM-3CTDSM-4CTDSM-5ArchitectureSingle-loopBandpassSingle-Loop1-1-1 MASHBandpassTechnology(nm)2828284065Order44436CalibrationDigital DAC Error CorrectionDigital
285、 DAC Error CorrectionDigital DAC Error CorrectionDigital NCF Fcenter&GmPerformanceVdd(V)0.9/1.50.95/1.50.9/1.51.8/1.1/11.2FS (GHz)666510.8OSR254525764Fcenter(MHz)n.a.200n.a.n.a.2700Bandwidth(MHz)1206612036084DR(dB)72.37473.468n.a.SNR(dB)72.372.672.865n.a.SNDR(dB)72.372.672.86562FinTHD(MHz)38.8n.a.38
286、115n.a.THD(dBc)-101.1n.a.-98.3-78n.a.FinIMD(MHz)88&94210&22088&94320&3302769&2771IM3(dBc)-105.7-100.3-105.8-77-54SFDR(dBFS)119115122100dBc and SFDR 100dBFSMulti-Frequency and Multipath Chopping at GHz sampling ratesADCs employing noise-shaping SAR architecturesNS-SAR improves power efficiency of CT-
287、DSM at the cost of AAF&MetastabilityZoom&incremental ADCs employ NS-ADCs to improve performance Standalone noise-shaping ADC achieved 200MHz bandwidth for an OSR of 4 Common choice of architecture is Pipeline and Time-interleavingDynamic amplifiers to reduce power dissipationConclusions Muhammed Bol
288、atkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCs 2025 IEEE International Solid-State Circuits Conference57 of 63Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsThank you 2025 IEEE International Solid-State Circuits Conference58 of 63Noise Shaping SAR ADCs(2020
289、-2024)Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsPipe TI SARIntegrator Residue,NTF a.OSR=4Pipe-NS-SAR(Hybrid V-T-V)RA is noise shaped.OSR=44thorder NS Pipe-SARRA error shaped,NTF a.OSR=3.8Partial TI NS Pipe-SARError feedback,NTF a.OSR=7.5Pipe NS-SAR with GESError feedb
290、ack+/-20%,NTF a.OSR=8x TI Passive NS-SARPassive residue generation.OSR=4Pipe NS-SAR with GESError feedback+/-20%,NTF a.OSR=8x5thNS SARV-t-V amp.OSR=44thNS SARDA,OSR=254thNS SARBuffer in loopOSR=5CT 1stNS SARBuffer in loop!OSR=162ndNS SARMES w/extended input rangeOSR=64,NTF a.4thNS SARDyn.Buf.+Cap st
291、ackingOSR=103rdNS SARkT/C noise cancel w/DA,NTF a.,OSR=81stNS SAR,2ndMESPassive GainOSR=253rdNS SARCL DAOSR=84thNS SARCascaded NSOSR=10NS-SAR+VCO OSR=11Abbreviations:CL:Closed-LoopDA:Dynamic Amplifier(Ring/FIA)RA:Residue AmplifierOSR:Oversampling RatioNS:Noise ShapingTI:Time-interleavingCT:Continuou
292、s-timeGES:Gain error shapingMES:Mismatch error shapinga.:availableS-1S-2S-3S-4S-5S-6S-7S-8S-9S-11S-12S-10S-13S-14S-15S-16S-17S-18 2025 IEEE International Solid-State Circuits Conference59 of 63Muhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsReferences 2025 IEEE Internationa
293、l Solid-State Circuits Conference60 of 63References-CTDSMMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsctdsm-1M.Bolatkale et al.,A 28-nm 6-GHz 2-bit Continuous-Time ADC With 101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction,in IEEE Journal of Soli
294、d-State Circuits,vol.57,no.12,pp.3768-3780,Dec.2022,doi:10.1109/JSSC.2022.3202977.ctdsm-2S.Bajoria et al.,A 6GHz Continuous-Time Bandpass ADC with Background Filter Calibration and 100dBc IM3 for a Mixer-Less DAB Band III Receiver,2024 IEEE European Solid-State Electronics Research Conference(ESSERC
295、),Bruges,Belgium,2024,pp.637-640,doi:10.1109/ESSERC62670.2024.10719573ctdsm-3S.Javvaji et al.,A 120-MHz BW,122-dBFS SFDR CT ADC With a Multi-Path Multi-Frequency Chopping Scheme,in IEEE Journal of Solid-State Circuits,vol.59,no.4,pp.1184-1193,April 2024,doi:10.1109/JSSC.2024.3354574.ctdsm-4Q.Liu,L.J
296、.Breems,S.Bajoria,M.Bolatkale,R.Rutten and G.Radulov,A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS,in IEEE Journal of Solid-State Circuits,vol.57,no.12,pp.3781-3793,Dec.2022,doi:10.1109/JSSC.2022.3204871.ctdsm-5A.Sayed et al.,A 10.8GS/s,84MHz-BW RF Bandpass ADC
297、with a 89dB-SFDR and a 62dB-SNDR for LTE/5G Receivers,2024 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Honolulu,HI,USA,2024,pp.1-2,doi:10.1109/VLSITechnologyandCir46783.2024.10631461ctdsm-6S.Li,S.Javvaji,V.Pecanins-Martinez,E.Aydin,R.van Veldhoven,and K.A.A.Makinwa,“
298、A Beyond-the-rail Audio CTM with a Passive Input Stage and 99.2dB SNDR,”in 2024 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Jun.2024,pp.12.doi:10.1109/VLSITechnologyandCir46783.2024.10631367.2025 IEEE International Solid-State Circuits Conference61 of 63References AD
299、C Architectures with NS-SARMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCsd-1Z.Wang et al.,“10.6 A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer,”in 2023 IEEE International Solid-State Circuits Conferenc
300、e(ISSCC),Feb.2023,pp.911.doi:10.1109/ISSCC42615.2023.10067696.d-2S.Mehrotra et al.,A 590 W,106.6 dB SNDR,24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC,ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference(ESSCIRC),Milan,Italy,2022,pp.253-256,doi:10.1109/ESSCIRC55480
301、.2022.9911295.d-3W.Shi et al.,“10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR,”in 2021 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2021,pp.170172.doi:10.1109/ISSCC42613.2021.9366023.d-4K.Xing,W.Wang,Y.Zhu,C.-H.Chan,and R.P.Martins,“A 10.4mW 50MH
302、z-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp,”in 2020 IEEE Symposium on VLSI Circuits,Jun.2020,pp.12.doi:10.1109/VLSICircuits18222.2020.9162797.d-5S.Lee,T.Kang,S.Song,K.Kwon,and M.Flynn,“An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Qu
303、antizer,”in 2022 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Jun.2022,pp.5455.doi:10.1109/VLSITechnologyandCir46769.2022.9830207.d-6L.Jie,H.-W.Chen,B.Zheng,and M.P.Flynn,“10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shapin
304、g SAR Quantizer,”in 2021 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2021,pp.167169.doi:10.1109/ISSCC42613.2021.9366006.d-7A.Subramanian,T.Halder,L.V.Tripurari,and A.Kannan,“9.5 A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor DAC,Non-Overlap DEM and Continuous-Time Quantizer,
305、”in 2024 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2024,pp.176178.doi:10.1109/ISSCC49657.2024.10454526.d-8H.-W.Chen et.al.,“A 0.024mm284.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer(NSQ VCO CTDSM),”in 2023 IEEE VLSI,Jun.2023,pp.12.doi:10.23919/VLSITechnologyan
306、dCir57934.2023.10185345.2025 IEEE International Solid-State Circuits Conference62 of 63References Noise Shaping SAR ADCMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCss 1X.He,M.Gu,H.Jiang,Y.Zhong,N.Sun,and L.Jie,“9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Sha
307、red Residue Integrating Amplifier Achieving 173dB FoMs,”in 2024 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2024,pp.172174.doi:10.1109/ISSCC49657.2024.10454431.s 2Y.Song,Y.Zhu,C.H.Chan,and R.P.Martins,“9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipe
308、line ADC With Background Inter-Stage Offset Calibration,”in 2020 IEEE International Solid-State Circuits Conference-(ISSCC),Feb.2020,pp.164166.doi:10.1109/ISSCC19947.2020.9063047.s 3Y.Zhang et al.,“10.7 A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplif
309、ier Error Shaping,”in 2023 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2023,pp.911.doi:10.1109/ISSCC42615.2023.10067689.s 4H.Zhang,Y.Zhu,C.-H.Chan,and R.P.Martins,“10.5 A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-U
310、nrolled Scheme,”in 2023 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2023,pp.174176.doi:10.1109/ISSCC42615.2023.10067438.s 5C.-Y.Lin,Y.-Z.Lin,C.-H.Tsai,and C.-H.Lu,“27.5 An 80MHz-BW 640MS/s Time-Interleaved Passive Noise-Shaping SAR ADC in 22nm FDSOI Process,”in 2021 IEEE Internatio
311、nal Solid-State Circuits Conference(ISSCC),Feb.2021,pp.378380.doi:10.1109/ISSCC42613.2021.9365754.s 6H.Zhang,Y.Zhu,C.-H.Chan,and R.P.Martins,“27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration,”in 2021 IEEE International
312、 Solid-State Circuits Conference(ISSCC),Feb.2021,pp.380382.doi:10.1109/ISSCC42613.2021.9365833.s 7Y.Lyu and F.Tavernier,“A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS,”in 2020 IEEE Symposium on VLSI Circuits,Jun.2020,pp.12.doi:10.1109/VLS
313、ICircuits18222.2020.9162805.s 8S.T.Chandrasekaran,S.P.Bhanushali,S.Pietri,and A.Sanyal,“OTA-free 1-1 MASH ADC using Fully Passive Noise Shaping SAR&VCO ADC,”in 2021 Symposium on VLSI Circuits,Jun.2021,pp.12.doi:10.23919/VLSICircuits52068.2021.9492344.s 9P.-S.Liu,Y.-H.Huang,and C.-C.Hsieh,“A Low-OSR
314、5th-Order Noise Shaping SAR ADC Using EF-EF-CIFF Structure with PVT-Robust Differential V-T-V Converter,”in 2024 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuits),Jun.2024,pp.12.doi:10.1109/VLSITechnologyandCir46783.2024.10631390.s 10K.-C.Cheng,S.-J.Chang,C.-C.Chen,and S.-
315、H.Hung,“9.7 A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator,”in 2024 IEEE International Solid-State Circuits Conference(ISSCC),Feb.2024,pp.180182.doi:10.1109/ISSCC49657.2024.10454362.2025 IEEE International Solid-State Circuits Conference6
316、3 of 63References Noise Shaping SARMuhammed BolatkaleISSCC 2025-Forum 4.5 High-performance Noise-shaping ADCss 11T.Wang,T.Xie,Z.Liu,and S.Li,“An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique,”in 2022 IEEE I
317、nternational Solid-State Circuits Conference(ISSCC),Feb.2022,pp.418420.doi:10.1109/ISSCC42614.2022.9731771.s 12H.Li,Y.Shen,E.Cantatore,and P.Harpe,“A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator,”in 2022 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology
318、and Circuits),Jun.2022,pp.5859.doi:10.1109/VLSITechnologyandCir46769.2022.9830373.s 13K.Hasebe et al.,“A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques,”in 2022 IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circuit
319、s),Jun.2022,pp.5657.doi:10.1109/VLSITechnologyandCir46769.2022.9830166.s 14T.-H.Wang,R.Wu,V.Gupta,and S.Li,“27.3 A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation,”in 2021 IEEE International Solid-Stat
320、e Circuits Conference(ISSCC),Feb.2021,pp.374376.doi:10.1109/ISSCC42613.2021.9365990.s 15J.Liu,D.Li,Y.Zhong,X.Tang,and N.Sun,“27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering,”in 2021 IEEE International Solid-State Circuits Conference(ISSCC),Feb.20
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322、g,Z.Gao,M.Zhan,X.Tang,and N.Sun,“9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4 Passive Gain and 2nd-Order Mismatch Error Shaping,”in 2020 IEEE International Solid-State Circuits Conference-(ISSCC),Feb.2020,pp.158160.doi:10.1109/ISSCC19947.2020.9063159.s 18L.Jie,B.Zheng,H.-W.Chen,R.Wang,and M.P.F
323、lynn,“9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth,”in 2020 IEEE International Solid-State Circuits Conference-(ISSCC),Feb.2020,pp.160162.doi:10.1109/ISSCC19947.2020.9062905.2025 IEEE International Solid-State Circuits ConferenceHighlights of Power-Efficient AD
324、CsYoungcheol ChaeYonsei University,Seoul,Korea1 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceOutlineIntroductionADC Treads and ScopeADC Design TechniquesArchitectural-level TechniquesCircuit-level TechniquesConclusion 2 of 55ISSCC2025 Forum 4 2025 IEEE International
325、Solid-State Circuits ConferenceADC Papers(or ADC-related Papers)in ISSCC 2025 (30+papers)Session 3:3.1(Audio)Session 4:4.1(subsampling ADC)Session 6:6.5(Pixel-parallel ADC),6.6(IDC),6.10(Touch IC)Session 7:7.5(ADC)Session 8:8.7/8(TDC)Session 15:15.6(ADC)Session 18:18.18(Noise-Shaping and SAR-Based A
326、DCs)Session 24:24.18(High Frequency ADCs)Session 27:27.3(CT ADC),27.4/5(TDC)Session 28:28.14(CDC)Introduction3 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceADC LandscapeSchreier FoM(FoMS)=DR+10log(BW/P)or SNDR+10log(BW/P)The FoMSof 185dB seems to be the STOA for SNDR
327、 of 70dB M.Jang,OJ-SSCS234 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceADC Landscape(SNDR versus Fs,nyq)New ApplicationsSNDR improvements in Low-Speed(500MHz)ADCs M.Jang,OJ-SSCS231997-2020 NQ1997-2020 OS2011-2023 NQ2011-2023 OSHigher SNDRHigher SNDR5 of 55ISSCC2025
328、Forum 4 2025 IEEE International Solid-State Circuits ConferenceADC Landscape(Schreier FoM versus Fs,nyq)M.Jang,OJ-SSCS23Energy-Efficiency Improvements Steady progress for both Nyquist ADCs and Oversampling ADCsFoMSProgress rate:1dB per year and the hill of FoM increases at the same rate1997-2020 NQ1
329、997-2020 OS2011-2023 NQ2011-2023 OS6 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceHybrid ADCs(NS SAR,Zoom)Incremental ADCsContinuous-Time ADCsADC Design TechniquesKT/C noise cancellationCapacitively biased Amplifiers Amplifiers&Assisted Amplifiers Architectural Techn
330、iquesCircuit Techniques7 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceHybrid ADCs(NS SAR,Zoom)Incremental ADCsContinuous-Time ADCsADC Design TechniquesKT/C noise cancellationCapacitively biased Amplifiers Amplifiers&Assisted Amplifiers Architectural TechniquesCircuit
331、 Techniques8 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceNS SAR ADC J.Fredenburg,ISSCC12 +SAR:targeting 12bit or more Co-integrating DAC(Single DAC)DAC-Centric(cf.LF-Centric,DTM)CIFF loop filter:1/(1+LF(z)EF loop filter:1-LF(z)S.Li,ISSCC18Noise-Shaping SAR ADCs 9 of
332、 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceSmall Residue Simple,Low-power,Low-noise amplifierSmall swing Small non-linearity Open loop amplifier Low Settling error Relaxed Speed Low Power Low(amplifier)bandwidth filtered amplifier noise Low noise Loop Filter of Noise
333、-Shaping SAR ADCs 10 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State Circuits ConferenceCIFFEFFilter LF2(z):IIR FilterLF1(z):FIR Filter NTF1/(1+LF2(z)1-LF1(z)QE x NTF 0LF2(z)LF1(z)1Circuit Gain StageAccurate coefficientPVT Less sensitiveMore SensitiveDesign Sufficient GainCoefficient controlNS SAR ADC:CIFF vs.EF Architecture11 of 55ISSCC2025 Forum 4 2025 IEEE International Solid-State C
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