SESSION 28 Capacitive Sensor Readout.pdf

《SESSION 28 Capacitive Sensor Readout.pdf》由會員分享，可在線閱讀，更多相關《SESSION 28 Capacitive Sensor Readout.pdf（191頁珍藏版）》請在三個皮匠報告上搜索。

1、ISSCC 2025SESSION 28Capacitive Sensor Readout28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference1 of 50An 18.5nF-Input-RangePM-SAR Hybrid Capacitance-to-Digital Con

2、verter Achieving 6.1s Conversion Timeat 18.1pF Input CapacitanceDonghyun Youn1,Kyeongwon Jeong2,Woongro Youn1,Hoyong Seong1,Yechan Park1,Sohmyung Ha3,Minkyu Je11KAIST,Daejeon,Korea2ETH Zrich,Zrich,Switzerland3New York University Abu Dhabi,Abu Dhabi,United Arab Emirates 28.1:An 18.5nF-Input-Range PM-

3、SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference2 of 50Outline Motivation Proposed PM-SAR Hybrid CDC Circuit Implementation Measurement Results Conclusion28.1:An 18.5nF-Input-Range PM-SAR Hyb

4、rid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference3 of 50Outline Motivation Proposed PM-SAR Hybrid CDC Circuit Implementation Measurement Results Conclusion28.1:An 18.5nF-Input-Range PM-SAR Hybrid Cap

5、acitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference4 of 50Microfluidic ChannelPolymeric membraneDielectricInsulatorPrinciples of Capacitive SensingPressureAir flowHumidityCytometryC1C2Absorptionor evaporation

6、InflowDielectricInsulatordACS=Cd1C 28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference5 of 50Challenges in CDC DesignCS A d=Capacitance=Permittivity=Area=DistancedA

7、CS=ADCAFEDOUTCapacitiveSensor CSCapacitance-to-DigitalConverter(CDC)Accelero-meterPressure HumidityDNAGasCytometry DisplacementBiomimeticsVibration1 Wide Input Range(pFnF)Fast Conversion(down to few-s)3 OptimizedNoise-Energy Trade-Off2Excellent CDC for Broad Applications28.1:An 18.5nF-Input-Range PM

8、-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference6 of 50Challenges in CDC Design Broad requirements on 1)input range ranging from pF to nFSNR100dB75dB50dB1pF 10nF 100pF Input rangeDisplace-me

9、ntDNA&BiomoleculeAcceleratorPressureHumidityGas28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference7 of 50Challenges in CDC Design Applications requiring 2)fast conv

10、ersion down to few sBiomimeticsA.Dagamseh,J.M.M.13Flow cytometryJ.Chien,JSSC 16Industrial displacementS.Xia,ICIE 1028.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conferen

11、ce8 of 50Challenges in CDC Design Optimized 3)noise-energy performanceADCAFEDOUTCapacitance-to-DigitalConverter(CDC)System batteryCSCrmsFoMS=RES*dB10log10(Conv.energy)*RES dB=20log10()(2 2)CrmsCSFoMW=2ENOB*Conv.energy*ENOB=6.02RES dB 1.7628.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digita

12、l ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference9 of 50Prior CDC TopologiesPMMSAR Period-Modulation(PM)Delta-Sigma-Modulation(M)Successive-Approximation-Register(SAR)DIVRSTCLKCSCRDOUTDOUTVEXTSARlogicCSCRDOUTCSCRC-DAC28.1:An

13、 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference10 of 50Prior CDC TopologiesSAR/NR,L,C,V,I,TTt0Nt0Time-domain:No saturationVoltage saturation by supply railPMV,IV,IAvin

14、 100s conversion time due to a counter blockDIVRSTCLKCSCRDOUT91113151719ENOB bit7Conv.time s102101100103104FoMS dB130160170190180140104103102101100105Input range pF150PMSARM28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacit

15、ance 2025 IEEE International Solid-State Circuits Conference12 of 50M CDCEnergy efficiency ResolutionInput rangeConv.speed Highest resolution thanks to noise-shaping behavior Still,trade-off between resolution and conversion time91113151719ENOB bit7Conv.time s102101100103104FoMS dB130160170190180140

16、104103102101100105Input range pF*150PMSARM*Off-chip CR usedDOUTCSCRC-DAC28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference13 of 50SAR CDCEnergy efficiency Resoluti

17、onInput rangeConv.speed Time-and energy-efficient thanks to digital-friendly operation But less than 12b ENOB due to lack of front-end gain91113151719ENOB bit7Conv.time s102101100103104FoMS dB130160170190180140104103102101100105Input range pF*150PMSARMDOUTVEXTSARlogicCSCR28.1:An 18.5nF-Input-Range P

18、M-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference14 of 50Design GoalsFoMS dB130160170190180140104103102101100105Input range pF150PMSARMOur goal91113151719ENOB bit7Conv.time s102101100103104O

19、ur goalA CDC to support broad applications with1)Wide input range2)Fast conversion among similar ENOB3)Optimized noise-energy performance28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-S

20、tate Circuits Conference15 of 50Design GoalsDIVRSTCLKCSCRDOUT10-bSARDLSBS-OSCR-OSCCRTRDMSBIUPIDNCSNNTTSPD AMPCPSAR ADCVCP+VPMFront-EndSAR-ADCBack-EndDOUTVEXTSARlogicCSCRInput rangeResolutionConv.speedEnergy eff.PM+SARHybrid!28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAch

21、ieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference16 of 50Outline Motivation Proposed PM-SAR Hybrid CDC Wide input range Fast conversion Noise optimization Circuit Implementation Measurement Results Conclusion28.1:An 18.5nF-Input-Range PM-

22、SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference17 of 50Proposed PM-SAR Hybrid CDC PM front-end Sensor oscillator(S-OSC)Reference oscillator(R-OSC)Period-difference amplifier(PD AMP)SAR-ADC b

23、ack-endCharge pump(CP)SAR ADC10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBConversion StepConversion step Input capacitance(C)Period amplified(NT)CP voltage(V)ADC output(DLSB)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18

24、.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference18 of 50Basic Operation10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTS-OSCR-OSCTSTRConversion StepConversion step Input capacitance(C)Period amplified(NT)CP voltage(V)ADC output(DLSB)28.1:An 18.5n

25、F-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference19 of 50Basic Operation10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTS-OSCR-OSCTRTS=T CConversion St

26、epConversion step Input capacitance(C)Period amplified(NT)CP voltage(V)ADC output(DLSB)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference20 of 50Basic Operation10-

27、bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTS-OSCR-OSCNTSNTNTRConversion StepConversion step Input capacitance(C)Period amplified(NT)CP voltage(V)ADC output(DLSB)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF

28、 Input Capacitance 2025 IEEE International Solid-State Circuits Conference21 of 50Basic Operation10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTS-OSCR-OSCNTSNTRVInitially precharged at half VDDConversion StepConversion step Input capacitance(C)Period amplified(NT)CP voltage(

29、V)ADC output(DLSB)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference22 of 50Basic Operation10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUT

30、S-OSCR-OSCNTSNTRDLSBConversion StepConversion step Input capacitance(C)Period amplified(NT)CP voltage(V)ADC output(DLSB)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Con

31、ference23 of 50Basic Operation10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTS-OSCR-OSCNTSNTRDLSBConversion StepConversion step Input capacitance(C)Period amplified(NT)CP voltage(V)ADC output(DLSB)Special case(CS CR)so far,what if CS 2PCR?28.1:An 18.5nF-Input-Range PM-SAR Hy

32、brid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference24 of 501)Wide Input Range10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTNTVDLSBS-OSCR-OSCNTS2PNTRPeriod amplificationin dif

33、ferent ratiosConversion stepConversion Step C=CS 2PCR NT=N(2PTR TS)V NT DLSBV*P:0-to-10 integer 28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference25 of 501)Wide In

34、put Range10-bSARS-OSCR-OSCDMSBIUPIDNNPD AMPCPSAR ADCCSCRTSTRNTVCP+VDLSBVCPADC OUTNTVDLSBS-OSCR-OSCNTS2PNTRPeriod amplificationin different ratios*P:0-to-10 integer Wide input range up to CS 210CRw/o off-chip capacitor Easily extendable increasing P with divider chains in PD AMPConversion stepConvers

35、ion Step C=CS 2PCR NT=N(2PTR TS)V NT DLSBV28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference26 of 502)Time-Efficient Conversion Conventional PM CDCS-OSCR-OSCCRCS/M

36、TSMTSS-DIVRSTCLKCounterTRDOUT=M+MMTSTR=S-OSCR-OSCMTRTConv=MTSExcessive conv.time for baseline value of CS(M)to count C component(M)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State C

37、ircuits Conference27 of 502)Time-Efficient Conversion Proposed PM-SAR CDCS-OSCR-OSCCRCS10-bSARDLSBTRIUPIDNNNTTSPD AMPCPSAR ADCVCP+VS-OSCR-OSCPeriod difference amplifiedTConv NTSTConv 1001()NT28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18

38、.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference28 of 502)Time-Efficient Conversion Proposed PM-SAR CDCS-OSCR-OSCCRCS10-bSARDLSBTRIUPIDNNNTTSPD AMPCPSAR ADCVCP+VS-OSCR-OSCPeriod difference amplifiedTConv NTSTConv 100 faster than SoTA PM CDCs28.1:An 18.5nF-Input-Range PM

39、-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference29 of 503)Noise-Efficient ConversionS-OSCR-OSCCRCS10-bSARDLSBTRIUPIDNNNTTSPD AMPCPSAR ADCVCP+V SAR-ADC back-end provides much lower Q-noise th

40、an counter.CDC noise&energy optimized to PM front-end(S-&R-OSC)(S-&R-OSC)TConvNoise contribution1/f noiseQ-noise(ADC)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Confer

41、ence30 of 50Outline Motivation Proposed PM-SAR Hybrid CDC Circuit Implementation Measurement Results Conclusion28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference31

42、 of 50Overall Implementation CDC operation with fully-on-chip-generated clocks1:enables CP only when it is needed2:delivers CP output voltage to SAR ADC input3:enables SAR ADC only when it is neededS-OSCR-OSCCRTRDMSBIUPIDNCPCSNNTSARSwitches2C C29CDLSBSAR ADC231(RST)0(EN)S312BCSARVCP+VCCPTSPD AMP(ICP

43、=IUP=IDN)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference32 of 50 Startup difference inevitable between S-OSC&R-OSCInitial startup error affects DOUT.The error i

44、s canceled out by the front-end PD AMP.Overall Implementation28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference33 of 50S-OSC&R-OSC:RC Swing-BoostVSSVDDVoltage slop

45、e timing jitterJ.Lee,JSSC 20 FoMOSC=160.2dBc/Hz CRis determined proportional to DMSBby tri-state inverters.28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference34 of

46、50Period-Difference Amplifier(PD AMP)Counter block+dividers 2-stage operation1)Initial startup detection to cancel out2)Period amplified by dividers TRTSS-DIVR-DIVTSTRAdjacent edge detectorNSUABAB:Output HS-DIV first?R-DIV first?UPDNNTEN 2(N2P)EN 2NStartup detectorFrequency dividerPulse generator28.

47、1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference35 of 50S-DIVR-DIVVCPADC OUTS-OSCR-OSCSingle C2D Conversion:Startup DetectionTSUNSUperiods(S-OSC)VSUD1kAdjacent edge

48、(R-OSC)TRTSS-DIVR-DIVTSTRAdjacent edge detectorNSUABAB:Output HS-DIV first?R-DIV first?UPDNNTEN 2(N2P)EN 2NStartup detectorFrequency dividerPulse generator28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE Int

49、ernational Solid-State Circuits Conference36 of 50Single C2D Conversion:Period AmplificationS-DIVR-DIVVCPADC OUTS-OSCR-OSCTSUVSUD1kTSU+NTVSU+VD2kNTS2PNTRTRTSS-DIVR-DIVTSTRAdjacent edge detectorNSUABAB:Output HS-DIV first?R-DIV first?UPDNNTEN 2(N2P)EN 2NStartup detectorFrequency dividerPulse generato

50、r28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference37 of 50Single C2D Conversion(DLSB)S-DIVR-DIVVCPADC OUTS-OSCR-OSCTSUVSUD1kTSU+NTVSU+VD2kNTS2PNTR DLSBk=D1kD2k:1)

51、Desired C component(NT)2)Cancel DC offsets at SAR-ADC back-end DOUTk=2P(29DMSB+DLSBk)28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference38 of 50Coarse-Bit(DMSB)Sele

52、ction Process01023DMSB iswell-selectedDLSB:Fine scale255256DMSB:Coarse scale2PCRDLSBk1DLSBkDLSBk+1Time.Input capacitance Zoom conversion within the region of interest Once DMSBselected,DLSBconversion starts consecutively.28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchiev

53、ing 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference39 of 50Outline Motivation Proposed PM-SAR Hybrid CDC Circuit Implementation Measurement Results Conclusion28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.

54、1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference40 of 50Chip Micrograph and Measurement Setup65nm CMOS w/1V SupplyCore Area:0.209mm2PCE36312A Power SupplyDSOX3054T OscilloscopeFSWP8 Signal Source AnalyzerU3Pro32Logic AnalyzerArduino DUEDUTS-OSCR-

55、OSC237m287m287m237mPD AMP+CP397m161m67m131mSARADC28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference41 of 501)Input Range:18.5nF(b):18.1pF Input(a):18.5nF InputDIV=

56、1.0s/2.0VTStartupTAMPTADCD1k&D2k generatedOSC_RSTR-OSCS-OSC3(ADC reset)DIV=190s/2.0V=TStartup+TAMP+TADCConversion time TConvTAMPTADCTStartupD1k&D2k generatedR-OSCS-OSCOSC_RST3(ADC reset)101102103104102103104105106Crms aFrms105106107108109DOUTCS pF18,500(b)(a)28.1:An 18.5nF-Input-Range PM-SAR Hybrid

57、Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference42 of 502)Conversion Time:6.1s with 14.5b ENOB6533N=17for the same ENOBFastest TConvConv.time(TConv)s10210110010310491113151719ENOB bit7561211113910872143

58、415.4b 20s14.9b14.5b11s6.1sENOBTConvPM/IDD*SARMThis Work*Iterative delay-chain discharge106105104103102Conv.time(TConv)s101102103CS pF104 18.1pF Input1.2ms 18.5nF6.1s 18.1pF TConvover CS28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF

59、Input Capacitance 2025 IEEE International Solid-State Circuits Conference43 of 503)Noise and Energy Optimized to PM Front-End18.10318.102220230240Measured CS pFCrms aFrmsTime ms0.00.51.01.52.02.51234567Chip#233aFrms(worst case)Crms2=(233aFrms)2EConv=3.1nJRCOSCs89.3%Noise Crms2Conv.energy JADC1.6%RCO

60、SCs97.3%PD AMP+CP2.5%ADC0.2%PD AMP+CP9.1%28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference44 of 503)Noise and Energy Optimized to PM Front-End CDC performance nea

61、r the achievable limits101102105106Crms/C0Allan dev.33651292575131051061/f-noise levelof 2 oscillatorsTAMP s101102102103FoMW fJ/c-s.138TAMP s101102171173175170172174FoMS dBMax.achievable173.9N=17FoMSTAMP s/s28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conve

62、rsion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference45 of 50Comparison with State-of-the-Artsa:Input range extended by off-chip CRd:For a fair comparison,all the FoMW and FoMS are calculated by the same standards in slide 8.MethodProcess nmArea mm2Input rang

63、e pFConv.energy nJConv.time sENOB bitAbsoluteresolution aFrmsFoMW fJ/c-s.FoMS dB401801800.0017b0.1750.70010,00046,00033,0000.0354105.33192,9307908.0515.714.512,30011.3pF21840pF57445pF1417,740d234d154.8160d171.5dTwo-stepSB PMSwing-boosted(SB)PMIterative delay-chain discharge650.20918,500c3.16.114.523

64、318.1pF138173.9PM-SARhybridThis WorkTCAS-I2212ASSCC2213ISSCC1514SAR+2nd-orderTD 22180180280.0871.030.6900.065.16185.12 5.50.0241727.710.17852,4003205.311.518.817.413.737.12384fF11.0918pF8.785.12pF1195.5pF7.93674613177.6182.8187.4181.82nd-orderHP 4th-order CT-BP PipelinedSARISSCC234JSSC235JSSC246CICC

65、247c:Extendable with lower CP currentb:CR not included in the reported area28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference46 of 50Comparison with State-of-the-A

66、rtsa:Input range extended by off-chip CRd:For a fair comparison,all the FoMW and FoMS are calculated by the same standards in slide 8.MethodProcess nmArea mm2Input range pFConv.energy nJConv.time sENOB bitAbsoluteresolution aFrmsFoMW fJ/c-s.FoMS dB401801800.0017b0.1750.70010,00046,00033,0000.0354105

67、.33192,9307908.0515.714.512,30011.3pF21840pF57445pF1417,740d234d154.8160d171.5dTwo-stepSB PMSwing-boosted(SB)PMIterative delay-chain discharge650.20918,500c3.16.114.523318.1pF138173.9PM-SARhybridThis WorkTCAS-I2212ASSCC2213ISSCC1514SAR+2nd-orderTD 22180180280.0871.030.6900.065.16185.12 5.50.0241727.

68、710.17852,4003205.311.518.817.413.737.12384fF11.0918pF8.785.12pF1195.5pF7.93674613177.6182.8187.4181.82nd-orderHP 4th-order CT-BP PipelinedSARISSCC234JSSC235JSSC246CICC247c:Extendable with lower CP currentb:CR not included in the reported area28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-D

69、igital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference47 of 50Comparison with State-of-the-Artsa:Input range extended by off-chip CRd:For a fair comparison,all the FoMW and FoMS are calculated by the same standards in slide

70、8.MethodProcess nmArea mm2Input range pFConv.energy nJConv.time sENOB bitAbsoluteresolution aFrmsFoMW fJ/c-s.FoMS dB401801800.0017b0.1750.70010,00046,00033,0000.0354105.33192,9307908.0515.714.512,30011.3pF21840pF57445pF1417,740d234d154.8160d171.5dTwo-stepSB PMSwing-boosted(SB)PMIterative delay-chain

71、 discharge650.20918,500c3.16.114.523318.1pF138173.9PM-SARhybridThis WorkTCAS-I2212ASSCC2213ISSCC1514SAR+2nd-orderTD 22180180280.0871.030.6900.065.16185.12 5.50.0241727.710.17852,4003205.311.518.817.413.737.12384fF11.0918pF8.785.12pF1195.5pF7.93674613177.6182.8187.4181.82nd-orderHP 4th-order CT-BP Pi

72、pelinedSARISSCC234JSSC235JSSC246CICC247c:Extendable with lower CP currentb:CR not included in the reported area28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference48

73、 of 50Comparison with State-of-the-ArtsA CDC to support broad applications with1)Wide input range2)Fast conversion among similar ENOB3)Optimized noise-energy performance91113151719ENOB bit7Conv.time s102101100103104FoMS dB130160170190180140104103102101100105Input range pF150PMSARMOur goalOur goalwid

74、e-input-range(100pF)CDCsBest FoMS among For the same ENOBFastest TConv28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference49 of 50Outline Motivation Proposed PM-SAR

75、Hybrid CDC Circuit Implementation Measurement Results Conclusion28.1:An 18.5nF-Input-Range PM-SAR Hybrid Capacitance-to-Digital ConverterAchieving 6.1s Conversion Time at 18.1pF Input Capacitance 2025 IEEE International Solid-State Circuits Conference50 of 50Conclusion Wide-Input-Range Fast-Conversi

76、on PM-SAR Hybrid CDC is proposed:Easily extendable input range via PM front-end with the proposed PD AMPFast conversion by time-efficient SAR-ADC back-endOptimized noise-energy trade-off thanks to noise-efficient SAR-ADC back-end Performance Comparison with the State-of-the-Art CDCs18.5nF-input-rang

77、e without off-chip capacitors6.1s-conversion-time 18.1pF input and 14.5b ENOBBest FoMW(138fJ/c-s.)and FoMS(173.9dB)among wide-input-range(100pF)CDCs:The better oscillator performance,the better CDC performanceThank you for your attention!28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise

78、-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference1 of 47A 189.3dB-FoMS14.5fJ/Conversion-StepContinuous-Time Noise-Shaping SAR Capacitance-to-Digital ConverterGichan Yun1,Haidam Choi1,Yoontae Jung1,2,Jiho Myung1,Sein Oh1,Sohmyung Ha3,Minkyu Je11Kore

79、a Advanced Institute of Science and Technology,Daejeon,Korea2*now at imec,Leuven,Belgium3New York University Abu Dhabi,Abu Dhabi,United Arab Emirates28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuit

80、s Conference2 of 47Outline Backgrounds Proposed CDC Architecture Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference3 of 47Outline Back

81、grounds Proposed CDC Architecture Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference4 of 47Capacitive Sensors Principles Permittivity

82、variations()and distance variations(d)induce small capacitance change.0Distance(d)VariationPermittivity()VariationC 1dC C=Add028.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference5 of 47Capa

83、citive Sensors Applications Various physical quantities sensingHumidityPressureZ.Tan,JSSC13B.Assadsangabi,Sensors13P.Ciccarella,JSSC16Airborne Particles 28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Cir

84、cuits Conference6 of 47Target of the Proposed CDCSARPMMSARPMM170180190FoMSdBFoMWfJ/conv.-step104103100102160101102103104Resolution aFrmsFoMWfJ/conv.-step104103102101101105 Conventional M structure High resolution(FoMS)Limited energy efficiency(FoMW)10028.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Contin

85、uous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference7 of 47Target of the Proposed CDCSARPMMSARPMM170180190FoMSdBFoMWfJ/conv.-step104103100102160101102103104Resolution aFrmsFoMWfJ/conv.-step104103102101101105 Proposed M structure High res

86、olution(FoMS)High energy efficiency(FoMW)TargetTarget10010028.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference8 of 47Conventional M CDCsSignalCircuit noiseFrequencyPowerQ noiseCCVCDOUTLoop

87、Filter SAMM Quantization noise:over-sampling and noise-shaping Requiring for thermal noise and flicker noise mitigation28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference9 of 47CDOUTPrior

88、High-Resolution CDCsCT BP MDT HP NS-SARBP MCDOUTCT CVCHP NS-SARCDOUTCT CVC AAFSTFADCFrequencyVN,CVCPowerCVCfSAMCT CVC?SignalCircuit noiseFrequencyPowerQ noiseSignalCircuit noiseFrequencyPowerQ noiseCT CVCS.Park,JSSC23Y.Jung,JSSC2428.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping

89、 SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference10 of 47SignalCircuit noiseFrequencyPowerQ noiseCDOUTPrior High-Resolution CDCsCT BP MDT HP NS-SARBP MCDOUTCT CVCHP NS-SARCDOUTCT CVC AAFSTFADCVN,CVCPowerCVCfSAMCT CVC?CT CVCS.Park,JSSC23Y.Jung,JSSC24 Inhere

90、nt anti-aliasing(+)Resolution(+)Measurement time()Power consumption()Frequency28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference11 of 47CDOUTPrior High-Resolution CDCsCT BP MDT HP NS-SARB

91、P MCDOUTCT CVCHP NS-SARCDOUTCT CVC AAFSTFADCVN,CVCPowerCVCfSAMCT CVC?CT CVCS.Park,JSSC23Y.Jung,JSSC24 Inherent anti-aliasing(+)Resolution(+)Measurement time()Power consumption()Required AAF()Resolution(+)Measurement time()Power consumption(+)Frequency28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continu

92、ous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference12 of 47Prior High-Resolution CDCsThis WorkCT NS-SAR Inherent anti-aliasing(+)Resolution(+)Measurement time(+)Power consumption(+)CT BP MDT HP NS-SARBP MCDOUTCT CVCHP NS-SARCDOUTCT CVC A

93、AFS.Park,JSSC23Y.Jung,JSSC24 Inherent anti-aliasing(+)Resolution(+)Measurement time()Power consumption()Required AAF()Resolution(+)Measurement time()Power consumption(+)CDOUTCT CVC28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE In

94、ternational Solid-State Circuits Conference13 of 47Outline Backgrounds Proposed CDC ArchitectureFully Continuous-Time(CT)OperationChopper-based Highpass(HP)Loop FilterReplica Duty-Cycled Integrator(RDI)Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Con

95、tinuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference14 of 47Overall ArchitectureH(s)Replica Duty-CyclingHP Loop FilterCT NS-SAR ADC DRV DRVCINCoarseSARCVCCREF SAMDOUTCSAR CH CHSARLogicCDAC Power-efficient CT NS-SAR ADC with inherent a

96、nti-aliasing28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference15 of 47CT NS-SAR ADCH.Li,JSSC23CSARSwitchesVREFPVCMVREFNVCMCDACVINDOUTH(s)VRESVINTSARLogic INT SARVCMRBDuty-Cycled Integrato

97、r SAR INT SAR INTTimeVINDAC levelVRES Quantizing the non-sampled input with duty-cycled integratorTimeTimingTSAR28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference16 of 47IdealDuty(3%)Effe

98、cts of Duty-Cycling11.52fIN/fSAM|STF|dB200-60-200.5-400SignalbandAliasingbandfIN/fSAM|NTF|dB200-60-20-4010-110-2 Duty-cycling rate:3%&OSR:16 STF:anti-aliasing effect near the multiples of fSAM(28dB)NTF:0.5dB degradation of quantization noise suppression IdealDuty(3%)1-601.0250.975-40-2028.2:A 189.3d

99、B-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference17 of 47Fully Continuous-Time OperationCN,IN 22kTCINVDRV21+2RONgm7/3+4RONgmkTCINVDRV2CN,IN 2CINVDRV22(4kTRON+)16kT3gm2fBW,SIG(w.anti-aliasing)14.0aFrm

100、sSTFADCFrequencyVN,CVCCVC(w.o anti-aliasing)67.5aFrmsFrequencyVN,CVCPowerAliasingCINCF DRV DRVCTCVCCT NS-SARCINCF DRV DRV DRV DRVDTCVC Noise improvement by 4.8x with fully CT operationPower28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 202

101、5 IEEE International Solid-State Circuits Conference18 of 47Outline Backgrounds Proposed CDC ArchitectureFully Continuous-Time(CT)OperationChopper-based Highpass(HP)Loop FilterReplica Duty-Cycled Integrator(RDI)Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion

102、-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference19 of 47Loop Filter ImplementationCEQCT CVCDOUT CT CVC followed by the power-efficient CT NS-SAR ADC 2nd-order duty-cycled loop filter with feed-forward path2nd-OrderLoop Fi

103、lter28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference20 of 47CT LP NS-SAR CDC with Down-ConversionCEQCT CVC1.5DOUT,LPDOUT,HP Power efficient 2nd-order LP noise-shapingFrequencyPowerSigna

104、lCircuit noiseQ noise28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference21 of 47CT LP NS-SAR CDC with Down-ConversionCEQCT CVC1.5DOUT,LPDOUT,HP1/f noise&offsetFrequencyPowerSignal Power ef

105、ficient 2nd-order LP noise-shaping Low frequency noise Offset calibration due to DC shift Circuit noiseQ noise28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference22 of 47Equivalence Circuit

106、CEQCT CVC1.5DOUT,LPDOUT,HP1/f noise&offsetEquivalentCancelled Power efficient 2nd-order LP noise-shaping Low frequency noise Offset calibration due to DC shift FrequencyPowerSignalCircuit noiseQ noise28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Co

107、nverter 2025 IEEE International Solid-State Circuits Conference23 of 47CT HP NS-SAR CDCCEQCT CVCDOUT,LPDOUT,HPFrequencyPowerSignal1/f noise&offsetChopperembedded GM-C1.5 Power efficient 2nd-order HP noise-shaping Up-modulated low-frequency noise No offset calibration Circuit noiseQ noise28.2:A 189.3

108、dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference24 of 47Outline Backgrounds Proposed CDC ArchitectureFully Continuous-Time(CT)OperationChopper-based Highpass(HP)Loop FilterReplica Duty-Cycled Integ

109、rator(RDI)Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference25 of 47Prior Duty-Cycled IntegratorH.Li,JSSC23 DUTY DUTY DUTY DUTYVRES,PV

110、CMIBIASIBIASVX,NVY,NVINT,N DUTY DUTY DUTY DUTYVRES,NVCMVX,PVY,PVINT,P Two input branches are alternated in a current-steering manner.Error charges are induced during DC bias settling.Voltage drop during duty-cyclingVYVX DUTY28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR C

111、apacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference26 of 47Replica Duty-Cycled Integrator(RDI)Replica GMcell with shorted input is implemented.The DC bias level is maintained during duty-cycling.VRES,PCL1GM1GM2 DUTY CHVCMVCMCDMY CHCL2GM3 CH CH DUTY DUTYVINT2,PVINT

112、2,NVINT1,PVINT1,NVRES,N28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference27 of 47Operation of RDI:(n)thIntegration Phase GM1&GM3integrate the residue voltage.GM2maintains the DC bias leve

113、l to prevent voltage drop.CDMYCL1CL2GM3VINT2,PVINT2,NVINT1,PVINT1,NGM1GM2VCMVCMVRES,PVRES,N CH CH CH CH DUTY DUTY DUTYTiming DiagramCycle SAM SAR DUTY CH(n+1)th(n)thTSAM*TDUTY*TDUTY 28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE

114、International Solid-State Circuits Conference28 of 47Operation of RDI:(n+1)thSAR Conversion Phase Residue voltage is unavailable during SAR conversion.CDMYCL1CL2GM3VINT2,PVINT2,NVINT1,PVINT1,NGM1GM2VCMVCMVRES,PVRES,NCDAC switching CH CH CH CH DUTY DUTYTiming DiagramCycle SAM SAR DUTY CH(n+1)th(n)thT

115、SAM*TDUTY*TDUTY 28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference29 of 47Operation of RDI:(n+1)thSAR Conversion Phase Switching noise from CDAC switching is bypassed to CDMY.CDMYCL1CL2GM

116、3VINT2,PVINT2,NVINT1,PVINT1,NGM1GM2VCMVCMVRES,PVRES,NCDAC switchingBypass to CDMY CH CH CH CH DUTY DUTYTiming DiagramCycle SAM SAR DUTY CH(n+1)th(n)thTSAM*TDUTY*TDUTY 28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International S

117、olid-State Circuits Conference30 of 47Operation of RDI:(n+1)thSAR Conversion Phase CL1&CL2hold the integrated voltages.No error charge integrationCDMYCL1CL2GM3VINT2,PVINT2,NVINT1,PVINT1,NGM1GM2VCMVCMVRES,PVRES,N CH CH CH CH DUTY DUTYTiming DiagramCycle SAM SAR DUTY CH(n+1)th(n)thTSAM*TDUTY*TDUTY 28.

118、2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference31 of 47Operation of RDI:(n+1)thIntegration Phase Residue signal is demodulated and integrated.Flicker noise and offsets are up-modulated to

119、 out-band.CDMYCL1CL2GM3VINT2,PVINT2,NVINT1,PVINT1,NGM1GM2VCMVCMVRES,PVRES,N CH CH CH CH DUTY DUTY DUTYTiming DiagramCycle SAM SAR DUTY CH*TDUTY*TDUTY(n+1)th(n)thTSAM28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Sol

120、id-State Circuits Conference32 of 47Outline Backgrounds Proposed CDC Architecture Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference33

121、 of 47Overall Circuit SchematicVRES,NVCMCFRF RSTCFRF RSTCSARCSARVRES,PVRES,NVCMCL1GM1GM2 DUTY CHVCMVCMCDMY CHReplica Duty-CycledIntegratorCL2GM3 CH CH SARDOUTSAR DUTY DUTYVINT2,PVINT2,NVINT1,PVINT1,NVRES,PSwitches8CU16CUCUVREFPVCMVREFNSwitches8CU16CUCUVREFNVCMVREFPCF=100fFCSAR=640fFCU=10fFCL1,DMY=5p

122、FCL2=3.5pFRBRB SAMC28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference34 of 47CT CVC&Coarse SARCoarse SARS.Park,JSSC19CFRF RSTCFRF RSTSARLogicVCM64CCVOUT,PVOUT,N128CD7D6D0D7D6D0 DRV DRVCIN

123、On-chip CREFDVN1VN2VP2VOUTPVOUTNVCMFBVINPVINN On-chip 8b CDAC with an unit capacitance of 20fF for CREF5A28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference35 of 47CT CVC&Coarse SARCFRF RS

124、TCFRF RSTSARLogicVCM64CCVOUT,PVOUT,N128CD7D6D0D7D6D0 DRV DRVCINOn-chip CREFDCoarse SARS.Park,JSSC19 40%of the SAR ADCs input range(1b redundancy)0.48Vpp(Max)TimeVOUT0.6V0.6V28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE Internati

125、onal Solid-State Circuits Conference36 of 47Circuit Diagram for RDI Degeneration resistor(RD):200kVCMFBVP2VN2VN1VINT1,PVINT1,N CH CHVRES,PVRES,NVP1 DUTYFolding input stage of GM1Cascode stage of GM1CL1100nARDRD200nAVCMVCMVP1Folding input stage of GM2RDRDCascodestage of GM228.2:A 189.3dB-FoMS14.5fJ/C

126、onversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference37 of 47Outline Backgrounds Proposed CDC Architecture Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-Time

127、Noise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference38 of 47Die Micrograph&Measurement SetupCDACCDACCVC340m520mCT NS-SAR ADC530m430mSPIFaraday CagePCBatteryDUTLogic AnalyzerFPGA 180-nm 1P6M CMOS process Core area:0.41mm228.2:A 189.3dB-FoMS14.5fJ/

128、Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference39 of 47CDC Output Spectrum100Frequency kHz100989694Power dB0-40-80-160-120-20-60-140-100CIN=2.56pFCIN=5.12pFfSAM=200kHzOSR=16102030405060708090Frequency kHzPower

129、dB0-40-80-160-120-20-60-140-100CIN=2.56pFCIN=5.12pF0 FFT of 128k-point with 2.56pF and 5.12pF input capacitance 2nd-order highpass noise-shaping28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Con

130、ference40 of 47CDC Output Spectrum with Demodulation105Frequency Hz103102101Power dB0-40-80-160-120-20-60-140-100CIN=2.56pFCIN=5.12pFfSAM=200kHzOSR=16101102103104Frequency HzPower dB0-40-80-160-120-20-60-140-100CIN=2.56pFCIN=5.12pF FFT of 128k-point with 2.56pF and 5.12pF input capacitance 2nd-order

131、 lowpass noise-shaping40dB/dec.28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference41 of 47Capacitance Resolution2000400060008000Number of ConversionsCapacitance Dev.aF100500-100-500CIN=5.1

132、2pFMeasured Capacitance pF5.12015.120055.119955.1199Number of Bins2000010005001500CIN=5.12pF=17.5aF5.12 Decimated after demodulation to DC Capacitance resolution:17.5aFrms(CIN=5.12pF)28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE

133、 International Solid-State Circuits Conference42 of 47Capacitance Resolution vs.OSR&Variation 101102Over-Sampling RatioCapacitance Res.aFrms103102101100Chip No.5421Capacitance Res.aFrms2018101412163CVC noise dominantADC noisedominantOSR=16CIN=2.56pFCIN=5.12pFCIN=2.56pFCIN=5.12pF Thermal noise domina

134、tes when OSR is above 16.Worst case among 5 samples:17.7aFrms(CIN=5.12pF)12.9aFrms13.6aFrms17.1aFrms17.7aFrms28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Solid-State Circuits Conference43 of 47Measured vs.Input ca

135、p.&Power BreakdownCT CVC6.1WDigital6.9WTotal:15.2WGM-C2.2W1235Input Capacitance pFMeasured Capacitance pF532010445.12pF Input range:0-5.12pF Total power consumption:15.2W(fSAM=200kHz)28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE

136、 International Solid-State Circuits Conference44 of 47Comparison TableJSSC22 10ISSCC23 11JSSC23 6JSSC24 5CICC24 12This workArchitectureDT NS-SARPipelined-SARCT BPMDT HP NS-SARSAR+TD-MCT HPNS-SARProcess nm1802218018028180Input Range0-13.6pF0-5.16pF0-18pF0-5.12pF0-5.5pF0-5.12pFOSR16-256641616Meas.Time

137、 s50-5000524003205.380Power W0.69-63.284.7171.724.133.615.2Resolution aFrms172(13.6pF)37.12(384fF)3.68(10fF)11.09(18pF)5.85(2.56pF)8.78(5.12pF)86(0.5pF)119(5.5pF)13.6(2.56pF)17.7(5.12pF)SNR1dB88.971.3115.2106.384.3100.2FoMW2fJ/conv.-step139(13.6pF)7.9(384fF)373(18pF)61(2.56pF)46(5.12pF)13.2(5.5pF)22

138、.4(2.56pF)14.5(5.12pF)FoMS3dB173.8(13.6pF)177.5(384fF)182.8(18pF)184.9(2.56pF)187.4(5.12pF)181.8(5.5pF)185.6(2.56pF)189.3(5.12pF)1=20 102 2 .2=.21.76/6.023=+10 101.28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Soli

139、d-State Circuits Conference45 of 47Performance SummarySARPMMSARPMM170180190FoMSdBFoMWfJ/conv.-step104103100102160101102103104Resolution aFrmsFoMWfJ/conv.-step104103102101101105100ProposedProposed28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Convert

140、er 2025 IEEE International Solid-State Circuits Conference46 of 47Outline Backgrounds Proposed CDC Architecture Circuit Implementation Measurement Results Conclusion28.2:A 189.3dB-FoMS14.5fJ/Conversion-Step Continuous-TimeNoise-Shaping SAR Capacitance-to-Digital Converter 2025 IEEE International Sol

141、id-State Circuits Conference47 of 47Conclusion High-resolution energy-efficient CT HP NS-SAR CDC Fully continuous-time operation Chopper-based highpass loop filter Replica duty-cycled integrator(RDI)Compared to the state-of-the-art CDCs:Power:15.2W,resolution:17.7aFrms,meas.time:80s FoMS:189.3dB(bes

142、t FoMSamong state-of-the-art CDCs)FoMW:14.5fJ/conv.-stepThank you for your attention!28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Ci

143、rcuits Conference1 of 51A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation TechniqueBingrui Li,Zilong Shen,Haoyang Luo,Jiachang Yang,Zongnan Wang,Yuan Wang,Xiyuan Tang Peking University,Bei

144、jing,China28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference2 of 51Outline Motivation Proposed Zoom CDCChopping-based

145、kT/C noise cancellationAdd-then-subtract phase-domain lead compensationAdaptively-biased cascoded FIA Circuit Implementation Measurement Results Conclusion28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Dom

146、ain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference3 of 51Outline Motivation Proposed Zoom CDCChopping-based kT/C noise cancellationAdd-then-subtract phase-domain lead compensationAdaptively-biased cascoded FIA Circuit Implementation Measurement Results Conclusion

147、28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference4 of 51 Real-time(RT)applications require CDCs withLow latencyHigh r

148、esolutionGood energy efficiencyCDC Requirements in RT Systems28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference5 of 51

149、Zoom CDC with Time-Domain M Zoom architecture:High resolution High energy efficiency Time-domain(TD)M:Infinite DC gain Intrinsic multi-bit quantizer Scaling-friendly Mostly digital Tang,ISSCC 2019Shen,CICC 2024Li,JSSC 202428.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Cho

150、pping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference6 of 51Challenges in RT Systems Challenge 1:low latency reduced OSRSampling noise problem is exacerbated 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capa

151、citance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference7 of 51Challenges in RT Systems Challenge 2:high resolution high-order loopFeedforward compensationVCO intrin

152、sically fused integrator and quantizer hard to feedforward Better linearity Lower hardware cost 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Sol

153、id-State Circuits Conference8 of 51Challenges in RT Systems Challenge 2:high resolution high-order loopFeedforward compensationFeedforward at 1st-stage integrator Matching or kickback problems Better linearity Lower hardware cost 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter

154、with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference9 of 51Outline Motivation Proposed Zoom CDCChopping-based kT/C noise cancellationAdd-then-subtract phase-domain lead compensationAdaptivel

155、y-biased cascoded FIA Circuit Implementation Measurement Results Conclusion28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Con

156、ference10 of 51Overall Architecture Zoom SAR+2nd-order TD MChopping-based kT/C noise cancellationAdd-then-subtract phase-domain lead compensationAdaptively-biased cascoded FIA28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-The

157、n-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference11 of 51Prior kT/C Noise Cancellation Eliminate kT/C noise by CDSCancel 1/f noise and offset Extra power consumption Extra noise extraction time Gao,ISSCC 2023Shen,CICC 202428.3:A 185.2dB-FoMs

158、8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference12 of 51Chopping-Based kT/C Noise Cancellation Eliminate kT/C noise by choppingCancel 1/

159、f noise and offset No extra hardware cost No extra time cost Ezekwe,ISSCC 2008Jie,ISSCC 202228.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-S

160、tate Circuits Conference13 of 51Chopping-Based kT/C Noise Cancellation Sampling phase kT/C noise is sampled28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE Intern

161、ational Solid-State Circuits Conference14 of 51Chopping-Based kT/C Noise Cancellation Coarse conversion phase(SAR phase)kT/C noise is preserved at the top plate28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phas

162、e-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference15 of 51Chopping-Based kT/C Noise Cancellation Fine conversion phase(M phase)kT/C noise is chopped together with the offset of Gm128.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Cho

163、pping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference16 of 51Chopping-Based kT/C Noise Cancellation Fine conversion phase(M phase)kT/C noise is chopped together with the offset of Gm128.3:A 185.2dB-F

164、oMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference17 of 51Chopping-Based kT/C Noise Cancellation 2nd-order chopping pattern to match d

165、ecimation filter weightsChopping pattern=+1-1-1+128.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference18 of 51Prior Feedf

166、orward Compensation in TD M Pseudo-virtual ground feedforwarding techniqueFeedforward compensation at the 1st-stage integratorVCO noise kickback Pochet,JSSC 202228.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Pha

167、se-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference19 of 51Prior Feedforward Compensation in TD M Feedforward based on Gm-RC integratorFeedforward compensation at the 1st-stage integratorkf/k1=RkfC1 bad matching Lee,JSSC 2020Shen,CICC 202428.3:A 185.2dB-FoMs

168、 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference20 of 51Proposed Compensation Technique Add-then-subtract phase-domain lead compensatio

169、nFeedforward compensation at the 2nd-stage integratorNo kickback path from VCO to DAC kf/k2=Gmkf/Gmk2 good matching 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IE

170、EE International Solid-State Circuits Conference21 of 51Proposed Compensation Technique Before phase quantization(1 phase)k2n and kfn are added to n-1i:the differential phase of the dual-CCO28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellat

171、ion and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference22 of 51Proposed Compensation Technique Before phase quantization(1 phase)k2n and kfn are added to n-128.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with C

172、hopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference23 of 51Proposed Compensation Technique After phase quantization(2 phase)kfn is subtracted from n28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitanc

173、e-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference24 of 51Proposed Compensation Technique After phase quantization(2 phase)kfn is subtracted from n28.3:A 185.2dB-FoM

174、s 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference25 of 51Proposed Compensation Technique kfcontributes to quantization w/o affecting th

175、e integratorThe feedforward path is implemented equivalently28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference26 of 51

176、1st-stage Loop Filter Design Open-loop dynamic IntegratorHigh efficiency Floating Inverter Amplifier(FIA)is a good candidateCurrent reuse Intrinsic CMFB Tang,JSSC 2020 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtr

177、act Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference27 of 511st-stage Loop Filter Design Conventional FIAHigh transconductance Insufficient DC gain VCM-based cascoded FIALarge DC gain Low transconductance Tang,JSSC 2020 Tang,ISSCC 2021 28.3:A 185.2dB-F

178、oMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference28 of 51Proposed Loop Filter Adaptively-biased cascoded FIA28.3:A 185.2dB-FoMs 8.7-a

179、Frms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference29 of 51Proposed Loop Filter Adaptively-biased cascoded FIABalanced transconductance and DC g

180、ain High energy efficiency Proposed FIA transitions gradually from a conventional FIA to a cascoded one28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE Internatio

181、nal Solid-State Circuits Conference30 of 51Proposed Loop Filter Adaptively-biased cascoded FIAThick-oxide devices to avoid gate leakageDummy transistors for kickback cancellationSplit CR for performance fine control28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-B

182、ased kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference31 of 51Output CM Variation of FIA The output CM variation comes fromUnbalanced parasiticsInput common-mode voltage variationProcess variation FIA serves

183、 as a Gm-C integrator in the oversampling systemCLOAD is not reset,and repeated FIA operations accumulate errors,Tang,JSSC 2020 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Techn

184、ique 2025 IEEE International Solid-State Circuits Conference32 of 51Conventional Chopping28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-Stat

185、e Circuits Conference33 of 51Conventional Chopping28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference34 of 51Convention

186、al ChoppingCM errors will accumulate and degrade system robustness28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference35

187、 of 51Output CM Variation of FIA The output CM variation comes fromUnbalanced parasiticsInput common-mode voltage variationProcess variationThe output CM variation is similar in different Fine Conv.FIA ResetFIA IntegrateFIA Reset28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter w

188、ith Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference36 of 51CM-Variation-Tolerant Chopping28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise

189、Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference37 of 51CM-Variation-Tolerant Chopping28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subt

190、ract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference38 of 51CM-Variation-Tolerant Chopping28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compens

191、ation Technique 2025 IEEE International Solid-State Circuits Conference39 of 51CM-Variation-Tolerant ChoppingThe output CM voltage remains VCMwithout CMFB28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Doma

192、in Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference40 of 51Outline Motivation Proposed Zoom CDCChopping-based kT/C noise cancellationAdd-then-subtract phase-domain lead compensationAdaptively-biased cascoded FIA Circuit Implementation Measurement Results Conclusion

193、28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference41 of 51Zoom CDC Design Zoom SAR+2nd-order TD M 1st-stage integrator

194、:Gm-C 2nd-stage integrator:Gm-CCO28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference42 of 51Zoom CDC Design 9-bit Coars

195、e SAR CDC(1-bit redundancy)28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference43 of 51Zoom CDC Design 5-bit Fine CDC 2n

196、d-order CIFF architecture Time-domain operation28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference44 of 51Outline Motiv

197、ation Proposed Zoom CDCChopping-based kT/C noise cancellationAdd-then-subtract phase-domain lead compensationAdaptively-biased cascoded FIA Circuit Implementation Measurement Results Conclusion28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancel

198、lation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference45 of 51Chip Micrograph 28nm CMOS Active area:0.032mm2 Analog supply:1V Digital supply:0.5V Measurement time:10.4s One-time foreground calibration is adopted to address capaci

199、tor mismatches28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference46 of 51Measurement Range&Spectrum Measurement range:0

200、1.2pFMeas.Time=10.4sCS=1.2pFCrms=8.7aFSNR=93.8dB 28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference47 of 51Measurement

201、 Resolution Crms 1.2pF=8.7aF；Crms 13fF=5.0aF28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference48 of 51PVT Robustness&P

202、ower Breakdown 2.7dB&1.9dB variations under temperature&supply variations 70.1W 27 temperature,1/0.5V supply voltage28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IE

203、EE International Solid-State Circuits Conference49 of 51Comparison with Prior WorksISSCC-23 GaoCICC-23 JungJSSC-23 ParkJSSC-24 JungCICC-24 ShenISSCC-21 LiThis WorkProcess nm22651801802811028ArchitecturePipelined-SARLP MCT-BP MHP MZoom SAR+MSupply V1.11.2/0.81.11.3/1.20.91.21/0.5Active Area mm20.0460

204、.130.580.690.060.460.032Cap.Range pF0-5.160-2.560-180-5.120-5.50-3.150-1.2OSR1162566416101128Meas.Time s512824003205.3101010.4Power W4.719.871.724.133.61.02-3.1970.1Resolution aF37.12(384fF)25.2(140fF)-30.9(2.38pF)3.68(10fF)-11.09(18pF)5.85(2.56pF)-8.78(5.12pF)86(0.5pF)-119(5.5pF)17.9(1pF)5.0(13fF)-

205、8.7(1.2pF)SNR1dB71.3(384fF)88.7(2.38pF)115.2(18pF)106.3(5.12pF)84.3(5.5pF)85.9(1pF)93.8(1.2pF)FoMw2fJ/c-s7.9(384fF)56.4(2.38pF)373(18pF)46(5.12pF)13.2(5.5pF)94(1pF)18.2(1.2pF)FoMs3dB177.5(384fF)177.7(2.38pF)182.8(18pF)187.4(5.12pF)181.8(5.5pF)174.1(1pF)185.2(1.2pF)1=20 log102 22W=.21.76/6.023S=+10 l

206、og101.28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference50 of 51Performance Summary Best SNR and FoMs among low-latenc

207、y CDCs(10s meas.time)28.3:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique 2025 IEEE International Solid-State Circuits Conference51 of 51Conclusion Zoomed Capacitance-to-Digita

208、l ConverterLow-cost chopping-based kT/C noise cancellationAdd-then-subtract phase-domain lead compensation for loop stabilityAdaptively-biased cascoded FIA with CM-variation-tolerant chopping Compared to the prior Capacitance-to-Digital ConvertersHigh resolution with a short measurement timeState-of

209、-the-art energy-efficiency Slide 51Thank you for your attention!28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference1 of 42A 143dB Dynamic Range 119dB CMRR Capacitance-t

210、o-Digital Converter for High-Resolution Floating-Target Displacement Sensing Sining Pan1,Xiaolong Zhang1,Baoyi Zheng1,Yihang Cheng1 Hui Jiang2 and Huaqiang Wu11 School of Integrated Circuits,Tsinghua University,China2 CoSensing,Utrecht,the Netherlands28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance

211、-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference2 of 42Micro-epsilonMotivationof thin gaps28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sens

212、ing 2025 IEEE International Solid-State Circuits Conference3 of 42 Eddy-CurrentVikram,JSSC18 CapacitiveJiang,SSCL20Ravi,Sensors18 Laser MagneticYang,Sensors09Displacement Sensor Types28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displaceme

213、nt Sensing 2025 IEEE International Solid-State Circuits Conference4 of 42 Displacement Cs of a single parallel plate capacitor High energy efficiency Not contactless Jiang,SSCL20Conventional Capacitance Sensing Method28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Res

214、olution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference5 of 42Target PlateProbeCSdCPSingle-ended CDCViQS Coupled electrical interference via parasitic cap CP QNIndistinguishable with the signal QSConventional Capacitance Sensing MethodQN28.4:A 143dB-Dynam

215、ic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference6 of 42QSProbeCS1CS2dDifferential CDCTarget PlateCPVi Differential CS1and CS2 Floating target Interference becomes CM High interference

216、 immunity Differential Floating Target SensingJiang,SSCL20QN28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference7 of 42CS1CS2CPVDDAmp.Freq.FS/2QN noise foldingQNVDD CS t

217、o QSS T SC ADCViQSFS Signal charge QSfrom sampling VDDusing stacked CS CSmismatch QN limited CMRR Switched capacitor readout QNfolding and degraded CMRRJiang,SSCL20Amp.Freq.FS/2QN noise foldingSwitched-Capacitor Readout28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-R

218、esolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference8 of 42Proposed Cont.Time RC Readout CS-dependent phase(current)Swith a fixed FD=1st-order RC low-pass filterCS1CS2RSRS CS to SRSRSRS-ADCSFSJiang,ISSCC2128.4:A 143dB-Dynamic-Range 119dB-CMRR Capacit

219、ance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference9 of 42Proposed Cont.Time RC Readout CS-dependent phase(current)Swith a fixed FD CSmismatch QN RC topology QNHP filtered improved CMRRCS1CS2CPRSQNFD RS CS to SRSR

220、SRS-ADCSFSViAmp.Freq.FS/2QN noise filtering28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference10 of 42CS1CS2CPRSQNFD RS CS to SVi-ACINTCT first stageSPDMRSRSRSProposed

221、Cont.Time RC Readout RC low-pass filter generates a CS-dependent phase(current)S CSmismatch QN Cont.time readout QNLP filtered improved CMRRAmp.Freq.FS/2QN noise filtering28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2

222、025 IEEE International Solid-State Circuits Conference11 of 42Proposed RC Front-end:a Closer Look10-1100101102103022.54567.590CS(pF)S()RC low-pass filter(RS=32k),FD=1MHz,Srange of 0,90 A proper phase DAC ultra wide CSsensing rangeCS1CS2RSRS CS to SRSRSRS-ADCSFS28.4:A 143dB-Dynamic-Range 119dB-CMRR C

223、apacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference12 of 42Effect of Parasitic Capacitance CPAR reduced Srange,still wide CSsensing range10-1100101102103022.54567.590CPAR effectCS(pF)S()RSRSRSRSCS1CS2Target

224、PlateCPAR1CPAR2On-chip-ADCFSS28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference13 of 42Readout ArchitecturePan,JSSC18 2nd-order Phase-Domain Modulator(PDM)Chopper-base

225、d demodulatorCint1Cint1SgmRffRffCint2MUX10BSSCH-ARC front-endFD 28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference14 of 42Effect of ZIN ZINof the PDM(1st-stage integ.)

226、is not distinguishable with RS Should be minimized to reduce phase sensing errorsIdealPDMFSCS1RSRS CS to SRSFD ZINPDMFSCS1RSRS CS to SRSSS28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-Stat

227、e Circuits Conference15 of 42 Feedforward compensated Opamp large bandwidth Combined with high Opamp gain minimized ZIN sensing error of 143dB with Inter.OSC 147dB with Exter.OSCDynamic Range28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Di

228、splacement Sensing 2025 IEEE International Solid-State Circuits Conference32 of 42 Characterized sensing range:25m 600m(25m step)Overall effect of displacement to cap.sensitivity and cap.resolution Displacement resolution varies by less than 2xDisplacement Sensing2KGMain PCBElectrode PCBMylar spacer

229、s(25 um thick)Metal plateMetal frameSetup28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference33 of 42Down convert all interferences to 1kHz for a fair comparisonBandpass

230、 noise filtering featureCS1CS2CPRSQNFD RS CS to SRSRSRS-ADCSFSViCS=4pF,CP=10pF,Ext.FD=1MHz,2VPPsinusoid ViCMRR28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Conference34 of 4

231、2 Relatively flat CMRR near multiples of FD(=1MHz)8 samples measured Worst CMRR near DC:119dB Worst CMRR near 100MHz:97dBCMRR28.4:A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing 2025 IEEE International Solid-State Circuits Co

232、nference35 of 42Comparison with State-of-the-ArtSSCL202ISSCC123 JSSC174 Sensors235This workOff-chip FrefOn-chip FrefSensor typeDTDSMDTDSMDTDSMDTDSMCTDSMCMOS Technology180 nm350 nm350 nm130 nm180 nmChip area mm20.52.660.2640.255Capacitance range pF01001062202150500Resolution aF423.5pF6510pF425.5pF426

233、4.4pF21.34pF35.24pFDynamic range dB107.5103.7114.4105147143Power consumption W560150007604040499625Conversion time ms10.0210.54.12FoM Jppm2115.712.770423352544145Temperature drift ppm/C-7.5 a-1500147143Power consumption W560150007604040499625Conversion time ms10.0210.54.12FoM Jppm2115.712.7704233525

234、44145Temperature drift ppm/C-7.5 a-1500147143Power consumption W560150007604040499625Conversion time ms10.0210.54.12FoM Jppm2115.712.770423352544145Temperature drift ppm/C-7.5 a-1500147143Power consumption W560150007604040499625Conversion time ms10.0210.54.12FoM Jppm2115.712.770423352544145Temperatu

235、re drift ppm/C-7.5 a-1500147143Power consumption W560150007604040499625Conversion time ms10.0210.54.12FoM Jppm2115.712.770423352544145Temperature drift ppm/C-7.5 a-1500147143Power consumption W560150007604040499625Conversion time ms10.0210.54.12FoM Jppm2115.712.770423352544145Temperature drift ppm/C-7.5 a-1500143dB)Wide temperature range(TC143dB)Wide temperature range(TC24.7ppm/C from-40C to 85C)Enabled by:Novel differential RC front-end High resolution PDM Frequency-based temperature compensationThank you for your attention!