Session 27Sensor Interfaces.pdf

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1、Session 27 Overview:Sensor Interfaces ANALOG SUBCOMMI TTEEDuty-cycling and dynamic biasing improve power ef ficiency and scalability of sensor interf aces,while precision circuit techniques enable new levels of absolute accuracy.The first paper describes a partially duty-cycled MEMS Gyroscope drive

2、control loop that minimizes standby power dissipation,while the third paper presents a f requency-controlled biasing method that enables a wide range of conversion rates.The second paper demonstrates a CMOS Hall sensor with state-of-the-art of f set perf ormance.Two final papers present temperature

3、sensors that achieve state-of-the-art perf ormance in both their power ef ficiency and temperature-sensing inaccuracy.Session Chair:Caspar van Vroonhoven Analog Devices,Munich,Germany Session Co-Chair:Chinwuba Ezekwe Robert Bosch,Sunnyvale,CA 468 2025 IEEE International Solid-State Circuits Conf ere

4、nceI SSCC 2025/SESSI ON 27/SENSOR I NTERFACES/OVERVI EW979-8-3315-4101-9/25/$31.00 2025 IEEE8:25 AM 27.2 A Volt age-Biased CMOS Hall Sensor wit h 1.0T(3)Offset and a 60nT/Hz Noise-Floor Floris J.P.van Mourik,TU Delf t,Delf t,The Netherlands In Paper 27.2,TU Delf t presents a voltage-biased CMOS Hall

5、 sensor.Octagonal Hall plates are operated in spinning-current mode and read out using a current-to-digital converter.The sensor achieves a magnetic field of f set of 1.0T(3)and a noise floor of 60nT/Hz.8:50 AM 27.3 A Sub-1V 14b 5.8nW/Hz BW/Power-Scalable CT Sensor I nt erface wit h a Frequency-Cont

6、 rolled Current Source Achieving a 225 Scalable Range Xinjie Wu,Zhejiang University,Hangzhou,China In Paper 27.3,Zhejiang University and Vango Technologies present a continuous-time sensor interf ace.A f requency-controlled current source enables a gm-C CTM to achieve a near-consistent SNDR of 84dB

7、over a 225 bandwidth range.The sensor interf ace operates f rom a sub-1V supply,has an input-ref erred noise density of 46nV/rtHz and an FoM of 178.2dB.9:15 AM 27.4 A BJT-Based Temperat ure Sensor wit h an 80fJK2 Resolut ion FoM Nandor G.Toth,TU Delf t,Delf t,The Netherlands In Paper 27.4,TU Delf t

8、presents an NPN-based temperature sensor that uses a noise-optimized charge-balancing scheme and a current-assisted two-stage amplifier to improve both energy ef ficiency and accuracy.The sensor achieves an 80f JK2 resolution FoM and an inaccuracy of 0.1C(3)f rom-70C to 125C.9:30 AM 27.5 A 4,100m2 W

9、ire-Met al-Based Temperat ure Sensor wit h a Fract ional-Discharge FLL and a Time-Domain Amplifier wit h 0.2C I naccuracy(3)from 40 t o 125C and 45fJK2 Resolut ion FoM in 28nm CMOS Dan Shi,University of Macau,Macau,China In Paper 27.5,the University of Macau presents a wire-metal-based temperature s

10、ensor that uses a f ractional-discharge f requency-locked-loop and a time-domain amplifier to achieve a resolution FoM of 45f JK2 and an inaccuracy of 0.2C(3)f rom-40C to 125C.I SSCC 2025/February 19,2025/8:00 AM469 DIGEST OF TECHNICAL PAPERS 8:00 AM 27.1 A 3-Axis MEMS Gyroscope wit h 2.8ms Wake-Up

11、Time Enabled by a 1.5W Always-On Drive Loop Ling Wang,Xidian University,Xian,China In Paper 27.1,Xidian University presents a MEMS Gyroscope with an always-on drive loop,enabled by a burst-mode phase-locked loop.A partially duty-cycled drive excitation loop maintains the gyroscope in semi-stable osc

12、illation to enable a wake-up time of 2.8ms while limiting the average standby power consumption to 1.5W.27470 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025/SESSI ON 27/SENSOR I NTERFACES/27.1979-8-3315-4101-9/25/$31.00 2025 IEEE27.1 A 3-Axis MEMS Gyroscope wit h 2.8ms Wake-Up T

13、ime Enabled by a 1.5W Always-On Drive Loop Longjie Zhong1,Jinwen Zhang1,Chengyue Li1,Ling Wang1,Mingsheng Zhong1,Kangkang Cai2,Ji Gao2,Tiegang Hu2,Zhangming Zhu1 1Xidian University,Xian,China 2Silan Microelectronics,Hangzhou,China MEMS gyroscopes are widely used in mobile and wearable devices with h

14、uman-machine interf aces f or motion detection and indoor navigation 1-5.In these applications,the always-on mode(i.e.,standby or suspend mode)is required to support event-driven operation and extend battery lif e 3-5.One of the key design challenges is the trade-of f between the always-on current c

15、onsumption and the wake-up time.To meet this challenge,an always-on MEMS gyroscope with burst-mode phase-locked loop(BPLL)technique was reported,which achieved an always-on current of 737nA and a wake-up time of 5.45ms 6.However,the BPLL-based drive loop suf f ers f rom an instability problem due to

16、 the parasitic-relaxation-oscillation(PRO)ef f ect triggered by temperature variation,deteriorating the reliability.This paper presents an always-on MEMS gyroscope employing a duty-cycle-automatic-optimization(DAO)technique to control the PRO,achieving a wake-up time of 2.8ms and 5%wake-up time stab

17、ility f rom 40 to 85C.The conventional BPLL-based drive channel f or the always-on gyroscope is shown in the top of Fig.27.1.1 6.The capacitance-to-voltage converter(C/V),the peak detection circuit,the bandgap ref erence(BGR),the low-power track-and-hold circuit(T&H)and the driver buf f er constitut

18、e a loop(highlighted in blue)f or amplitude regulation of the drive voltage VDRV.The C/V,the comparator,the BPLL and the driver buf f er constitute a loop(highlighted in red)f or f requency regulation of the drive voltage VDRV.In the normal operation mode,in order to accurately detect a Coriolis sig

19、nal,both loops of the drive channel are f ully powered and guarantee the oscillation of the sensor with fine-resonance amplitude control.This is achieved by regulating the amplitude of the drive voltage VDRV with its f requency locked to the resonance f requency D of the sensor.In the always-on mode

20、,in order to achieve low current consumption and f ast wake-up time,the drive channel is duty-cycle powered and guarantees the oscillation of the sensor with coarse-resonance amplitude control.This is achieved by shutting down the most power-hungry modules with the help of a drive-power-gate(DPG)sig

21、nal during the major time TS,and powering all modules to correct the drive voltage error during the minor time TC.As a result,the average current consumption can be significantly reduced to TC/(TC+TS)(typically more than 100).The smaller the correction time TC is,the lower the average current consum

22、ption will be.However,the parasitic-relaxation-oscillation(PRO)problem limits the minimum value of TC 6.This is illustrated in the bottom lef t of Fig.27.1.1.The PRO f eatures large relaxation oscillation of the resonance amplitude of the sensor,leading to the f ailure of the resonance amplitude con

23、trol.The bottom right of Fig.27.1.1 theoretically explains the PRO mechanism.The BPLL-based drive channel can be modeled as a sampled-delay negative f eedback loop where the delay operation is of f ered by the sensor and the sampling operation is of f ered by the T&H.The TCMIN is the minimum value o

24、f the TC to avoid PRO.The TCMIN is proportional to the parameters AD,RD and CD,where the AD is the equivalent drive gain of the sensors resonance amplitude,and the RD and the CD determine the equivalent drive time constant of the sensors resonance amplitude.The parameter AD is very sensitive to the

25、temperature variation with a high-quality-f actor sensor,leading to a temperature coef ficient on the order of 10000ppm/C of the TCMIN with a 5000 quality-f actor sensor in this work.According to this model,the large temperature variation leads to large variation of the TCMIN.Given the TC with a con

26、stant minimum value,the PRO is inevitable.To overcome the PRO problem under large temperature variation,this work proposes an interf ace IC with dynamic optimized TC value,as shown in Fig.27.1.2.This is achieved by employing the duty-cycle-automatic-optimization(DAO)technique in the drive channel.Th

27、e circuit modules f or the DAO are composed of a dynamic-power-gate generator that generates power-gate signals(DPG and SPG)f or both the drive channel and the sense channels,the DAO register determining the duty cycle of the power-gate signals,and the PRO detector determining the calculation value

28、of the DAO register.When the always-on mode starts,the DAO register is reset.The PRO flag FPRO outputted by the PRO detector is 0 and the downward optimization process of the DPGs duty cycle is activated.During the downward optimization process,the DAO register continuously reduces period by period

29、with a long time step.As a result,the TC value and the average always-on current consumption continue to decrease.The downward optimization process ends when the TC value is smaller than the TCMIN value and the PRO is triggered.With PRO,the flag FPRO turns to 1 and the upward optimization process is

30、 activated.During the upward optimization process,the DAO register increases with short time steps.As a result,the TC value increases and the drive loop is temporarily f ully powered to settle out the PRO.Af ter the PRO is settled out,the flag FPRO returns to 0 and the downward optimization process

31、starts again.The times-interleaved operation of the upward optimization process and the downward optimization process keep the drive channel dynamically stable,which is robust to the environmental temperature variations.Figure 27.1.3 shows the key circuit implementations of the DAO module.As an alwa

32、ys-on analog circuit,the PRO detector should be implemented with extremely low power and acceptable accuracy.Three designs are utilized to meet these requirements.First,the PRO detector is implemented with a passive switched-capacitor double-sampling dif f erentiator,a dynamic-window comparator and

33、a threshold-voltage(VH and VL)generator,to reduce power consumption of this structure to about 50nA.To suppress the spurious detection due to the switch activities,the window comparator and the dif f erentiator are driven by the clocks(1,2,3 and 4)with edge delayed by TD compared to the DPG signal.S

34、econdly,the voltage VT&H f rom the T&Hs output is chosen as the detection object,in order to reduce the detection error due to the mismatch of the capacitors CD1 and CD2,the mismatch of the comparators input transistors and the output drif t of the threshold-voltage generator.This is because the VT&

35、H provides large voltage fluctuation during PRO due to the small AD value,thus relaxing the detection accuracy of the PRO detector.Thirdly,a hybrid ref erence generator is employed to provide detection threshold voltage|VH-VL|with acceptable low power consumption and small chip area 7.The detection

36、threshold voltage|VH-VL|has an optimized value between 100 and 200mV,as shown in the bottom right of Fig.27.1.3.Below 100mV,the mis-trigger rate of the PRO flag increases due to the spurious detection,leading to the increase of the power consumption.Above 200mV,the PRO cannot be detected timely and

37、immediately,leading to the runaway of the PRO(shown in bottom lef t of Fig.27.1.3)and the temporary f ault of the resonance amplitude control.As a result,the worst wake-up time is significantly deteriorated.This work is implemented in a 0.18m BCD process with 3.84mm2 active chip area.The measurement

38、 results of typical transient wavef orms during the always-on mode are shown in the top of Fig.27.1.4.At time T0=14s,the gyroscope suf f ers a random thermal shock which leads to a temperature step f rom 25C to 55C within 2s,and the amplitude of the drive voltage VT&H shows a significant drop of 200

39、mV due to the PRO.At the time T1=15s,as the PRO is detected,the upward optimization of the DAO is activated and the correction time TC is increased f rom 6.25ms to 100ms to settle out the PRO,leading to an increase of the average current consumption f rom 0.8A to 8A.At the time T2=17s,as the PRO has

40、 been settled out,the downward optimization of the DAO is activated and the power consumption reduces gradually.The transient wavef orms of the wake-up process are shown in the bottom of Fig.27.1.4.At time T3=30s,the gyroscope system is switched f rom the always-on mode to the normal operation mode.

41、The resonance amplitude of the sensor can be observed f rom the output voltages of the T&H and the C/V(VCV and VT&H),which show that the wake-up time is 2.8ms with a settling accuracy of 99%.The ef f ect of the temperature variation on the wake-up time is shown in the top of Fig.27.1.5.The variation

42、 of the wake-up time is 5%over 40 to 85C temperature range,which significantly improves the reliability of the always-on gyroscope system.The measurement noise perf ormance under normal operation mode is shown in the bottom of Fig.27.1.5.The bias-instability by the Allan variance curve is 9/hr.The a

43、verage noise floor is 0.006/s/Hz.A comparison with other state-of-the-art interf ace ICs is shown in Fig.27.1.6.Compared to previous works 1-5,6 achieved the best wake-up time(5.45ms)with lowest always-on current(737nA)f or a single axis system.Compared to 6,this work reduces the wake-up time by 1.9

44、 with 847nA always-on current f or the 3-axis system.Furthermore,thanks to the duty-cycle automatic optimization,the temperature-variation-induced stability problem of the always-on mode is solved,leading to 5%wake-up time stability f rom40 to 85C.Ac k nowl edgement:This work is supported by NSFC(62

45、021004,62474132).The corresponding author is Zhangming Zhu.Figure 27.1.1:The Burst-mode Phase-locked-loop(BPLL)-based always-on MEMS gyroscope syst em.Figure 27.1.2:The proposed BPLL-based always-on MEMS Gyroscope syst em wit h dut y-cycle aut omat ic opt imizat ion(DAO).Figure 27.1.3:The key circui

46、t implement at ion of t he DAO.Figure 27.1.4:The measurement t ransient responses showing t he always-on operat ion wit h DAO.Figure 27.1.5:The measurement result s of noise performance,power consumpt ion and wake-up t ime against t emperat ure variat ions from 34 samples.Figure 27.1.6:The compariso

47、n wit h t he st at e of t he art.I SSCC 2025/February 19,2025/8:00 AM471 DIGEST OF TECHNICAL PAPERS 27 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025 PAPER CONTI NUATI ONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 27.1.7:The micrographs of t he int erface I C.Ref

48、 er enc es:1 Y.Zhao et al.,“A Sub-0.1/h Bias-Instability Split-Mode MEMS Gyroscope with CMOS Readout Circuit,”IEEE JSSC,vol.53,no.9,pp.2636-2650,Sept.2018.https:/doi.org/10.1109/JSSC.2018.2844285 2 M.Marx et al.,“A 141-W High-Voltage MEMS Gyroscope Drive Interf ace Circuit Based on Flying Capacitors

49、,”IEEE JSSC,vol.54,no.2,pp.511-523,Feb.2019.https:/doi.org/10.1109/JSSC.2018.2875109 3 TDK Invensense,ICM45686 Datasheet,July 2024.https:/ 4 Analog Devices,ADXRS290 Datasheet,Jan.2021.https:/ 5 Bosch Sensortec,BMI323 Datasheet,Jan.2024.https:/www.bosch- 6 L.Zhong et al.,“A 737nA Always-On MEMS Gyros

50、cope with 5.45ms Start-up Time Using Burst Mode PLL Technique,”IEEE CICC,pp.1-2,Apr.2024.https:/doi.org/10.1109/CICC60959.2024.10529034 7 Y.Osaki et al.,“1.2-V Supply,100-nW,1.09-V Bandgap and 0.7-V Supply,52.5-nW,0.55-V Subbandgap Ref erence Circuits f or Nanowatt CMOS LSIs,”IEEE JSSC,vol.48,no.6,p

51、p.1530-1538,June 2013.https:/doi.org/10.1109/JSSC.2013.2252523472 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025/SESSI ON 27/SENSOR I NTERFACES/27.2979-8-3315-4101-9/25/$31.00 2025 IEEE27.2 A Volt age-Biased CMOS Hall Sensor wit h 1.0T(3)Offset and a 60nT/Hz Noise-Floor Floris J

52、.P.van Mourik1,Sining Pan2,Karen M.Dowling1,Kofi A.A.Makinwa1 1TU Delf t,Delf t,The Netherlands 2Tsinghua University,Beijing,China Hall sensors are the only CMOS devices capable of measuring DC magnetic fields and so they are used in a wide range of applications,such as in compasses and current sens

53、ors.In such applications,their Achilles heel is their of f set,which is typically in the order of several(tens of)T 1-3.Conventionally,Hall sensors are biased by current sources and output voltages that are proportional to an external magnetic field.In this work,a dual arrangement is proposed,in whi

54、ch a Hall sensor is biased by a voltage source and outputs a current.In a standard 0.18m CMOS process,a prototype Hall sensor with a low-of f set readout circuit achieves an of f set of 1.0T(3)with a noise floor of 60nT/Hz.Compared to the state-of-the-art 1,this represents a 3 reduction in of f set

55、and a 5 improvement in resolution.As shown in Fig.27.2.1(lef t),a typical CMOS Hall sensor consists of an n-well plate,which is biased by a current source and outputs a Hall-ef f ect induced voltage Vh,which is proportional to the out-of-plane magnetic field.Asymmetry,e.g.due to n-well inhomogeneity

56、 or contact misalignment will give rise to a static of f set VOS,with typical values in the order of tens of mT.Fortunately,this can be suppressed by the spinning-current technique 7,which involves periodically changing the direction of the biasing current and averaging the resulting output voltages

57、.For a linear Hall plate,the 2-phase scheme shown in Fig.27.2.1(right)would result in zero of f set.Due to the non-linear anisotropy of silicon,however,an 8-phase scheme is necessary to minimize the residual of f set 1.The ef f ectiveness of spinning is limited by the JFET ef f ect 4,which is caused

58、 by the asymmetric depletion region f ormed between the biased n-well and the grounded p-type substrate.The voltage-dependent thickness of this region modulates the n-well resistance(Fig.27.2.1,lef t)and causes residual of f set and non-linearity 8.In this work,the JFET ef f ect is significantly red

59、uced by biasing the n-well with a voltage and reading out the Hall-induced short-circuit current Ih,thus stabilizing the voltage across the n-well during all spinning phases,Fig.27.2.1(middle).Simulations based on a detailed Hall sensor model f rom 4,indicate that the use of voltage biasing and curr

60、ent readout should result in a 40 reduction in residual of f set compared to the use of current biasing and voltage readout.In practice,however,this can only be achieved if the output impedance of the voltage source(Rdrive)and the input impedance of the current readout(Rsense)are well matched and mu

61、ch lower than the resistance of the Hall sensor(RH).As in 1,the Hall sensor used in this work consists of f our orthogonally coupled,8-phase spinning-current Hall plates,and has a nominal impedance of 300.Simulations show that to achieve a residual of f set of 1T,Rdrive and Rsense should then be les

62、s than 0.7,while the equivalent voltage of f set of the entire current readout should be well below 60nV.The block diagram of the proposed readout circuit is shown in Fig.27.2.2.Low Rdrive is achieved by generating the upper(VU)and lower(VL)biasing voltages of the Hall sensor with two unity-gain buf

63、 f ers based on high-gain amplifiers,while low Rsense is achieved by connecting the sensors output terminals to the virtual ground of a high-gain preamp.To f acilitate spinning,three switch matrixes(SM1-3)are used to connect each Hall-plate terminal either to the output of a biasing amplifier or to

64、the preamp inputs.Kelvin connections maintain the low impedances of the biasing and readout circuits.With this arrangement,only the switches in series with the preamp input are sized f or noise,while the other switches are much smaller.The output of the preamp is digitized by a 2nd-order continuous-

65、time delta-sigma ADC,similar to the one described in 9.To achieve 1st-order compensation f or temperature and bias voltage variations,its resistive DAC,like the Hall sensor,is implemented with n-well resistors.Furthermore,they are ref erenced to the sensors biasing voltages,which cancels the sensiti

66、vity of the system gain to these voltages,allowing them to be flexibly adjusted to optimize the sensors perf ormance.As in 1,3,the pre-amps of f set and 1/f noise are mitigated by chopping(at Fchop),and the residual of f set is then mitigated by system-level chopping(at Fsys_chop).In this work,the i

67、nput of the preamp is chopped by appropriately configuring the existing switch matrix SM3,rather than by inserting additional(noisy)chopper switches.To minimize the residual of f set,using system-level chopping,the resistances around the high-f requency chopping switches(in SM3)should be constant du

68、ring both Fsys_chop phases 5.In this work,this is accomplished by using the bias-switch matrixes(SM1-2)to swap the Hall sensors bias voltages,which ef f ectively chops its output while maintaining a constant source resistance.This approach allows system-level chopping and spinning to be implemented

69、with the same set of switches.To block the spikes that occur while the Hall sensor is transitioning between the various spinning/chopping phases,a deadband signal(DB)and some extra switches are used to briefly disconnect the ADC f rom the preamp.The chip can be programmed to f ollow any 8-phase spin

70、ning sequence via an on-chip shif t-register,allowing e.g.4-phase spinning to be compared with 8-phase spinning.The circuit implementations of the preamp and the upper biasing amplifier are shown in Fig.27.2.3.The preamp is a transimpedance amplifier,whose f eedback resistors RFB(44k)converts the Ha

71、ll sensors output current Ih into a dif f erential output voltage.It is based on a two-stage opamp that consists of a double-cascoded telescopic amplifier f ollowed by a Class-A output stage.This ensures that its supply current,which also generates a magnetic field,is independent of the external mag

72、netic field.Its high DC gain(140dB)ensures that the preamps input impedance is less than 8m,while its input-ref erred noise,2.3nV/Hz,is about the same as that of the Hall sensor.To keep the deadband short,the preamp is designed to settle to within-130dB(25m)in 1s in response to a 65mT input step.The

73、 biasing amplifiers are 2-stage amplifiers,with f olded-cascode input stages that drive 8 multiplexed output stages(SM1-2),which are connected to each Hall sensor terminal.Their noise requirements are relaxed,since their output noise appears as a common-mode signal to the preamp.Since VU VL,the lowe

74、r biasing amplifier employs a PMOS input pair.The output impedance of the biasing amplifiers is less than 3m,and settles to 5m within 1s.To ensure that the contact resistances associated with each Hall sensor terminal remain constant during the biasing and readout phases,the virtual grounds of the b

75、iasing amplifiers and the preamps are connected to the same point in the layout.The Hall sensor and its readout circuit were f abricated in a standard 0.18m CMOS process.As shown in Fig.27.2.7,the Hall sensor occupies 0.18mm2,while the readout circuit occupies 0.67mm2 and draws 5.2mA f rom a 1.8V su

76、pply(Vb=VU-VL=1.2V).The biasing voltages VU and VL are generated of f-chip by external DACs.Since standard lead-f rames and PCB traces contain f erromagnetic material that may become magnetized,samples of the sensor were glued and bonded to Ag surf ace-finished PCBs.Figure 27.2.4(top)shows an FFT of

77、 the Hall sensors output spectrum during one of the system-chop phases,with the ADC sampling at 400kHz.With both spinning and preamp chopping turned of f,its spectrum is dominated by the preamps 1/f noise.This is well suppressed by chopping(Fchop=25kHz),revealing the sensors own 1/f noise,which has

78、a corner f requency of about 20Hz.This can be removed by 8-phase spinning at Fspin=400Hz,where Fspin is defined as the number of bias direction changes per second.The sensors static of f set mainly manif ests itself as peaks at odd harmonics of Fspin/4,the f requency at which 90 direction changes oc

79、cur,and at odd harmonics of Fspin/8,the f requency of a complete spinning cycle.The sensor has a thermal noise floor of 60nT/Hz,indicating that the noise contribution of the readout is only 33%higher than that of the Hall sensor(35nT/Hz).With system-level chopping enabled and of f-chip decimation,th

80、e sensors output is shown in Fig.27.2.4(bottom lef t)with an applied external magnetic field between 0 and 25mT.A maximum non-linearity of 37T(0.15%)is observed.Figure 27.2.4(bottom right)shows the dependence of the system gain on the bias voltage(Vb)around a 900mV common-mode.The decrease with Vb(4

81、%)is due to the voltage sensitivity of the n-well resistance.Residual of f set measurements were perf ormed on 16 samples f rom one batch in a zero-gauss chamber.Figure 27.2.5(top right)shows the measured residual of f set with 8-phase and 4-phase spinning,respectively.With 8-phase spinning,the sens

82、or achieves a mean of 150nT with a standard deviation of 340nT.The use of 4-phase spinning increases the latter by 73%.In Fig.27.2.5(bottom right)the standard deviation of the residual of f set(normalized to 340nT)is shown as a f unction of Vb.Except at low values of Vb,when the sensors output appro

83、aches the readout circuitry of f set(3.5 and 2.1dB improvements in noise and energy ef ficiency,respectively.Compared to their DT counterparts,sensor interf aces based on CTDSMs can achieve lower noise without power-hungry driving stages and have an inherent anti-aliasing filter.However,a convention

84、al CTDSM based on an active RC integrator cannot scale its power and sampling f requency fs over a large range due to its fixed RC constant.As a result,it has a variable output swing as fs changes(Fig.27.3.1 bottom,lef t).Compared to the RC integrator,the Gm-C integrator can achieve low noise in a m

85、ore energy-ef ficient way due to its open-loop structure.Moreover,if the transconductance Gm can track the scalable fs,then the transf er f unction(Gm/CiS)also scales,thus keeping a stable output swing despite changes in fs.This enables a wide-range BW/power scalability even with a limited supply he

86、adroom.To achieve this,an FCCS is required to scale the Gm linearly with fs(Fig.27.3.1 bottom,right).To realize the FCCS,the capacitively-biased-diode(CBD)technique 12 is used in this work.As shown in Fig.27.3.2(lef t),the capacitor Cs is pre-charged to an initial voltage and then discharged through

87、 the diode.Af ter a short settling time,the residual voltage VD on Cs will exhibit a logarithmic f unction of the discharging time t independent of the initial voltage 12.Moreover,the bias current through diode ID will be proportional to VTCS/t 13 (VT=kT/q).If the diode is realized by a diode-connec

88、ted MOSFET MD,then a current-mirror transistor MC can be readily added to replicate ID to bias the amplif ying transistor MA.Operating in the subthreshold region,the transconductance Gm of MA then satisfies:GmCS/t.Theref ore,a linear FCCS can be realized by using fs to define the discharge duration(

89、1/fs).Figure 27.3.2(right-top)shows the simulated Gm and ID at dif f erent fs.Within the fs range of 300,both Gm and ID are linear with fs.To demonstrate the robustness,the simulated Gm and ID vs.temperature and supply are shown in Fig.27.3.2(right-bottom).Similar to the conventional static constant

90、-gm bias current,the output of the FCCS also shows a PTAT property,achieving a relatively constant Gm over temperature(Gm4%f rom-40C to 125C).Furthermore,the Gm exhibits minimal variation with supply changes(Gm5%f rom 0.6V to 1.1V).Figure 27.3.3(top)shows the architecture of the proposed BW/power-sc

91、alable CT interf ace targeting f or low-noise and small-input(82dB over fs f rom 10kHz to 2.25MHz(225)with a 76mV sinusoidal input(Fig.27.3.4 bottom,lef t).Within this fs range,it also exhibits a 5.8nW/Hz linear power scalability(Fig.27.3.4 bottom,right)and a stable FoM of 174dB(Fig.27.3.5 top,lef t

92、).Noticing that more than 70%of the power is dissipated by the digital logic in the 0.13m CMOS,it can be significantly reduced in an advanced process.To demonstrate the robustness of the proposed interf ace,it was measured with a 0.7V-to-1.1V DC supply.The SNDR variation is within 1.3dB over supply(

93、Fig.27.3.5 top,right).Figure 27.3.5(bottom,lef t)shows the gain error of 10 samples at room temperature,which is within-0.08%to 0.06%(untrim)thanks to the good matching of capacitors(Cin and Cdac).The gain variation over temperature(-40C to 125C)is less than 0.04%(Fig.27.3.5 bottom,right).10-sample

94、measurement shows that it has a maximum of f set of 207V.The proposed sensor interf aces perf ormance is summarized in Fig.27.3.6 and compared to the state-of-the-art high-resolution(SNDR 80dB)sensor interf aces with a similar bandwidth.This is the only BW/power-scalable CT sensor interf ace(225)in

95、the table.Compared to the scalable DT interf aces 5-7,it achieves the lowest input-ref erred noise density(3.5 improvement)and the state-of-the-art energy ef ficiency.This work also achieves sub-1V operation down to 0.7V,making it suitable f or various sensing applications.Ac k nowl edgement:This wo

96、rk was supported by the National Key Research and Development Program of China under Grant 2023YFB4405001.The corresponding author is Zhong Tang().Figure 27.3.1:Report ed sensor int erfaces based on:discret e-t ime ADC(t op,left);I A+ADC(t op,right);act ive RC-CTDSM(bot t om,left);t he proposed sens

97、or int erface:direct conversion based on a GmC-CTDSM wit h a FCCS(bot t om,right).Figure 27.3.2:Capacit ively-biased-diode(CBD)operat ion principle and it s circuit implement at ion(left);t he simulat ed Gm and ID at different fs,t emperat ures and supplies(right).Figure 27.3.3:The archit ect ure of

98、 t he proposed sensor int erface(t op);t he current-reuse pseudo-different ial amplifier(bot t om,left);t he FCCS operat ing in a ping-pong mode(bot t om,middle);t he syst em t iming diagram(bot t om,right).Figure 27.3.4:Measured spect rum at fs=1MHz wit h/wit hout DEM(t op,left);SN(D)R vs.input amp

99、lit ude(t op,right);SN(D)R/Noise densit y(bot t om,left),power consumpt ion(bot t om,right)vs.fs at a 0.9V supply.Figure 27.3.5:FoM at different fs(t op,left);SN(D)R vs.supply at fs=1MHz(t op,right);Measured gain error of different chips at room t emperat ure(unt rim)(bot t om,left);gain variat ion

100、over t emperat ure(1-point t rim)(bot t om,right).Figure 27.3.6:Performance summary and comparison wit h t he st at e of t he art.I SSCC 2025/February 19,2025/8:50 AM475 DIGEST OF TECHNICAL PAPERS 27 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025 PAPER CONTI NUATI ONS AND REFERE

101、NCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 27.3.7:Die micrograph.Ref er enc es:1 H.Jiang et al.,“An Energy-Ef ficient 3.7nV/Hz Bridge Readout IC With a Stable Bridge Of f set Compensation Scheme,”I EEE J SSC,vol.54,no.3,pp.856-864,Mar.2019.https:/doi.org/10.1109/JSSC.2018.2885556 2 Z.Tang et al

102、.,“A 40A Shunt-Based Current Sensor with 0.2%Gain Error f rom 40C to 125C and Self-Calibration,”I SSCC,pp.348-350,Feb.2023.https:/doi.org/10.1109/ISSCC42615.2023.10067304 3 H.Jiang et al.,“A 4.5nV/Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Ef ficient Chopping Scheme

103、,”I EEE SSCL,vol.1,no.1,pp.18-21,Jan.2018.https:/doi.org/10.1109/LSSC.2018.2803447 4 J.Jun et al.,“A 22-bit Read-out IC with 7-ppm INL and Sub-100-Hz 1/f corner For DC Measurement Systems,”I EEE JSSC,vol.54,no.11,pp.3086-3096,Nov.2019.https:/doi.org/10.1109/JSSC.2019.2934817 5 Z.Tang et al.,“A 14b 9

104、8Hz-to-5.9kHz 1.7-to-50.8 W BW/Power Scalable Sensor Interf ace with a Dynamic Bandgap Ref erence and an Untrimmed Gain Error of 0.26%f rom 40C to 125C,”I SSCC,pp.60-62,Feb.2024.https:/doi.org/10.1109/ISSCC49657.2024.10454378 6 M.Zhao et al.,“A 4-W Bandwidth/Power Scalable Delta-Sigma Modulator Base

105、d on Swing-Enhanced Floating Inverter Amplifiers,”I EEE J SSC,vol.57,no.3,pp.709-718,Mar.2022.https:/doi.org/10.1109/JSSC.2021.3123261 7 Y.Zhao et al.,“Fully Dynamic Zoom-ADC Based on Improved Swing-Enhanced FIAs Using CLS Technique with 1250 Bandwidth/Power Scalability,”I EEE TCASI I,vol.70,no.6,pp

106、.1901-1905,June 2023.https:/doi.org/10.1109/TCSII.2023.3235752 8 X.Tang et al.,“A 0.4-to-40 MS/s 75.7 dB-SNDR Fully Dynamic Event-driven Pipelined ADC with 3-stage Cascoded Floating Inverter Amplifier,”I SSCC,pp.376-378,Feb.2021.https:/doi.org/10.1109/ISSCC42613.2021.9365753 9 P.Harpe et al.,“A 7-to

107、-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16f J/conversion-step,”I SSCC,pp.472-474,Feb.2012.https:/doi.org/10.1109/ISSCC.2012.6177096 10 R.Theertham et al.,“Design Techniques f or High-Resolution Continuous-Time Delta-Sigma Converters with Low In-Band Noise Spectral Density,”I EEE J SCC,vol.55,no

108、.9,pp.2429-2442,Sept.2020.https:/doi.org/10.1109/JSSC.2020.2979454 11 M.Jang et al.,“A 134w 24kHz-BW 103.5dB-DR CT Modulator with Chopped Negative-R and Tri-level FIR DAC,”I SSCC,pp.1-3,Feb.2020.https:/doi.org/10.1109/ISSCC19947.2020.9062904 12 M.Eberlein et al.,“A 40nW,Sub-1V Truly Digital Reverse

109、Bandgap Ref erence Using Bulk-Diodes in 16nm FinFET,”A-SSCC,pp.99-102,Nov.2018.https:/doi.org/10.1109/ASSCC.2018.8579306 13 Z.Tang et al.,“A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor with an Inaccuracy of 0.15 C(3)From-55 C to 125 C,”I EEE J SSC,vol.58,no.12,pp.3433-3441,Dec.2023.http

110、s:/doi.org/10.1109/JSSC.2023.3308554 14 S.Pan et al.,“A 10 f JK2 Wheatstone Bridge Temperature Sensor with a Tail-Resistor-Linearized OTA,”I EEE JSSC,vol.56,no.2,pp.501-510,Feb.2021.https:/doi.org/10.1109/JSSC.2020.3018164 15 B.Nauta,“Racing Down the Slopes of Moores Law,”I SSCC,pp.16-23,Feb.2024.ht

111、tps:/doi.org/10.1109/ISSCC49657.2024.10454417476 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025/SESSI ON 27/SENSOR I NTERFACES/27.4979-8-3315-4101-9/25/$31.00 2025 IEEE27.4 A BJT-Based Temperat ure Sensor wit h an 80fJK2 Resolut ion FoM Nandor G.Toth,Kofi A.A.Makinwa TU Delf t,D

112、elf t,The Netherlands BJT-based temperature sensors are widely used because they can achieve a high accuracy af ter applying a low-cost 1-point trim.In terms of energy ef ficiency,however,they are still outperf ormed by resistor-based sensors 1.Recently,significant improvements in energy ef ficiency

113、 have been achieved by using charge-balancing continuous-time-modulators(CTM)to digitize the ratio of PTAT and CTAT currents generated by BJT-based f ront-ends 2,3.In this work,an NPN-based temperature sensor is presented that uses a noise-optimized charge-balancing scheme and a current-assisted amp

114、lifier to achieve both high energy ef ficiency(80f JK2 FoM)and low inaccuracy(0.1C(3)f rom-70C to 125C),while occupying only 0.05mm2.Compared to the state-of-the-art 2-5,the proposed sensor is 2.5 more energy ef ficient,achieves similar accuracy,and occupies 1.5 less area.Figure 27.4.1(top lef t)ill

115、ustrates the operation of a sensor with a previous charge-balancing readout scheme 2.A low-power BJT-based f ront-end generates a PTAT current(IPTAT VBE)and a CTAT voltage(VBE),which is converted into a current(ICTAT)by a resistor at the 1st integrators virtual ground.This current is then balanced b

116、y the bitstream-modulated output of an IPTAT DAC.As shown in Fig.27.4.1(top right),the resulting BS-average()is proportional to ICTAT/IPTAT,and is a well-defined f unction of temperature.Since VBE is an order of magnitude smaller than VBE,however,the SNR of IPTAT is much lower than that of ICTAT.It

117、becomes even lower af ter it is attenuated by the DAC,thus limiting the sensors resolution.Moreover,since the DAC attenuation increases with temperature,the sensors resolution also gets worse with temperature(Fig.27.4.1,bottom right).Intuitively,higher resolution can be achieved by increasing ICTAT

118、and balancing IPTAT with an ICTAT DAC(Fig.27.4.1,bottom lef t),such that is now proportional to IPTAT/ICTAT.Simulations show that this approach maintains the SNR of IPTAT,which improves the sensors resolution by up to 2 and makes it quite temperature-independent(Fig.27.4.1,bottom right).As shown in

119、Fig.27.4.2(top),an ICTAT DAC can be readily implemented by adding a switch in series with R2.In this design,however,R2(1.7M)has a large parasitic capacitance Cpar(300f F).The charging and discharging of Cpar during DAC transitions will then cause charge-balancing errors that degrade the sensors accu

120、racy.Furthermore,the finite rise-time of the transitions at the integrators virtual ground will cause inter-symbol interf erence(ISI),which will significantly degrade the sensors resolution.The errors associated with Cpar can be mitigated by splitting R2 into N segments and using additional series s

121、witches(Fig.27.4.2,bottom).As in 6,7,this ensures that the charge stored on their parasitic capacitances(Cpar/N)is preserved when the DAC switches open and redistributed when they close,reducing both the settling transients and the error charge that the 1st integrator needs to provide.Increasing N d

122、ecreases these errors,but also increases errors due to the charge injection and the on-resistance(RON)of the extra switches.In this work,N=4,which ensures that the quantization-noise floor due to residual ISI is around 20dB lower than the thermal noise floor.Figure 27.4.3 shows a detailed block diag

123、ram of the proposed sensor.As in 2,IPTAT is generated by using two NPNs(Q1,2)biased at a 1:7 current-density ratio and f orcing the resulting VBE across a resistor(R1).To minimize errors due to the Early ef f ect,an opamp(A1)ensures that their collector voltages are the same,while another f eedback

124、loop ensures that they are set to the VGS of an HVt NMOS(M1).Dynamically matched current mirrors then copy the resulting collector current(IC)and the average base current(IB,av)of the NPNs to the 1st-integrators virtual ground,thus compensating f or the-dependent error associated with Q1 2.In this w

125、ork,the currents are copied with a 2:1 ratio,which halves the power consumption of the CTM without a significant noise penalty.Also,R2=13R1,which ensures that the ICTAT DAC can balance IPTAT over the targeted-70C to 125C range.To save area,R1 and R2 are minimum-width poly resistors.The accuracy of t

126、he charge-balancing scheme is limited by the spread in the R2/R1 ratio.As in 2,this is calibrated by reconfiguring the modulator so that the 1st integrators virtual ground is set to VBE instead of VBE,and then balancing IPTAT1=VBE/R1 with IPTAT2=VBE/R2.Since IPTAT1 IPTAT2,charge balancing is accompl

127、ished by using an additional switch to attenuate IPTAT1 2.The exact value of R2/R1 can then be determined f rom the resulting bitstream average RCAL and used to trim the sensors output.As explained earlier,the finite rise-time of the transitions at the 1st-integrators virtual ground is a potential s

128、ource of residual ISI.To mitigate this,the bandwidth of the 1st integrator should be maximized.In this work,it is based on an opamp with a high-gain f olded-cascode input stage(A2)and a source-f ollower(SF)output stage.Unlike the common-source output stage used in 2,this avoids the need f or Miller

129、compensation and the associated loss of bandwidth.Furthermore,noting that the amplifiers output current is a deterministic f unction of the BS state,the current-assist technique can be used to improve its speed and reduce its power dissipation 8.As shown in Fig.27.4.3(top),when BS=0,the 1st integrat

130、or si nk s the IPTAT supplied by the current mirrors,but when BS=1,it sources ICTAT-IPTAT due to the extra current drawn by R2.When BS=0,the SF can thus be assisted by connecting its output to an IPTAT current source.This can be turned of f when BS=1,thus reducing the drain current of the SF(ISF)by

131、IPTAT,or a 2 reduction at room temperature(Fig.27.4.3,top).To avoid causing extra switching transients,a keep-alive current(IKA)is added to ensure that the SF never turns of f completely.Its temperature dependence is roughly CTAT,which limits the change in ISF(ISF)during DAC transitions and thus red

132、uces the modulators clock f requency sensitivity.As shown in Fig.27.4.3,the sensor employs a 2nd-order CTM,which operates at sampling f requencies ranging f rom 50kHz to 400kHz.The GBW of A2(700kHz over PVT)is large enough to ensure that the equivalent settling errors due to DAC-and chopping transit

133、ions are below 20mK.Furthermore,its open-loop gain(78dB over PVT)is high enough to ensure that the equivalent errors in the VBE f orced across R2 are below 30mK,and that the noise contribution of the switched-capacitor(SC)2nd integrator is negligible.Compared to the 1st integrator,it consumes 4 less

134、 power and occupies 8 less area.To f acilitate 1-point trimming,dynamic-error-correction techniques are used to ensure that VBE spread is the sensors dominant source of error.A2 is chopped at fs/256 to mitigate its 1/f noise and mismatch,while the 5 IC-and IB-current sources and the 8 NPNs are dynam

135、ically matched at fs/(532)and fs/(832),respectively.To minimize leakage errors,the NPNs DEM switches and the DAC switches are realized with I/O devices,which are driven by clock-boosted signals to reduce their RON.At room temperature,simulations show that the sensors resolution is dominated by the n

136、oise power of IPTAT(due to R1,the NPNs,and the current mirrors),which is 3 larger than the noise power of ICTAT(due to R2 and A2).Two sensors were f abricated on the same die in a 0.18m CMOS process,thus enabling dif f erential resolution measurements to suppress ambient temperature drif t 9.A singl

137、e sensor occupies 0.05mm2(Fig.27.4.7)and draws 1.8A f rom a 1.4V supply,of which 56%is dissipated in the f ront-end,38%in the modulator,and 6%in the digital logic.The sinc2 decimation filter was implemented of f-chip f or flexibility.The temperature spread of 40 sensors on 20 dies in ceramic package

138、s was characterized f rom-70C to 125C.As suggested in 4,the mapping f rom into temperature was done with a 5th-order polynomial,which can be implemented within a sub-1W power budget.The sensor has an untrimmed inaccuracy of 0.9C(3)(Fig.27.4.4,top lef t),which improves to 0.5C(3)af ter a 1-point PTAT

139、 trim(Fig.27.4.4,top right).Applying resistor calibration to compensate f or the spread of R2/R1 results in an inaccuracy of 0.1C(3)(Fig.27.4.4,bottom lef t).As shown in Fig.27.4.4(bottom right),assisting the 1st integrator improves the sensors clock f requency sensitivity f rom 0.4mK/kHz to 0.07mK/

140、kHz.This is 10 less than that reported in 2 and demonstrates the ef f ectiveness of the various techniques used to mitigate the impact of switching transients.Figure 27.4.5(top)shows an FFT of the sensors bitstream with dif f erent DAC switch configurations(fs=50kHz).Only driving the top switch resu

141、lts in significant quantization noise f olding,which is eliminated by driving all the switches and thus segmenting the DAC.The various tones at multiples of fs/256(NPN DEM,chopping)and fs/160(current-mirror DEM)are removed by the notches of the 2560bit sinc2 decimation filter.As shown in(Fig.27.4.5,

142、bottom),the sensors resolution is quite constant over temperature(fs=50kHz).At room temperature,it achieves 0.79mK resolution in a conversion time of 51ms,resulting in a resolution FoM of 80f JK2.Increasing fs to 400kHz reduces the conversion time to 6.4ms while achieving similar accuracy and only i

143、ncreasing the FoM to 160f JK2.The perf ormance of this sensor is benchmarked against state-of-the-art CMOS temperature sensors in Fig.27.4.6.Compared to other BJT-based sensors,it achieves the highest energy ef ficiency(FoM=80f JK2),as well as state-of-the-art accuracy(0.1C(3)f rom-70C to 125C)and t

144、he lowest area(0.05mm2).These results demonstrate that BJT-based sensors can achieve energy ef ficiencies in the same range as those of resistor-based sensors,while still maintaining their superior accuracy.Figure 27.4.1:Block diagram of BJT-based t emperat ure sensors wit h PTAT or CTAT DACs(left),

145、t he result ing current s,BS-average(t op right),and resolut ion(bot t om right)vs.t emperat ure.Figure 27.4.2:Simplified circuit diagram of t he 1st int egrat or and t he corresponding DAC waveforms wit h and wit hout segment at ion.Figure 27.4.3:Block diagram of t he proposed sensor and t he curre

146、nt drawn by t he 1st int egrat ors SF out put st age(t op right).Figure 27.4.4:Measured t emperat ure error of 40 samples wit hout t rimming(t op left),wit h RT PTAT t rim(t op right),wit h RT PTAT t rim and resist or-rat io calibrat ion(bot t om left),and t heir clock frequency sensit ivit y(bot t

147、om right).Figure 27.4.5:Bit st ream FFTs wit h and wit hout DAC segment at ion(t op),resolut ion vs.conversion t ime at 3 different t emperat ures(bot t om).Figure 27.4.6:Performance summary and comparison wit h st at e-of-t he-art int egrat ed t emperat ure sensors.I SSCC 2025/February 19,2025/9:15

148、 AM477 DIGEST OF TECHNICAL PAPERS 27 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025 PAPER CONTI NUATI ONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 27.4.7:Die micrograph of t he sensor.Ref er enc es:1 K.A.A.Makinwa.Smart Temperature Sensor Survey.Accessed:Aug.202

149、4.Online.Available:http:/ei.ewi.tudelf t.nl/docs/TSensor_survey.xls.2 N.G.Toth,K.A.A.Makinwa,“A -Compensated NPN-Based Temperature Sensor with 0.1C(3)Inaccuracy f rom-55C to 125C and a 200f JK2 Resolution FoM,”I SSCC,pp.66-68,Feb.2024.https:/doi.org/10.1109/ISSCC49657.2024.10454408 3 S.H.Shalmany et

150、 al.,“A 620 W BJT-Based Temperature-to-Digital Converter with 0.65mK Resolution and FoM of 190f JK2,”I SSCC,pp.70-71,Feb.2020.https:/doi.org/10.1109/ISSCC19947.2020.9063007 4 Z.Tang et al.,“A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy of 0.15 C(3)From-55 C to 125 C”I

151、 EEE J SSC,vol.58,no.12,pp.3433-3441,Dec.2023.https:/doi.org/10.1109/JSSC.2023.3308554 5 B.Yousef zadeh et al.,“A BJT-Based Temperature-to-Digital Converter With 60mK(3)Inaccuracy From 55C to+125C 0.16-m CMOS”IEEE JSSC,vol.52,no.4,pp.1044-1052,April 2017.https:/doi.org/10.1109/JSSC.2016.2638464 6 C.

152、Livanelioglu et el.,“A compact and PVT-robust segmented duty-cycled resistor realizing TO impedances f or neural recording interf ace circuits,”IEEE Solid-State Circuits Lett.,vol.6,pp.25-28,2023.https:/doi.org/10.1109/LSSC.2023.3238206 7 Z.Tang et al.,“A versatile 25-a shunt-based current sensor wi

153、th 0.25%gain error f rom 40C to 85 C,”IEEE J.Solid-State Circuits,vol.57,no.12,pp.3716-3725,Dec.2022.https:/doi.org/10.1109/JSSC.2022.3204520 8 S.Pavan and P.Sankar,“Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique,”IEEE J.Solid-State Circuits,vol.45,no.7,

154、pp.1365-1379,Jul.2010.https:/doi.org/10.1109/JSSC.2010.2048082 9 S.Pan and K.A.A.Makinwa,“A 10f JK2 wheatstone bridge temperature sensor with a tail-resistor-linearized OTA,”IEEE J.Solid-State Circuits,vol.56,no.2,pp.501-510,Feb.2021.https:/doi.org/10.1109/JSSC.2020.3018164478 2025 IEEE Internationa

155、l Solid-State Circuits Conf erenceI SSCC 2025/SESSI ON 27/SENSOR I NTERFACES/27.5979-8-3315-4101-9/25/$31.00 2025 IEEE27.5 A 4,100m2 Wire-Met al-Based Temperat ure Sensor wit h a Fract ional-Discharge FLL and a Time-Domain Amplifier wit h 0.2C I naccuracy(3)from 40 t o 125C and 45fJK2 Resolut ion Fo

156、M in 28nm CMOS Dan Shi1,Ka-Meng Lei1,Rui P.Martins1,2,Pui-In Mak1 1University of Macau,Macau,China 2Instituto Superior Tecnico/University of Lisboa,Lisbon,Portugal Resistance-based temperature sensors f eature a compact area(5,000m2)1-3 with high accuracy and superior resolution FoM(100f JK2)4,5.In

157、contrast to the sensing element using active devices(e.g.,BJT and MOSFET)that require biasing,the resistor does not pose restrictions on the VDD.Such property f acilitates the deployment of resistor-based temperature sensors in the advanced processes with core VDD 0.1%/C:a metal resistor with a TC o

158、f 0.2%/C and a silicide-dif f usion resistor with a TC of 0.15%/C(Fig.27.5.1,top).While metal resistors exhibit a high TC,they are seldom selected f or temperature sensing in the mature process(e.g.,0.18m)due to its low sheet resistance(0.5/).Yet,the downscaling of the metal interconnects in the dee

159、p-submicron process,together with the availability of multi-metal layers,f acilitates its area reduction;the minimum area to realize a 25k resistor with 5 metal layers is 12%smaller than that built by the silicide-dif f usion resistor.Hence,we implement the temperature-sensing resistor(RM,25k)using

160、5 metal layers and 2 shielding layers on top and bottom.Notably,metal interconnects are elementary in all CMOS processes.As their dimensions continue to shrink,we can still utilize them f or temperature sensing with a more compact f ootprint in advanced processes(e.g.,FinFET 1-2).We adopt an FLL as

161、the readout f or probing RM(Fig.27.5.1,bottom).It comprises the temperature-sensing f ront-end,a TDA,a phase-f requency detector(PFD),a charge pump(CP),a notch filter,a VCRO,a phase generator to distribute the control signals to dif f erent blocks,and a f ractional-pulse extractor(FPE).The temperatu

162、re-sensing f ront-end incorporates a pair of RMC filters,with C(1.4pF)implemented as MOM capacitors with a negligible TC(50ppm/C).The FLL can detect the filters temperature-dependent time constant(=RMC,or 35ns at 25C)as it can lock its output(FOUT)to a ratio of in the steady state,wherein the output

163、s of the RMC filters(VRC+/-)equal 0.5VDD.Specifically,during the reset phase(RST),the FLL pre-charges C to VDD/VSS(Fig.27.5.2,top).Then,in the discharge phase(DIS),the RMC filters discharge C towards 0.5VDD in 0.7.Once DIS turns low,the FLL goes into the amplification phase(AMP),where the TDA transd

164、uces the input voltage(Vi+/-)into output pulses(VO+/-);the bidirectional delay between VO+/-(td)is proportionate to the dif f erence between Vi+/-.Then,the FLL converts this delay to current and integrates it at the capacitor CINT through the PFD and CP to yield VINT.The output of the notch filter(V

165、C)directs the VCRO and locks its period into a portion of .Although the metal resistors in the selected process can achieve a satisf actory resistance-to-area ratio,we propose the f ractional-discharge scheme to alleviate the resistance demand under the same FOUT to guarantee the compactness of the

166、sensors while preserving the FLLs power consumption(proportional to FOUT).Instead of discharging C in the entire FOUTs period(TOUT),we leverage the 5-phase output of the VCRO(1-5)to synthesize 10 pulses(D1-10)in one FOUT cycle,each with a width of 10%of TOUT,and utilize 1 of these pulses to discharg

167、e C and perf orm amplification and integration.Hence,TOUT=0.710(i.e.,FOUT=4MHz)in the steady state.Such a scheme can reduce the RMC value by 10,thereby minimizing the entire area by 2.6 under the same FOUT.Practically,mismatch exists among the delay cells inside the VCRO,resulting in unequal pulse w

168、idths among D1-10 and imposing inaccuracy on the temperature sensor if not appropriately treated.To mitigate this issue,we sequentially select D1-10 to discharge C in 10 individual comparison cycles(CMP);as the sum of D1-10s width is equal to TOUT,this disposition can ensure that the total duration

169、of 10 consecutive discharges is stable amid mismatch and process/voltage variations(Fig.27.5.2,bottom-right).For deep-submicron processes with VDD1V,designing a voltage-mode amplifier with suf ficient gain f or precise comparison is a complex task.Comparators f or digital FLL can operate down to 0.4

170、V 7.Yet,chopping on the comparator cannot eliminate the comparators 1/f-noise and dc-of f set due to non-linear quantization,thereby imposing noise and inaccuracy on the sensor output.To this end,we utilize a TDA to translate the dif f erential input voltage(Vi)to td(Fig.27.5.3,lef t).When AMP is lo

171、w,M5/6 charge VL+/-to VDD and both Vo+/-are at VSS.Once AMP turns to VDD,the conversion starts by discharging VL+/-to VSS through M1/2 with current IM1/2.As the dif f erence between IM1 and IM2 correlates with Vi,the discrepancy in discharge rates on VL+/-is also proportional to Vi.Once VL+/-drops b

172、elow the inverters threshold,Vo+/-is charged to VDD,where the delay between Vo+/-(i.e.,td)is commensurate with Vi.We set td/Vi to 3s/V to achieve 2 lower than 3,5,7,8)among the temperature sensors implemented in the sub-100nm processes.Also,this sensor achieves a compact area(4,100m2),benefitting f

173、rom the proposed f ractional-discharge scheme with the wire metal resistors.Compared to 6 which utilizes the same process node,the proposed sensor achieves 12 reduction in power,2.2 reduction in area,and 4.3 improvement in relative accuracy,rendering the proposed sensor an ef f ective temperature se

174、nsing solution f or modern SoC.Ac k nowl edgement:The work is f unded by The Macau Science and Technology Development Fund 004/2023/SKL and 0149/2022/A3,and 0005/2024/RIC and the University of Macau(MYRG-GRG2024-00125-IME).Corresponding author:Ka-Meng Lei.Figure 27.5.1:(Top)Available resist ors for

175、t emperat ure sensing in t he select ed process and t he adopt ed st acked-met al resist or.(Bot t om)Proposed wire-met al-based t emperat ure sensor.Figure 27.5.2:(Top)Timing diagram of t he proposed t emperat ure sensor feat uring a fract ional-discharge scheme.(Bot t om)Schemat ic and t iming dia

176、gram t o generat eDISenabled byD1-10.Figure 27.5.3:Schemat ic of t he t ime-domain amplifier,bias reference,current-st arved VCRO,and t he fract ional pulse ext ract or.Figure 27.5.4:Measured FOUT(t op-left)and it s non-linearit y aft er 1st-order fit (bot t om-left)from 30 samples,and t he t empera

177、t ure error aft er 1-point and 2-point t rimmings wit h 3rd-polynomial fit (right).Figure 27.5.5:Measured supply sensit ivit y and power consumpt ion of t he t emperat ure sensors across 0.7 t o 0.9V(left)and t he t emperat ure resolut ion wit h and wit hout chopping on t he TDA(right).Figure 27.5.6

178、:Performance summary and comparison wit h t he st at e-of-t he-art sub-100nm CMOS t emperat ure sensors.I SSCC 2025/February 19,2025/9:30 AM479 DIGEST OF TECHNICAL PAPERS 27 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025 PAPER CONTI NUATI ONS AND REFERENCES979-8-3315-4101-9/25/$

179、31.00 2025 IEEEFigure 27.5.7:Die micrograph of t he t emperat ure sensor(t op)and it s power and area breakdown(bot t om).Ref er enc es:1 B.-S.Lien et al.,A 0.65V 900m2 BEoL RC-Based Temperature Sensor with 1C Inaccuracy f rom 25C to 125C,I SSCC,pp.68-70,Feb.2024.https:/doi.org/10.1109/ISSCC49657.20

180、24.10454423 2 J.Park et al.,A 0.65V 1316m2 Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving 0.16nJ%2-Accuracy FoM in 5nm FinFET CMOS,I SSCC,pp.220-222,Feb.2022.https:/doi.org/10.1109/ISSCC42614.2022.9731766 3 J.A.Angevare et al.,A Highly Digital 2210m2 Resistor-Based Tempera

181、ture Sensor with a 1-Point Trimmed Inaccuracy of 1.3C(3)f rom 55C to 125C in 65nm CMOS,I SSCC,pp.76-78,Feb.2021.https:/doi.org/10.1109/ISSCC42613.2021.9365995 4 S.Pan et al.,A 10 f JK2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA,I EEE JSSC,vol.56,no.2,pp.501-510,Feb.2021

182、.https:/doi.org/10.1109/JSSC.2020.3018164 5 A.Khashaba et al.,A 0.0088mm2 Resistor-Based Temperature Sensor Achieving 92f JK2 FoM in 65nm CMOS,I SSCC,pp.60-62,Feb.2020.https:/doi.org/10.1109/ISSCC19947.2020.9062956 6 J.Kim et al.,A 0.9V Self-Ref erenced Resistor-Based Temperature Sensor With 0.62/+0

183、.81C(3)Inaccuracy,I EEE TCAS-I I,vol.70,no.12,pp.4319-4323,Dec.2023.https:/doi.org/10.1109/TCSII.2023.3291621 7 D.Shi et al.,A 0.4-V 0.0294-mm2 Resistor-Based Temperature Sensor Achieving 0.24 C p2p Inaccuracy From 40 C to 125 C and 385 f JK2 Resolution FoM in 65-nm CMOS,I EEE J SSC,vol.58,no.9,pp.2543-2553,Sep.2023.https:/doi.org/10.1109/JSSC.2023.3269077 8 Y.Lee et al.,A 0.9-V 6,400-m2 Resistor-Based Temperature Sensor With a One-Point Trimmed 3 Inaccuracy of 0.64 C f rom 50C to 125 C,I EEE TCAS-I I,vol.70,no.9,pp.3313-3317,Sep.2023.https:/doi.org/10.1109/TCSII.2023.3268166