F3 - Digitally Enhanced Analog Circuits_Trends & State-of-the-art Designs.pdf

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1、ISSCC 2024Forum 3Digitally Enhanced Analog Circuits:Trends&State-of-the-art Designs 2024 IEEE International Solid-State Circuits ConferenceForum 3:Digitally Enhanced Analog Circuits:Trends&State-of-the-art DesignsInternational Solid State Circuit ConferenceFebruary 22nd,2024Start of presentations at

2、 8:15amISSCC 2024 Forum 3 Introduction1 of 6 2024 IEEE International Solid-State Circuits ConferenceOrganizer:Ben Calhoun,University of California,Charlottesville,VA Co-Organizers:Visvesh Sathe,Georgia Institute of Technology,Atlanta,GA Jiawei Xu,Fudan University,Shanghai,China Jeff Walling,Virginia

3、 Tech,Blacksburg,VA Masum Hossain,Carleton University,Ottawa,Canada Yan Lu,University of Macau,Macao,China Champions:Makoto Nagata,Kobe University,Kobe,Japan Man-Kay Law,University of Macau,Macau,ChinaOrganizing Committee2 of 6ISSCC 2024 Forum 3 Introduction 2024 IEEE International Solid-State Circu

4、its ConferenceGeneral Information 3 of 6ISSCC 2024 Forum 3 Introduction8 talksEach 40-45 minute talk will be followed by a Q&A period2 coffee breaks and one lunch breakElectronic copies for Forums are available for downloadPlease switch your mobile devices to muteRemember to fill out the speaker eva

5、luation using the ISSCC appNo panel session at the end of the Forum 2024 IEEE International Solid-State Circuits ConferenceForum Topic4 of 6ISSCC 2024 Forum 3 IntroductionTraditional all-analog circuits consume large area,power,and design time in advanced technology nodes and are highly susceptible

6、to process,voltage,and temperature(PVT)parameter variations.Digital circuits with analog functionality or digitally assisted analog circuits help to mitigate these challenges.Digital circuits require less area and power,offer fast time-to-market,provide greater tolerance to PVT variations,and enable

7、 critical storage,programmability,and runtime computational capabilities that enhance traditional analog circuits through techniques like calibration and signal processing.This forum presents the recent treads and state-of-the-art designs for digitally enhanced analog circuits while highlighting the

8、 specific circuit components more favorable to digital or analog implementations to improve target metrics in analog,mixed-signal,RF,and power management systems.2024 IEEE International Solid-State Circuits ConferenceForum Topic5 of 6ISSCC 2024 Forum 3 IntroductionDigitally Enhanced Analog Circuits:

9、Trends&State-of-the-art Designs 2024 IEEE International Solid-State Circuits ConferenceForum Topic5 of 6ISSCC 2024 Forum 3 IntroductionDigitally Enhanced Analog Circuits:Trends&State-of-the-art Designs 2024 IEEE International Solid-State Circuits ConferenceAgenda6 of 6StartTitleSpeakerAffiliation8:1

10、5IntroductionBen CalhounU.Virginia8:25Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeSSCS9:15Digitally Enhanced Clock Generation and DistributionPing-Hsuan HsiehNatl Tsing Hua University10:05Break10:20From Microwatts to Terawatts:Managing GPU Power T

11、awfik Rahal-ArabiAMD11:10Digital and Mixed-Signal ADC Enhancement Techniques Pieter HarpeEindhoven U.Technology12:10Lunch13:20Sensitivity and Robustness Enhancement of Ultra-Low Power Digitally Assisted Wakeup Receivers Steven BowersU.Virginia14:10Digitally Enhanced Transceiver for High-Speed Signal

12、lingCharlie BoeckerMicrosoft15:00Break 15:15Applications of Time-Domain Circuits in SoCs Stephen KosonockyAMD16:05Analog Enhanced Digital and Memory Circuits Jaydeep KulkarniU.Texas Austin16:55Closing remarksISSCC 2024 Forum 3 Introduction 2024 IEEE International Solid-State Circuits ConferenceExten

13、ding and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Lokealvin.lokeieee.orgIEEE Solid-State Circuits SocietySan Diego,California,USAISSCC 2024-Forum 3.11 of 45 2024 IEEE International Solid-State Circuits ConferenceSpoiler AlertThe solution to analog design in scal

14、ed CMOS?“Take the analog out.”Dick Hester,2003ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling Limitations2 of 45Alvin LokeBut the physical world remains analogAnd analog still does some things better than digital.2024 IEEE International Solid-State Ci

15、rcuits ConferenceMore Compute with More,Smaller,Cheaper Switches3 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeStrain+HKMGDennardFinFET+DTCOGAA+DTCOWikipedia 1197019801990200020102020203010M100M1B10B100B1T1k10k100k1MCMOS M

16、icroprocessorTransistor Count 2024 IEEE International Solid-State Circuits Conferencefocus of this ForumAnalog Scaling A Story of Resilience&InnovationISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling Limitations4 of 45Piovaccari 2log(Functional Density

17、)Technology NodeMoores Law(ideal)DigitalMemoryAnalogDigital-Centric AnalogAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceOutline Eras of CMOS Scaling Unfriendliness of Scaling on Analog Design Adapting Analog to Scaling Looking Ahead Conclusions5 of 45ISSCC 2024-Forum 3.1:Extendin

18、g and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceOutline Eras of CMOS Scaling Dennard Scaling Equivalent Scaling(Strain,HKMG)Fully Depleted Devices(FinFET,FDSOI)Lithography&Design/Technology Co-Optimizati

19、on Unfriendliness of Scaling on Analog Design Adapting Analog to Scaling Looking Ahead Conclusions6 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceShort-Channel Effects

20、(SCEs)LgateVTVDSVTDIBLgateLgateCGPdrainsourcebody(well)contact Area scaling smaller Contacted Gate Pitch(CGP)smaller Lgate Scaling Lgateweakens gate control of body depletion&channel formation More S/D junction control of body depletion VTrolloff VDSincreases drain-side depletion drain-induced barri

21、er lowering(DIBL)7 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceDennard Blueprint to Mitigate Short-Channel Effect8 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting

22、 Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeDennard et al.,IBM 3/Frank et al.,IBM 4thicknessoftheburiedoxide.Forthickburiedoxide,thereisnobacksidescreeningofthedrainpotential,resultinginrelativelypoor scaling characteristics compared to other device types1013.Since such

23、devices are not likely to be used at thelimits ofscaling theyare notdiscussed here.Wedo,however,discussthescaling advantages ofthemorenoveldoublegatedtypeofFD-SOI MOSFETs,wherein both theinsulator onthebacksideoftheSichannellayerandtheSilayeritselfareverythin so that both sides of the channel are ga

24、ted.There are alsoin-betweenFD-SOIMOSFETswithburiedoxidethinenoughto offer some screening,but not thin enough for use in activeswitching.Thesedevicesareinterestingfromacircuitpointofviewsincethebackgatecanbeusedtodynamically adjustthethresholdvoltage,butarenotdiscussedhereforlackofspace.The outline

25、of the paper is as follows.Section II ad-dresses some of the more fundamental limitations to thecontinued scaling of MOSFETs that appear to be on thehorizon.Based only on these fundamental limits,it maybe possible to scale FETs down to very small dimensions,e.g.,10-nm channel length or smaller.Secti

26、on III describesresearch results related to this fundamental limit regime:very tiny one-of-a-kind FETs.In the more practical world ofmanufacturing,however,there are many types of variationsand fluctuations that require the design of MOSFETs withtolerances.In Section IV,we look at some of these pract

27、icallimitations and their consequences for device design.Sec-tion V describes how the concepts of the previous sectionsplay out when they are applied to meeting the needs ofspecific classes of applications.The paper ends in Section VIby summarizing all of the limits into a large table,followedby the

28、 conclusion in Section VII.II.FUNDAMENTALSCALINGLIMITSA.Scaling TheoryFor many years now,the shrinking of MOSFETs has beengoverned by the ideas of scaling 14,15.The basic idea isillustrated in Fig.1:a large FET is scaled down by a factorto produce a smaller FET with similar behavior.When allof the v

29、oltages and dimensions are reduced by the scalingfactorand the doping and charge densities are increasedby the same factor,the electric field configuration inside theFET remains the same as it was in the original device.Thisis called constant field scaling,which results in circuit speedincreasing in

30、 proportion to the factorand circuit densityincreasing as.These scaling relations are shown in thesecond column of Table 1 along with the scaling behavior ofsome of the other important physical parameters.Fig.2 illustrates the actual past and projected futurescaling behavior of several of these para

31、meters versus thechannel length 16.As can be seen,the voltages have notbeen scaled at the same rate as the length,in violation of thesimple scaling rules outlined above.In earlier generations ofMOSFETs,this occurred because carrier velocities were in-creasing with increasing field,yielding higher pe

32、rformance,while deleterious high-field effects were kept in check bythe gradually descending voltage.More recently,carriervelocities have become saturated,but voltage scaling hasFig.1.Schematic illustration of the scaling of Si technology by afactor alpha.Adapted from 5.Table 1Technology Scaling Rul

33、es for Three Casesis the dimensional scaling parameter,is the electric field scalingparameter,andandare separate dimensional scaling parameters forthe selective scaling case.is applied to the device vertical dimensionsand gate length,whileapplies to the device width and the wiring.been slow because

34、of the nonscaling of the subthresholdslope and theOFFcurrent.To accommodate this trend,more generalized scaling rules have been created,in whichthe electric field is allowed to increase by a factor17.Furthermore,the device widths and wiring dimensions havenot been scaled as fast as the channel lengt

35、hs,leading toa further scaling parameter for those dimensions.Thesegeneralized rules are also shown in Table 1 and are describedin more detail in 5,9,and 18.The preceding scaling rules do not tell a designer howshort he can make a MOSFET for given doping profiles andlayer thicknesses;they only descr

36、ibe how to shrink a knowngood design.Furthermore,since the built-in potentials arenot usually scaled,the rules are inaccurate anyway.To findthe minimum gate length at each generation of technology,one must analyze the two-dimensional(2-D)field effectsinside the FET.This is often done numerically usi

37、ng com-plex 2-D simulation tools,but the recent analytic analysisby Frank et al.19 reveals the primary dependencies.Other260PROCEEDINGS OF THE IEEE,VOL.89,NO.3,MARCH 2001thicknessoftheburiedoxide.Forthickburiedoxide,thereisnobacksidescreeningofthedrainpotential,resultinginrelativelypoor scaling char

38、acteristics compared to other device types1013.Since such devices are not likely to be used at thelimits ofscaling theyare notdiscussed here.Wedo,however,discussthescalingadvantagesofthemorenoveldoublegatedtype ofFD-SOI MOSFETs,wherein both theinsulator on thebacksideoftheSichannellayerandtheSilayer

39、itselfareverythin so that both sides of the channel are gated.There are alsoin-betweenFD-SOIMOSFETswithburiedoxidethinenoughto offer some screening,but not thin enough for use in activeswitching.Thesedevicesareinterestingfromacircuitpointofviewsincethebackgatecanbeusedtodynamically adjustthethreshol

40、dvoltage,butarenotdiscussedhereforlackofspace.The outline of the paper is as follows.Section II ad-dresses some of the more fundamental limitations to thecontinued scaling of MOSFETs that appear to be on thehorizon.Based only on these fundamental limits,it maybe possible to scale FETs down to very s

41、mall dimensions,e.g.,10-nm channel length or smaller.Section III describesresearch results related to this fundamental limit regime:very tiny one-of-a-kind FETs.In the more practical world ofmanufacturing,however,there are many types of variationsand fluctuations that require the design of MOSFETs w

42、ithtolerances.In Section IV,we look at some of these practicallimitations and their consequences for device design.Sec-tion V describes how the concepts of the previous sectionsplay out when they are applied to meeting the needs ofspecificclasses of applications.The paper ends in Section VIby summar

43、izing all of the limits into a large table,followedby the conclusion in Section VII.II.FUNDAMENTALSCALINGLIMITSA.Scaling TheoryFor many years now,the shrinking of MOSFETs has beengoverned by the ideas of scaling 14,15.The basic idea isillustrated in Fig.1:a large FET is scaled down by a factorto pro

44、duce a smaller FET with similar behavior.When allof the voltages and dimensions are reduced by the scalingfactorand the doping and charge densities are increasedby the same factor,the electric field configuration inside theFET remains the same as it was in the original device.Thisis called constant

45、field scaling,which results in circuit speedincreasing in proportion to the factorand circuit densityincreasing as.These scaling relations are shown in thesecond column of Table 1 along with the scaling behavior ofsome of the other important physical parameters.Fig.2 illustrates the actual past and

46、projected futurescaling behavior of several of these parameters versus thechannel length 16.As can be seen,the voltages have notbeen scaled at the same rate as the length,in violation of thesimple scaling rules outlined above.In earlier generations ofMOSFETs,this occurred because carrier velocities

47、were in-creasing with increasing field,yielding higher performance,while deleterious high-field effects were kept in check bythe gradually descending voltage.More recently,carriervelocities have become saturated,but voltage scaling hasFig.1.Schematic illustration of the scaling of Si technology by a

48、factor alpha.Adapted from 5.Table 1Technology Scaling Rules for Three Casesis the dimensional scaling parameter,is the electric field scalingparameter,andandare separate dimensional scaling parameters forthe selective scaling case.is applied to the device vertical dimensionsand gate length,whileappl

49、ies to the device width and the wiring.been slow because of the nonscaling of the subthresholdslope and theOFFcurrent.To accommodate this trend,more generalized scaling rules have been created,in whichthe electric field is allowed to increase by a factor17.Furthermore,the device widths and wiring di

50、mensions havenot been scaled as fast as the channel lengths,leading toa further scaling parameter for those dimensions.Thesegeneralized rules are also shown in Table 1 and are describedin more detail in 5,9,and 18.The preceding scaling rules do not tell a designer howshort he can make a MOSFET for g

51、iven doping profiles andlayer thicknesses;they only describe how to shrink a knowngood design.Furthermore,since the built-in potentials arenot usually scaled,the rules are inaccurate anyway.To findthe minimum gate length at each generation of technology,one must analyze the two-dimensional(2-D)field

52、 effectsinside the FET.This is often done numerically using com-plex 2-D simulation tools,but the recent analytic analysisby Frank et al.19 reveals the primary dependencies.Other260PROCEEDINGS OF THE IEEE,VOL.89,NO.3,MARCH 2001Original DeviceScaled Device(Factor of a a)Lg V xD NA tox 2024 IEEE Inter

53、national Solid-State Circuits ConferenceAfter 30 Years of Dennard Scaling Recipe for 10+nodes:10m to 0.13m 100 x reduction in Lgate&tox Optimized body doping profile&Source/Drain to recover short-channel control Lateral halo implants under gate edge Retrograded well with surface VTimplant Gate space

54、r to form self-aligned shallow S/D extension&deeper extrinsic S/D Obstacles to further Lgatescaling More body doping worse channel mobility Thinner tox severe Igate,poly gate depletion&channel quantum confinementpolygateS/DextensiongatespacerS/Dhaloretrograded wellSTI9 of 45ISSCC 2024-Forum 3.1:Exte

55、nding and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeIgatepoly depletionquantumconfinement 2024 IEEE International Solid-State Circuits ConferenceEquivalent Scaling(Mechanical Strain+HKMG)10 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digita

56、l to Overcome Technology Scaling LimitationsAlvin Loketension forfaster NMOScompression forfaster PMOSMechanical Stressors Strain channel lattice to improve channel mobility Surround channel with GPa stress Effective for short Lgateonly More effective for PMOSHigh-K Dielectric&Metal Gate Extend Coxs

57、caling with less Igate(HfO2HK)&gate depletion(MG)VTset by Mmetals&HK dipoles Gate-last/replacement-gate integration,silicide-last,trench contactsChan et al.,IBM 5,Auth et al.,Intel 6,Packan et al.,Intel 7 PMOSNMOSHKMNMPP metal fillN metal filltrenchcontact 2024 IEEE International Solid-State Circuit

58、s ConferenceShift to Fully Depleted Devices More body dopants in shorter Lgatedevices no longer work Subthreshold gate control weakened by strong scoupling to body&drain Reducing VT&VDDwould compromise Ion&Ioff11 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Tech

59、nology Scaling LimitationsAlvin LokedrainbodygateVBSVGSVDSsourceCoxCDCBs Surface dopants not fundamental for establishing dipoles/E-fields that induce surface inversion Push dopants away from surface to create fully depleted surface(like parallel-plate capacitor)CB,CD SS,DIBL,body effect,VT,VDD Othe

60、r benefits:,no RDF(not dopant-based)fully depleted undopedsurface+Yan et al.,Bell Labs 8VTsatVTlinVDDIDsatIDlinIoffSSVGSDIBL log(ID)2024 IEEE International Solid-State Circuits ConferenceFully Depleted Options12 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Techn

61、ology Scaling LimitationsAlvin LokeNMOSPMOSAuth et al.,Intel 10fully depleted fin bodyn+drainSTIn+sourcep-well tiep-wellp-substratep+drainp+sourcen-well tien-wellp-substrateTri-Gate FinFETMagarshack et al.,STMicroelectronics 9fully depletedSOI body islandp-substratep-wellp-well tien+drainn+sourcebur

62、iedoxideisolationp-substraten-wellp+drainn-well tiep+sourceFully DepletedSilicon-On-Insulator(FDSOI)2024 IEEE International Solid-State Circuits ConferenceLithography Scaling Helping but Not Good Enough 13 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology

63、Scaling LimitationsAlvin LokeLoke et al.,Qualcomm 11;Arnold et al.,ASML 12;Choi et al.,UC Berkeley 13;Yeap et al.,Qualcomm 142008 2010 2012 2014 2016 2018 2020Minimum Pitch(nm)193i single exposure limitmetalgatefin7nm1016/142028404060802000.7xper 2 years20100 Physical scaling slower than 0.7x per no

64、de Node name tied to area scaling,no longer to LgateFive193imasksOneEUV mask 13.5nm EUV finally arrives for 7nm+Complex&costly stop gaps for sub-76nm pitch without EUV Pitch splittingcut mask pattern Cut masksSADPSAQP Self-aligned double/quadrature patterning(spacer-based)2024 IEEE International Sol

65、id-State Circuits ConferenceLogic-Driven Design/Technology Co-OptimizationExamples of technology innovations to shrink standard cell logic&maximize connectivity14 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeAuth et al.,In

66、tel 10;Loke et al.,TSMC 15;Auth et al.,Intel 16;Lu,TSMC 17,Greene et al.,IBM 18 self-alignedgate contactgate cut lastreduced overhangsingle diffusionbreakdense MEOL&lower BEOLfin depopulation for energy efficiencyFrequencyPower4-fin3-fin2-finself-aligneddiffusion contactgate cap 2024 IEEE Internatio

67、nal Solid-State Circuits ConferenceThe 40%Rule For the next node,silicon will cost 40%more per unit area To economically justify the next node(same functionality),a chip must satisfy15 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAl

68、vin Loke=,=,1.4Disclaimer:Based on personal observation,so take 40%with a grain of salt.where D=Digital,M=Memory,A=Analog,RF=RF&IO=I/O 2024 IEEE International Solid-State Circuits ConferenceOutline Eras of CMOS Scaling Unfriendliness of Scaling on Analog Design Impact on Transistors Impact on Passiv

69、es Process Variation Adapting Analog to Scaling Looking Ahead Conclusions16 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceThe FET is an Increasingly Nonideal gm Scalin

70、g goal:make small,fast,energy-efficient switches Lgate-min,VDD But heart of traditional analog is an ideal voltage-controlled current source(gm)17 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeNMOSstackedgateDSGBDSGB routde

71、grading with each new nodeChannel halos,even in long channelsMultiple process reasons reducing Lgate-max(e.g.,gate litho loading,contact ILD CMP,HKMG CMP)Standard mitigation compromises area&speedLonger channel,device stackingWider channel to recover some headroomArea overhead for guard rings&transi

72、tions between regions with different Lgate VDDdecreasingFewer circuit options to get high rout inaccuracyWeak/moderate inversion nonlinearity,distortionLoke et al.,Qualcomm 11;Cao et al.,UC Berkeley 19IDVD 2024 IEEE International Solid-State Circuits Conference40nm28nm16nm7nm5nmMx Resistance(vs.40nm

73、)07560451530Mx Capacitance(vs.40nm)0.82.01.61.41.01.21.8Resistance The defining agony of finFET era design Rinterconnects(mainly MEOL&lower BEOL)Rcontact&Rvia severe IR droop Rgate non-quasistatic effects Rwell well-ties,latchupCapacitance Strong gate coupling to S/D contacts&overlying metalMany ite

74、rations to reconcile gap between pre-&post-layout simulations!Loke,TSMC 15;Hou,TSMC 20Price of Logic Density Parasitics18 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits Conferenc

75、eStress-Related LDEs&VTmodulated by surrounding stressMmetalmetal fillDensity Gradient Effect PMOS finsNMOSfinsM1gateM2gateMetal Boundary EffectLength of ODGate PitchODWidthOxideSpaceBasic LDEsfinsgategatecutimpacted deviceFinFETLDEEven more design iterations!Price of Logic Density Layout-Dependent

76、Effects19 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeHKMG-Related LDEs VTmodulated by gate metal diffusion&heightLoke et al.,Qualcomm 11;Faricelli,AMD 21;Yang et al.,Qualcomm 2223;Hamaguchi et al.,IBM 24 2024 IEEE Intern

77、ational Solid-State Circuits ConferencePrice of Logic Density Highly Constrained Layout20 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke Many critical process steps with increasingly narrow process window Area&perimeter pat

78、tern densities sensitive to short-&long-range variations Increasingly strict restrictions on allowed min/max densities,even gradients 1000s of DRC rules many layout iterations inevitable Constraints to limit variation&ensure validity of process corner modelsAuth et al.,Intel 6;Loke et al.,Qualcomm 1

79、1Short-range,e.g.,deposition loading Spacer width variation(e.g.,SADP/SAQP)gate&metal CD variationPre-optimizedGate DensityRTA Temperature SimulationLong-range,e.g.,RTA heat absorption Active area&gate density variations non-uniform heating device variation 2024 IEEE International Solid-State Circui

80、ts ConferenceEvolution of CMOS Transistor Performance Stagnant Lgatescaling More parasitic Cgs&Cgd Degraded gmfrom Rsource Increasing impact of Rgate Decreasing voltage headroom21 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin L

81、oke4000100200300Transistor T(GHz)500Transistor Density(per mm2)100k1M10M100M1M130nm90nm65nm45nm7nm10nm16nm22nm FDSOIPlanarFinFETHeydari,UC Irvine 25 gm2CggT600 2024 IEEE International Solid-State Circuits ConferenceThick-Oxide I/O Device Getting Annihilated22 of 45ISSCC 2024-Forum 3.1:Extending and

82、Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeWei et al.,Globalfoundries 26;Shroff and Loke,NXP 27 tox VDD General-Purpose I/O voltage of peripheral ICs not scaling Aggressive fin pitch tough gate-last HKMG fill with thick gate dielectric,even worse in nanosheets

83、finFETnanosheet1.8V 0.3VRegulatorLevel Shifter1.8V 1.5VRegulatorinoutLevel Shifter1.8V0.3V1.5V Stacked drivers required to provide higher voltage than I/O device VDD large,power-hungry Punting GPIOs off-die inevitable chipset/chiplet solutions 2024 IEEE International Solid-State Circuits ConferenceR

84、esistors HKMG thin film precision resistor,poly resistor obsolete Gate resistor available but have much higher variationPassives Limited to No Node-to-Node Scaling23 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeInductors U

85、nchanged in upper BEOL Some Q impact from fill DRCsp-substratep-welln-wellemitterbasecollectorn+p+p+RwellDiodes&BJTs ESD,bandgap references&thermal sensors High series resistance Stricter well tie density,guard ring&latch-up rulesCapacitors Lower BEOL scaling some increase in capacitance density Pla

86、nar MIM capacitor in upper BEOL for supply noise reductionThe same device will cost 40%more in the next node.2024 IEEE International Solid-State Circuits ConferenceProcess Variation Through the Decades24 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Sc

87、aling LimitationsAlvin Loke Process control increasingly challenging in pushing manufacturability limits Correlated(e.g.,active&gate patterning)vs.uncorrelated(e.g.,implants,M)More total variation&increasing NMOS-PMOS uncorrelation(less shared steps)Increasingly dominant random local mismatch(histor

88、ical&new contributors)Exploding design effort over PVT passing just TT is easyTTFFGSSGFSGSFGFFFSSSSFNormalized NMOSPerformanceNormalized PMOSPerformanceTTFFGSSGFSGSFGFFFSSSSF3s global(chip-mean)variation3s total single-device variation 2024 IEEE International Solid-State Circuits ConferenceModel Rea

89、lities to Add Insult to Injury Bleeding-edge design models are speculative&target-based to enable technology/design co-development faster product time-to-marketDesign is inherently iterative using multiple models of increasing maturity&decreasing uncertainty Model accuracy prioritizes digital&memory

90、 analog-centric designs vulnerable to off-target silicon&slowest to react25 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeBair,AMD 28InitialDesignTimeUpdatedDesignFinalDesignTest ChipModel UncertaintySpeculativeModelsSilico

91、n-InfluencedModelsSilicon-BasedModels 2024 IEEE International Solid-State Circuits ConferenceOutline Eras of CMOS Scaling Unfriendliness of Scaling on Analog Design Adapting Analog to Scaling Essence of Digitally-Assisted/Enhanced Analog Examples of Techniques Looking Ahead Conclusions26 of 45ISSCC

92、2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceMixed-Signal Explorations as Old as CMOS Itself Scaling goal:make small,fast,energy-efficient switches(not transconductors)Use judic

93、iously clocked switches to cleverly overcome analog IC limitations(e.g.,process variation,poor matching,speed,large resistors impractical)A few historical examples27 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeDynamic Ele

94、ment Matching1976Van de Plassche,Philips 29;Galton,UCSD 30Switched Capacitor Circuit1977Hosticka et al.,UC Berkeley 31 2024 IEEE International Solid-State Circuits Conference28 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke

95、Murmann,Stanford 32Essence of Digitally-Assisted/Enhanced AnalogWithout digital assistDigitalprocessingSignalconditioningSignalconditioningADC(TDC)DAC(DTC)Analogmedia&transducers 2024 IEEE International Solid-State Circuits ConferenceEssence of Digitally-Assisted/Enhanced Analog29 of 45ISSCC 2024-Fo

96、rum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeMurmann,Stanford 32DigitalpostprocessingDigital preprocessingDigitalprocessingEstimation of nonidealitiesEstimation of nonidealitiesWith digital assistMinimalisticsignalconditioningMinimalisticsi

97、gnalconditioningMinimalisticADC(TDC)MinimalisticDAC(DTC)Analogmedia&transducers 2024 IEEE International Solid-State Circuits ConferenceCalibration to Trim Global Variation Example:wireline termination impedance Calibrate out resistor variation using R-DAC vs.accurate off-chip RREF30 of 45ISSCC 2024-

98、Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeCommonCalibrationTX Lane 20TX Lane 14mmTX Lane 2TX Lane 3RX Lane 20RX Lane 1RX Lane 2RX Lane 3Z0Lane TXTerminationLane RXTerminationOff-ChipRREFIREFIREFLow-OffsetComparatorVAVBCommon Calibratio

99、n BlockFeng et al.,Globalfoundries 33 2024 IEEE International Solid-State Circuits ConferenceCalibration to Trim Random Local Mismatch Example:high-speed SerDes RX front-end amp High bandwidth min Lgate high input-referred offset Remove offset with auxiliary input&calibration achieve high bandwidth&

100、low offset Many other application-specific techniques to remove offsets,e.g.,chopping,auto-zeroing31 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeLoke et al.,AMD 34DACDACmainauxiliarylow-offsetcomparatorCalibration State M

101、achineout+out-in+in-2024 IEEE International Solid-State Circuits ConferenceDigital Linearization of Amplifier Nonlinearities32 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeMurmann,Stanford 32Saleh&Salz,Nokia Bell Labs 35Pi

102、pelined ADCRF Power Amplifier with Digital Predistortion 2024 IEEE International Solid-State Circuits ConferenceTime Interleaving for Unprecedented Performance 33 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeKhairi et al.,

103、Intel 36224Gb/s PAM-4 ADC-Based SerDes Receiver2-stage T/H tree to feed 64 SAR-ADCs operating at only 1.75GS/s 2024 IEEE International Solid-State Circuits ConferenceOutline Eras of CMOS Scaling Impact of Scaling on Analog Design Unfriendliness of Digital Assistance&Enhancement Looking Ahead Device

104、Options on the Horizon Design Implications System/Technology Co-Optimization Conclusions34 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceDevice Options on the Horizon3

105、5 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeFinFETStacked NanosheetsAuth et al.,Intel 10Loubet et al.,IBM 37CFET of Stacked NanosheetsHuang et al.,Intel 38CFET of Stacked2D MaterialsAsselberghs et al.,imec 39 Further Lg

106、ate&CGP scaling weakens finFET gate control Gate-All-Around(GAA)Increase Weffper unit area stack nanosheets Stack NMOS/PMOS on top of each other Complementary FET(CFET)Mobility degrades when nanosheet is too thin 2D materials 2024 IEEE International Solid-State Circuits ConferenceCMOS Technology Tre

107、nds36 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeTransistors Continued&relentless focus on logic scaling Scaling of Lgate&active area getting stagnant Increase routing density to pack more logic,i.e.,maximize active area

108、 utilization Aggressive MEOL&lower BEOL pitch Backside power(also big help for IR droop)Place&route efficiency will AI save Moores Law?Consequences Poor SRAM scaling on-&off-die/3D alternatives Even worse analog scalingShamana et al.,Intel 40 2024 IEEE International Solid-State Circuits ConferenceSo

109、me Design Implications Uniform®ular pattern density offers best process control&model validity Adapt to highly constrained layout innovate/differentiate at higher abstraction37 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin L

110、okeSemiwiki,TSMC 41 Analog cells/templates Design productivity win FET+MEOL+lowerBEOL inside a box Fixed cell height for easy abutment DRC-&density-clean by construction Facilitates auto place-and-route Simplifies silicon validation Nanosheets(2nm to 1.?nm)Even more restrictive DRCs Expect severe re

111、duction in Lgate-max Availability of I/O FETs?Multi-VT?BJT?CFETs(beyond 1nm)Way more restrictive DRCs Circuit topologies with balanced NMOS&PMOS usage for smallest areaRadosavljevi et al.,Intel 42 2024 IEEE International Solid-State Circuits ConferenceSystem/Technology Co-Optimization Overall board-

112、&package-level system must be optimized for cost&performance Dont force the analog onto a die where it doesnt belong Example Partitioning of ADC/DAC in cellular modem-transceiver chipsetMigrating ADC/DAC to transceiver die(older node)offers lower chipset cost,simpler ADC/DAC design&smaller overall P

113、CB form factor38 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeLee et al.,Samsung 43 2024 IEEE International Solid-State Circuits ConferenceExamples of Heterogeneous Integration39 of 45ISSCC 2024-Forum 3.1:Extending and Aug

114、menting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke16nmMCUNVM55nmEEPROM5V Analog I/OsLoke et al.,NXP 46Naffziger et al.,AMD 44Gomes et al.,Intel 457nmCPU14nmI/O die7nmCPU7nmCPU7nmCPU7nmCPU7nmCPU7nmCPU7nmCPUHigh-Performance ComputeAutomotiveMicrocontroller47 tiles5 proces

115、s nodesFigures not drawn to scale 2024 IEEE International Solid-State Circuits ConferenceConclusions Resistance is futile embrace the technology Logic-driven CMOS scaling will only make traditional analog more expensive in each new node Replace/augment the analog with digital wherever possible Analo

116、g design innovation must shift to higher level of abstraction with design efficiency and productivity being increasingly integral Think outside the die the system is your toolbox40 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin

117、Loke 2024 IEEE International Solid-State Circuits ConferenceAcknowledgments41 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin LokeSincere thanks to the following friends for valuable assistance and discussions Nihaar Mahatme Coli

118、n McAndrew Alessandro Piovaccari Visvesh Sathe Rocco Tam Carlos Tokunaga Keith Bowman Jeff Cunningham Thanh Viet Dinh Paul Grudowski Hasnain Lakdawala Mike Leary 2024 IEEE International Solid-State Circuits ConferenceReferences(1/4)1 https:/en.wikipedia.org/wiki/Transistor_count2 A.Piovaccari,“The S

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126、with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceReferences(2/4)13 Y.-K.Choi,T.-J.King,and C.Hu,“A spacer patterning technology for nanoscale CMOS,”IEEE Trans.Electron Devices,vol.49,no.3,pp.436441,Mar.2002,doi:10.1109/16.987114

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137、 A.L.S.Loke,“Design-technology co-optimization for reliability and quality in advanced nodes,”in SPIE Advanced Lithography Conf.in Design-Technology Co-optimization XV,Virtual,Feb.2021,doi:10.1117/12.2585220.28 L.Bair,“Process/product interactions in a concurrent design environment,”in IEEE Custom I

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142、 power amplifiers in digital radio systems,”The Bell System Tech.Journal,vol.62,no.4,pp.10191033,Apr.1983,doi:10.1002/j.1538-7305.1983.tb03113.x.44 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Soli

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149、omes et al.,“Ponte Vecchio:A multi-tile 3D stacked processor for exascale computing,”in IEEE Int.Solid-State Circuits Conf.,San Francisco,CA,USA,Feb.2022,pp.4244,doi:10.1109/ISSCC42614.2022.9731673.46 A.Loke et al.,“Driving automotive ICs into advanced CMOS nodes,”in Int.Conf.on IC Design and Techno

150、logy,Virtual,Sep.2021,Keynote.45 of 45ISSCC 2024-Forum 3.1:Extending and Augmenting Analog with Digital to Overcome Technology Scaling LimitationsAlvin Loke 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024-Forum 3.1:Extending and Augmenting Analogwith Digital to Overcome Technology

151、Scaling Limitations46 of 45Please Scan to Rate Please Scan to Rate This PaperThis Paper 2024 IEEE International Solid-State Circuits ConferenceDigitally-Enhanced Clock Generation and DistributionPing-Hsuan HsiehAssociate ProfessorDepartment of Electrical EngineeringNational Tsing Hua University,Hsin

152、chu,Taiwan1 of 71Ping-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution 2024 IEEE International Solid-State Circuits ConferenceIntroductionLoop characteristics calibrationNoise and error cancellationAccurate phase/delay controlConclusionOutline:Digitally-Enhanced C

153、K Gen&DistributionPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution2 of 71where analog precision meet digital innovation 2024 IEEE International Solid-State Circuits ConferenceClocking/Synchronization in Electronic Systems3 of 71Ping-Hsuan HsiehISSCC 2024-Foru

154、m 3.2:Digitally-Enhanced Clock Generation and DistributionClock generation and distribution,frequency synthesis,and clock recoveryEntail modules of PLLs/DLLs,oscillators,phase interpolators,and buffers*ISSCC 2022 paper2.2*ISSCC Digital Architectures&Systems Trends 2022*ISSCC 2022 paper4.4 2024 IEEE

155、International Solid-State Circuits ConferenceAnalog Phase-Locked LoopPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution4 of 71 2024 IEEE International Solid-State Circuits Conferencedigital circuits and switches in building blocksAPLL:Mixed-Signal Implementatio

156、n in NaturePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution5 of 71 2024 IEEE International Solid-State Circuits ConferenceFractional-N PLLPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution6 of 71 2024 IEEE International

157、Solid-State Circuits Conference1.Overcome PVT variations2.Reduce KVCO Improve noise performanceDiscrete(Digital)Frequency TuningPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution7 of 71*E.Hegazi,et al.,JSSC,Dec.2001.*M.Ferriss,et al.,JSSC,April 2013.PVT variati

158、ons 2024 IEEE International Solid-State Circuits ConferenceTransfer Function and Loop CharacteristicsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution8 of 71=2+1=121+2+2+2 2024 IEEE International Solid-State Circuits ConferenceTransfer Function and Loop Charac

159、teristicsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution9 of 71=2+1=121+2+2+2 2024 IEEE International Solid-State Circuits Conference20.126.7GHz w/32nm CMOS SOIIntegral path:CP:10 10A current slicesCapacitor bank:5-bit,total 217pFProportional path:CP:15 50A

160、current slices4-bit resistor bankTo set loop parameters precisely Digital calibration enabled with DAC Minimum programmable range to cover PVT,BW,and fREFPVT Compensation with Programmable DAC Ping-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution10 of 71*M.Ferriss

161、,et al.,JSSC,April 2013.2024 IEEE International Solid-State Circuits ConferenceKVCOplot:combination of digital/analog tuningWith a specific digital setting:Analog tuning still subject to PVT+nonlinearity calibration requiredGain Variation due to PVT or NonlinearityPing-Hsuan HsiehISSCC 2024-Forum 3.

162、2:Digitally-Enhanced Clock Generation and Distribution11 of 71*M.Ferriss,et al.,JSSC,April 2013.2024 IEEE International Solid-State Circuits ConferenceDual-Path ArchitecturePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution12 of 71*M.Ferriss,et al.,JSSC,April 2

163、013.Proportional gainstabilized with VcmIntegral gainsubject to nonlniearity/variationVcmCalibrationState MachineProportionalpathIntegralpath 2024 IEEE International Solid-State Circuits ConferenceVcmCalibrationState MachineProportionalpathIntegralpathIntegral Path CalibrationPing-Hsuan HsiehISSCC 2

164、024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution13 of 71*M.Ferriss,et al.,JSSC,April 2013.1.Allow PLL lock2.Disable proportional path&inject phase step3.Count time-to-cross-over4.Repeat with opposite phase stepInject phase stepby temporarilychanging N 2024 IEEE International Solid-

165、State Circuits ConferenceMeasurements at different frequencies in one coarse tuning bandLoop Bandwidth and Phase Noise PerformancePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution14 of 71*M.Ferriss,et al.,JSSC,April 2013.Digital calibration made possible with

166、TDC and DACs 2024 IEEE International Solid-State Circuits ConferenceSmaller areaBetter scaled with technologyBetter programmabilityBetter testability/observabilityDigital Phase-Locked LoopsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution15 of 71 2024 IEEE Int

167、ernational Solid-State Circuits ConferenceDigital runtime solver moduleSolve phase-frequency update equations iterativelyComputational Locking for Faster AcquisitionPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution16 of 71Solver*F.Rahman et al.,JSSC Sep.2019.F

168、ast acquisition steps:1.Re-Snap2.Frequency acquisition3.Phase acquisition 2024 IEEE International Solid-State Circuits Conference34%area overhead,gated-off to minimize power dissipationPVT-robust Tlockof 12TREFCLK(re-lock)and 16TREFCLK(cold-start)Computational Locking for Faster AcquisitionPing-Hsua

169、n HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution17 of 71*F.Rahman et al.,JSSC Sep.2019.12Histogram of Tlockfor re-lock16Histogram of Tlockfor cold-start 2024 IEEE International Solid-State Circuits ConferenceDigital loop filter free from inaccuracyHowever,TDC(KPD)and

170、DCO(KDCO)still have spreads Calibration requiredLoop Parameters in DPLLPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution18 of 71 2024 IEEE International Solid-State Circuits ConferenceBang-Bang Phase DetectorPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhan

171、ced Clock Generation and Distribution19 of 71Simple and fast operation suitable for DPLLHowever,KBBPDdepend on input noise level function of loop BW function of KBBPD Loop characteristics determined implicitlyCKREFCKDIV*J.Lee et al.,JSSC Sep.2004.2024 IEEE International Solid-State Circuits Conferen

172、ceControlled jitter injected into reference pathInjected jitter-shaped to frequencies loop BWKBBPDAdjustment Through DitheringPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution20 of 71A.Rylyakov et al.,ISSCC2009,paper 5.3.MDELAY87delay line controlsEN1 EN7fract

173、ional delay bits 2024 IEEE International Solid-State Circuits ConferenceIncrease loop gain to improve jitter trackingLoop Gain Calibration for Digital CDRPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution21 of 71*J.Liang et al.,JSSC Sep.2018.KGPDOUT 2024 IEEE I

174、nternational Solid-State Circuits ConferenceKGPDOUTIncrease loop gain to improve jitter tracking degrade phase margin excessive tracking jitterLoop Gain Calibration for Digital CDRPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution22 of 71*J.Liang et al.,JSSC Se

175、p.2018.2024 IEEE International Solid-State Circuits ConferenceIncrease loop gain to improve jitter tracking degrade phase margin excessive tracking jitterMonitor auto-correlation of PD output to prevent underdampLoop Gain Calibration for Digital CDRPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enha

176、nced Clock Generation and Distribution23 of 71*J.Liang et al.,JSSC Sep.2018.Auto-correlationMeasurement 2024 IEEE International Solid-State Circuits ConferenceNear-optimal high-frequency JTOL&recovered clock jitterLoop Gain Calibration for Digital CDR24 of 71Ping-Hsuan HsiehISSCC 2024-Forum 3.2:Digi

177、tally-Enhanced Clock Generation and DistributionJ.Liang et al.,JSSC Sep.2018.2024 IEEE International Solid-State Circuits Conference1.Estimate loop gain that involve analog parameters2.Multiply loop gain by inverse of estimateDesensitize Loop Gain to Analog ParametersPing-Hsuan HsiehISSCC 2024-Forum

178、 3.2:Digitally-Enhanced Clock Generation and Distribution25 of 71*M.Mercandelli et al.,JSSC Nov.2018.Digital intensive design facillitate loop gain calibration with digital algorithm 2024 IEEE International Solid-State Circuits ConferenceLoop Gain EstimationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digit

179、ally-Enhanced Clock Generation and Distribution26 of 71*M.Mercandelli et al.,JSSC Nov.2018.1.Inject a suitable digital training signal at DCO inputDigitalLoop FilterDividerDCOOUTqkREFekTDC 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Calibration with Digital Adaptive FilterPing-H

180、suan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution27 of 71*M.Mercandelli et al.,JSSC Nov.2018.1.Inject a suitable digital training signal at DCO input2.Correlate it with TDC output with digital adaptive algorithm3.Multiply loop gain by inverse of estimateDigitalLoop

181、FilterDividerDCOREFOUTekqkTDCLMS eng11z 11z 1GgkEgk=g G 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Calibration with Digital Adaptive FilterPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution28 of 71*M.Mercandelli et al.,JSSC Nov.2018.Traini

182、ng sequence needed modulator refine DCO resolution while adding quantization noiseDigitalLoop FilterDividerDCOOUTqk11z 1qkREFekTDCLMS eng1z 1GgkEgk=g G 2024 IEEE International Solid-State Circuits ConferenceLoop Gain Calibration with Digital Adaptive FilterPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digita

183、lly-Enhanced Clock Generation and Distribution29 of 71Use quantization noise without additional noise and overhead*M.Mercandelli et al.,JSSC Nov.2018.DigitalLoop FilterDividerDCOOUT11z 1qkREFekTDCLMS eng1z 1GgkEgk=g G 2024 IEEE International Solid-State Circuits ConferenceBackground calibration dese

184、nsitize NTF from analog parameters Predictable BW depend on repeatable and controllable digital parametersMeasured Phase Noise PerformancePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution30 of 71*M.Mercandelli et al.,JSSC Nov.2018.2024 IEEE International Solid

185、-State Circuits ConferenceIntroductionLoop characteristics calibration(enabled by DACs and ADCs)Noise and error cancellationAccurate phase/delay controlConclusionOutlinePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution31 of 71 2024 IEEE International Solid-Sta

186、te Circuits ConferencePhase/noise information can be easily extracted in DPLL architecture Facilitate pure digital error extraction&pure digital error correction Digital Intensive DesignPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution32 of 71 2024 IEEE Intern

187、ational Solid-State Circuits Conference1.Inject a test signal2.Correlate it with DLF outputSupply Noise CancellationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution33 of 71*A.Elshazly et al.,JSSC Dec.2011.2024 IEEE International Solid-State Circuits Conferenc

188、eMeasurement ResultsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution34 of 71Testing structure occupies 12.5%of overall areaSupply noise cancellationFor supply noise frequency from 0.1M to 2GHzFor output frequency from 0.8 to 2.6GHz 32 dB improvement in power

189、supply noise rejection*A.Elshazly et al.,JSSC Dec.2011.2024 IEEE International Solid-State Circuits ConferenceVCDL with opposite supply sensitivity2nd-order adaptive filter with SSLMS minimize output rms jitterSupply Noise Cancellation for Clock DistributionPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digit

190、ally-Enhanced Clock Generation and Distribution35 of 71*Y.Jung et al.,JSSC,Jan.2023.2024 IEEE International Solid-State Circuits Conference6.4-Gb/s data,3.2-GHz clock for LPDDR5 DRAM with 28-nm CMOS1-MHz 60-mVpp sinusoidal supply noiseSupply Noise Cancellation for Clock DistributionPing-Hsuan HsiehI

191、SSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution36 of 71READWRITEeye opening 22.43 ps 104.73 psrms jitter 27.84 ps 4.28 ps*Y.Jung et al.,JSSC,Jan.2023.2024 IEEE International Solid-State Circuits ConferenceSupply Noise CancellationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitall

192、y-Enhanced Clock Generation and Distribution37 of 71!Analog cancellation!Mixed-signal design-noise amplifier-phase detector-VCDL*A.Elshazly et al.,JSSC Dec.2011.*Y.Jung et al.,JSSC,Jan.2023.2024 IEEE International Solid-State Circuits Conference1.Learning phase:estimate interference periodicity2.Can

193、cellation phase:adjust gain/phase with 2D coordinate descent algorithm minimize spur-induced eror at TDC outputMitigation of External Noise from VCO PathPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution38 of 71*C.-R.Ho and M.Chen,ESSCIRC 2016.180 out-of-phase

194、spur replica at DCO input Zero spur at DCO output 2024 IEEE International Solid-State Circuits ConferenceDifferent Coupling PathsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution39 of 713)DCO bias1)DCO supply2)Driver supply10dB spur suppressioncancel.scheme2.4

195、mADPLL:17.2mA+1.7mA*C.-R.Ho and M.Chen,ESSCIRC 2016.2024 IEEE International Solid-State Circuits ConferenceDigital information used for noise esitmationCancellation through AF zero spur at DLF inputMitigation of External Noise from REF PathPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Cloc

196、k Generation and Distribution40 of 71*C.-R.Ho and M.Chen,TCAS-I,Aug.2016.2024 IEEE International Solid-State Circuits ConferenceProvide 20dB spur suppressionOnly address interference that is1.Single-tone2.With known frequency3.coupled through reference pathAdaptive Single-Tone Spur CancellationPing-

197、Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution41 of 16*C.-R.Ho and M.Chen,TCAS-I,Aug.2016.cancel.scheme3.6mA15.8mA+1.8mA 2024 IEEE International Solid-State Circuits ConferenceDithering division ratio produce quantization noiseDelta-sigma operation push error to

198、 high frequenciesQuantization Noise in Fractional-N PLLPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution42 of 71 2024 IEEE International Solid-State Circuits ConferenceDigital error extractionAnalog correction vs.digital correction?Internal Noise:Quantization

199、Noise CancellationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution43 of 71*C.-M.Hsu et al.,JSSC,Dec.2008.quantization errorD/AGainControlResidual Noise Due toGain Mismatch!2024 IEEE International Solid-State Circuits ConferenceDigital Quantization Noise Cance

200、llationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution44 of 71*C.-M.Hsu et al.,JSSC,Dec.2008.Digital error extractionAnalog correction vs.digital correction?2024 IEEE International Solid-State Circuits Conference3.6 GHz with 0.13-m CMOS15 dB noise cancellati

201、on st.VCO dominate out-of-band noiseDigital Quantization Noise CancellationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution45 of 71*C.-M.Hsu et al.,JSSC,Dec.2008.2024 IEEE International Solid-State Circuits ConferencePerformance Limited by TDC DesignPing-Hsua

202、n HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution46 of 71*C.-M.Hsu et al.,JSSC,Dec.2008.Require TDC with high resolution and high linearity 2024 IEEE International Solid-State Circuits ConferenceFractional-N DPLL with BBPD(1-Bit TDC)Ping-Hsuan HsiehISSCC 2024-Forum 3.2

203、:Digitally-Enhanced Clock Generation and Distribution47 of 7110-bit fractional divider allow BBPD better efficiencyDTC gain calibrated with digital adaptive filter*D.Tasca et al.,JSSC,Dec.2011.2024 IEEE International Solid-State Circuits Conference2.9-4.0 GHz with 65-nm CMOS560-fs rms jitter with 4.

204、5 mW FoM of 238.3 dBWorst-case fractional spur of 42 dBc(at 100-kHz offset)Fractional-N DPLL with BBPDPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution48 of 71before calibrationafter calibration*D.Tasca et al.,JSSC,Dec.2011.2024 IEEE International Solid-State

205、Circuits ConferencePerformance Limited by TDC DesignPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution49 of 71*C.-M.Hsu et al.,JSSC,Dec.2008.Require TDC with high resolution and high linearity 2024 IEEE International Solid-State Circuits ConferenceFrequency Acc

206、umulation-Type DPLLPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution50 of 71*F.Opteynde,ISSCC2012,paper 20.3.*C.-R.Ho and Mike Chen,IEEE Microwave Magazine,2019ILRO-based TDC provide gain/resolution trackingQuantization noise result in fractional spurs 2024 IE

207、EE International Solid-State Circuits ConferenceDirect Quantization Noise CancellationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution51 of 71*F.Opteynde,ISSCC2012,paper 20.3.*C.-R.Ho and Mike Chen,IEEE Microwave Magazine,2019Truncate accumulated FCW(phase)to

208、 match TDC resolution Cancellation degradation from TDC nonlinearity result in fractional spursExtremely low HW cost!2024 IEEE International Solid-State Circuits ConferenceScramble fractional spurs from TDC quantization noise and nonlinearityReference Path DitheringPing-Hsuan HsiehISSCC 2024-Forum 3

209、.2:Digitally-Enhanced Clock Generation and Distribution52 of 71*C.-R.Ho and M.Chen,ISSCC2018,paper 25.3.2024 IEEE International Solid-State Circuits ConferenceDithering noise cancellation with adaptive filterReference Path DitheringPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Genera

210、tion and Distribution53 of 71*C.-R.Ho and M.Chen,ISSCC2018,paper 25.3.2024 IEEE International Solid-State Circuits ConferenceDithering-Based Spur MitigationPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution54 of 71*C.-R.Ho and M.Chen,ISSCC2018,paper 25.3.30 dB

211、spur improvement 2024 IEEE International Solid-State Circuits ConferenceMinimize TDC quantization noise and nonlinearityCancel dithering noise with adaptive filterDigital MDLL with Reference Path DitheringPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution55 of

212、71*Q.Zhang and M.Chen,ISSCC2021,paper 29.4.2024 IEEE International Solid-State Circuits ConferenceRing oscillator adopted to reduce power and areaInjection applied to clean up in-band noiseFractional-N Digital MDLLPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribut

213、ion56 of 71*Q.Zhang and M.Chen,ISSCC2021,paper 29.4.Subject to gain and offset error 2024 IEEE International Solid-State Circuits ConferenceError observed at TDC output Calibration accuracy limited by TDC resolution/linearity!DTC Gain Error and Offset CalibrationPing-Hsuan HsiehISSCC 2024-Forum 3.2:

214、Digitally-Enhanced Clock Generation and Distribution57 of 71*Q.Zhang and M.Chen,ISSCC2021,paper 29.4.Offset cancelled in digital domainGain error cancelled in analog domainaccuracy of 25-dB spur reductionMeasurement ResultsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and

215、Distribution59 of 71*Q.Zhang and M.Chen,ISSCC2021,paper 29.4.2024 IEEE International Solid-State Circuits ConferenceOutput Phase Adjustment for Phased ArraysPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution60 of 71Conventional RF phase-shiftingProposed localiz

216、ed LO phase-shifting*F.Tesolin et al.,JSSC,Sep.2023.2024 IEEE International Solid-State Circuits ConferenceLO Phase Shifting TechniquePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution61 of 71*F.Tesolin et al.,JSSC,Sep.2023.Output phase adjusted by injecting a

217、time errort0 2024 IEEE International Solid-State Circuits ConferenceOutput phase adjusted digitally by stepping FCW up/dn momentarilyEffectively set by PCW linearily with fractional-N resolutionLO Phase Shifting TechniquePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Di

218、stribution62 of 71*F.Tesolin et al.,JSSC,Sep.2023.2024 IEEE International Solid-State Circuits ConferenceOutput phase adjusted digitally by stepping FCW up/dn momentarilyEffectively set by PCW linearily with fractional-N resolutionLO Phase Shifting TechniquePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digit

219、ally-Enhanced Clock Generation and Distribution63 of 71*F.Tesolin et al.,JSSC,Sep.2023.2024 IEEE International Solid-State Circuits ConferenceSources of Static OffsetPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution64 of 71*F.Tesolin et al.,JSSC,Sep.2023.1.DTC

220、 nonlinearity2.DTC/BBPD mismatch3.Reference path mismatch 2024 IEEE International Solid-State Circuits ConferenceTwo-element array8.5-10.0 GHz with 28-nm CMOS19-bit phase-shifting resolutionPeak-to-peak phase error 2.1 and rms error of 0.76(Core-to-core coupling of k=40.86dB result in sinusoidal dep

221、endancy)Measurement ResultsPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution65 of 71*F.Tesolin et al.,JSSC,Sep.2023.2024 IEEE International Solid-State Circuits ConferenceEver-increasing system performance necessitates precise timing controlLoop characteristic

222、s calibrationNoise and error cancellationAccurate phase/delay controlAnalog(mixed-signal)PLLCalibration with DAC(capacitor-bank,current-DAC,voltage-DAC,etc.,)Digital PLLDigital intensitve implementation allow pure digital error extraction&correction Performance limited by TDC or DTC resolutionAccura

223、te yet efficient solution remain challenging as precision requirement increasePing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution66 of 71Conclusions:Digitally-Enhanced CK Gen&Distribution 2024 IEEE International Solid-State Circuits ConferencePing-Hsuan HsiehISS

224、CC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution67 of 71DigitalLoop FilterDividerDCOREFOUTTDCLMS eng11z 1qkLoop characteristics calibration(AF)External noise cancellation(AF)for noise shaping error cancellation(AF)DTC gain calibration(AF)for noise shapingILRO-TDC w/gain trackin

225、g,DTC gain calibration(AF),for noise shaping,error cancellation(AF)Internal error cancellation for noise shaping error cancellation(AF)Linear phase shift 2024 IEEE International Solid-State Circuits ConferenceEver-increasing system performance necessitates precise timing controlLoop characteristics

226、calibrationNoise and error cancellationAccurate phase/delay controlAnalog(mixed-signal)PLLCalibration with DAC(capacitor-bank,current-DAC,voltage-DAC,etc.,)Digital PLLDigital intensitve implementation allow pure digital error extraction&correction Performance limited by TDC or DTC resolutionAccurate

227、 yet efficient solution remain challenging as precision requirement increaseConclusions:Digitally-Enhanced CK Gen&DistributionPing-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution68 of 71 2024 IEEE International Solid-State Circuits ConferenceReferences(I)E.Hegazi

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229、48,no.4,pp.996-1008,April 2013,doi:10.1109/JSSC.2013.2239114.F.ur Rahman,G.Taylor and V.Sathe,A 12 GHz Computational-Locking ADPLL With Sub-20-Cycle LocktimeAcross PVT Variation,in IEEE Journal of Solid-State Circuits,vol.54,no.9,pp.2487-2500,Sept.2019,doi:10.1109/JSSC.2019.2926191.Jri Lee,K.S.Kunde

230、rt and B.Razavi,Analysis and modeling of bang-bang clock and data recovery circuits,in IEEE Journal of Solid-State Circuits,vol.39,no.9,pp.1571-1580,Sept.2004,doi:10.1109/JSSC.2004.831600.A.Rylyakov et al.,Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial

231、communication applications,2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers,San Francisco,CA,USA,2009,pp.94-95,95a,doi:10.1109/ISSCC.2009.4977324.J.Liang,A.Sheikholeslami,H.Tamura,Y.Ogata and H.Yamaguchi,Loop Gain Adaptation for Optimum Jitter Tolerance in Digital C

232、DRs,in IEEE Journal of Solid-State Circuits,vol.53,no.9,pp.2696-2708,Sept.2018,doi:10.1109/JSSC.2018.2839038.M.Mercandelli,L.Grimaldi,L.Bertulessi,C.Samori,A.L.Lacaita and S.Levantino,A Background Calibration Technique to Control the Bandwidth of Digital PLLs,in IEEE Journal of Solid-State Circuits,

233、vol.53,no.11,pp.3243-3255,Nov.2018,doi:10.1109/JSSC.2018.2866454.A.Elshazly,R.Inti,W.Yin,B.Young and P.K.Hanumolu,A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration,in IEEE Journal of Solid-State Circuits,vol.46,no.12,pp.2759-2771,Dec

234、.2011,doi:10.1109/JSSC.2011.2162912.69 of 71Ping-Hsuan HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution 2024 IEEE International Solid-State Circuits ConferenceC.-R.Ho and M.S.-W.Chen,Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS,ES

235、SCIRC Conference 2016:42nd European Solid-State Circuits Conference,Lausanne,Switzerland,2016,pp.213-216,doi:10.1109/ESSCIRC.2016.7598280.C.-R.Ho and M.S.-W.Chen,A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme,in IEEE Trans

236、actions on Circuits and Systems I:Regular Papers,vol.63,no.8,pp.1111-1122,Aug.2016,doi:10.1109/TCSI.2016.2577858.C.-M.Hsu,M.Z.Straayer and M.H.Perrott,A Low-Noise Wide-BW 3.6-GHz Digital$DeltaSigma$Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noi

237、se Cancellation,in IEEE Journal of Solid-State Circuits,vol.43,no.12,pp.2776-2786,Dec.2008,doi:10.1109/JSSC.2008.2005704.D.Tasca,M.Zanuso,G.Marzin,S.Levantino,C.Samori and A.L.Lacaita,A 2.94.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs rms Integrated Jitter at 4.5-mW Power

238、,in IEEE Journal of Solid-State Circuits,vol.46,no.12,pp.2745-2758,Dec.2011,doi:10.1109/JSSC.2011.2162917.F.Opteynde,A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration,2012 IEEE International Solid-State Circuits Conference,San Francisco,CA,USA,2012,pp.346-347,doi:10.1109

239、/ISSCC.2012.6177039.C.-R.Ho and M.S.-W.Chen,Smoothing the Way for Digital Phase-Locked Loops:Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference,in IEEE Microwave Magazine,vol.20,no.5,pp.80-97,May 2019,doi:10.1109/MMM.2019.2898022.Reference(II)Ping-Hsua

240、n HsiehISSCC 2024-Forum 3.2:Digitally-Enhanced Clock Generation and Distribution70 of 71 2024 IEEE International Solid-State Circuits ConferenceC.-R.Ho and M.S.-W.Chen,A fractional-N digital PLL with background-dither-noise-cancellation loop achieving 1GHZ,edge rates much higher =0 1 =15RC:0.01(1.5m

241、m)Antenna:/2(75mm)Wave propagation needs to be considered in droop simulations,management,and measurementsModeling and Simulation of DroopsISSCC 2024:From Microwatts to Terawatts,Managing GPU Power18 of 45 2024 IEEE International Solid-State Circuits ConferenceOutlineData center challenges&recent AI

242、 trendsGPU power optimizationsDigital optimizationsAnalog and mitigation featuresTechnology,packaging,and testD2D interfacesPower management,what can data centers learn from the mobile worldLooking aheadGPU power and power delivery challengesAMD response and Call to actionISSCC 2024:From Microwatts

243、to Terawatts,Managing GPU Power19 of 45 2024 IEEE International Solid-State Circuits ConferencePkg CapDie CapBulk CapTest ChallengesDroops are different(especially 1stdroop)in test and application environmentsCorrelation between the two environments could result in guard bands and performance loss I

244、SSCC 2024:From Microwatts to Terawatts,Managing GPU Power20 of 45 2024 IEEE International Solid-State Circuits ConferenceTechnology,Packaging,and Test OptimizationsRing oscillators for speed measurements:spread over the die acting as speed monitors and providing accurate assessment of per part speed

245、 capability.PSM:Power supply monitors used for calibrating out the voltage droop as well and voltage tolerances in the power delivery network.Temperature Sensors:Temperature remote sensors across the die feeding information regularly to the adaptive management systems on the processorTogether these

246、enable a dynamic,adaptive,and optimal voltage-frequency scaling as a function of the operating condition and workloadsPower efficiency enhanced via self-calibration that removes traditional guard bands around worst-case operating conditions(aging,temperature,VR tolerances,process/manufacturing distr

247、ibutions)ISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerROPSMTemp.Sense21 of 45 2024 IEEE International Solid-State Circuits ConferenceMulti Vt-Multi Corner OptimizationPer-Part Vmin:Optimizing performance down to functional Vmin through innovative characterization and testing.Very critic

248、al since several data center workloads often reside Vmin.Seamlessly support power efficient operation for wide array of workloads that traverse large dynamic voltage range of operation under infrastructure constraintsISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerTechnology,Packaging,and

249、Test Optimizations22 of 45 2024 IEEE International Solid-State Circuits ConferenceChiplets and InterconnectsCost Adder($/wafer)Lower Interconnect PowerHybrid Bonding(3D)MCMWafer Level Fan Out(2.5D)100400-1500Med-High BWUltra-High BW10k-500kAreal Interconnect Density(wires/mm2)ISSCC 2024:From Microwa

250、tts to Terawatts,Managing GPU Power23 of 45 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerTechnology,Packaging,and TestChiplet and advanced packaging technologies have enabled us to build large and complex data center processors at h

251、igh yields.Traditional product test and binning at die-chiplet level is enhanced with innovative assembly instruction viz.,optimize packaging of dies from similar or different bin(s)depending on ease of voltage scaling at component level,power sloshing between components etc.Significant improvement

252、in final processor delivered performance and tightening of performance variation across process/manufacturing distribution window is achieved.24 of 45 2024 IEEE International Solid-State Circuits ConferenceOutlineData center challenges&recent AI trendsGPU power optimizationsDigital optimizationsAnal

253、og and mitigation featuresTechnology,packaging,and testD2D interfacesPower management,what can data centers learn from the mobile worldLooking aheadGPU power and power delivery challengesAMD response and Call to actionISSCC 2024:From Microwatts to Terawatts,Managing GPU Power25 of 45 2024 IEEE Inter

254、national Solid-State Circuits ConferenceInterconnects Hybrid Bonding Driving Moores Law Scaling1stWave of 3D Product Launched in 20222ndWave of Product Launched in 2023Chip on Wafer12k-30k wires/mm2Wafer on Wafer200k-500k wires/mm2ISSCC 2024:From Microwatts to Terawatts,Managing GPU Power26 of 45 20

255、24 IEEE International Solid-State Circuits ConferenceAdvanced Packaging Can Enable Integration Schemes Not Possible With Monolithic DesignsDRAM on CPUCPU on CPUCores on CoresCores on UncorecarryDie 1Die 2TSVTSVXXDie 1Die 2ISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerFuture of 3D Stackin

256、g27 of 45 2024 IEEE International Solid-State Circuits ConferenceInterconnect Power With 3D StackingISSCC 2024:From Microwatts to Terawatts,Managing GPU Power28 of 45 2024 IEEE International Solid-State Circuits ConferenceOutlineData center challenges&recent AI trendsGPU power optimizationsDigital o

257、ptimizationsAnalog and mitigation featuresTechnology,packaging,and testD2D interfacesPower management,what can data centers learn from the mobile worldLooking aheadGPU power and power delivery challengesAMD response and Call to actionISSCC 2024:From Microwatts to Terawatts,Managing GPU Power29 of 45

258、 2024 IEEE International Solid-State Circuits ConferenceWhat Can We Learn From the Mobile World 10 hrs.of active use battery life Weeks of airplane mode/modern standbySophisticated platform power managementOrder of magnitudes improvements in performance per watt Order of magnitude improvements in ca

259、rbon footprintISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerBarnes Cooper:Bits 2018 Distinguished Speaker30 of 45 2024 IEEE International Solid-State Circuits ConferenceWhat Can WeLearn from the Mobile WorldISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerTypical energy use sets

260、 carbon footprint,utility bills,and environmental impactAMD Ryzen TM7 4800H consumes less than 1/6ththe typical energy of our 2014 APU while still delivering the 5X performance gain1 As defined by:ECTC(typicalconsumption of notebook computers by Energy Star Program Requirements Rev 6.1 10/2014)31 of

261、 45 2024 IEEE International Solid-State Circuits ConferencePower limits for different SKU/OPNs defined using platform infrastructureShort boost and sustained responses across workloadsPerformance is maximized and power minimizedTawfik Rahal-ArabiISSCC 2024:From Microwatts to Terawatts,Managing GPU P

262、owerWhat Can We Learn From the Mobile WorldThrottle down in MicrosecondsResidency controlled to millisecondsPower Can peak here for secondsResidency Controlled to SLOW_PPT_TIME_CONSTANTPower Can be sustained here to hundreds of secondsResidency controlled to STAPM_TIME_CONSTANTPower can sustain inde

263、finitely PEAK_PACKAGE_POWER_LIMIT(P3T)FAST_PPT_LIMIT(fPPT)APU Limit for System AC/DC power supply peak controlSLOW_PPT_LIMIT(sPPT)APU limit for system AC/DC power supply thermal controlSUSTAINED_POWER_LIMIT(SPL)APU limit for long term system skin temperature control TimePowerIdle Power32 of 45 2024

264、IEEE International Solid-State Circuits ConferenceSmart shift in laptops for active power and performance managementShift power away from inefficient IP to efficient onesPower algorithms with power,current,reliability,frequency,voltage,and thermal managementShort duration and long duration idle powe

265、r management for battery lifeSoC power statesSave-restore accelerationClock gating and power gating improvementsRace to idle and energy optimizationHW-SW codesign for power efficiencyHeterogeneous cores and accelerators usage in SoCTuning of the software&applications to our hardwareLearning algorith

266、ms to enhance user experienceWhat Can We Learn From the Mobile WorldISSCC 2024:From Microwatts to Terawatts,Managing GPU Power33 of 45 2024 IEEE International Solid-State Circuits ConferenceMobileBattery life driving idle power to a very small percentage of totalLaptop idle power very low,1%of total

267、Provisioned power(HW)is less than 2X of average power Dynamically re-allocating power budgets to components that need itSmart Shift/Smart Boost Sustainability driven by consumer awareness,such as Energy StarWhat Can we Learn from the Mobile WorldData CentersIdle power in data centers is a considerab

268、le percentage of totalPower bill(not directly visible to end users)Provisioned power/HW(4X)driven by peak power and availabilityNot done to the extent of laptops due to multiple clients residing on the same CPU/GPUNo consumer awareness of power consumption of VMsISSCC 2024:From Microwatts to Terawat

269、ts,Managing GPU Power34 of 45 2024 IEEE International Solid-State Circuits ConferenceOutlineData center challenges&recent AI trendsGPU power optimizationsDigital optimizationsAnalog and mitigation featuresTechnology,packaging,and testD2D interfacesPower management,what can data centers learn from th

270、e mobile worldLooking aheadGPU power and power delivery challengesAMD response and Call to actionISSCC 2024:From Microwatts to Terawatts,Managing GPU Power35 of 45 2024 IEEE International Solid-State Circuits ConferenceFiner Grain Power Management and Distribution=2+3 3VR100 cores/cu60V1VVR50 cores/

271、cu60V1VVR50 cores/cu60V0.8VChallengesGPUs trending to exceed 1 KWMultiple VRs higher cost and bigger real estateVR silicon integration power efficiency 25%PowerSavingsISSCC 2024:From Microwatts to Terawatts,Managing GPU Power36 of 45 2024 IEEE International Solid-State Circuits ConferencePower Conve

272、rsion Integration State of the Art and ChallengesDiscreteVCC2*VCCState-of-the-ArtNorth StarOff-ChipOn-Chip/PackageOn-Chip/Package VerticalSwitching Frequency(MHz)1-3 MHz130 MHz250 MHz(2ndStage)Input Voltage(Volts)12-20 or 481.848-300V(1stStage)Energy StorageDiscrete MagneticsAir-Core(in pkg)Low Loss

273、 IntegratedMagneticsDiscrete&Low DensityMIM CapsHD Mim/Silicon(DT)capsHD Caps on DieSystem Conversion Efficiency*89/7180/7592/90Distribution GranularityCoarseGoodFineAir CoreCascodeISSCC 2024:From Microwatts to Terawatts,Managing GPU Power*.6V SoC with/without routing losses at 1000W37 of 45 2024 IE

274、EE International Solid-State Circuits ConferenceOutlineData center challenges&recent AI trendsGPU power optimizationsDigital optimizationsAnalog and mitigation featuresTechnology,packaging,and testD2D interfacesPower management,what can data centers learn from the mobile worldLooking aheadGPU power

275、and power delivery challengesAMD response and call to actionISSCC 2024:From Microwatts to Terawatts,Managing GPU Power38 of 45 2024 IEEE International Solid-State Circuits ConferenceBoardBladeRackClusterAllocator SoftwareSmallest granularity is at the cluster level Virtual machines are statically as

276、signed based on availabilityEnergy blast radius is very largeNeed software control at core/cu levelSoftware Challenges With Finer Grain Power DeliveryISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerGPU39 of 45 2024 IEEE International Solid-State Circuits ConferenceData Center Challenges:AI

277、 Driving Compute&Memory GrowthISSCC 2024:From Microwatts to Terawatts,Managing GPU Power40 of 45 2024 IEEE International Solid-State Circuits ConferenceData Center Trends AMD Response and Call to ActionISSCC 2024:From Microwatts to Terawatts,Managing GPU PowerBased on 2015-2020 industry trends in en

278、ergy efficiency gains and data center energy consumption in 2025.*Includes AMD high performance CPU and GPU accelerators used for AI training and High-Performance Computing in a 4-Accelerator,CPU hosted configuration.Goal calculations are based on performance scores as measured by standard performan

279、ce metrics(HPC:Linpack DGEMM kernel FLOPS with 4k matrix size.AI training:lower precision training-focused floating point math GEMM kernels such as FP16 or BF16 FLOPS operating on 4k matrices)divided by the rated power consumption of a representative accelerated compute node including the CPU host+m

280、emory,and 4 GPU accelerators.Resulting node-level efficiency gainsAMD roadmap on track to exceed aggressive 30 x goalArchitecture,packaging and interconnect innovations pay offChiplet and 3D-enabled architecture put AMD Instinct products on a path to exceed 30 x goal41 of 45 2024 IEEE International

281、Solid-State Circuits ConferenceTawfik Rahal-Arabi,Brijesh Warrier,Jonathan Koomey,“Transformational Improvements in Data Center Power Efficiency and Sustainability”,2023 OCP regional summit.L.Su and S.Naffziger,1.1 Innovation For the Next Decade of Compute Efficiency,2023 IEEE International Solid-St

282、ate Circuits Conference(ISSCC),San Francisco,CA,USA,2023,pp.8-12,doi:10.1109/ISSCC42615.2023.10067810.R.Swaminathan,M.J.Schulte,B.Wilkerson,G.H.Loh,A.Smith and N.James,AMD InstinctTMMI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture,2023 IEEE Symposium on VLSI Techn

283、ology and Circuits(VLSI Technology and Circuits),Kyoto,Japan,2023,pp.1-2,doi:10.23919/VLSITechnologyandCir57934.2023.10185224.S.Naffziger et al.,Pioneering Chiplet Technology and Design for the AMD EPYC and RyzenProcessor Families:Industrial Product,2021 ACM/IEEE 48th Annual International Symposium

284、on Computer Architecture(ISCA),Valencia,Spain,2021,pp.57-70,doi:10.1109/ISCA52012.2021.00014.ReferencesISSCC 2024:From Microwatts to Terawatts,Managing GPU Power42 of 45 2024 IEEE International Solid-State Circuits ConferenceLeiserson,Charles E.,Neil C.Thompson,Joel S.Emer,Bradley C.Kuszmaul,Butler

285、W.Lampson,Daniel Sanchez,and Tao B.Schardl.2020.Theres plenty of room at the top:What will drive computer performance after Moores law?Science.vol.368,no.6495.pp.eaam9744.A.Muhtaroglu,G.Taylor and T.Rahal-Arabi,On-die droop detector for analog sensing of power supply noise,in IEEE Journal of Solid-S

286、tate Circuits,vol.39,no.4,pp.651-660,April 2004,doi:10.1109/JSSC.2004.825120.E.A.Burton et al.,FIVR Fully integrated voltage regulators on 4th generation Intel CoreSoCs,2014 IEEE Applied Power Electronics Conference and Exposition-APEC 2014,Fort Worth,TX,USA,2014,pp.432-439,doi:10.1109/APEC.2014.680

287、3344.K.L.Wong,T.Rahal-Arabi,M.Ma and G.Taylor,Enhancing microprocessor immunity to power supply noise with clock-data compensation,in IEEE Journal of Solid-State Circuits,vol.41,no.4,pp.749-758,April 2006,doi:10.1109/JSSC.2006.870925.ReferencesISSCC 2024:From Microwatts to Terawatts,Managing GPU Pow

288、er43 of 45 2024 IEEE International Solid-State Circuits ConferenceA.Waizman,M.Livshitz and M.Sotman,Integrated power supply frequency domain impedance meter(IFDIM),Electrical Performance of Electronic Packaging-2004,Portland,OR,USA,2004,pp.217-220,doi:10.1109/EPEP.2004.1407591.K.Wilcox et al.,4.8 A

289、28nm x86 APU optimized for power and area efficiency,2015 IEEE International Solid-State Circuits Conference-(ISSCC)Digest of Technical Papers,San Francisco,CA,USA,2015,pp.1-3,doi:10.1109/ISSCC.2015.7062937.ReferencesISSCC 2024:From Microwatts to Terawatts,Managing GPU Power44 of 45 2024 IEEE Intern

290、ational Solid-State Circuits Conference2023 Advanced Micro Devices,Inc.All rights reserved.AMD,the AMD Arrow logo,EPYC,Instinct,Ryzen,and combinations thereof are trademarks of Advanced Micro Devices,Inc.Other product names used in this publication are for identification purposes only and may be tra

291、demarks of their respective companies.The information presented in this document is for informational purposes only and may contain technical inaccuracies,omissions,and typographical errors.The information contained herein is subject to change and may be rendered inaccurate releases,for many reasons

292、,including but not limited to product and roadmap changes,component and motherboard version changes,new model and/or product differences between differing manufacturers,software changes,BIOS flashes,firmware upgrades,or the like.Any computer system has risks of security vulnerabilities that cannot b

293、e completely prevented or mitigated.AMD assumes no obligation to update or otherwise correct or revise this information.However,AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisio

294、ns or changes.THIS INFORMATION IS PROVIDED AS IS.AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES,ERRORS,OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION.AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF NON-INFRINGE

295、MENT,MERCHANTABILITY,OR FITNESS FOR ANY PARTICULAR PURPOSE.IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY RELIANCE,DIRECT,INDIRECT,SPECIAL,OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN,EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES

296、.Copyright and DisclaimerISSCC 2024:From Microwatts to Terawatts,Managing GPU Power45 of 45 2024 IEEE International Solid-State Circuits ConferenceTawfik Rahal-ArabiISSCC 2024:From Microwatts to Terawatts,Managing GPU Power46 of 46Please Scan to Rate Please Scan to Rate This PaperThis Paper 2024 IEE

297、E International Solid-State Circuits ConferenceDigital and Mixed-SignalADC Enhancement TechniquesPieter HarpeEindhoven University of Technology1 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceBackground&MotivationG

298、eneral trade-offsBasic principlesDesign examplesCalibration and enhancement techniquesDigitally-inspired analog designOutlookConclusionsOutline2 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceBackground&MotivationG

299、eneral trade-offsBasic principlesDesign examplesCalibration and enhancement techniquesDigitally-inspired analog designOutlookConclusionsOutline3 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceCalibrating one(or a f

300、ew)properties Relax trade-offs;better optimizationAnalog/ADC Trade-offs and Limitations4 of 57Analog design trade-offsAnalog limitationsAreaSpeedPoweretc.NoiseOffsetNo calibrationWith calibrationOffset relaxed thanks tocalibrationPerformanceCostCalibration overheadLimitation pushed forwardCalibratio

301、n can overcome certain limits,e.g.:mismatch,frequency limitsISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceTime-interleaving 3Beam-forming 4Trends in communicationHigher data rates(IO,wireline,wireless)Increased samplin

302、g rates¶llelization(time-interleaving)for ADCsMaximize spectral usage in spatial and amplitude domains:arrays and higher resolutionADC Application Trends(Communication)5 of 57Higher data rates 1,2Large ADC arraysHigher resolution 1,2ADC64xADC16xRFISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC

303、 Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceDigital design benefits from Moores law(scaling):Integration density,power efficiencyAnalog design is not necessarily improving much:Physical limitations(matching,SNR,VDD/Vth-ratio,ft&fmaxlimitations)Design rules becoming

304、 more restricted/complicated(FinFET,double patterning,)Logical choice to push things towards the digital domainBut technology scaling is slowing down“digital”is still“not for free”Technology Scaling6 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE Internationa

305、l Solid-State Circuits ConferenceDigital(Koomeys law 5)Efficiency doublesEvery 1.57 years(year 2000)ADC(estimated from data 6)Efficiency improves for allclasses of ADCs(regardless ofarchitecture,resolution,frequency)Conclusions:ADC Schreier FoM(FOMS)followsdigital Koomeys law quite well(!)ADC design

306、 keeps up with tech scaling,so digital costs remain relevant(not for free)Digital Scaling vs ADC Scaling(Efficiency)7 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceBackground&MotivationGeneral trade-offsBasic prin

307、ciplesDesign examplesCalibration and enhancement techniquesDigitally-inspired analog designOutlookConclusionsOutline8 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceAnalog design tends to scaleexponentially(2N,4N),

308、due to noise,mismatch,or number of componentsDigital design tends to scalelinearly/quadratically(N,N2)(dependent on implemented function)General trend:Digital enhancement is favorable at higher NFor low N,it is costly Optimize efficiency or minimize use of digital techniquesCrossing point depends on

309、 function,implementation,technology,etc.Analog vs Digital(as Function of Resolution)9 of 57AnalogDigitalISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceGeneral trend:Digital enhancement beneficial whenPushing analog spee

310、d limitationsAddressing shortcoming of inherently fast,efficient,but inaccurate circuitsAnalog vs Digital(as Function of Speed)10 of 57Sampling rateEnergy/sampleRegular ADCInterleaving+Calibration overheadSpeed benefitTime-interleaved ADCSampling rateEnergy/sampleClosed-loop amplifierCalibration to

311、deal with inaccuracyEfficiency and speed benefitOpen-loop amplifierTime-interleaving:Efficient at high speed,but(often)requires calibrationOpen-loop amplification:Efficient and fast,but(often)requires calibrationISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE Inter

312、national Solid-State Circuits ConferenceGeneral trend:Digital enhancement might become attractive at lower resolutions(weak trend)Application bandwidth demand increases much more rapidly than technology speed(ft,fmax)Digital enhancement becomes more essentialAnalog vs Digital(as Function of Technolo

313、gy)11 of 57ResolutionBandwidthApplication demand 1,2ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceDigital Enhancement Techniques in Practice12 of 57Sampling rateResolutionSAR ADCPipelined ADCTime-Interleaved ADCMismatc

314、h and noiseMismatch and noiseSettlingOffset,gain,distortion,mismatch,settlingChannel mismatch(gain,offset,time-skew,bandwidth)ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceBackground&MotivationGeneral trade-offsBasic p

315、rinciplesDesign examplesCalibration and enhancement techniquesDigitally-inspired analog designOutlookConclusionsOutline13 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceADC Error Types Examples14 of 57SystematicLin

316、earNon-linearAmplitude errorsOffsets,Gain errorsMismatch,Amplifier compression,Switch non-linearityTime-domain errorsSettling,Time-skewFrequency-dependent errorsFinite bandwidth,Bandwidth mismatchesTime-variant errorsDrift,Ageing,Voltage&Temperature variationsRandomQuantization noise,Thermal noise,1

317、/f noise,Clock jitterSystematic errors can be measured and then predictedRandom errors cannot be predicted(except for the statistics of the error)Note:Correlated random errors can be(partially)predicted(e.g.1/f noise)ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE

318、International Solid-State Circuits ConferenceEnhancement:Any technique that reduces the impact of a certain errorCalibration:Detect(measure)certain errors and(partially)correct themRelies on obtaining knowledge of the error sourceEnhancement techniques can deal with random&systematic errorsCalibrati

319、on can only deal with systematic or correlated errorsEnhancement vs Calibration15 of 57EnhancementChopping(offset,1/f noise)Dynamic Element Matching(mismatch)Calibration techniquesCalibration(sub-class of Enhancement)Offset calibrationMismatch calibrationISSCC 2024-Forum 3.4:Digital and Mixed-Signal

320、 ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceCalibration Foreground Detection16 of 57Example:Short input,measure offset at outputADC0Foreground CalibrationCan track time-variant errors only if operation interrupted regularlyDedicated(sometimes accurate)test sign

321、al needed+Detection tends to be fast and relatively straight-forwardForeground:Interrupt ADC operation for detectionTest signal can be applied at the input;internal ADC nodes can be controlledMeasurements are relatively directCan be performed once at start-up or at(ir)regular intervalsISSCC 2024-For

322、um 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceCalibration Background Detection(1/2)17 of 57ADCADCExample 1:Extract offset assuming signal is offset-freeExample 2:Inject PRN signal,extract info at output with correlation 7Background:

323、Detection during normal ADC operationMeasurements need to be separated from signal componentExample 1:Rely on signal assumptionsExample 2:Inject(pseudo-random noise)test signal and extract response at the outputExample 3:Split-ADC to get enough information for separationPRNISSCC 2024-Forum 3.4:Digit

324、al and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceCalibration Background Detection(2/2)18 of 57Background Calibration+Can track time-variant errors1)Input signal constraints,2)Signal injection,3)More H/WTends to have longer detection time and highe

325、r complexity for detectionContinuously active and consuming power,but can be duty-cycledExample 3:Split-ADC 8-One ADC is split in two halves(power&area neutral)-indicates the relative error between the ADCs-Together with decision path modulation,both errors can be tuned to zeroADC“A”DA+ADC“B”DB+Vin+

326、ADC output:D=(DA+DB)Difference:=DBDAError estimationISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceCalibration Correction19 of 57Post-Processing(Feed-Forward)Compensate afterwardsFeedbackCorrect error at(or near)the sou

327、rcePost-ProcessingFeedbackDigital correctionMixed-signal correction(trim)Digital function operates at fs PowerTrim setting is(semi-)static EfficientError polarity and magnitude need to be detected preciselyDetecting error polarity is sufficient;feedback can tune error magnitude to zeroLimited by cor

328、rection resolutionLimited by trimming resolutionFlexible,scalable,re-usableManual analog designADCTune offset to zeroDet.ADCCor.Det.Compensate offsetISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceBackground&MotivationGe

329、neral trade-offsBasic principlesDesign examplesCalibration and enhancement techniquesDigitally-inspired analog designOutlookConclusionsOutline20 of 57ISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceBasic architecture and

330、 successive approximationKey challenges:Switched-capacitor&comparator noiseCapacitor mismatch(non-linearity)Switch non-linearitySettling time(of VREFand Vres)Nyquist SAR ADC21 of 57VinLogicDoutSwitch controlVresVres0timeVREFISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enhancement Techniques 202

331、4 IEEE International Solid-State Circuits ConferenceSystem-level chopping to mitigate ADC offset,1/f noise,even-order distortionNegligible power and area overheadChopping 922 of 57fsWithout choppingfsWith choppingDistortionOffset&1/f noiseAt fs/2SignalISSCC 2024-Forum 3.4:Digital and Mixed-Signal AD

332、C Enhancement Techniques 2024 IEEE International Solid-State Circuits ConferenceMultiple comparator decisions can average out noise(efficiency neutral)If applied for critical decisions only Efficiency improvementMajority Voting 923 of 57MV LogicVresVres0Noise criticalNot noise criticalFor every step

333、 of the SAR conversion:Step 1:Detect if Vresis small or large by observing comparator decision time to determine if voting is useful or notStep 2:If noise-critical,repeat decisions and vote to average out noiseSelf-clocking used to have flexible number of clock cycles per SAR stepBreaks trade-off of 4x power for+6dB SNR at the cost of more timeISSCC 2024-Forum 3.4:Digital and Mixed-Signal ADC Enha