T3 - Fundamentals of Circuit Designs for 2.5D_3D Integration.pdf

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1、SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceISSCC 2024 TutorialsFundamentals of Circuit Designfor 2.5D/3D IntegrationKenny Cheng-Hsiang HsiehTSMC,Hsinchu,TaiwanFeb 18,2024ISSCC Tutorial1Kenny HsiehSpeakerVideoSecurity C-TSMC Secret 2024 IEEE Internationa

2、l Solid-State Circuits ConferenceSelf Introduction Kenny C.H.Hsieh Director in Design Technology Platform of TSMC Leads a division for Analog/Mixed-signal/RF designs30 years in the semiconductor industry,all in circuit designs Interests in high-speed IO mixed-signal circuits Equalization theory in d

3、igital communication2.5D/3D high-performance chipletsDesign/Technology co-optimization of advanced CMOS technologies.Kenny Hsieh2ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceMotivation to Go ChipletsClassic Problems in ComputingKenny Hsieh3I

4、SSCC Tutorial DraftSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceVertical IntegrationVertical integration getting everything under the same hoodNear memory computing data localization for low power&low latencyUltra dense vertical connectivity high bandwidt

5、hKenny Hsieh4ISSCC Tutorial DraftSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceOutline Background of 2.5D/3DIC Die to Die Interconnection Design Chiplet Architecture Complexity Drives For Advanced Solutions Future Trend Prediction ConclusionsKenny Hsieh5IS

6、SCC Tutorial DraftSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceDevice EvolutionKenny Hsieh6ISSCC Tutorial DraftSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceContinued Technology InnovationKenny Hsieh7ISSCC Tutor

7、ial DraftSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceTSMC 3DFabricTMIntegrationKenny Hsieh8ISSCC TutorialIntegration Interconnect DensityTimeCoWoS-SInFO_PoPInFO_3DSoIC+CoWoSInFO_oSSoICInFO-3D2D Packaging2.5D Packaging3D PackagingInFOCoWoSSoIC+InFO_oSCoWo

8、S-RCoWoS-LLSIInFO_LSICoWoS:Chip-on-Wafer-on-SubstrateInFO:Integrated Fan-OutSoIC:System-on-Integrated-ChipsSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceCross-Chip Interconnects EfficiencyKenny Hsieh9ISSCC TutorialCu-VIASolder bumpSpeakerVideoSecurity C-TS

9、MC Secret 2024 IEEE International Solid-State Circuits Conference3DIC Technology Benefits:PPACT Improved PPACT:Power,Performance,Area,Cost,TTMKenny Hsieh10ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceOutline Background of 2.5D/3DIC Die to Di

10、e Interconnection DesignArchitectureCircuitsJitter AnalysisChannel Optimization Chiplet Architecture Complexity Drives For Advanced Solutions Future Trend Prediction ConclusionsKenny Hsieh11ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceDie to

11、 Die InterconnectKenny Hsieh12ISSCC TutorialKey Performance IndicatorShoreline/Area bandwidth densityEnergy efficiencyLatencySpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceSerial vs.Parallel InterfacesSignificant advances in and research/publications on ser

12、ial interfaces over the last 20 yearsDifferential,CDR,equalizedParallel interfaces are very attractive for D2D due to lower power,lower latency,and(with advanced packaging)higher bandwidth densitySingle-ended,forwarded clock,unequalizedKenny Hsieh13ISSCC TutorialSource:Elad Alon 2023 ISSCC F1.2Speak

13、erVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceHigh-Level PHY ArchitectureSingle-ended parallel data bus with differential forwarded clockChannel,RX Clock tree,Tx Clock tree matched to minimize skewP2S and S2P to maximize the data bandwidth per micro-bumpKenny H

14、sieh14ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Conference2.5D Horizontal D2D InterconnectForwarded Clock for skew/jitter cancellationLane redundancy for defect repairMax Clock sharing to improve energy efficiencyAggregate Bandwidth:1280Gbps per ch

15、annel(160 lanes*8Gbps)Kenny Hsieh15ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Conference3D Vertical D2D InterconnectSimilar architecture as 2.5D designMore sharing of common blocksAggregate bandwidth:1280Gb/s per channel(80 lanes*16Gbps)Kenny Hsieh1

16、6ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Conference3D Die-to-Die Routing ConsiderationsLoading from horizontal interconnect is replaced with cascaded TSV in multi-dies stackingAcross-chiplet LVS verification is another challengeKenny Hsieh17ISSCC

17、 TutorialTSVDie-1Die-2Die-3Die-4AASpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Conference3D Die to Die InterconnectBetter bandwidth and energy efficiency at smaller bump pitchKenny Hsieh18ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Soli

18、d-State Circuits ConferenceTransmitter Front-End:Low Swing IOSource end termination,no termination necessary at Rx end given the short distanceLow voltage swing to reduce power and cross-talkVDDQ from external on board regulatorKenny Hsieh19ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE

19、International Solid-State Circuits ConferenceTransmitter Front-End:Terminated IOSST provide good linearity and feasible tuning MOS for driving capabilityGood impedance matching and signal integrity for 2mm interconnectsWatch out that fraction of resistance due to linear resistance is large enough to

20、 guarantee dynamic performance(in addition to static)Kenny Hsieh20ISSCC TutorialSource:Elad Alon 2023 ISSCC F1.2SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceReceiver CircuitSensing Amplifier based data sampler for data capture7bit binary weighted current

21、DAC for eye margining in post-si testNo offset calibration for Rx circuitsKenny Hsieh21ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceChiplet-to-Chiplet Clock Schemes Two Primaries Clock sources from both sides(symmetric)Same crystal oscillato

22、r(No PPM difference)Kenny Hsieh22ISSCC TutorialPLLPLL*P.Vivet et al.,CEA-LETI-MINATEC 2SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceChiplet-to-Chiplet Clock Schemes Primary/SecondaryDRAM die uses clock from SoC dieKenny Hsieh23ISSCC TutorialPLLCluster Clo

23、ck:many copiesSystem Clock:one copyPhaseAdjustment*C.-K.Lee et al.,Samsung 4SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceInter-Chiplet Interconnect(LIPINCON)Solution to cross-die timing variationDLL-Deskew:align clock phase between SoC and PHYDLL-R90:ensu

24、re 8Gb/s center-capture by calibrating the cross-die PVT variationKenny Hsieh24ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceWhat Are Inside the Boxes Dedicated PLL Kenny Hsieh25ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE Inter

25、national Solid-State Circuits ConferenceWhat Are Inside the Boxes Dedicated PLL De-skew DLLsTo align between SoC and PHY-TXSetup/Hold time auto-centering at cross die interfaceRX FIFOTo tolerate phase drift from clock-trees power supply noises and temperature variationKenny Hsieh26ISSCC TutorialVDDQ

26、=0.3VAC-coupleDLL(R90)(20+2)RXFIFO(20+2)ADPLLSub-Channel3:0DLL(Deskew)PDAC-coupleSOCs CLKTX_DQ19:0TX_DBITX_VLDVDDQ=0.3VRX_DQ19:0RX_DBIRX_VLDTX_DQS_t/cRX_DQS_t/cChannel(Master)Channel(Slave)CPUL3IOIOIOIOESD(CDM)SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Conference

27、De-Skew Circuit(DLL and PI)Two-step DLL 1st loop:lock clock period and divide into 8-phases2nd loop:interpolate 16 sub-phasesRequire only one clock phaseEasy scaling&with wide coverage rangeKenny Hsieh27ISSCC TutorialPD1FOUT360FOUT90PD2FIN28FOUTFBKFREFS2D0 180 45 225 90 270 135 315 360 180 PI15:00 4

28、5 90 135 180 225 270 315 VSSVDD.IN1IN2VSSVDD.OUTDCDL2ndLoop1stLoop2psSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceClock Generation Analog PLL with IDAC based digital band control to reduce Kvcc and supply noise sensitivityKenny Hsieh28ISSCC TutorialSpeake

29、rVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceNon-idealitiesBounded eye margin lossISI Minimize insertion loss.Use thick metal,organic substrate,or TX&RX equalization Xtalk-Reduce through shielding and proper groundingPDN noise-Use robust PDN network with suffic

30、ient decoupling capOffset and skew-managed by device and path matchingUnbounded eye margin lossRandom clock jitterRandom circuit noiseKenny Hsieh29ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceJitter Analysis&Modeling-DLLKenny Hsieh30ISSCC Tu

31、torialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceChannel DTCO with 3D EM SolverKenny Hsieh31ISSCC TutorialDie1Die2SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferencePower Delivery NetworkAccurate PDN modeling becom

32、es increasingly important(IR drop,AC noise,resonance)on advanced nodesPDN extraction:Top-Die(RCX),Interposer(RCX),Substrate(RLGC)Kenny Hsieh32ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceStory of“ESD Inside a Package”No need for HBM protecti

33、on,CDM substantially reducedLess loading from ESD lower area&powerKenny Hsieh33ISSCC TutorialMCMCoWoS/InFOSoICESD CDM Target HighMediumLowESD Capacitance LoadHighMediumLowEfficiencyLowMediumHighSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceRedundancy and R

34、epairTo improve the yield of the stacking samplesLeverage boundary-scan test to identify the bad laneThe more redundant lanesthe higher repairment-ratesthe less interconnect densityKenny Hsieh34ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceVa

35、rious Lane Redundancy SchemesKenny Hsieh35ISSCC Tutorial*I.Lee et al.,Yonsei University,Seoul,South Korea8Switching RepairShifting RepairRing Based Repair2019 New Proposal (Shift and Switching Repair)RTSV STSVSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceB

36、uilt-in Testability in 2.5D/3D Testing FlowsKGD(Known-Good-Die)DFT-DC,DFT-AC,Boundary scan TAP BISTAt-speed loopback BISTLoopback eye scan characterizationKGS(Known-Good-Stack)Interconnect-IO boundary scan for quick defect screen on interconnectCross die at-speed BISTEye scan characterization on int

37、erconnectKenny Hsieh36ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceBump Pitch(40m)Too Small to ProbeEye-Scan is the only way to characterize marginsKenny Hsieh37ISSCC Tutorial*M.-S.Lin et al.,TSMC 20000000000000000000000000000000000000000000

38、000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111000000000000000000000000000000000000000001111111111111111111111110000000000000000000000000000000000000001111111111111111111111111100000000000000000000000000000000000000111111

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40、000000000011111111111111111111111111111111111110000000000000000000000000111111111111111111111111111111111111111100000000000000000000000011111111111111111111111111111111111111110000000000000000000000011111111111111111111111111111111111111111100000000000000000000000111111111111111111111111111111111111

41、111110000000000000000000000111111111111111111111111111111111111111111110000000000000000000011111111111111111111111111111111111111111110000000000000000000101111111111111111111111111111111111111111111100000000000000000011111111111111111111111111111111111111111111110000000000000000000111111111111111111

42、111111111111111111111111110000000000000000000000111111111111111111111111111111111111111110000000000000000000000111111111111111111111111111111111111111111000000000000000000000001111111111111111111111111111111111111111100000000000000000000000001111111111111111111111111111111111111110000000000000000000

43、000000011111111111111111111111111111111111110000000000000000000000000000111111111111111111111111111111111110000000000000000000000000000000111111111111111111111111111111111000000000000000000000000000000000011111111111111111111101111110000000000000000000000000000000000000000000000000000000000000000000

44、0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000Eye Width:0.69UI(86ps)Eye Height:244mV0.3V0VVREF Code(9.4mV step)DCDL Code(2ps step)DQDQSIODe-s

45、kewPLL/DLLCKCKCKVSSVREFINVDDVSSSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceOutline Background of 2.5D/3DIC Die to Die Interconnection Design Chiplet Architecture Complexity Drives For Advanced Solutions Future Trends ConclusionsKenny Hsieh38ISSCC Tutoria

46、lSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceAbundant Architectures of 3DICsKenny Hsieh39ISSCC TutorialCoWoS-SCoWoS-LCoWoS-RInFO-2DTSMC-SoICCoWInFO-3DTSMC-SoICWoWTSMC 3DFabricTMInFO-PoPSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-Stat

47、e Circuits ConferenceAbundant Architectures of 3DICsKenny Hsieh40ISSCC TutorialCoWoS-SCoWoS-LCoWoS-RInFO-2DTSMC-SoICCoWInFO-3DTSMC-SoICWoWTSMC 3DFabricTMInFO-PoP1-Die2-Die3-DieActive DiesHorizontal 2.5D ConnectionPassive DiesVertical 3D ConnectionInterfacesSpeakerVideoSecurity C-TSMC Secret 2024 IEE

48、E International Solid-State Circuits ConferenceAbundant Architectures of 3DICsKenny Hsieh41ISSCC TutorialCoWoS-SCoWoS-LCoWoS-RInFO-2DTSMC-SoICCoWInFO-3DTSMC-SoICWoWTSMC 3DFabricTMInFO-PoP1-Die2-Die3-DieActive DiesHorizontal 2.5D ConnectionPassive DiesVertical 3D ConnectionInterfacesDesign Complexity

49、 Is On The Rise!SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceCurrent 3DIC Design RepresentationsKenny Hsieh42ISSCC TutorialPVPDNPDN/ThermalAPRAPRRCXFormatPhysical-basedConnection-based3D locationsVXLogical connectionXVVendor AVendor BVendor CVendor DSpeak

50、erVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceCurrent 3DIC Design RepresentationsKenny Hsieh43ISSCC TutorialPVPDNPDN/ThermalAPRAPRRCXFormatPhysical-basedConnection-based3D locationsVXLogical connectionXVA Fragmented Design Ecosystem!Vendor AVendor BVendor CVend

51、or DSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceMission StatementsFind a way to modularize design and EDA tools to make 3DIC design flow simpler and efficientEnsure standardized EDA tools and design flows compliant to TSMC 3DFabricTM technologyKenny Hsie

52、h44ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceMission StatementsFind a way to modularize design and EDA tools to make 3DIC design flow simpler and efficientEnsure standardized EDA tools and design flows compliant to TSMC 3DFabricTM technol

53、ogyKenny Hsieh45ISSCC Tutorial3DbloxTMStandardfrom TSMC&our OIP PartnersSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceEco-system to Support 3DICKenny Hsieh46ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Confe

54、renceTackle Complexity by UnificationKenny Hsieh47ISSCC TutorialInter-operability3DbloxTM StandardTop-Down Design MethodologyChiplet ReuseModularizationFormatPhysical-basedConnection-basedTSMC3DbloxTM3D locationsVXVLogical ConnectionXVVAssertionsXXVHierarchicalXXVto work togetherSpeakerVideoSecurity

55、 C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceTackle Complexity by UnificationKenny Hsieh48ISSCC TutorialInter-operability3DbloxTM StandardTop-Down Design MethodologyChiplet ReuseModularizationFormatPhysical-basedConnection-basedTSMC3DbloxTM3D locationsVXVLogical ConnectionXV

56、VAssertionsXXVHierarchicalXXVto work togetherSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceTSMC 3DbloxTM ModularizationKenny Hsieh49ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceTSMC 3DbloxTM Standa

57、rdGeneric 3DbloxTM language constructs aim for all current and future 3DFabricTM offeringsKenny Hsieh50ISSCC TutorialTSMC 3DbloxTMComponentsDie InterfaceRDL InterfaceBridge InterfaceTSMC 3DbloxTMLanguage ConstructsChiplet:Conn:Physical ConstructsConnection ConstructsList of physical Chiplet ChipletT

58、SMC 3DbloxTMFull Stack RepresentationsFull Stack-ConnectionConn1:Path1:Path AssertionsFull Stack-PhysicalFull Stack-ConnectionChiplet 2Chiplet 3Chiplet 1Chiplet 2&3Chiplet 1&3Chiplet 1 Chiplet 2Conn2:SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceTSMC 3Dblo

59、xTM StandardGeneric 3DbloxTM language constructs aim for all current and future 3DFabricTM offeringsKenny Hsieh51ISSCC TutorialTSMC 3DbloxTMComponentsDie InterfaceRDL InterfaceBridge InterfaceTSMC 3DbloxTMLanguage ConstructsChiplet:Conn:Physical ConstructsConnection ConstructsList of physical Chiple

60、t ChipletTSMC 3DbloxTMFull Stack RepresentationsFull Stack-ConnectionConn1:Path1:Path AssertionsFull Stack-PhysicalFull Stack-ConnectionChiplet 2Chiplet 3Chiplet 1Chiplet 2&3Chiplet 1&3Chiplet 1 Chiplet 2Conn2:SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Conference

61、CoWoS-S Step-by-Step with 3DbloxTMKenny HsiehISSCC TutorialChipletDefinition3DbloxTMDefinitions SOC3DbloxTMDefinition HBM3DbloxTMDefinitionRDLSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceCoWoS-S Step-by-Step with 3DbloxTMKenny Hsieh53ISSCC TutorialChiplet

62、DefinitionChiplet Instantiation3DbloxTMDefinitions SOC3DbloxTMDefinition HBM3DbloxTMDefinitionRDLInstancesABCDSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceCoWoS-S Step-by-Step with 3DbloxTMKenny Hsieh54ISSCC TutorialChipletDefinitionChiplet InstantiationC

63、onnectivity DeclarationRDL1r1r3r5r2r4r63DbloxTMDefinitions SOC3DbloxTMDefinition HBM3DbloxTMDefinitionRDLInstancesABCDConn1Conn2Conn3r3r4r5r6r1r2SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceCoWoS-S Step-by-Step with 3DbloxTMKenny Hsieh55ISSCC TutorialChip

64、letDefinitionChiplet InstantiationConnectivity DeclarationPathAssertionRDL1r1r3r5r2r4r6ABCr1r3r5r2r4r63DbloxTMDefinitions SOC3DbloxTMDefinition HBM3DbloxTMDefinitionRDLInstancesABCDConn1Conn2Conn3r3r4r5r6r1r2Path1r1r2SpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Con

65、ferenceSoIC Multi-Die Static Timing AnalysisKenny Hsieh56ISSCC Tutorial36366 x 2 TimesSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceHierarchical Thermal AnalysisFast coarse-grained analysis to identify hotspotsAccurate fine-grained analysis on targeted hot

66、spots10X EDA runtime reduction and within 2%golden simulation accuracyKenny Hsieh57ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceOutline Background of 2.5D/3DIC Die to Die Interconnection Design Chiplet Architecture Complexity Drives For Adva

67、nced Solutions Future Trends ConclusionsKenny Hsieh58ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceParallel D2D Interface StandardsKenny Hsieh59ISSCC TutorialSource:Elad Alon 2023 ISSCC F1.2SpeakerVideoSecurity C-TSMC Secret 2024 IEEE Interna

68、tional Solid-State Circuits ConferenceCo-Packaged Optic3D stacking eliminates power overhead of SerDes driving electrical channelFrom 2.5D to 3D CPO,energy efficiency is improved from 15pJ/bit to below 5pJ/bitKenny Hsieh60ISSCC TutorialCoWoSSource:Cyriel M,IET Optoelectronics 2021CPU with 3D CPOSpea

69、kerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceConclusionsWhile improvements in monolithic processes continue generation over generation,these alone are not going to satisfy demands on transistor-count per package in the AI eraReaching trillions of MOSs in a pa

70、ckage in 2030sChiplet integration in 2.5 or 3D becomes a mustDesigns with chiplets require designers to get familiar withAdvanced package options:what bump-pitch,TSV pitch,are right for me?Parallel interfaces as chiplet Phy:how to manage lane-to-lane skew?Minimizing power,area.Dealing with testabili

71、ty,redundancy,and thermalNew CAD tools and flows.3DBlox language,for exampleEmerging chiplet connectivity standards,UCIe and others,will be everywhere soonKenny Hsieh61ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceConclusionsWhile improvement

72、s in monolithic processes continue generation over generation,these alone are not going to satisfy demands on transistor-count per package in the AI eraReaching trillions of MOSs in a package in 2030sChiplet integration in 2.5 or 3D becomes a mustDesigns with chiplets require designers to get famili

73、ar withAdvanced package options:what bump-pitch,TSV pitch,are right for me?Parallel interfaces as chiplet Phy:how to manage lane-to-lane skew?Minimizing power,area.Dealing with testability,redundancy,and thermalNew CAD tools and flows.3DBlox language,for exampleEmerging chiplet connectivity standard

74、s,UCIe and others,will be everywhere soonKenny Hsieh62ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferencePaper to See at ISSCC 2024A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFETA 2.16pJ/b 112Gb/s

75、 PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOSA 464Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical TransmitterA 224Gb/s 3pJ/bit 35dB Insertion Loss Transceiver in 3-nm FinFET CMOSKenny Hsieh63ISSCC Tutoria

76、lSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceReferencesShenggao Li et al.,“Advanced Package and 3D-IC Interconnections”,in IEEE ISSCC,San Francisco,CA,Feb.2023Shenggao Li et al.,“Interconnect in the Era of 3DIC”,in IEEE CICC,April 2022S.Naffziger et al.,

77、“AMD Chiplet Architecture for High-Performance Server and Desktop Products,”in IEEE ISSCC,San Francisco,CA,Feb.2020M.-S.Lin et al.,“A 7nm 4GHz Arm-core-based CoWoS Chiplet Design for High Performance Computing,”in IEEE Symp.VLSI Technology,Tokyo,Japan,Jun.2019M.-S.Lin et al.,“A 16nm 256-bit Wide 89.

78、6GByte/s Total Bandwidth In-Package Interconnect with 0.3V Swing and 0.062pJ/bit Power in InFO Package,”in HotChips,Stanford,CA,Aug.2016R.Venkatesan et al.,“A 0.11 PJ/OP,0.32-128 Tops,Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology,

79、”in HotChips,Stanford,CA,Aug.2019I.Lee et al.,“Highly Reliable Redundant TSV Architecture for Clustered Faults,”in IEEE TRANSACTIONS ON RELIABILITY,Mar.2019S.Khushu et al.,“Lakefield:Hybrid cores in 3D Package,”in HotChips,Stanford,CA,Aug.2019M.-S.Lin et al.,“An extra low-power 1Tbit/s bandwidth PLL

80、/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application,”in IEEE Symp.VLSI Technology,Tokyo,Japan,Jun.2013Universal Chiplet Interconnect Express(UCIe)Specification Rev 1.0,2022Kenny Hsieh64ISSCC TutorialSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits Co

81、nferenceAcknowledgmentsKenny Hsieh65ISSCC Tutorial Victor Li Wei-Chih Chen Mu-Shan Lin Chien-Chun Tsai Wen-Hung Huang Yu-Chi Chen Shu-Chun Yang Kevin Wu Jerry Tzou Jim Chang Stefan Rusu Frank LeeSpeakerVideoSecurity C-TSMC Secret 2024 IEEE International Solid-State Circuits ConferenceKenny Hsieh66ISSCC Tutorial DraftPlease Scan to Rate Please Scan to Rate This PaperThis Paper