T2 - Fundamentals of Digital and Digitally-Assisted Linear Voltage Regulators.pdf

《T2 - Fundamentals of Digital and Digitally-Assisted Linear Voltage Regulators.pdf》由會員分享，可在線閱讀，更多相關《T2 - Fundamentals of Digital and Digitally-Assisted Linear Voltage Regulators.pdf（66頁珍藏版）》請在三個皮匠報告上搜索。

1、SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsArijit RaychowdhurySchool of Electrical and Computer EngineeringGeorgia Institute of Technologyarijit.raychowdhuryece.gatech.eduArijit Raychowdhury1 of 60Fundam

2、entals of Digital and Digitally-Assisted Linear Voltage RegulatorsSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsOutline Motivation Discrete Time All-Digital LDOs Q&A Switched Mode Control

3、 Continuous Time LDOs with Digital Gates Unified Voltage and Frequency Regulation Conclusions2 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsOutline Motivation Discrete Time All-Digi

4、tal LDOs Q&A Switched Mode Control Continuous Time LDOs with Digital Gates Unified Voltage and Frequency Regulation Conclusions3 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsFine-Gr

5、ain Power ManagementFine-Grain Power Management High Energy-EfficiencyDifferent cores/functional units can be at different operating points at the same timeThe cache may require higher VCCthan logicIdentical functional units may require different VCCs to perform the same task at the same frequency4

6、of 60Course-grain power managementFine-grain power managementSpace/TimeSpace/TimeEnergyEnergySpeakerVideo 2024 IEEE International Solid-State Circuits ConferencePower Management Challenges in Digital Load Circuits#1Transient Management under Wide Dynamic RangeArijit RaychowdhuryFundamentals of Digit

7、al and Digitally-Assisted Linear Voltage Regulators5 of 60TemperatureAgingPower Delivery NetworkDVFSVariable Workloads0.920.940.960.9810.0%1.0%2.0%3.0%4.0%5.0%6.0%0123P-N SkewFmax DegradationStress Time(Hrs)SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceEfficient Power Delivery

8、at Near Threshold VoltageArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators6 of 60Power Management Challenges in Digital Load Circuits#2SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceVoltage Guard-band ManagementArijit RaychowdhuryFundame

9、ntals of Digital and Digitally-Assisted Linear Voltage Regulators7 of 60Power Management Challenges in Digital Load Circuits#3SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLinear and Low Dropout RegulatorsAnalog PMOS based LDOThe important poles are internal(PINT)and output(POU

10、T)Power MOS+-VREFVOUTR1R2PINTPOUTArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators8 of 60 High efficiency Package integration Continuous Vout Large domains Fast responseLC-VR High efficiency Discrete Vout Medium response Low energy densitySC-VR Lower efficie

11、ncy Die integration Finest domains Fastest responseLinear RegulatorSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceAll-Digital Discrete-Time LDOAll-Digital LDOMostly synchronous;Continuous time systems are also possibleSingle stage comparatorControl Logic can implement PI control

12、ControlLogicComparator+-PMOS ArrayLoad CircuitVREFVINVOUTArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators9 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLDO Regulators:Analog vs DigitalAnalog LDO RegulatorDigital LDO Regulator+Hig

13、h bandwidth+Excellent small signal performance+High power supply rejection(PSR)+No Noticeable Ripple-Limited by slew rate of the power PMOS-Narrow operating rangeIdeal for supply sensitive analog load+No analog Components with synthesizable control+Decouples loop gain from operating voltage+Large op

14、erating range(both supply voltage and load current)-Output ripple-Low PSR,Low BandwidthIdeal for digital load supporting DVFSArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators10 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit R

15、aychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsOutline Motivation Discrete Time All-Digital LDOs Q&A Switched Mode Control Continuous Time LDOs with Digital Gates Unified Voltage and Frequency Regulation Conclusions11 of 60SpeakerVideo 2024 IEEE International Soli

16、d-State Circuits ConferenceA Brief History of Digital LDOsMitsubishi Electric Corp.,JSSC,1996 First industry design using digital LDO in parallel with an analog LDO for embedded DRAM Fast transient response Low current dissipation Limited flexibility for multiple voltage levels Large power transisto

17、r overheadArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators12 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOs1172IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.44,NO.4,APRIL 2009Fig.5.Local pausable clock ge

18、nerator.using a mutual-exclusion element which causes the clock to bemomentarily paused.Once the request is released,the clockcan restart again.If no asynchronous request is received,theclock(half-)period is determined by the value programmedin the delay line.The generated clock is then applied to t

19、hesynchronous unit through a classical clock-tree.The main difficulty is to obtain a precise,small and low-power delay line,while using if possible only standard-cellsso that it can be placed-and-routed as a hard-macro and thenreused for various units.The delay line is composed of delay el-ements bu

20、ilt with either available delay-cells or inverter-cells(according to the required delays),and of latches and multi-plexers.The latches offer a good compromise in terms of delayand energy in the targeted technology(STMicroelectronics 65nm),while filtering out all unnecessary pulses within the delayli

21、ne.Only one path through the delay line is activated accordingto the programmed binary value.C.Power Supply UnitThe power supply unit(PSU)manages the unit supplyvoltageaccording to the selected power modes usingsupply voltages provided by off-chip DC-DC converters.Thepower supply unit(Fig.6)is compo

22、sed of three main devices:the power switches(andpower transistors),theUltra Cut-Off voltage generator(UCO),and the-Hoppingunit.The UCO is used during OFF mode to reduce theunit leakage current.The-Hopping unit ensures smoothtransitions betweenandwithout stopping the unitclock and computations.In the

23、 case of FHT2 unit,the PSU isreplaced by a fully integrated buck-boost DC-DC converter.1)Dynamic Power Control:To do fine-grain voltage scalingand reduce dynamic power consumption of SoC and MPSoCcontaining more than ten functional cores,traditional DC-DCconverters have reached their limit.The simpl

24、est ones are linearconverters,small and easily integrated,but their efficiency islowered at low output voltage.More efficient converters likecapacitive or inductive ones are widely used in the industry,butthey are using capacitors and inductors that cannot be easilyintegrated.A fully integrated indu

25、ctive buck-boost DC-DCconverter has been implemented to compare on-chip a classicalLocal Dynamic Voltage and Frequency Scaling(LDVFS)approach with an innovative Local Adaptive Voltage and Fre-quency Scaling approach using a hopping technique.a)Integrated Buck-Boost DC-DC Converter:A microp-ower up-a

26、nd-down converter switching power supply is used toFig.6.Power supply unit.convert the available power from a battery into a regulated andcontrollable powersupply.Tendiscrete set pointvalues between0.6 V and 1.2 V are available for the power supply voltage toachieve dynamic voltage scaling on the su

27、pplied FHT2 digitalblock.The input power is processed by power switches and an L-Cpower filter,yielding the conditioned output power.The pas-sive devices values are chosen to be compatible with above-ICtechnologies to avoid any external devices:consequently,theinductor and capacitor values are drast

28、ically constrained.Thesystem controls the switch duty cycle so that the output voltagefollows a given reference.Therefore,the difference betweenone part of the power filter output voltageand avoltage setpoint is amplified and modulated into pulse densityinformation.The obtained clock is used to a ga

29、te a drive cir-cuit(non-overlapping clocks generator and buffer)controllingthe power filter MOS switches.The innovative pulse densitymodulation(PDM)is based on an asynchronous passivemodulator instead of the traditional PWM controller for sim-plicity of implementation(two RC filters,a comparator and

30、 twoinverters),low power consumption and spectral spread of theswitch noise.CEA-LETI,JSSC,2009 Digital controlled loop for supply hopping in NoC processor Fast supply voltage switching Integration with IP Core Not a voltage regulatorArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted L

31、inear Voltage Regulators13 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOsU.Of Tokyo,CICC 2010 First stand-alone discrete-time digital LDO proof of concept All-digital clocked design High current efficiency Integration with Error Detection Lim

32、ited operational range Stability/control not exploredArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators14 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOsNCT Univ./RealTek Taiwan,VLSIC 2012 Clock-less co

33、ntinuous-time digital LDO controller Saves clock distribution overhead Digital LDO used in parallel with a switching converter Limited transient performanceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators15 of 60SpeakerVideo 2024 IEEE International Solid-St

34、ate Circuits ConferenceA Brief History of Digital LDOsGaTech/Intel,VLSIC 2012,JSSC 2014 Continuous-time phase-locked LDO Small signal gain through phase-locked control No output ripple Limited voltage scalability Analog Control and larger controller currentArijit RaychowdhuryFundamentals of Digital

35、and Digitally-Assisted Linear Voltage Regulators16 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOsIBM,JSSC 2012 Dual loop distributed voltage regulator on Power Processor Line Outer loop based on digital calibration Internal loop based on cont

36、inuous time micro-regulator Low Current Efficiency866IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.47,NO.4,APRIL 2012Fig.5.Distributed regulator with multiple comparator-based UREGs sup-plying current to common power parators are also connected locally,so the UREGs respondto the regulated output voltage

37、in their vicinity of the grid.Adistributed regulator system offers a few key benefits.If theUREGs are placed close to the various load circuits that theypower,relatively little current needs to be redistributed throughthe grid,and the associated IR drops can be minimized.As anexample,in the DDR3 I/O

38、 application,simulations with an ex-tracted RC model of the Vout power grid show that if a single(centrally located)regulator were employed,the errors due toIR drops could be as high as 22 mV under maximum load con-ditions,whereas such errors are reduced to only 2.4 mV withthe distributed system dev

39、eloped in this work.Another advan-tage of distributed regulation is that the power dissipated in thepassgatesismoreevenlyspreadacrossthechip15;thisadvan-tage becomes especially valuable if the distributed regulator isscaled up to handle a much larger load current(e.g.,1 A)thanthat of the present app

40、lication(42 mA maximum).Since boththe sense point and output of each UREG are connected locally,an ultra-fast load response time can be maintained without con-cern for RC wire delay and without the power penalty of dis-tributing a fast passgate control signal over an appreciable dis-tance.As the num

41、ber of UREGs is increased(and their spacingdecreased),the impedance between any spot on the power gridand the nearest actively regulated node drops,so the entire gridbecomes more tightly regulated.On the other hand,due to theoverhead of the high-speed comparators,using many smallerUREGs is less area

42、-and power-efficient than using a few largerUREGs.Adoptingadistributedregulatorarchitectureintroducessomechallenges,the most serious of which is the problem of loadsharing.If,as indicated in Fig.5,the UREGs have differentinput-referred offsets,they will not agree what the regulatedoutput voltage sho

43、uld be.Assuming the error amplifiers havehigh gain,a UREG which desires a higher value of Vout mayturn on its passgate to the maximum capacity,while a UREGwhich desires a lower value of Vout may shut off its passgatecompletely.Thus,the load sharing among UREGs may becomeextremelyimbalanced,andcurren

44、thoggingcan leadtolocalhotspots and electromigration problems.Imbalanced load sharingalso impairs the ability of the distributed regulator to respondto local disturbances,as UREGs which have already turned ontheir passgates fully cannot provide additional current to thegrid when the local regulated

45、voltage drops.Providing an ac-curate reference voltage to each UREG is another challenge.Including a separate reference voltage generator inside eachFig.6.Dual-loop architecture of distributed regulator system.Fig.7.Waveforms illustrating how outer feedback loop adjusts VCP in orderto bring Vout to

46、desired target level.UREG is costly in area,and mismatches between different ref-erence voltages can exacerbate load sharing problems.Trans-mitting a global reference voltage to every UREG is a betteridea,but care must be taken to avoid picking up noise or IRdrops along the distribution wires.An alt

47、ernative to providingan accurate reference voltage to each UREG is to employ thedual-loop architecture described in the next section;this archi-tecture also solves the problem of load sharing.III.DESIGN OFDISTRIBUTEDREGULATORSYSTEMA.Dual-Loop ArchitectureFig.6 presents the dual-loop architecture of

48、the distributedregulator system implemented in this work.Eight comparator-based UREGs supply current to a common power grid for Vout.The UREGs do not receive an accurate DC reference voltage.Instead,the trip point of the comparator inside each UREG istunedwithalocalchargepump(CP).Acentralvoltageregu

49、latorcontroller(VREGC)provides feedback to the charge pumps inthe form of UP/DOWN currents.This outer feedback loop es-tablishes the dc accuracy of the regulator.VREGC comparesVout at a sense point on the power grid to a bandgap reference(BGR)and adjusts the ratio of UP current to DOWN currentso tha

50、t the charge pump voltage(VCP)of each UREG movesin the direction necessary to reduce the DC error.The heart ofVREGC is a high-gain transconductance(Gm)amplifier.A re-sistor digital-to-analog converter(RDAC)placed between theArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Vol

51、tage Regulators17 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOsColumbia U.,JSSC 2017 PI Control Event driven Reduces output ripple High energy efficiency Complex control Limited small signal performanceArijit RaychowdhuryFundamentals of Digi

52、tal and Digitally-Assisted Linear Voltage Regulators18 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOsIntel,ISSCC 2015,JSSC 2016 Discrete-time all-digital LDO Digital LDO is operated at high supply voltages with switched capacitor converter at

53、 lower supply voltage.Fast transient performance Limited small signal performanceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators19 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceA Brief History of Digital LDOsArijit RaychowdhuryUn

54、iv of Washington,ISSCC 2019 Use compute to provide convergence of the loop Takes advantage of process improvement via scaling Excellent convergence time and efficiency Relies on second order dynamics and Model Predictive ControlFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators

55、20 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceAll-Digital Discrete Time LDOs+128VREFVINVREG4:1 Mux4:1 MuxFFCLK()A0-127128 Bit Bidirectional Barrel Shifter with built in Programmable Gain and Fine Grained Clock GatingD128N0-2Q0-2To PadCL=1.0nFScan Programmable Noise Gene

56、ratorScan Programmable LoadHigh Speed Noise GeneratorSyntheticLoad CircuitsBarrel shifters 0:63Power PFETs 0:63Clock Gen.Adaptation LogicComparatorsScan and glue logicIO pads and level shiftersIO pads and level shiftersIO pads and level shiftersBarrel shifters 64:127Power PFETs 64:127ProcessIBM 130n

57、m CMOS 8-MTotal Area2 mm2Active Area0.3552 mm2LDO Area0.114 mm2Testing InterfaceQFN PackagePad Count32IBM 130nm ProcessVIN=1.0V-0.50VVOUT=0.9V-0.45VMax ILOAD=5mA Fully digital and synchronous design with variable gain control through a 128-bit barrel shifter Fine-grained clock gating reduces 30%of c

58、ontroller power Clocked comparator input provides high input gain.ISSCC 2015 TPEL 2016Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators21 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLinearized Control ModelVREF+-ee*z-11Barrel Shi

59、fterDelay between comparator&shifterZero Order Hold1-e-TsssFLOADKDC1+Output Stagee-Ts/2KBARRELOutput Node:VREGArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators22 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceDesign Parameters and S

60、pecificationsArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators23 of 60Silicon areaInput,reference,and output voltage(Vin,Vref,Vout)Edge time(tedge)Voltage droop and overshoot(Vdroop,Vovershoot)Response and settling time(tresponse,tsettle)Load,quiescent,power

61、-FET,and capacitor current(Iload,Iq,Ipwr,Icap)Peak current and power efficiency(CEpeak,PEpeak)Dropout voltage(Vdropout)Power supply rejection ratio(PSRR)Load regulation performance FoMs:ps FoM and pF FoMMaximum and minimum load current(Iload,max,Iload,min)DAC and ADC number of bits(NDAC,NADC)Dead-zo

62、ne voltage(Vdz)DAC step size(VDAC,ss)IR drop voltage(VIR)Adapted from Mingoo Seok,ISSCC2020 SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLight LoadNominal LoadHeavy LoadLoop Response under Varying Load1mA Load Step1mA Load Step1mA Load Step At light load conditions,at iso-FS t

63、he loop becomes underdamped and even oscillatory.The rule of thumb is to change FS with ILOAD(hence,FLOAD).Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators24 of 60Real(z)Imag(z)Real(z)Imag(z)Real(z)Imag(z)Time(a.u.)Voltage(V)Time(a.u.)Voltage(V)Time(a.u.)Vo

64、ltage(V)SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceLimit Cycle Oscillations and Ripple!(a)!(b)!Fig.19:(a)Measured line regulation for the LDO design.(b)Measured regulation against load switching frequency.The steady state ripple of 10mV limits the measurement of line-!(a)!(b

65、)pole filters out the ripple noise and a residual ripple voltage of 10mV is noted at FS100MHz.Origin of Limit Cycle Oscillations Quantization of the control loop at the comparator and at the output plant Relay based control is the key quantizing block in the loopControl Principle and Modeling Descri

66、bing function models the interaction of linear and non-linear components of the control loopKey Results and Observations Increasing sampling frequency increases the mode of oscillation FLOAD/FSneeds to be bounded to limit output rippleArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted

67、 Linear Voltage Regulators25 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTowards Adaptive ControlExternally controlled incubation time.FScan be either FHIGH,FNOMor FLOW.Externally controlled VCOs allow fine-grained selection of FHIGH,FNOMand FLOW.0.4 0.5 0.60.70.80.91.0

68、1.1 1.20.41.20.81.00.60.50.70.91.1VIN 100mVOver-dampedUnder-damped010002000300040005000020406080Quiescent Sampling Freq.,FSMHzSettling Time,TSnsILOAD=4.6mAILOAD=0.8mAILOAD=0.7mAILOAD=0.12mASmall Load Transient VDROOP=50mVIHEAVYINOMILIGHTTS 0.65m ms TS 0.5m ms0.40.50.60.70.80.1110Output Voltage,VREGV

69、Load Current,ILOADmAVREF=0.75VVREF=0.7VVREF=0.6VVREF=0.5VILOADISINGLE LDO PMOSIMAXfor LDO reached50X RangeThis Work456TypeLDOLDOLDOLDOTechnology130 nm65 nm40 nm45 nm SOIControl methodologydigital digitaldigitalmultiloop AnalogAdaptive ControlYesNoNoNoRDSYesNoNoNoVin(V)0.5-1.20.60.51.179-1.625Vout(V)

70、0.45-1.140.40.450.9-1.1Load Current:Imax(mA)4.62000.242Load Regulation(mV/mA)100.050.659.8Controller Current:ICTL(uA)24-22125.12.79450Active Area(mm2)0.1140.03750.0420.075Peak Current Efficiency%98.3099.9998.7077.50Max voltage droop Load Step 40 mV 0.7 mANA40 mV 200uA 7.6 4.5 mAFOM1%90.80%NA55.40%44

71、.90%FOM2(process normalized)ns0.0765NA2700.0624FOM2-Performance Metric-(Transient Time)*ICTL/ImaxFOM1-Efficiency Metric-Average current efficiency across a 50X current dynamic rangeNA-Insufficient data Adaptive control allows scaling of the controller power with ILOADwhile maintaining output ripple

72、and damping factor.Over 80%current efficiency across a 50X load range.Measured 4X improvement in light load current efficiency.Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators27 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceEnhanc

73、ing Transient Performance Higher CLK Frequency&Gain for large load steps enable RDS An externally programmable D(nominally 50mV)and fast,transient clocks(nominally 400MHz)are employed.0.4 0.5 0.60.70.80.91.0 1.1 1.20.41.20.81.00.60.50.70.91.1VIN 100mVOver-dampedUnder-damped01000200030004000500002040

74、6080Quiescent Sampling Freq.,FSMHzSettling Time,TSnsILOAD=4.6mAILOAD=0.8mAILOAD=0.7mAILOAD=0.12mASmall Load Transient VDROOP=50mVIHEAVYINOMILIGHTTS 0.65m ms TS 0.5m msArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators29 of 60SpeakerVideo 2024 IEEE Internation

75、al Solid-State Circuits ConferenceLDOs with Transient Detection Coarse Loop detects large transients and enables fast recovery Fine loop allows regulation with limited rippleArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators30 of 60KAIST/Samsung,ISSCC 2016Spe

76、akerVideo 2024 IEEE International Solid-State Circuits ConferenceLDOs with Transient Detection Detect large transients and switch to wider PMOS transistors Similar in principle to RDSArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators31 of 60Intel,ISSCC 2015Sp

77、eakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators32 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted L

78、inear Voltage RegulatorsOutline Motivation Discrete Time All-Digital LDOs Q&A Switched Mode Control Continuous Time LDOs with Digital Gates Unified Voltage and Frequency Regulation Conclusions33 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceConventional LDOs with Two Loops

79、Conventional LDOs with two Loops Fast transient loop Slow reference tracking loop Limited large signal performance Slew limited for large current transientsArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators34 of 60SpeakerVideo 2024 IEEE International Solid-St

80、ate Circuits ConferenceSwitched Mode Control(SMC)LDOsDual Loop Switched Mode Hybrid Control Two loops separated not in frequency,but in time(or voltage error)Good small signal performance(analog loop)Fast large signal performance(digital controller)VIN+VREFControllerHigh Small Signal Gain and Bandwi

81、dth LoopFast Large Signal Performance Loop ILOADVREF Operation Divided on Voltage Error(VREG-VREF)JSSC 2017Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators35 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceHybrid SMC LDOArijit Raych

82、owdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators36 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceOptimality in SMC LDO DesignsFaster Rise TimeFaster SettlingLarge Signal Pole LocationImagRealSmall Signal Pole LocationTimeVoltageHigh Small Sig

83、nal Performance RegionFast Large Signal Response RegionVREF-VREF+VREFS-planeRe(s)Im(s)Faster Rise TimeFaster SettlingSMC Design Principle Large transients(|VOUT-VREF|D):Place poles in unshaded region for faster rise time(Underdamped)Near regulation(|VOUT-VREF|D):Place poles in shaded region for fast

84、er settling(Overdamped)Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators37 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceOutput Pole Dominant Analog Loop OTA()VREFShunt Feedback Buffer2Capacitor Less Output Pole Dominant Analog LDO

85、VssMPA=3/4VIN20A+ILOAD3.5A2.1A28AM1M2M3M4M6M5M7M8M9M10M11M12M13P2P3ROUT,OTAROUT,BUFFPDOMDigital LDOAnalog LDOControl UnitLoad and Output Capacitance0.8mm1mmProcessGF 130nm CMOSPackageQFNActive Area0.0818mm2VIN0.6V,1.1-1.2VILOAD30A 12mAVOUT0.5-0.55V,0.8-1.1VLoad Capacitance10mA.Arijit Raychowdhury39

86、of 60202530354030 40 50 60 70 80 90 100110 mVTSETTLINGnsFS=426 MHzOptimal for Settling timeSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceHybrid LDO with Digitally Controlled Leakage SupplyArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulator

87、s40 of 60 Header switches in a digital SoC can be programmed to supply leakage current Such hybrid configurations reduce load requirement on the high-speed analog LDO SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceHybrid LDO Improves Droop ResponseArijit RaychowdhuryFundamentals

88、 of Digital and Digitally-Assisted Linear Voltage Regulators41 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceSummary:All-digital and Hybrid SMC LDOsAll-Digital LoopHybrid SMC Loop+Excellent small signal gain and performance+No ripple+Fast transient response with high-speed

89、 digital loop+Output pole dominant analog-Limited operating range-Lower current efficiency-Not synthesizable+Wide operating range+High current efficiency with adaptive control+Low-overhead adaptation with clock control+Fast transient response enabled by RDS-Output ripple-Limited small signal perform

90、ance-Limited Clock FrequencyArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators42 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsOutline Motiva

91、tion Discrete Time All-Digital LDOs Q&A Switched Mode Control Continuous Time LDOs with Digital Gates Unified Voltage and Frequency Regulation Conclusions43 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceDigital but Continuous TimeKVCOsKVCOsVCOOutput Stagev vs sREFREFS SVIN

92、D DRLCLv vREFREFSCLKRCLKRCLKSCLKD D In Steady State VCO frequencies are identical FRCLK=FSCLK Phase difference between RCLK and SCLK(D)is held constant Output PMOS controlled via pulse wide modulation(PWM)Multiphase design allows ripple free operation Intel 32nm Process VIN=0.9V-0.7V VOUT=0.75V-0.6V

93、 Max ILOAD=5.0mAVLSIC 2012JSSC 2014Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators44 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMultiphase Design via Johnson Counter A Johnson Counter generates multiple phases of the clock eac

94、h shifted in time by one period.As SCLK and RCLK feed into two separate Johnson Counters,each flip-flop output is phase compared and a PMW signal is generated The design enables low-overhead multi-phase regulationArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regula

95、tors45 of 60QQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDRCLKR0R1R2R31RCLKR0R1QQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDSCLKS0S1S2S31SCLKS0S1SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceRelocking the Loop under TransientsRCLKR0SCLKS0Arijit RaychowdhuryFundamentals of Digital and Digitally-As

96、sisted Linear Voltage Regulators46 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceRCLKR0SCLKS0RCLKR0SCLKS0Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators47 of 60Relocking the Loop under TransientsSpeakerVideo 2024 IEEE Internation

97、al Solid-State Circuits ConferenceRCLKR0SCLKS0RCLKR0SCLKS0RCLKR0SCLKS0Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators48 of 60Relocking the Loop under TransientsSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceMeasurement Results50%60%70%

98、80%90%100%0.50.550.60.650.70.75Power Efficiency VLDOVIdealVLG=0.8VLG=0.7VLG=0.6VLG=0.5MeasuredPower EfficiencyLoad RegulationArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators49 of 600.580.600.620.640.660.680.700.720.740.7601234VLDOVILOAD mAVREF=0.7VVREF=0.65

99、VVREF=0.6VSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsOutline Motivation Discrete Time All-Digital LDOs Q&A Switched Mode Control Continuous Time LDOs with Digital Gates Unified Voltage

100、 and Frequency Regulation Conclusions50 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceUnifying LDO VR and ClockingPhase DetectorPWM GeneratorVREG(Digital Supply)Digital Logic LoadFREFLocal TRC VCOFLOC(Digital Clock)Multi(32)-phase design+-NVINPUPU#1 1PUPU#2 2PUPU#3 3PUPU#4

101、 4N N1 1,F FR REFEFN N3 3,F FR REFEFN N2 2,F FR REFEFN N4 4,F FR REFEFSoC PM VisionLoop Transfer Characteristics The local clock and the local supply are generated from the same control loop Clock jitter correlated with VREG No small signal sensingArijit RaychowdhuryFundamentals of Digital and Digit

102、ally-Assisted Linear Voltage Regulators51 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceTRC VCO and Load CircuitsTuning BitsTuning BitsTunable Replica Circuit(TRC)Interconnect Dominated Transistor DominatedVINVREGLevel ShifterFLOCFFPositiveLatchDataOutErrorError Detection

103、Sequential(EDS)Launching Flip-FlopPipelineReceiving FF w/EDSInput BufferOutput Logic&Error DetectionCLKTuning BitsDigital Load CircuitNoise GenVREGVREGHigh Speed PadCLKTunable Replica Circuit VCO Composed of logic and interconnect dominant paths Programmable to tens of ps resolution Non-inverting pa

104、th closed via level shifting inverter to create a tunable VCOPrototypical Load Circuit 3-stage pipeline with built in self-test Error Detection Sequentials to detect timing errors High-speed noise generator replicates power state transitionsArijit RaychowdhuryFundamentals of Digital and Digitally-As

105、sisted Linear Voltage Regulators52 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceKey Measurement ResultsLoad?CircuitsPower?MOSFETsLocal?VCOScan?&?Glue?LogicProcessGF 130nm 8M-CMOSPackageQFNActive Area0.0204mm2Total area includingperipherals0.11mm2Input VDD0.6V-1VOutput VRE

106、G0.38V-0.81VReference Frequency100KHz-500MHzLoad Current100uA 6mAChip CharacteristicsESSCIRC 2016JSSC 2014 IBM 130nm Process VIN=0.1V-0.6V VREG=0.81V-0.27V FREF=10-500MHz Max ILOAD=2.5mA TRC VCO always tracks VOUT Frequency&litude independent Clock-Data compensation Controller current scales with

107、 logic frequency and provides high current efficiencyArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators53 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceResponse to Voltage DroopsArijit RaychowdhuryFundamentals of Digital and Digital

108、ly-Assisted Linear Voltage Regulators54 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceResponse to Voltage DroopsArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators55 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits Conf

109、erenceRuntime Temp and Aging Adaptation TRC calibration is equivalent to VDD calibration for a given frequency Guard band reduction:14%-32%for Temperature,30%for Process,6%-7%for agingArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators56 of 60SpeakerVideo 2024

110、 IEEE International Solid-State Circuits ConferenceResiliency through UVFR Design0.400.600.801.00101001000Baseline DesignCurrent UFVR DesignFREF MHz VREG V New operating point 500MHz 27%18%Baseline Design:Pipeline clocked by FREFBaseline Design:Pipeline clocked by FREF UVFR allows co-regulation of t

111、he load supply and the local clock frequency A maximum reduction of 27%of voltage guard-band is measured at 10MHzArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators57 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceSummary:Continuous T

112、ime LDOsPhase Based Design+Continuous time control+Designed with digital gates only+Low-overhead multi-phase design+Fast transient response and no ripple-Larger area and controller power-Limited bandwidth(dominant pole at the origin)Unified Voltage and Frequency Regulation+Single loop control for bo

113、th supply and clocking+Local clock tracks dynamic variations;no timing error-Droop response limited by the reference frequencyArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators58 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceArijit

114、RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsOutlineMotivationDigitally Assisted LDOs:1996-presentDiscrete Time All-Digital LDOsLoop Architecture and Circuit DesignConcepts of Adaptive DesignSwitched Mode ControlHybrid,Dual-Loop TopologiesImplications on the An

115、alog Loop DesignContinuous Time LDOs with Digital GatesLoop Architecture and CircuitsLinear Control Unified Voltage and Frequency RegulationConclusions59 of 60SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceConclusionsDigital LDO regulators demonstrateLow Operating Voltage(to NTV

116、)&Low Dropout Voltage(50mV)Fast Transients with DVFS Support for Digital Load CircuitsAdaptive Control in Digital LDOsEnables Consistent Damping across Load RangeRestricts Limit Cycle OscillationsSwitched Mode Control(SMC)allowsExcellent Small Signal Analog PerformanceFast Transient Response enabled

117、 by the Digital LoopPhase Based regulation allows ripple free operationUVFR allows voltage-clock co-regulation and reduction of voltage guard-band in digital load circuitsArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage Regulators60 of 60SpeakerVideo 2024 IEEE Interna

118、tional Solid-State Circuits ConferenceArijit Raychowdhury61 of 62Fundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsPlease Scan to Rate Please Scan to Rate This PaperThis PaperSpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceRelevant Papers to Look out for in

119、ISSCC 202414.6“A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET,”D.Lee,S.Kim,T.Nomiyama,D-H.Jung,D.Kim,J.Lee,S.Kwak Samsung Electronics,Hwaseong,Korea28.1“A Full

120、y Integrated,Domino-Like-Buffered Analog LDO Achieving 28dB Worst Case Power-Supply Rejection Across the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance,”J-G.Lee1,H-H.Bae1,S.Jang2,H-S.Kim11Korea Advanced Institute of Science and Technology,Daejeon,Korea2Electronics and Telecommuni

121、cations Research Institute,Daejeon,KoreaArijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsISSCC2024SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceReferences:1.Ooishi,T.,et al.,“A mixed-mode voltage-down converter with impedance adjustment

122、 circuitry for low-voltage wide-frequency DRAMs.”IEEE Journal of Solid-State Circuits,Vol.31,No.4,April,19962.Beign,Edith,et al.An asynchronous power aware and adaptive NoC based circuit.IEEE Journal of solid-state Circuits,pp.1167-1177,Vol.44,No.4,2009.3.Okuma,Yasuyuki,et al.0.5-V input digital LDO

123、 with 98.7%current efficiency and 2.7-A quiescent current in 65nm CMOS.Custom Integrated Circuits Conference(CICC),2010.4.Hirairi,Koji,et al.13%power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection(pepd)and fully in

124、tegrated digital LDO.IEEE International Solid-State Circuits Conference(ISSCC),2012.5.Lee,Yu-Huei,et al.A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.Symposium on VLSI Circuits(VLSIC),2012.6.Nasir,S.B,et al.

125、,5.6 A 0.13m fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range.IEEE International Solid-State Circuits Conference(ISSCC),2015.Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsREF 1SpeakerVide

126、o 2024 IEEE International Solid-State Circuits ConferenceReferences:7.Yang,Fan,et al.,A 0.61V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5 b over 500mA loading range in 65-nm CMOS.European Solid-State Circuits Conference(ESSCIRC),ESSCIRC 2015-41st.IEEE,201

127、5.8.Raychowdhury,A.,et al.A fully-digital phase-locked low dropout regulator in 32nm CMOS.Symposium on VLSI Circuits(VLSIC),2012.9.Kim,S.T.,et al.Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.I

128、EEE International Solid-State Circuits Conference(ISSCC),2015.10.Bulzacchelli,J.F.,et al.Dual-loop system of distributed microregulators with high DC accuracy,load response time below 500 ps,and 85-mV dropout voltage.IEEE Journal of Solid-State Circuits,pp.863-874,Vol 47 No.4,2012).11.Toprak-Deniz,Z

129、.,et al.Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 TM microprocessor.IEEE International Solid-State Circuits Conference Digest of Technical Papers(ISSCC),2014.12.Lee,Y-J,et al.A 200mA digital low-drop-out regulator with coarse-fine dual loop in m

130、obile application processors.IEEE International Solid-State Circuits Conference(ISSCC),2016.Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsREF 2SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceReferences:13.F.Yang and P.K.T.Mok,5.11 A 65

131、nm inverter-based low-dropout regulator with rail-to-rail regulation and over 20dB PSR at 0.2V lowest supply voltage,IEEE International Solid-State Circuits Conference(ISSCC),2017.14.S.B.Nasir,S.Sen and A.Raychowdhury,Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital

132、Load Circuits,in IEEE Journal of Solid-State Circuits,2018.15.S.Kundu,M.Liu,R.Wong,S.-J.Wen and C.H.Kim,A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning,IEEE International Solid-State Circuits Conferenc

133、e(ISSCC),2018.16.X.Sun,A.Boora,W.Zhang,V.R.Pamula and V.Sathe,14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS,2019 IEEE International Solid-State Circuits Conference(ISSCC),2019.17.S.J.Kim,D.Kim,Y.Pu,C.Shi

134、and M.Seok,A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load,Symposium on VLSI Circuits,2019.18.J.-E.Park,J.Hwang,J.Oh and D.-K.Jeong,32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Ba

135、sed PSR Enhancement,2020 IEEE International Solid-State Circuits Conference(ISSCC),2020.Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsREF 3SpeakerVideo 2024 IEEE International Solid-State Circuits ConferenceReferences:19.D.-H.Jung et al.,29.6 A Distribute

136、d Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFETCMOS,IEEE International Solid-State Circuits Conference(ISSCC),2021.20.F.Chen,Y.Lu and P.K.T.Mok,A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-V/

137、mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS,in IEEE Journal of Solid-State Circuits,2021.21.S.Kim et al.,A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications,IEEE Symposium on VLSI Technology and Circuits(VLSI Technology and Circui

138、ts),2022.22.M.Zelikson et al.,14.3 A Digital Low-Dropout(LDO)Linear Regulator with Adaptive Transfer Function Featuring 125A/mm2 Power Density and Autonomous Bypass Mode,IEEE International Solid-State Circuits Conference(ISSCC),2023.23.H.Kim,C.Park,I.Park,T.Park,S.Park and C.Kim,A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications,in IEEE Journal of Solid-State Circuits,2023.Arijit RaychowdhuryFundamentals of Digital and Digitally-Assisted Linear Voltage RegulatorsREF 4