在半雙工以太網PLCA多點上啟用時間感知整形器.pdf

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1、IEEE-SA Ethernet&IP Automotive Technology DayBrazil-September 2023#Universidade Federal de Pernambuco Brazil*Instituto Federal de Pernambuco BrazilRuhr University Bochum-GermanyEnabling Time-Aware Shaper on Half-Duplex Ethernet PLCA MultidropDavid A.Nascimento#*(dancin.ufpe.br)Steffen Bondorf(steffe

2、n.bondorfruhr-uni-bochum.de)Divanilson R.Campelo#(dcampelocin.ufpe.br)AgendaAgenda Introduction Time-Aware Shaper(TAS)10BASE-T1S Physical Layer Collision Avoidance(PLCA)TAS+PLCA Full-duplex switched Ethernet vs Half-duplex PLCA Multidrop Ethernet Results Conclusion Future work2IntroductionIntroducti

3、onTime-Sensitive Networking(TSN)Time Synchronization,Ultra reliability,Bounded low latency,and Dedicated Resources&APITSN includes IEEE 802.3Qbv Time-Aware Shaper(TAS)Ultra-low latency,jitter,and loss TAS is a solution for deterministic systems Real-time and safety-critical applications31 K.Matheus

4、and T.Knigseder,Automotive Ethernet,3rd ed.Cambridge University Press,2021.Most Ethernet implementations today Switched networks with full-duplex linksProblems They may be costly for some use cases,mainly automotive Over 90%of the current internal communication links need less than 10 Mbps1 100BASE-

5、T1 is not cost-efficient for replacing CAN(Controller Area Network)or CAN-FD(CAN with Flexible Data Rate)Solution 10BASE-T1SIntroductionIntroductionThe integration of TAS and 10BASE-T1S PLCA enables many possibilities No gateways End-to-end transmissions of scheduled traffic Ethernet flows All-Ether

6、net Vehicle4TimeTime-AwareAware ShaperShaper Gate Control List(GCL)Clock-based open-close gate scheduling for all priority queues Scheduled Traffic(ST)Time slots for transmissions(windows)Exclusive windows Lowest delay bounds More complex to provide(NP-hard)Similar to Time Division Multiple Access(T

7、DMA)Desired in automotive Overlapping windows Low delay bounds More simple to provide Strict Priority(no preemption)Not desired in automotive5GCL Hyperperiod76543210tttttttt0 1 2 3 4 5 6 7 8 9Time ID:Gate Control List(GCL)Time IDGate States000000100110000100200010000301000000401001000500001000600100

8、000700000010800000010900000000Ethernet interfaceGCL schedulingGate states over timeTimeTime-AwareAware ShaperShaper6Gate Control List(GCL)Time IDGate States000000100110000100200010000301000000401001000500001000600100000700000010800000010900000000GCL Hyperperiod76543210tttttttt0 1 2 3 4 5 6 7 8 9Time

9、 ID:Ethernet interfaceGCL schedulingGate states over timeOverlappingOverlappingTimeTime-AwareAware ShaperShaper7TimeTime-AwareAware ShaperShaper Transmissions within the open window The guard band is considered Overlapping among windows In the worst case,the whole window is not available Guaranteed

10、windows must be calculated2 Guaranteed window Within an open window No overlappings among distinct priority queues from a single interface In the worst-case,a frame transmission can start anytime within a guaranteed window Max length:window length guard band length Min length:zero82 L.Zhao and P.Pop

11、 and S.S.Craciunas,“Worst-Case Latency Analysis for IEEE 802.1Qbv Time Sensitive Networks Using Network Calculus,”IEEE Access,vol.6,pp.41 80341 815,2018.10BASE10BASE-T1ST1S Single Pair Ethernet Half-duplex Multidrop Up to 8 nodes Physical Layer Collision Avoidance(PLCA)Avoids frame collisions Provid

12、es bounded latency No more exponential random wait time from CSMA/CD due to collisions CSMA/CD is a MAC feature Collisions are avoided in the PHY Optimal bandwidth utilization No waste in transmission time Guaranteeing fairness among nodes9PhysicalPhysical LayerLayer CollisionCollision AvoidanceAvoi

13、dance (PLCA)(PLCA)Frame transmissions within a Transmit Opportunity(TO)Each node has a single TO per PLCA cycle Two modes for transmission Normal mode Burst mode Silence when there is no frame to transmit Commit symbols are transmitted just before frame transmission when beacon and silence is shorte

14、r than an IFGShortest PLCA cycle Silence from all nodesLongest PLCA cycle Transmissions of max frame size from all nodes10Figures adapted from Figures 5.39 and 5.40 from 1 K.Matheus and T.Knigseder,Automotive Ethernet,3rd ed.Cambridge University Press,2021.TAS+PLCATAS+PLCABest of the two worlds?!Tim

15、e-Aware Shaper 10BASE-T1S PLCAUltra-low latency,jitter,and loss on half-duplex multidrop links?!11They are cyclical but not synchronized TAS is TDMA-like PLCA is Weighted Round-Robin(WRR)-based Both can work together Mistakes in the planning of TAS or PLCA parameters may cause packet loss or even st

16、arvationTAS+PLCATAS+PLCAThe choice of a TAS scheduling is not an easy task TAS on 10BASE-T1S PLCA is harderDeterministic systems require certification Performance guarantees Worst-case analysis Deterministic Network CalculusProviding optimal TAS scheduling is hard PLCA is not aware of frame priority

17、 All scheduled traffic flows must be compliant A tool is required for calculating worst-case boundsThere was neither an analytical solution nor an open-source tool for calculating the worst-case bounds of systems with TAS and PLCA We provide both3123 David A.Nascimento and Steffen Bondorf and Divani

18、lson R.Campelo,“Modeling and Analysis of Time-Aware Shaper on Half-Duplex Ethernet PLCA Multidrop”.IEEE Transactions on Communications,71(4):22162229,2023.TAS+PLCATAS+PLCASlide 18Worst-case:A graphical exampleGuaranteed window finishes earlier than TO from Node 2Frame missed the TO of current PLCA c

19、ycleTAS+PLCATAS+PLCAIn a worst-case situation A frame is transmitted lastwithin a PLCA cycle composed of frames from overlapping guaranteed windows among distinct nodes Worst-case WRR behavior A PLCA cycle must fit within a guaranteed window Otherwise a frame can miss its open window Deadline is not

20、 metSlide 19Guaranteed window finishes earlier than TO from Node 2Frame missed the TO of current PLCA cycleTAS+PLCATAS+PLCATAS scheduling shall have few overlapping guaranteed windows among distinct nodesFewer overlappings Shorter PLCA cycles Lower boundsNo overlappings The best situation Lowest wai

21、t time for transmission PLCA cycle is composed of a frame from the current node and silence from the other nodesSlide 20Guaranteed window finishes earlier than TO from Node 2Frame missed the TO of current PLCA cycleFullFull-duplex duplex switchedswitched Ethernet Ethernet vsvs HalfHalf-duplex PLCA M

22、ultidrop Ethernetduplex PLCA Multidrop Ethernet 13 distinct TAS scheduling cases2 Different overlapping scenarios,lengths of open window,open-close cycles,and priority assign 13 scheduled traffic flows2 e.g.:Hypothetical“1000BASE-T1S”3 Sum of flows bandwidth exceeds 100 Mbps Worst-case delay analysi

23、s Network Calculus162 L.Zhao and P.Pop and S.S.Craciunas,“Worst-Case Latency Analysis for IEEE 802.1Qbv Time Sensitive Networks Using Network Calculus,”IEEE Access,vol.6,pp.41 80341 815,2018.3 David A.Nascimento and Steffen Bondorf and Divanilson R.Campelo,“Modeling and Analysis of Time-Aware Shaper

24、 on Half-Duplex Ethernet PLCA Multidrop”.IEEE Transactions on Communications,71(4):22162229,2023.Frame size(bytes)Period(s)Deadline(s)4002508908.040025056935.040025035879.0400250170198.0foiFullFull-duplex duplex switchedswitched Ethernet Ethernet vsvs HalfHalf-duplex PLCA Multidrop Ethernetduplex PL

25、CA Multidrop EthernetResults Flow of interest(foi)As expected,there was an increase on delay bounds Increase ranges from 10.7%to 27.6%3 Below the deadline17tt11tt113 David A.Nascimento and Steffen Bondorf and Divanilson R.Campelo,“Modeling and Analysis of Time-Aware Shaper on Half-Duplex Ethernet PL

26、CA Multidrop”.IEEE Transactions on Communications,71(4):22162229,2023.FullFull-duplex duplex switchedswitched Ethernet Ethernet vsvs HalfHalf-duplex PLCA Multidrop Ethernetduplex PLCA Multidrop EthernetResults 5 of 13 scheduled traffic flows with source and destination ES in the same multidrop All 5

27、 flows have a reduction in delay bounds when using a single-hop PLCA multidrop instead of two hops of full-duplex links3 Decrease ranges from 16.7%to 33.2%318e.g.tt4e.g.tt43 David A.Nascimento and Steffen Bondorf and Divanilson R.Campelo,“Modeling and Analysis of Time-Aware Shaper on Half-Duplex Eth

28、ernet PLCA Multidrop”.IEEE Transactions on Communications,71(4):22162229,2023.ConclusionConclusionTAS and 10BASE-T1S PLCA Ultra-low latency on half-duplex multidrop links Reliable and cheaper solution Less PHYs than full-duplex switched End-to-end transmissions of scheduled traffic Ethernet flows Av

29、ailable models and tools for analyzing TAS scheduling over 10BASE-T1S PLCA multidrop“Ubiquitous Ethernet In-Vehicle Networks”Future works Worst-case jitter analysis Analysis of more use cases:Automotive networks with 10BASE-T1S 10BASE-T1S PLCA without TAS Integration of 10BASE-T1S PLCA with other TSN protocols E.g.,Asynchronous Traffic Shaping(ATS)IEEE 802.1Qcr1920Thank you