重新定義連接性：在 Chiplet 互連中繪制下一代路徑.pdf

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1、1Alphawave SEMI All Rights Reserved.Accelerating the Connected WorldRedefining Connectivity:Charting Next-Gen Pathways in Chiplet InterconnectsTony Chan Carusone,CTOAI Hardware and Edge AI SummitSeptember 11,20242Alphawave SEMI All Rights Reserved.Delivering Custom Silicon in the Data CentreCompute

2、CPUCustom xPUsNetworkingCustomised compute and connectivity reliant on chiplets3Alphawave SEMI All Rights Reserved.Outline Scaling AI with Connectivity The Role of Chiplets for AI Compute Enabling a Chiplet Ecosystem4Alphawave SEMI All Rights Reserved.Accelerating the Connected WorldScaling AI with

3、Connectivity 5Alphawave SEMI All Rights Reserved.Evolving Data Centre Connectivity LandscapeSwitchesCompute Servers Optical and electrical links Flexible and redundant networkingThis evolution is accelerating and diversifying with AI deployment in the data centre6Alphawave SEMI All Rights Reserved.A

4、I in the Data Centre Proliferating ConnectivityFront-End Data Centre NetworkBack-End ML Network Low-latency&high-speedAI Cluster7Alphawave SEMI All Rights Reserved.Scaling Up and OutScale UpScale OutDriving growth and R&D investment8Alphawave SEMI All Rights Reserved.Distributed AI Data security&pri

5、vacy Energy efficiency Relies heavily on connectivity9Alphawave SEMI All Rights Reserved.Higher per-lane data ratesScale up and out to larger clustersLow latency;Low power;Low failure rateProliferation of new optical connectivity technologiesConnectivity Demands for AI10Alphawave SEMI All Rights Res

6、erved.Accelerating the Connected WorldThe Role of Chiplets for AI Compute11Alphawave SEMI All Rights Reserved.LogicI/OI/OI/OI/OI/OI/OI/OI/OHBMHBMHBMMemoryHBMMemoryMemoryMemoryMonolithic SolutionsBenefits and Drawbacks Requires integration of external IP Design and verification time and risk Licensin

7、g cost Maximum size is limited by reticle Yield reduced by large die size I/O must be in the most advanced technology Every I/O must be capable of driving any interconnect 12Alphawave SEMI All Rights Reserved.Chiplet-Optimized NodeAdv.Logic NodeBandwidth Density Reticle-limited die sizes afford roug

8、hly 50mm die edge on the east+west 50Tbps aggregate I/O bandwidth requires 1 Tbps/mmLogicI/OI/OI/OI/OI/OI/OI/OI/OHBMHBMHBMMemoryHBMMemoryMemoryMemory13Alphawave SEMI All Rights Reserved.HBMLogicUCIeUCIeUCIeUCIeUCIeUCIeI/OI/OUCIeUCIeHBMLogicUCIeUCIeUCIeUCIeUCIeUCIeI/OI/OUCIeLogicI/OI/OUCIeUCIeUCIeUCI

9、eUCIeUCIeUCIeUCIeHBMMemoryLogicI/OI/OUCIeUCIeUCIeUCIeUCIeUCIeUCIeUCIeHBMMemoryMemoryMemoryChiplet-Optimized NodeAdv.Logic NodeUCIeChiplets Reduced design time,risk,NRE and silicon costs Composability14Alphawave SEMI All Rights Reserved.Accelerating Hardware Upgrades Reduced design time Reduced risk

10、Composability Reduced NRE+Silicon CostDie-to-Die Interfaces Required for the Chiplet Era15Alphawave SEMI All Rights Reserved.Switch SystemPluggable Modules or TransceiversConnectivity Hardware in the Datacenter16Alphawave SEMI All Rights Reserved.Chiplet devices on a low-cost substrateBenefits:Power

11、 Performance CostOptical Module Anatomy with Chiplets17Alphawave SEMI All Rights Reserved.Optical fiberMiniature optical enginesCo-Packaged Optics(CPO)18Alphawave SEMI All Rights Reserved.Bandwidth(“Beachfront”)Density Up to 10 Tbps/mmBeachfront density can be limited by fiber pitch,optical DSP die

12、areaCPO ChipletsLogicUCIeUCIeHBMHBMHBMHBMUCIeI/OI/OUCIeI/OI/OUCIeUCIeMemoryMemoryMemoryMemoryUCIeOptical I/OPhotonic I.C.UCIeOptical I/OPhotonic I.C.Mix-and-match with electrical I/O chiplets for different applications Optical I/O density being pushed by new solutions:Multiple wavelengths Dense fibe

13、r arrays Package fan-out19Alphawave SEMI All Rights Reserved.Distributed Data Centers Driving New ConnectivityCoherent-LiteFuture solutions are needed to address these new requirementsGeographically-distributed compute requires broadband connectivity20Alphawave SEMI All Rights Reserved.Accelerating

14、the Connected WorldEnabling the Chiplet Ecosystem21Alphawave SEMI All Rights Reserved.Design Paradigm TransformationMonolithic Design with Foundry-Enabled Foundation IPAccelerated designLogicI/OI/OI/OI/OI/OI/OI/OI/ODDRDDRDDRDDRLogicUCIeUCIeHBMHBMHBMHBMUCIeI/OI/OUCIeI/OI/OUCIeI/OI/OUCIeI/OI/OUCIeUCIe

15、MemoryMemoryMemoryMemoryHeterogeneous Design with Foundry-Enabled Foundation ChipletsEvolution of Hardware Design22Alphawave SEMI All Rights Reserved.Die-to-Die Interfaces Supporting a Chiplet EcosystemBandwidth densityEnergy efficiencyLatencyReachAvailability,Interoperability,Reliability23Alphawave

16、 SEMI All Rights Reserved.Key Technologies in Die-to-Die InterfacesSignal Integrity Managing Crosstalk Interconnect loss compensationPower Integrity Limited area for supply decoupling Variation in packaging technology and dense signal routing complicate power deliveryClocking Low-power and low-jitte

17、r clock distribution Clock/Data alignment24Alphawave SEMI All Rights Reserved.A Chiplet Portfolio I/O Chiplet Multi-Standard SerDes IO with Integrated Protocol Controllers:PCIe Gen6/CXL 3.0/112Gbps Ethernet Compute Chiplet High Performance,Arm-Based Compute Memory Expansion Chiplet Low Latency DDR/H

18、BMUCIe Die-to-Die Interfaces25Alphawave SEMI All Rights Reserved.Takeaways AI has redefined datacenter infrastructure Connectivity technologies are the key to scaling AI clusters and geographically distributed datacenters effectively Chiplets enable custom silicon solutions optimized for AI workload

19、s Essential to affordably scale performance,achieve lower power,and faster time to market A chiplet ecosystem is emerging,enabled by die-to-die interfaces and allowing for a wide variety of chiplet use casesChiplet EcosystemCustom Silicon and ChipletsAI Connectivity26Alphawave SEMI All Rights Reserved.Accelerating the Connected WorldThank You!