Session 9Ubiquitous Power Delivery.pdf

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1、Session 9 Overview:Ubiquitous Power Delivery POWER MANAGEMENT SUBCOMMITTEEPower delivery circuits are employed in all types of electronic applications,and their technological innovations continue to advance.In this session,the latest advanced technologies for AC-DC converters,supply modulators for R

2、F power amplifiers,low dropout regulators,wireless power transfer,and hybrid converters are presented to demonstrate their novel topologies achieving higher efficiency,higher output power,faster transient response and smaller form factor.Session Chair:Dongsu Kim Samsung Electronics,Hwaseong,Korea Se

3、ssion Co-Chairs:Chen-Yen Ho MediaTek,Hsinchu,Taiwan 176 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE8:00 AM 9.1 An 85-to-230VAC to 3.3-to-4.6VDC 1.52W Capacitor-Drop Sigma-Floating-SC AC-DC Convert

4、er with 81.3%Peak Efficiency Fei Song,University of Macau,Macau,China In Paper 9.1,University of Macau presents a capacitor-drop sigma-floating-SC AD-DC converter for IoT and smart home devices.With a sigma-SC rectifier and a floating-SC converter,it achieves 81.3%peak efficiency and maintain high e

5、fficiency for wide load current range.8:25 AM 9.2 A 400MHz Symbol-Power-Tracking(SPT)Supply Modulator with SPT-Adaptive-Biasing Network Supporting 5G FR2 CMOS PA Jongbeom Baek,University of California,Berkeley,CA In Paper 9.2,University of California,Berkeley presents a fully integrated symbol-power

6、-tracking(SPT)CMOS RF power amplifier with a non-uniform multi-level supply modulator and a SPT-adaptive-biasing network.This work supports 5G FR2 standard with 400MHz channel bandwidth and has a 30%improved efficiency compared to the average power tracking operation.8:50 AM 9.3 A 74W/48V Monolithic

7、-GaN Integrated Adjustable Multilevel Supply Modulator for 5G Base-Station Massive-MIMO Arrays Hieu Minh Pham,University of California,San Diego,CA In Paper 9.3,University of California,San Diego presents a GaN monolithic integrated adjustable supply modulator for digital envelope tracking transmitt

8、ers in 5G base stations.The implemented circuit supports 4 tunable voltage levels and improves the power-added efficiency of a transmitter with a rated power of 74W/48V by 6.9%.9:15 AM 9.4 A 102ns/V 94.3%-Peak-Efficiency Symbol-Power-Tracking Supply Modulator for 5G NR Power Amplifiers Minghao Shang

9、,University of Science and Technology of China,Hefei,China In Paper 9.4,University of Science and Technology of China presents a symbol-power-tracing(SPT)supply modulator for 5G NR power amplifiers.With a ripple-cancellation technique and a small load capacitance,it achieves fast up-and down-trackin

10、g of 510ns/5V and 900ns/5V,and 12mV output voltage ripple.10:55 AM 9.8 A 50W 98%-Efficiency High-Power Wireless-Charging System with an Acoustic Noise-Reduced ASK Modulation Technique and Internal Hybrid Voltage-/Current-Mode ASK Demodulation Seongjin Oh,Samsung Electronics,Hwaseong,Korea In Paper 9

11、.8,Samsung Electronics presents a 50W high-power wireless charging system with an acoustic noise-reduced ASK modulation technique and an internal hybrid voltage-/current-mode ASK demodulator.This work significantly reduces an acoustic noise of MLCC capacitors up to 20dB and eliminates all related ex

12、ternal components of the demodulator.11:20 AM 9.9 A Bi-Directional Dual-Path Boost-48V-Buck Hybrid Converter for High-Voltage Power-Transmission Cable in Light-Weight Humanoid Robots Wenjie Yang,University of Macau,Macau,China;UM Hetao IC Research Institute,Shenzhen,China In Paper 9.9,University of

13、Macau presents a bi-directional dual-path boost-48V-buck hybrid converter for a high-voltage power transmission cable in light-weight humanoid robots.By reusing a parasitic cable inductor and employing a phase alignment scheme,the converter achieves a peak efficiency of 96.7%at 16.5W and a maximum t

14、ransmission power of 45W without requiring an additional bulky power inductor.11:35 AM 9.10 A 93%-Peak-Efficiency Battery-Input 12-to-36V-Output Inductor-in-the-Middle Hybrid Boost Converter with Continuous Input and Output Currents and Fast Transient with No RHP Zero Yifan Jiang,Southern University

15、 of Science and Technology,Shenzhen,China;University of Macau,Macau,China In Paper 9.10,Southern University of Science and Technology presents a hybrid boost converter with continuous input and output currents.By placing an inductor between two switched-capacitor step-up stages,the converter has a s

16、ignificantly reduced inductor current at a high voltage conversion ratio and a fast transient response due to the elimination of a right-half-plane zero.It delivers a maximum output power of 10.8W with a peak efficiency of 93%and a high power density of 49.5mW/mm3.11:50 AM 9.11 A 98.3%-Peak-Efficien

17、cy Single-Mode Hybrid Buck-Boost Converter with 7mV Maximum Output Ripple for Li-Ion Battery Management Ji Jin,University of Science and Technology of China,Hefei,China In Paper 9.11,University of Science and Technology of China presents a single-mode hybrid buck-boost converter for Li-ion battery m

18、anagement.The converter has a half-Vin voltage stress and a continuous output current delivery using 7 switches and 2 flying capacitors,and it achieves 98.3%peak efficiency and 7mV output voltage ripple without mode transition issues.10:30 AM 9.7 A 6.78MHz 94.2%Peak Efficiency Class-E Transmitter wi

19、th Adaptive Real-Part Impedance Matching and Imaginary-Part Phase Compensation Achieving a 33W Wireless-Power-Transfer System Yuhao Xiong,Xian JiaoTong University,Xian,China In Paper 9.7,Xian JiaoTong University presents a Class-E transmitter for a wireless power transfer system.With an adaptive rea

20、l-part impedance-matching technique and an imaginary-part phase compensation controller,the transmitter achieves high transmitter efficiencies of 88.0 to 94.2%for very wide load range from 3 to 29W,and a maximum E2E output power of 33W.ISSCC 2025/February 18,2025/8:00 AM177 DIGEST OF TECHNICAL PAPER

21、S 10:05 AM 9.6 A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2%Efficiency and 131mW Output Power Quanrong Zhuang,Nanjing University,Nanjing,China In Paper 9.6,Nanjing University presents a 6.78MHz single-stage dual-output regulating

22、 rectifier for a biomedical wireless powering.By supporting a simultaneous charging of dual outputs in a half cycle and a charge distribution operation,it achieves 92.2%peak efficiency with a negligible load transient response and an unnoticeable cross-regulation.9:30 AM 9.5 A Sub-1V,50mV Dropout LD

23、O Using Pseudo-Impedance Buffer with Phase-Margin Improvement Design Young-Jun Jeon,Sogang University,Seoul,Korea In Paper 9.5,Sogang University presents a sub-1V PMOS analog low dropout regulator(LDO).The LDO with a rail-to-rail pseudo impedance buffer(RRPB)and a load-independent Gm-boosting cell(L

24、IGC)supports very wide load current from 0 to 1.2A,input voltage from 0.7 to 1.4V and dropout voltage from 0.05 to 0.2V while maintaining the phase margin.9178 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.1979-8-3315-4101-9/25/$31.00 2025 IE

25、EE9.1 An 85-to-230VAC to 3.3-to-4.6VDC 1.52W Capacitor-Drop Sigma-Floating-SC AC-DC Converter with 81.3%Peak Efficiency Fei Song*1,Shousheng Han*1,2,Rui P.Martins1,Yan Lu1,2 1University of Macau,Macau,China 2Tsinghua University,Beijing,China *Equally Credited Authors(ECAs)The internet-of-things(IoT)

26、and smart home devices,such as smart power meters and smart remote control,have great demand for high-efficiency,low-cost and compact non-isolated AC-DC converter,which operates on the AC mains and delivers a battery-voltage output with a large voltage conversion ratio(VCR).These devices are becomin

27、g increasingly more intelligent and thus have higher power consumption.Traditional approaches involve inductive switching converter 14 and high-voltage linear regulator 5,6,which lead to bulky volume or low efficiency.In contrast,fully integrated switched-capacitor(SC)topology 7 or SC-LDO hybrid top

28、ology 8 can achieve high power density.In addition,capacitive division 911 can convert high-voltage AC input to low-voltage AC,where the X-capacitor connected to the AC mains can block a large portion of the high voltage,then low voltage converters can easily handle the rest and be fabricated on chi

29、p.However,the output power of these capacitive converters is limited to W levels,and the output cannot be adjusted due to the lack of regulation control.As shown in Fig.9.1.1,to regulate the DC line VREC,the current adjustment method is achieved by a semi-active rectifier in 12,13,and by a three-mod

30、e active rectifier in 14,superseding the passive rectifier.As an AC voltage source with CX can be regarded as an AC current source,prior works operate in two phases:1)the CREC charging phase and 2)the current freewheeling phase where the rectifier yields no output current.In 14,C1 and C2 are added i

31、n series with CX to increase the loop impedance of the current freewheeling phase,thereby reducing the idle current.Although the current adjustment method can help regulating VREC,it inevitably leads to considerable constant current loss.This work(Fig.9.1.1 bottom)proposes a voltage adjustment metho

32、d with a semi-active sigma-floating-SC rectifier,to mitigate the current freewheeling.Comparing with the previous works,an output capacitor CL(3.34.6V)and a high-voltage capacitor CH(5070V)are stacked to provide two different VREC voltages:VO and VH.And a floating-SC is used to convert VH to VO.The

33、SC network will work in step-up mode for start-up and in step-down mode to deliver energy to VO.In this way,besides charging CL through the floating-SC,two energy flow paths(EFPs)to CL are added:the output current of the sigma-SC rectifier charges 1)CL directly and 2)the stack of CH and CL.The EFPs

34、can help to share the current stress of the floating-SC,meaning that the proposed topology could have higher output power than the previous works,even with the same SC design.Also,VREC is modulated by being switched between VH and VO.As the PREC equation given in Fig.9.1.1,the output power of the re

35、ctifier PREC is modulated as well.Thus,PREC can well match PO.Moreover,there is no current freewheeling under normal load conditions,PO=PREC,LPREC,H,where PREC,L is the output power of the sigma-SC Rectifier when VREC=VO and PREC,H is the output power of the sigma-SC rectifier when VREC=VH.However,t

36、he voltage adjustment method is not suitable for light load when PO PREC,L.So,a current adjustment method is also employed in this work for light load cases.Compared with 14,though the idle current does not reduce,the idle time is diminished since VREC switches to VO,resulting in a reduction in powe

37、r loss.But it has to be admitted that increase the free-wheeling loop impedance is a more significant method for light-load reduction.Figure 9.1.2 shows the implementation of the sigma-SC rectifier.Switches M1,2 and ML are fabricated on chip using 65V NLDMOS,while D1-2 and DH are discrete off-chip S

38、chottky diodes.As mentioned above,the proposed topology works in the voltage adjustment mode for normal load and in current adjustment mode for light load.There are two operating phases for each load case.The phase selection signals,or in other words,load case detection,are determined by four hyster

39、esis comparators and VM1,VM2,VML are generated for gate driving.In the high-side-charge phase,the result of VX and VY comparison decides the AC current phase.When VX is larger than VY,M2 is on,and AC input voltage VLINE charges CH and CL through D1,DH and VH rises.Similarly,M1 turns on and CH and CL

40、 are charged through D2,DH,when VY is larger than VX.If we neglect the forward voltage of DH,D1,and D2,VREC will be equal to VH.The same principle applies to VX and VY depending on the AC current phase.For the low-side-charge phase,ML is on and the current flows to CO beyond CH and the other parts w

41、ork in the same way as the high-side charge phase.And at the same time,VREC switches from VH to VO.To prevent possible CX hard charging,the changeover from VH to VO must wait for the next AC phase.In the zero-wave phase,M1 and M2 turn on to enable the current freewheeling loop.The truth table of the

42、 sigma-rectifier operation is illustrated in Fig.9.1.2(right-bottom).A high VCR switched-capacitor DC-DC converter is required to achieve high power density.A 3-phase 1/4 2-fly-cap SC DC-DC converter is used in 13 and a 4-phase 10 DC-DC converter with 3 fly-caps is introduced in 14.This work propose

43、s a 5-phase floating-SC DC-DC converter to attain 14 conversion ratio with 4 fly-caps.The circuit implementation and operation principles of the floating-SC are shown in Fig.9.1.3.In 1,MH,MM1-3,and MT4 are on and VH charges CF1-CF3 and CF4|CL in series.In 2,MB1,MT1,MM2,3,and MT4 turn on to allow CF1

44、 to charge CF2,CF3 and CF4|CL in series.In 3,MB2,MT2,MM3 and MM4 are on and CF2 discharges to CF3,CF4 and CL.In 4,MB3,MT3 and MM4 are on and CF3 charges the stacked CF4 and CL.In 5 or idle phase,MT4 and MB4 are on to let CF4 and CL connect in parallel.The five-phase operation can help to increase CL

45、 equivalently,for normal load,19F improved to 25F and for light load,19F enhanced to almost 30F,meanwhile each fly-cap is 10F.All the switches are implemented by NMOS to reduce the conduction loss.The bootstrap capacitors of MT1-MT3 are charged by those of MM1-MM3,when MM1-MM3 are on and the MT4 boo

46、tstrap capacitor charging source is VCF4.However,if the bootstrap charging sequence is too long,large chip area is used for bootstrap capacitors.So,the floating driver voltage of MH is generated by a source follower with a Zener diode 14.In the steady state,the flying-capacitor voltages are VCF1=1/2

47、 VH,VCF2=2/7 VH,VCF3=1/7 VH,and VCF4=1/14 VH.For the floating-SC control method,a pulse-frequency modulation(PFM)control using a hysteresis comparator shown in Fig.9.1.2 is introduced to reduce the loss and more suitable for the low power application.When VO is lower than VLRL,a trigger signal of th

48、e floating-SC is generated,and the switching period of each phase is 200ns.As for the start-up period,due to the body diode blocking the current from charging CL initially,VH is charged up through the body diodes of M1 and M2,and through off-chip diodes D1,D2 and DH.When VO reaches the reference VLR

49、H,the floating-SC works in step-up mode to charge VH until it reaches the upper boundary VHRH,and then the sigma-floating-SC starts to operate to provide large output power.The design is fabricated in a 0.18m BCD process,and the active chip area is 2.8mm1.6mm.All the diodes and capacitors are off-ch

50、ip components.The three operation of Sigma-SC rectifier is shown in Fig.9.1.4 when VLINE=12060Hz,CX=1F,VO=3.3V,and VH is set to 55V.In the measured waveforms,it can be seen that VREC switches between VH and VO.Meanwhile,the zero-wave freewheeling phase can also be observed.When working in low-side-c

51、harge phase and zero-wave phase,CF4 is in parallel with CL to increase the equivalent output capacitor,thus reducing the output voltage ripple.The topology reaches 60mV output ripple when IO=340mA and gets 246mV ripple in light-load cases.When the topology switches its working phase from low-side-ch

52、arge phase to zero-wave phase,CX needs to be charged rapidly to withstand the AC mains.Due to the slow reverse recovery time of the rectifier diodes D1 or D2,during the M1 or M2 on period,a large current will charge CL,causing 246mV glitches.And the transient response is measured with Io changing be

53、tween 50mA(light load)and 250mA(normal load)with about 40ns rising and falling edges.There is no VO voltage drop observed.Switch nodes voltage of floating-SC DC-DC converter is shown in Fig.9.1.5(left-top),when it works in conversion period and VH delivers energy to VO.Each phase is 200ns and the ov

54、erall switching period is 1MHz.Fig.9.1.5 also shows the measured efficiencies with different AC input voltage and DC output voltage.When VLINE=120V60Hz,CX=1F and VO=4.6V,an 81.3%peak efficiency is achieved.The measured maximum output power is 1520mW.By introducing the sigma-floating-SC,compared with

55、 14,the topology can achieve higher efficiency over a large load current range,with a maximum efficiency improvement of approximately 8%.Figure 9.1.6 lists the performance comparison with state-of-the-art works.Compared with prior works,this work achieves higher peak efficiency and improves the effi

56、ciency over a large load current range.In addition,higher output power and power density are obtained as well.Figure 9.1.7 shows the chip micrograph photo and essential external components.Ac knowle dge me nt:This work was supported by the National Natural Science Foundation of China(62122001),the M

57、acau Science and Technology Development Fund(FDCT/0103/2022/AFJ,004/2023/AKP and 004/2023/SKL).Corresponding Author:Yan Lu.Figure 9.1.1:Topology comparison of capacitor-drop non-isolated AC-DC converters and the proposed sigma-floating-SC AC-DC Converter.Figure 9.1.2:Circuit implementation of the si

58、gma-SC rectifier and three operational modes with working waveforms.Figure 9.1.3:The implementation and operation phases of floating-SC DC-DC converter.Figure 9.1.4:Measured three phases of sigma-SC rectifier and step-up/down transient response result of the proposed topology.Figure 9.1.5:Switch nod

59、es voltage of floating-SC DC-DC converter and measured power efficiencies versus load current at different AC input and DC output voltages.Figure 9.1.6:Comparison table with the prior state-of-the-art designs.ISSCC 2025/February 18,2025/8:00 AM179 DIGEST OF TECHNICAL PAPERS 9 2025 IEEE International

60、 Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 9.1.7:Chip micrograph and essential external components.Re f e re nc e s:1 C.Rindfleisch and B.Wicht,“A 110/230 V AC and 15–400 V DC 0.3 W Power-Supply IC With Integrated Ac

61、tive Zero-Crossing Buffer,”I EEE J SSC,vol.57,no.12,pp.3816-3824,Dec.2022.2 C.Rindfleisch and B.Wicht,“A Resonant One-Step 325 V to 3.310 V DCDC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques,”I EEE J SSC,vol.56,no.11,pp.3511-3520,Nov.2021.3 J.Zhang et a

62、l.,“A High Efficiency Flyback Converter With New Active Clamp Technique,”I EEE Tra ns a c ti ons on Powe r Ele c troni c s,vol.25,no.7,pp.1775-1785,July 2010.4 C.Rindfleisch et al.,“A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7%Peak Efficiency,”I EEE CI CC,pp.1-2,Apr

63、.2022.5 ON Semiconductor,“Wide Input Voltage Range 10mA Ultra-Low Iq,High PSRR Linear Regulator,”Rev.3,Mar.2023.Accessed on Dec.3,2024,.6 Fairchild Semiconducto,“AC-DC Linear Regulator,”Rev.1.0.1,Apr.2012.Accessed on Dec.3,2024,.7 T.Van Daele and F.Tavernier,“Fully Integrating a 400 V-to-12 V DCDC C

64、onverter in High-Voltage CMOS,”I EEE J SSC,vol.58,no.3,pp.732-741,March 2023.8 T.Van Daele and F.Tavernier,“Monolithic 230-VRMS-to-12-VDC ACDC Converter at 9 mW/mm2 Enabled by a 31325-VDC Input Range Capacitive Multi-Ratio DCDC Converter,”I EEE J SSC,vol.59,no.4,pp.1067-1077,April 2024.9 N.O.Sokal e

65、t al.,“A Capacitor-Fed,Voltage-Step-Down,Single-Phase,Nonisolated Rectifier,”Appli e d Powe r Ele c troni c s Conf e re nc e a nd Ex pos i ti on,pp.208-215,Feb.1998.10 A.A.Tamez et al.,“An Integrated 120 Volt AC Mains Voltage Interface in Standard 130 nm CMOS,”ESSCI RC,pp.238-241,Sept.2010.11 E.De P

66、elecijn and M.S.J.Steyaert,“A Fully Integrated Switched-Capacitor-Based ACDC Converter for a 120 VRMS Mains Interface,”I EEE J SSC,vol.54,no.7,pp.2009-2018,July 2019.12 H.Meyvaert et al.,“A 265 VRMS Mains Interface Integrated in 0.35 m CMOS,”I EEE J SSC,vol.48,no.7,pp.1558-1564,July 2013.13 Y.Ramada

67、ss et al.,“A 120mA Non-Isolated Capacitor-Drop AC/DC Power Supply,”I SSCC,pp.290-292,Feb.2020.14 G.Liu et al.,“An 85-264Vac to 3-4.2Vdc 1.05W Capacitive Power Converter with Idle Power Reduction and 4-Phase 1/10X SC Converter Achieving 5.11mW Quiescent Power and 78.2%Peak Efficiency,”I SSCC,pp.512-5

68、13,Feb.2024.180 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.2979-8-3315-4101-9/25/$31.00 2025 IEEE9.2 A 400MHz Symbol-Power-Tracking(SPT)Supply Modulator with SPT-Adaptive-Biasing Network Supporting 5G FR2 CMOS PA Jongbeom Baek,Ali Niknejad

69、 University of California,Berkeley,CA The 5G new-radio(NR)frequency-range-2(FR2)for cellular communications supports a maximum channel bandwidth of 400MHz 1 and utilizes orthogonal frequency-division multiplexing(OFDM)to support high data rates with complex modulations such as the quadrature amplitu

70、de modulation(QAM).The mm-wave CMOS power amplifiers(PAs)still consume large amounts of power at their average output power due to high peak-to-average ratios(PAPRs).Envelope tracking(ET)has been a candidate for improving the PAs deep power-back-off(PBO)efficiency by adjusting the VDD of the PA(VDDP

71、A)based on the output power level of the PA.The analog envelope tracking supply modulator(AET-SM)enables the ET bandwidth(BW)up to 200MHz 2 but enhancing beyond this range is challenging.Therefore,digital envelope tracking(DET)3 and symbol power tracking(SPT)46 have been suggested to surpass BW bott

72、lenecks.The SPT needs to finish its voltage transition within the time duration of the cyclic prefix(CP).For NR frequency-range-1(FR1)with 60kHz sub-carrier spacing(SCS),the maximum transition time is 1.2s 6,whereas for NR FR2 with 240kHz SCS,it is 290ns 5.Hence,the SPT modulator for NR FR2 must com

73、plete the voltage transition within a time window of 290ns,and concurrently,the multi-level supply voltage must not have a detrimental effect on CMOS PAs linearity performances and voltage reliability.However,fast-voltage transition for CMOS PAs can cause a significant voltage spike on the VDDPA whe

74、n the stepwise output voltage of the SPT modulator encounters the PCB inductance by the long distance from the SM to the PA.This can potentially damage the CMOS PA or accelerate device aging.Also,multi-level VDDPA affects the bias current of PA,which causes gain variations of the PA for each VDD,eff

75、ectively compromising the CMOS PA linearity.To mitigate the voltage reliability issue while maintaining the linearity performance of the CMOS PA,this paper proposes a fully integrated SPT-modulating CMOS PA with the SPT-adaptive-biasing network(SABN)for 5G NR FR2.As shown in Fig.9.2.1,the proposed S

76、M-PA architecture is compared with the previous architectures,which were manufactured using heterogeneous integration.This implies that SM and PA are fabricated using different technologies and connected on the PCB,generating a trace inductance between SM output(VSM_OUT)and VDDPA.However,the PCB tra

77、ce inductance causes a potential damage issue to the CMOS PA designed using low-voltage(LV)transistors if the stepwise fast-tracking supply voltage 3-6 excites a high Q LC circuit formed by PCB trace inductance(LPCB),the decoupling capacitor of PA(CPA),and SPT switches(SWSPT)having a small on-resist

78、ance for the low conduction loss.Its crucial to consider the worst value of LPCB when designing fast-tracking SMs such as SPT modulators because the placement of the SM and PA on the RF board in the mobile handsets is hard to predict in various commercial productions.3 implemented an RLC filter on t

79、he PCB between SM and PA to mitigate the voltage ringing on the VDDPA,but it is cost-inefficient and increases PCB complexity.To overcome the voltage reliability issue,this paper integrates the SPT modulator and CMOS PA in the same 28nm bulk CMOS process.The integration of SM and PA has advantages:(

80、1)SM-PA PCB trace inductance is eliminated,mitigating damage to the PA;(2)The PA can take advantage of multi-level supply voltages in the PA biasing circuit for its linearity performance with a proposed SPT-adaptive-biasing network.For the SPT modulator in the proposed SPT-PA,this paper utilizes a 6

81、-output single-inductor multiple-output(SIMO)DC-DC converter,as shown in Fig.9.2.1.Previous works 3,4 adopted the multilevel switched-capacitor(MLSC)converter for the SPT operation,but it is suitable for a compound-semiconductor PA with a high-voltage(HV)supply ranging from 0.4V to 5.5V 3.However,th

82、e CMOS PA for FR2 has a narrower VDDPA range than the HV RF-PAs because most FR2 CMOS power amplifiers have utilized an LV CMOS transistor with a cascode structure to support higher RF output power 1 with the maximum/minimum supply voltage of 1.8V/1.0V for the CMOS PA.For this application,the SIMO c

83、onverter is better suited for a multilevel power supply for CMOS PA because its output voltages can be adjusted to any level by controlling the reference voltages.Additionally,by leveraging the SIMO converters non-uniform VDD distribution,more VDD levels can be allocated to the average power at whic

84、h the PA predominantly operates.If the MLSC converter is used for CMOS PA,only a few VDD levels can be used for the PAs multilevel supply.Moreover,since the SPT switches select a single output of the SIMO converter,it is free from a cross-regulation issue.Figure 9.2.2 illustrates the overall archite

85、cture of the proposed SPT-PA,including the SPT modulator,28GHz CMOS PA,and SPT-adaptive-biasing network.The PA consists of a 2-stage differential amplifier with a driver and power stage.For impedance matching and DC blocking,transformers are implemented at the input,inter-,and output stages.The SIMO

86、 converter pre-regulates the 6-output voltages,and one of the SPT switches(SWSPT)is connected to the VDDPA,which is fed into the center tap of the output matching transformer of PA.In the conventional PA structure,the current mirror with the current source(IB_PA)and mirror transistor(MBN1)are used t

87、o bias the PA.However,as the VDDPA decreases due to the SPT operation,the DC current flowing through the PA is also decreased due to the reduced drain-source voltage(VDS),causing the drop of transconductance(gm1)and power gain(GP)at the fundamental frequency of 28GHz.To overcome this GP variation is

88、sue,the proposed SABN compensates for the decreasing GP as VDDPA reduces by pushing more bias current than the conventional biasing network.The additional bias current(IB_SPT)is generated by sensing the voltage difference between VDDPA and the maximum output voltage of the SIMO converter(VO_MAX=1.8V

89、),and the sensing gain is controlled by a sense-resistor(RSENSE).In this manner,the bias current of PA(IB_SUM)is the sum of IB_SPT and IB_PA.In the low VDDPA,the IB_SPT compensates for the decreased gm1,making GP constant to the VDDPA transitions.Therefore,SABN improves the PA linearity by mitigatin

90、g the PA gain variation of multilevel VDDPA.Figure 9.2.3 depicts the circuit implementations for the SPT modulator,including the 6-output SIMO DC-DC converter,inductor(1H),capacitors(4.7F),and SPT switches.The SPT switches controller handles the SPT switches,which determines which one of the SPT swi

91、tches is connected to the VDDPA by referencing the digital envelope input(DIN)transmitted from a DSP.The binary DIN can experience a timing skew while passing through from the DSP to the binary-1hot decoder in the chip,potentially causing glitches on VDDPA.To prevent this,the SPT switches controller

92、 has a de-skew function.By sensing the occurrence of an event at the DIN and activating it using the clock for the D-flip flop after a certain delay,the timing skew can be eliminated.The tunable delay in the de-skew block can also be used for RF-SM time alignment.The 6-output SIMO DC-DC converter is

93、 regulated by the error-based control with a maximum error selector(MES)7,and the buck switches are controlled by a type-II compensator,a PWM controller,a gate driver with a zero current sensor(ZCS),an over-current protection(OCP),and an over-voltage protection(OVP).The 6 SIMO switches are controlle

94、d by a finite state machine(FSM)according to MES output states:(1)if MES detects none of the channels(CH),the CH with the highest output voltage of SIMO converter(e.g.,VO=1.8V)turns on for SIMO switches,(2)if only 1 CH is detected,the CH detected by MES turns on,(3)if two or more CHs,including the o

95、ne where the SWSPT is ON,are detected,the corresponding CH turns on,(4)if two or more CHs,excluding the one where the SWSPT activates,are detected,the CH with a higher voltage level turns on.The proposed SPT-PA is fabricated in the 28nm bulk CMOS process.Figure 9.2.4 shows the measured waveforms of

96、the proposed SPT modulator:(1)with a non-uniformly distributed VDDPA(top-left)and(2)with a uniformly distributed VDDPA(bottom-left),which transition from a minimum VDDPA to a maximum VDDPA or with a minimum step.The proposed SPT modulator achieves up-and-down transition times of 20ns.The voltage gli

97、tch is eliminated due to the de-skew function from the re-timer in the SPT controller.As shown in Fig.9.2.5,the SPT voltage waveforms for the 5G FR2 64-QAM 400MHz are measured.The proposed SPT-PA architecture has a lower RMS VDDPA than the previous MLSC structure because it can effectively utilize a

98、ll VDDPA levels,which leads to better SM-PA system efficiency.Figure 9.2.5(bottom-left)shows the measured efficiency of the SPT modulator versus load current with the breakdown of the power loss.Total power consumption(including SPT modulator and PA)is measured,saving 21mW for a single PA core at 10

99、dB PBO during LV operation,which can save 336mW for a 16-element array system.The SABN reduces the gain variation from 3.8dB to 0.1dB,as shown in Fig.9.2.5(bottom-right).Figure 9.2.6(top)shows the modulated signal measurements with 400MHz 64-QAM under the SPT operation without the digital pre-distor

100、tion(DPD)with the average power-added efficiency of SPT-PA(PAEAVG,SPT)of 13.3%,which is 1.3x improved from the average power tracking(APT)with 10.2%PAEAVG.The SABN contributes 2.7%improvement to the PAE at 1.0V VDDPA by boosting the power gain and the output power.Overall performance summary and com

101、parison with prior arts are shown in Fig.9.2.6(bottom).The die micrograph is shown in Fig.9.2.7.Ac knowle dge me nt:The authors would like to acknowledge the Berkeley Wireless Research Center(BWRC)and the TSMC University Shuttle Program for chip fabrication.Figure 9.2.1:System comparison of the prev

102、ious architecture(heterogeneous integration)and proposed SPT-PA architecture(homogeneous integration).Figure 9.2.2:Detailed schematic of the SPT-adaptive-biasing network(SABN)and 28GHz CMOS power amplifier.Figure 9.2.3:Circuit implementations for the SPT modulator including 6-output SIMO DC-DC conve

103、rter and SPT switches.Figure 9.2.4:Measured voltage waveforms of SPT transitions:non-uniformly distributed VDDPA(top)and uniformly distributed VDDPA(bottom).Figure 9.2.5:Measured voltage waveforms(5G FR2 64-QAM 400MHz),the efficiency curve of the SPT modulator,and large-signal CW performances with S

104、PT-Adaptive-Biasing Network and SPT modulator.Figure 9.2.6:Measured SPT-PA performances and comparison table.ISSCC 2025/February 18,2025/8:25 AM181 DIGEST OF TECHNICAL PAPERS 9 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$3

105、1.00 2025 IEEEFigure 9.2.7:Die micrograph with a PA core area 0.12mm2.Re f e re nc e s:1 C.Kuo et al.,“A 5G FR2(n257/n258/n261)Transmitter Front-End with a Temperature-Invariant Integrated Power Detector for Closed-Loop EIRP Control,”I EEE RF I C,pp.175-178,June 2021.2 C.Chen et al.,“An 83.4%-Peak-E

106、fficiency Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 200MHz Bandwidth 5G New Radio RF Applications,”I SSCC,pp.496-497,Feb.2024.3 J.-S.Bang et al.,“2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Chan

107、nel Bandwidth and 93.6%Efficiency for 2G/3G/LTE/NR RF Power Amplifiers,”I SSCC,pp.236-237,Feb.2022.4 H.Pham et al.,“Adjustable 4-Level Hybrid Converter for Symbol Power Tracking in 5G New Radio,”I EEE APEC,pp.1858-1861,Mar.2023.5 J.-S.Paek et al.,“A 90ns/V Fast-Transition Symbol-Power-Tracking Buck

108、Converter for 5G mm-Wave Phased-Array Transceiver,”I SSCC,pp.240-241,Feb.2019.6 I.-H.Kim et al.,“A 950ns 0.5-to-5.5V 5G NR RF PA Supply Modulator with Floating Capacitor Control for Symbol Power Tracking,”I SSCC,pp.500-501,Feb.2024.7 M.-Y.Jung et al.,“An Error-Based Controlled Single-Inductor 10-Out

109、put DC-DC Buck Converter with High Efficiency at Light Load Using Adaptive Pulse Modulation,”I SSCC,pp.222-223,Feb.2015.182 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.3979-8-3315-4101-9/25/$31.00 2025 IEEE9.3 A 74W/48V Monolithic-GaN Integ

110、rated Adjustable Multilevel Supply Modulator for 5G Base-Station Massive-MIMO Arrays Hieu Minh Pham1,Peter Asbeck1,Donald F.Kimball1,Navneet Sharma2,Shenggang Dong2,Masoud Shahshahani2,Won Suk Choi2,Gary Xu2,Marcus Michel3,Ratul Das3,4,Robert Beach3,Hanh-Phuc Le1 1University of California,San Diego,

111、CA 2Samsung Research America,Plano,TX 3Efficient Power Conversion,El Segundo,CA 4University of Minnesota-Twin Cities,Minneapolis,MN Efficient power management for RF power amplifiers(PAs)is emerging as a critical requirement for the development and adoption of next-generation wireless communication

112、systems.To achieve higher transmitter efficiency,envelope tracking(ET)using supply modulators(SM)is widely used in todays systems.However,the demands for high bandwidth,complex modulation and multiple access schemes in 5G and upcoming 6G systems have exposed serious limitations of analog ET(AET)that

113、 get worse in high-power high-voltage applications,e.g.,base-station transmitters.As a promising alternative to AET,digital envelope tracking(DET)has proven its advantages and capabilities to support various signal bandwidths and power profiles 1-8.DET architectures in Figure 9.3.1 achieve higher ef

114、ficiency by separating the voltage generation(VG)stage and tracker(TR)stage,in which the former aimed for relatively slow but efficient generations of multiple voltage levels and the latter for fast voltage tracking.The key to a successful DET implementation relies on specific design,integration,and

115、 distribution of VG and TR stages in certain systems.Particularly in massive MIMO(mMIMO)base stations,the size,complexity,and stringent system layout requirements of the RF PA array 9 pose additional daunting challenges to power delivery.To provide higher power efficiency for the PA array,a DET SM c

116、an increase tracking resolution with a larger number of voltage levels.Conventional solutions achieve this by multiple high-voltage(HV)discrete power converters for VG,for simplicity,and discrete or integrated TR.A centralized discrete VG+TR SM solution(Figure 9.3.1,top right)can achieve high conver

117、sion efficiency 6,but suffers from serious supply ringing from fast TR transitions imposed on parasitic inductances of long SM-PA connections.Mismatches in PA supply impedance caused by distribution can further degrade beamforming and signal qualities.Adding large local decoupling capacitance can mi

118、tigate this problem at the cost of limiting SM speed and lowering system efficiency.A more favorable way to mitigate the supply problem is to keep a central VG stage but place TR units close to PA elements 5.This approach decouples and improves global and local supply impedances compared with the pr

119、evious solution.However,it requires multiple high-current VG-TRs paths,causing an undesirable trade-off between the number of voltage levels versus system routing complexity and loss.In addition,when all TR units share the same VG levels,high voltage margins are required to account for different pow

120、er profiles among PA elements that lower overall system efficiency and reduce DET benefits.There is therefore a strong motivation for a granular SM(gSM)solution that integrates and distributes both VG and TR locally to each PA unit(Figure 9.3.1,bottom).Local gSMs can provide individual supply profil

121、es at PA-subarray or even single-PA levels for different communication needs,e.g.,multiple access with different bandwidths,power,and symbol rates to save base-station and edge-device power consumption.While an integrated VG+TR solution was demonstrated at low voltage and power for mobile handsets,h

122、igh voltage and power demands remain the critical challenge to its design and application to mMIMO base stations.In this paper,as a solution for gSM for base station mMIMO arrays,we propose to design a monolithic-GaN integrated adjustable supply modulator(iASM)in Figure 9.3.1(bottom).The architectur

123、e includes both VG and TR stages on a single GaN die.The TR stage comprises 4 switches that provide fast voltage transitions for the PA from 4 voltage levels VO1-4 generated by a multilevel switched-capacitor converter(MLSC)in VG.To extend the voltage coverage to support more individual management t

124、o enhance the PA power saving and performance at a lower frequency such as at the 5G NR frame rate(100 Hz),the base level VOB of MLSC is adjusted by a buck level modulator(LM)8.As a result,VO1-4 can be adjusted to appropriate levels to provide unique voltage profiles for individual PAs.To meet the d

125、esign goals,a monolithic enhancement mode GaN-on-Si(e-GaN)process is chosen,leveraging low parasitic capacitance and low resistance while supporting high channel break-down voltages.Figure 9.3.2 shows the detailed architecture of the proposed design.VG employs a 4-level ladder SC converter with 8 sw

126、itches S1-8.TR consists of 4 one-hot switches,SO1 and 3 four-quadrant(4Q)switches SO2-4,that connect VOUT to one of VO1-4.The GaN process only supports e-GaN devices with the VGS breakdown voltage of 6V which requires careful design and layout to safely integrate and operate all the power switches,g

127、ate drivers,level shifters,and bootstrap circuits in the right voltage levels.Particularly,the design requires 9 isolated voltage supplies:VDR2-9 for S1-8 and SO11-42;VDRB for S2B from VDR1 and VDD,respectively.A stacked bootstrap structure is integrated to generate VDR2-9 and VDRB from VDD 10.While

128、 capable of supporting up to 50V input,the LM Buck input VINB can be connected to a lower voltage,e.g.,VO1 of an adjacent iASM IC in the array,to reduce the blocking voltage and switching loss of S1B and S2B.Implementation details of the eGaN FET bootstrap cell,the self-bootstrap gate driver,and 4Q

129、TR switch driver are illustrated in Figure 9.3.3.The eGaN FET bootstrap cell,shown in Figure 9.3.3(top left),is used in the stacked gate drivers of all VG switches to generate VDRX+1 from VDRX of the lower stage.In particular,SBTX is driven synchronously with the gate signal NGX of SX to charge CBST

130、X at VDRX to CBSTX+1 at VDRX+1.A cross-coupled switch(CCS)pair MBT1,2 and two capacitors CBT1,2 with CBT2 larger to drive SBTX with sufficient VGS.Careful design of SBTX and CBT2 sizes is needed to ensure low RDS,on for SBTX to maintain low voltage drop across 8 stacked bootstraps.The voltages VDR(2

131、X+1)=VOX+5V are also used for TR drivers.Shown together with its timing diagram in Figure 9.3.3(top right),the TR driver circuit for SO2-4 is formed by a back-to-back switch pair SOX1,2 sharing the source voltage VSNX.Since the lowest VOUT is VO1,VSNX and NG_ENX are driven by SBX and SPD to VO1 to s

132、afely keep SOX off.NG_ENX is driven to VDR(2X+1)to turn SOX ON which connects VOUT to VOX.SO1 driver is similar without SBX as SO1 source is at VO1.The self-bootstrap driver(SBD)shown in Figure 9.3.3(bottom)is used to power the gate drivers for S1-8,S1B,and S2B.Since drive strength is important for

133、proper timings for large power switches SX,their driver is implemented by switches MPU and MPD1-2 for pull-up and pull-down,respectively.While SX is turned on at VDRX by MPU,MPUs ON state requires a higher voltage at VDRX+5V,assuming VDRX-VSX=5V.To generate this voltage,an integrated bootstrap circu

134、it,a smaller version of the CCS bootstrap,is fully integrated in the SBD,including CBT1,2 implemented with on-chip MIM and MOS capacitors.Driving much smaller loads,the drivers for MPU and MPD can use a pull-up resistor in the absence of a complementary device,i.e.,d-GaN,with a reasonable cost of po

135、wer consumption.The same method is used to implement all other logic gates.MPU is driven by a locally bootstrapped VGDR from the respective VDRX voltage.To avoid excessive gate voltage on SX,a break-before-make operation for PU and PD,as shown in the timing diagram,is implemented in the non-overlap

136、generator.Figure 9.3.4 shows the power performance of the proposed iASM prototype on a 500nm GaN-on-Si process,measured using an NXP A5G35H120N power amplifier,LB=4.7H,CF1-3=5F,CO1-4=5F,and COUT=3nF.The iASM efficiency versus constant DC load currents at VIN=48V and different VINB of the LM stage is

137、 shown in Figure 9.3.4(top left).The DC efficiency increases by 3%at the smallest conversion output VO1 when VINB changes from 48V to a VO1-equivalent supply of 18V for the same VOB=8V.In a CW test at 3.5GHz(Figure 9.3.4,top right),the PA PAE improves by 9%at 42dBm output power by changing its volta

138、ge from VO4 to lower VO3,proving the benefit of SM.Peak PAE is 61%at 41dBm and the peak DC efficiency from a generated level is 95%.Peak CW power achieved on the PA is 46dBm,which indicates 74W provided by the iASM.To demonstrate the tracking capability at sub-symbol rates,the prototype is tested wi

139、th a modulated signal representing a downlink 20MHz channel at 8dB PAPR.Figure 9.3.4(bottom left)shows the PA drain voltage under 1MHz and 2MHz tracking frequency.As the TR frequency increases,the difference between envelope voltage and iASM output becomes smaller and thus more power is saved.The pe

140、rformance summary of system PAE and net DC power consumption with the 20MHz signal at different tracking frequencies is shown in Figure 9.3.4(bottom right).Using a sub-symbol TR rate at 2MHz,the full system PAE increases from 35.7%to 42.6%at 39dBm average POUT of the tested PA and gains 3.4W of DC p

141、ower saved.Early evaluations of the PA linearity while powered by the iASM prototype with modulated downlink signals are summarized in Figure 9.3.5.For 100MHz 16-QAM signal at 37dBm average output power,7.6%EVM and-28.05dBc ACLR are achieved with a simple digital pre-distortion and 1MHz TR frequency

142、.With a higher modulation scheme at 64-QAM,20MHz signal bandwidth,and 35.9dBm output power,the EVM is 8.1%and-32.28dBc ACLR.Overall performances of the iASM prototype are summarized and compared with prior arts in Figure 9.3.6.To the authors knowledge,this work shows the first effort to integrate a

143、complete digital supply modulator for granular power delivery for base-station mMIMO applications with the highest output power.The die micrograph and the prototype PCB are shown in Figure 9.3.7.Ac knowle dge me nt:This work was supported in part by the Center for Wireless Communications(CWC)at the

144、University of California San Diego,in part by Qorvo,Inc.and other CWC industry members,in part by Efficient Power Conversion Corporation(EPC),and in part by the National Science Foundation(NSF)Faculty Early Career Development Program(CAREER)under Award 2042525.The authors would also like to acknowle

145、dge generous supports in the full system test by Vitali Loseu and Chance Tarver at Samsung Research America.Figure 9.3.1:Conventional and proposed digital envelope tracking(DET)architectures and their power distribution characteristics in mMIMO base station applications.Figure 9.3.2:Detailed schemat

146、ic of the proposed integrated GaN adjustable supply modulator.Figure 9.3.3:CCS Bootstrap Cell schematic(top left);Tracker Driver schematic&timing diagram(top right);Self-Bootstrap Driver schematic&timing diagram(bottom).Figure 9.3.4:iASM DC Efficiency(top left);system PAE 3.5GHz CW power(top right);

147、DET waveforms(bottom left);system PAE different TR frequencies(bottom right).Figure 9.3.5:Measured EVM&ACLR of 16-QAM 100MHz signal(top);measured EVM&ACLR of 64-QAM 20MHz signal(bottom).Figure 9.3.6:Comparison with prior arts.ISSCC 2025/February 18,2025/8:50 AM183 DIGEST OF TECHNICAL PAPERS 9 2025 I

148、EEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 9.3.7:Die and PCB photographs.Re f e re nc e s:1 P.Asbeck and Z.Popovic,“ET Comes of Age:Envelope Tracking for Higher-Efficiency Power Amplifiers,”IEEE Microwave

149、Magazine 2016.2 J.-S.Bang et al.,“2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6%Efficiency for 2G/3G/LTE/NR RF Power Amplifiers,”2022 IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2022.3 C.Chen,X.Li,R.Hu and L.Cheng,“An 8

150、3.4%-Peak-Efficiency Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 200MHz Bandwidth 5G New Radio RF Applications,”2024 IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2024.4 C.Nogales,L.Ma

151、rzall,G.Lasser and Z.Popovi,“Dynamic Supply Modulation of a 6-12 GHz Transmit Array,”2023 IEEE Wireless and Microwave Technology Conference(WAMICON).5 T.Cappello,C.Florian,D.Niessen,R.P.Paganelli,S.Schafer and Z.Popovic,“Efficient X-Band Transmitter With Integrated GaN Power Amplifier and Supply Mod

152、ulator,”IEEE Transactions on Microwave Theory and Technique 2019.6 N.Wolff,W.Heinrich and O.Bengtsson,“Highly Efficient 1.8-GHz Amplifier With 120-MHz Class-G Supply Modulation,”IEEE Transactions on Microwave Theory and Techniques 2017.7 A.Sepahvand,P.Momenroodaki,Y.Zhang,Z.Popovi and D.Maksimovi,“M

153、onolithic multilevel GaN converter for envelope tracking in RF power amplifiers,”2016 I EEE Ene rgy Conve rs i on Congre s s a nd Ex pos i ti on(ECCE),Milwaukee,WI,USA,2016.8 H.Pham,R.Das,C.Hardy,D.Kimball,P.Asbeck and H.-P.Le,“Adjustable 4-Level Hybrid Converter for Symbol Power Tracking in 5G New

154、Radio,”2023 IEEE Applied Power Electronics Conference and Exposition(APEC),Orlando,FL,USA,2023.9 5G America,“Advanced Antenna Systems for 5G”,2019 Technical White Paper.10 C.Chen,J.Liu and H.Lee,“A 2.5-5MHz 87%Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network wit

155、h Capacitor-Assisted Dual-Inductor Filtering,”2022 IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2022.184 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.4979-8-3315-4101-9/25/$31.00 2025 IEEE9.4 A 102ns/V 94.3%

156、-Peak-Efficiency Symbol-Power-Tracking Supply Modulator for 5G NR Power Amplifiers Minghao Shang,Baochuang Wang,Changjin Chen,Ji Jin,Lin Cheng University of Science and Technology of China,Hefei,China As 5G communication technology advances,the power consumption of radio frequency power amplifiers(R

157、FPAs)in 5G systems has become increasingly critical.To enhance efficiency,Symbol Power Tracking(SPT)has emerged as a key technique,allowing dynamic adjustment of the RFPA supply voltage to match the instantaneous power demands of each symbol.SPT must achieve these voltage transitions within the brie

158、f duration of the cyclic prefix(CP),as short as 1.17s in frequency range 1(FR1:410MHz 7125MHz),posing significant design challenges.Hybrid buck-boost converters without a right half-plane(RHP)zero are introduced in 1,2 to improve tracking speed.However,their MHz-range switching frequency,needed for

159、high efficiency,requires large output capacitors(CL)and inductors,limiting tracking speed to the order of microseconds per volt(s/V).Auxiliary LDOs are often added in parallel to accelerate CL charging 3,but this significantly degrades dynamic efficiency during tracking.In 4,a split-capacitor approa

160、ch is employed,dividing CL into a large capacitor(4.7F)and a smaller one(470nF).The large capacitor is floated during tracking to allow rapid charging of the smaller one,followed by slow charging of the large capacitor via an LDO.This method still degrades dynamic efficiency and limits the minimum s

161、ymbol duration to 30s.A complex SPT structure involving capacitor swapping and pre-charging is proposed in 5.The current draw from the LDOs is reduced as it only needs to charge a 220nF capacitor,with the main 4.7F pre-charged by the switching converter.However,the symbol duration remains limited,an

162、d this structure requires numerous off-chip components.In this paper,we propose a new SPT structure that breaks the trade-off between dynamic efficiency,tracking speed and minimum symbol duration in existing designs.As shown in Fig.9.4.1,the proposed supply modulator consists of a main 3-level buck-

163、boost(3L-BB)converter 1,a secondary 3L-BB converter,two 1H inductors(LM and LS),a 470nF flying capacitor(CAC),a 220nF output capacitor(CL),and two SPT mode switches(S6 and S7).Each 3L-BB converter includes five switches and one flying capacitor(CFM and CFS).The small CL enables the modulator to achi

164、eve fast up-tracking(510ns/5V)and down-tracking(900ns/5V)speeds without relying on an LDO for charging or discharging,while maintaining a low output voltage ripple VOUT(12mV)even at a 2MHz switching frequency.Figure 9.4.2 explains the operating principle of the proposed modulator,with its control st

165、ructure shown in Fig.9.4.1.In steady-state operation,S6 is turned on,and S7 is turned off.Similar to the ripple-cancellation technique proposed for the buck converter in 6,the main 3L-BB converter uses peak current-mode control to generate a proper PWM signal(PWMM)for regulating the output voltage(V

166、OUT).Meanwhile,the secondary 3L-BB converter operates in an open loop,controlled by the inverted PWMM signal(PWMS),generating a reversed inductor current ripple in LS that counteracts the ripple in LM.With opposite current slopes in the two inductors,the current flowing into CL is nearly zero with m

167、inimal ripple,resulting in a small VOUT of less than 12mV even with just a 220nF CL.Note that CAC blocks the DC current from the secondary 3L-BB converter,ensuring that only AC current flows through the secondary 3L-BB converter and LS.This reduces conduction loss and allows LS to be much smaller in

168、 size than LM.For the main 3L-BB converter,VSW1 swings between VIN and 0 in buck mode(when VOUTVIN).Hence,the voltage across CAC(VAC)is VIN2VOUT in buck mode and 3VIN2VOUT in boost mode,as derived in Fig.9.4.2.In SPT mode,S6 must be turned off;otherwise,the opposite current direction in LS would pre

169、vent LM from charging or discharging CL.S7 is then turned on to connect CAC to VIN,and the secondary 3L-BB converter operates in a closed loop with hysteresis control to rapidly regulate VAC to the desired level set by SPT.This means the two 3L-BB converters independently track the voltages on CL an

170、d CAC.Since both CL and CAC are as small as 220nF and 470nF,fast tracking speeds can be achieved with high dynamic efficiency,eliminating the need for LDOs as in previous designs.After tracking is accomplished,CAC should be connected to VOUT for ripple cancellation.As shown in Fig.9.4.3,to avoid dis

171、rupting VOUT,S6 must be turned on precisely at the zero-current crossing in LS,while PWMS takes over control of the secondary 3L-BB.However,due to circuit delays and mismatches,achieving a perfect transition without disrupting VOUT is extremely challenging.To address this issue,auxiliary LDOs are in

172、troduced to shape VOUT within a predefined window of approximately VOUT150mV.It is important to note that the LDOs are forced off during the tracking period to prevent dynamic efficiency degradation and are automatically deactivated in steady-state,ensuring no impact on steady-state efficiency.The L

173、DOs consist of two PLDOs for sourcing current and one NLDO for sinking current.The PLDOs need to be powered by a voltage source higher than VOUT,which can only be provided by the flying capacitor in the 3L-BB converters during the phase when they are pumped to 2VIN in boost mode.Thanks to the comple

174、mentary operation of the two 3L-BB converters,either CFS or CFM is always pumped to 2VIN.Therefore,two PLDOs,each using CFS or CFM as the power supply,are required for continuous shaping of VOUT.The proposed SPT modulator is fabricated in a 0.18m BCD process.The power stages switch at 2MHz with two

175、1H inductor(LM with DCR of 15m,LS with DCR of 150m),one 220nF output capacitor,one 470nF flying capacitor for ripple cancellation,two 10F flying capacitor for 3L-BB converters.Figure 9.4.4 shows the measured steady-state waveforms of VOUT,ILM and ILS.Due to the ripple-cancellation technique,the two

176、inductors exhibit reversed inductor current ripples,resulting in low output voltage ripples,even with a 220nF output capacitor.As depicted in Fig.9.4.4,ILM includes a 500mA DC current,matching the load current,and a 450mA current ripple,while ILS exhibits only a 450mA current ripple and zero DC curr

177、ent due to the presence of CAC in the structure when VIN=4V,VOUT=5.5V.This allows LS to use a compact inductor(1.60.81mm3)without compromising efficiency(e.g.,only 2.75mW loss on LS when VIN=4V,VOUT=5.5V,IO=0.5A,and the total loss is 175mW).Figure 9.4.4 also shows the measured efficiency under diffe

178、rent VOUT and ILOAD,with a peak efficiency of 94.3%.Figure 9.4.5 presents the measured transitions of the SPT modulator.The proposed design achieves rapid transitions,with rise and fall times of 510ns and 900ns,respectively,for a voltage change between 0.5V and 5.5V.This results in fast up-and down-

179、tracking speeds of 102ns/V and 180ns/V,respectively.Figure 9.4.6 summarizes the performance of the proposed SPT modulator and compares it with state-of-the-art designs.Thanks to the ripple-cancellation and SPT mode transition techniques,this modulator achieves a low output voltage ripple of 12mV usi

180、ng only 220nF CL and enables fast voltage tracking without the need for auxiliary current paths provided by LDOs during tracking,which incurs additional loss as in 3.Moreover,it eliminates the use of pre-charging technique by a buck converter before tracking as in 5,or slow-charging technique by an

181、LDO after tracking as in 4,both of which would limit the minimum symbol duration.This modulator achieves more than 8 faster up-tracking and 5 faster down-tracking speeds compared with those in 1,2.Figure 9.4.7 shows the die micrograph of the structure that occupies a silicon area of 1.54.4mm2.Ac kno

182、wle dge me nt:This work was supported in part by the National Natural Science Foundation of China under Grant No.62261160647.Corresponding author:Lin Cheng().Figure 9.4.1:System architecture of the proposed SPT modulator with small output capacitor.Figure 9.4.2:Operation principle of the proposed SP

183、T modulator in the steady state and the SPT mode.Figure 9.4.3:Auxiliary LDOs for VOUT shaping during mode transition.Figure 9.4.4:Measured waveforms of steady state and efficiency.Figure 9.4.5:Measured waveforms of up and down transitions.Figure 9.4.6:Performance summary and comparison with prior ar

184、ts.ISSCC 2025/February 18,2025/9:15 AM185 DIGEST OF TECHNICAL PAPERS 9 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 9.4.7:Die micrograph of the proposed modulator.Re f e re nc e s:1 J.Baek et al.,“A Vo

185、ltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8%Power Efficiency and 0.87s/V DVS Rate,”I SSCC,pp.202-203,Feb.2020.2 J.Ruan et al.,“A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost Convert

186、er Without RHP Zero Achieving 97.3%Peak Efficiency 6s Recovery Time and 1.13s/V DVS Rate,”I SSCC,pp.148-149,Feb.2024.3 P.Xu et al.,“A 0.15-s/V Buck-Boost Symbol-Power-Tracking Supply Modulator With Dual Auxiliary Current Paths and EPP Scheme for 5G NR Power Amplifiers,”I EEE TCAS-I,vol.70,no.11,pp.4

187、660-4670,Nov.2023.4 I.-H.Kim et al.,“A 950ns 0.5-to-5.5V 5G NR RF PA Supply Modulator with Floating Capacitor Control for Symbol Power Tracking,”I SSCC,pp.500-501,Feb.2024.5 J.-S.Paek et al.,“A 90ns/V Fast-Transition Symbol-Power-Tracking Buck Converter for 5G mm-Wave Phased-Array Transceiver,”I SSC

188、C,pp.240-241,Feb.2019.6 J.Wibben and R.Harjani,“A High-Efficiency DCDC Converter Using 2 nH Integrated Inductors,”I EEE J SSC,vol.43,no.4,pp.844-854,Apr.2008.186 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.5979-8-3315-4101-9/25/$31.00 2025

189、IEEE9.5 A Sub-1V,50mV Dropout LDO Using Pseudo-Impedance Buffer with Phase-Margin Improvement Design Young-Jun Jeon,Jeong-Hun Kim,Won-Gyu Kim,Sung-Wan Hong Sogang University,Seoul,Korea As technology continues to scale down,the supply voltage(VIN)of systems has gradually decreased.At the same time,d

190、evices require a larger load current(IL)due to a higher performance of the system.Accordingly,it is important that a low-dropout regulator(LDO)operates at low-VIN(specifically sub-1V)and drives heavy IL at the same time.Digital LDOs have been used in sub-1V applications.However,they suffer from a la

191、rge output voltage(VOUT)ripple 1 even with an off-chip output capacitor(CO)because of a limit cycle oscillation.On the other hand,the analog LDOs are free from the VOUT ripple.When an analog LDO uses a CO,a multi-stage structure usually has a narrow bandwidth(BW)and becomes unstable under light load

192、 conditions.This is because Miller compensation is not effective in this case.Therefore,to stably handle light load or even no-load conditions while maintaining sufficient BW at low-VIN,the LDO needs to be designed as a low-VIN structure,comprising a single-stage error amplifier(EA),a buffer,and a p

193、ass transistor(MP),avoiding the use of Miller compensation,as shown in Fig.9.5.1(top).In low-VIN analog LDOs,a current mirror(CM)buffer that composes the CM with the MP has been commonly used because this buffer properly operates with a small voltage headroom and has a relatively low resistance of 1

194、/gm,which widens BW.This CM buffer can be driven by a simple EA 2 or a transconductance(Gm)boosting cell 3-4,as shown in Fig.9.5.1(top-left and-middle),respectively.Since the EA cannot adopt a cascode structure due to the voltage headroom,an LDO that uses the EA exhibits a low DC gain,particularly w

195、hen supplying a large IL.Moreover,the output pole of the EA(EA)limits the BW under the heavy load condition.On the other hand,the Gm-boosting cell can have a higher gain than that of the simple EA while it does not have a low frequency EA because the Gm cell commonly comprises several current mirror

196、s of which ratio is larger than one.However,LDOs with not only the EA but also the Gm-boosting cell have limitations in supplying a wide range of IL because of the CM buffer.To supply a large IL,the ratio(K)between a CM buffer transistor(MC)and the MP must be high.However,with the high K(K2),the LDO

197、 cannot properly supply a small IL.This is because the bias current of MC(IC)becomes considerably small in this case,which increases the buffer resistance,and finally shifts the gate pole of the MP(G)to the low frequency.This phenomenon could be severe when the LDO uses the Gm-boosting cell because

198、the conventional Gm cell has a bias current related to the IL.On the other hand,when the ratio K is low(K1),the LDO can supply a small IL.However,this limits supplying a large IL due to the limited source-gate voltage(VSG)of the MP by the limited voltage headroom,especially in sub-1V VIN LDOs.Becaus

199、e of these reasons,previous LDOs using the CM buffer cannot cover a wide range of IL,as shown in Fig.9.5.1(top-right),and usually focus on the light IL to cover the no-load condition 24.To solve these problems,this paper proposes a rail-to-rail pseudo impedance buffer(RRPB)and a load independent Gm-

200、boosting cell(LIGC)as shown in Fig.9.5.1(bottom).Even though the RRPB is designed based on the CM buffer,the bias current of the proposed buffer remains almost unchanged compared with the previous CM buffers,as shown in Fig.9.5.1(top-right).In addition,the bias current of LIGC is also almost indepen

201、dent of the IL,which is in contrast to previous Gm-boosting cells.Thus,the bias current of the LDO merely changes over wide range of IL,which allows the MP to have a considerably high aspect ratio.As a result,the proposed LDO can supply much wider range of IL from no-load to hundreds of mA even at s

202、ub-1V VIN with a smaller dropout voltage(VDO)than previously reported LDOs 2-5.Meanwhile,the overall gain is obtained through the contributions of the LIGC,RRPB,and MP,as shown in Fig.9.5.1(bottom-right).Unlike the CM buffer that has a gain of 1,the RRPB has a gain of around 20 dB.In addition,the ou

203、tput stage has a much higher gain than that of previous low-VIN LDOs because the aspect ratio of the MP is much higher.Therefore,the proposed LDO has a higher gain than previous low-VIN LDOs.In addition,the RRPB has a smaller output resistance than that of the CM buffer.Therefore,despite a large par

204、asitic capacitance of the MP,the G can be located at a high frequency,which extends the BW.Figure 9.5.2(top)shows a schematic of the proposed LDO including the overall loop TOV(s),the buffer loop TBL(s),and Miller feedback loop TML(s).Figure 9.5.2(middle-left)indicates the bias current of the RRPB i

205、n relation to the load conditions.Under no or light load conditions,VSG,P of MP is small.In this case,the voltage at node N7 is higher than that of node N6,generating current that flows from N7 to N6 through R2.On the other hand,under heavy IL conditions,the VSG,P is large,which makes the voltage at

206、 node N7 lower than that of node N6.Thus,the current flows from N6 to N7 through R2.Comparing these two cases,the maximum variation of the total bias current is only 2(K1+K2+1)IR2 and this can be optimized by selecting a proper value of R2.Figure 9.5.2(middle-right)shows the transfer function of the

207、 RRPB,ARRPB(s),from its input(VIN,BUF)to output(VG,P).Since the RRPB has an internal feedback loop TBL(s),the ARRPB(s)is obtained by dividing the open-loop gain of RRPB,ARRPB,OL(s),by 1+TBL(s).When R2 is not used(Ca s e 1:R2=0),DC gain of ARRPB(s)is unity and the cut-off frequency(C)is shifted to a

208、higher frequency by the BW of TBL(s).Thus,it is possible to locate G at a higher frequency than the unity-gain frequency(u)of the TOV(s),which makes the LDO stable.However,a zero value of R2 can cause a huge variation of the bias current in RRPB like the conventional CM buffer.As explained previousl

209、y,with the proper value of R2(Case 2:R2 0),the variation of bias current in RRPB can be optimized.However,R2 increase the DC gain of ARRPB(s)and cannot sufficiently shift its C to a higher frequency due to the narrower BW of TBL(s).This results in the G being located at a lower frequency than u of t

210、he TOV(s),causing a stability problem.To take advantages of both case 1 and case 2,a capacitor CH is added in parallel to the R2(Thi s work:R2 0,CH 0).At a low frequency where the impedance of CH is large enough,the ARRPB(s)and TBL(s)follow those of the case 2.On the other hand,at a high frequency w

211、here the impedance of CH is small enough,the ARRPB(s)and TBL(s)follow those of the case 1.Therefore,a pair of zero-pole is inserted in ARRPB(s)and TBL(s),which finally locates G at a higher frequency than u of the TOV(s).As a result,the RRPB can avoid the stability problem and prevent a huge variati

212、on in the bias current regardless of IL.Along with the RRPB,the LIGC is designed by adopting the similar structure of the RRPB.Therefore,the gain of LIGC can be determined by a value of R1,as shown in Fig.9.5.1(bottom-left).Since there is a limitation in increasing R1 because G can be located at a l

213、ower frequency than the u.It is important to select the appropriate value of R1 to optimize the gain and BW.Figure 9.5.3(top-left)illustrates a transfer function of the overall LDO,TOV(s),which is determined by the product of gains of LIGC ALIGC(s),RRPB ARRPB(s),and the output stage gmpZL(s).As anal

214、yzed in Fig.9.5.2,the RRPB introduces a zero zero that can make the LDO stable.However,as IL increases,a pole at the output of the LDO(OUT)is pushed to a higher frequency,which degrades the phase margin(PM).To solve this problem,the proposed LDO uses the Miller feedback loop TML(s),as shown in Fig.9

215、.5.3(top-middle).At light IL,TML(s)has a mid-frequency gain lower than 0 dB,which has no effect on TOV(s).This is because OUT is located at a low frequency.In this condition,TOV(s)without the effect of TML(s)is stable enough.On the other hand,as IL increases,OUT can be located near the 2nd pole(2nd)

216、,which can cause an insufficient PM even with the inserted zero.In this condition,since TML(s)can have a gain higher than 0dB,TML(s)splits two poles to improve the PM.In this design,the TML(s)has a moderate gain to not reduce the BW,while only improving PM.Meanwhile,to enhance the undershoot respons

217、e,a significant sinking current for the gate capacitance(CG)is necessary,which is implemented by RRPB,as shown in Fig.9.5.3(bottom-left).Similarly,to improve the overshoot response,a significant sourcing current for CG is required,which is achieved by the overshoot reduction circuit,as shown in Fig.

218、9.5.3(bottom-middle).Figure 9.5.3(right)shows the optimal values of passive components used in the proposed LDO.A simulated frequency response based on the PCB model is shown in Fig.9.5.4(left).The PCB model includes several components;Multilayer ceramic capacitors with the SPICE netlist along with

219、the estimated resistance(RPCB)and inductance(LPCB)of the PCB.Figure 9.5.4(top-right)shows PM and gain margin(GM)in relation to IL.Figure 9.5.4 (right-bottom)plots the measured power supply rejection(PSR).Figure 9.5.5(left)shows the measured load transient responses as IL transitions between 0 A and

220、the maximum IL with different values of VDO.Although the proposed LDO is an analog LDO,the proposed LDO provides IL of 0.12 A at VIN=0.8 V with a VDO of 0.05 V,owing to the considerably high aspect ratio of MP.Figure 9.5.5(right)compares IL and VIN of the proposed LDO and other LDOs using an off-chi

221、p CO.A comparison table is shown in Fig.9.5.6.Among the state-of-the-art LDOs listed in the comparison table,the proposed LDO has the smallest load regulation despite the largest IL and the smallest VDO.Figure9.5.7 shows a chip micrograph.Ac knowle dge me nt:This work was supported by National Resea

222、rch Foundation of Korea(NRF)Granted funded by the Korea government(MSIT)under Grant RS-2023-00207919 and IITP-2024-RS-2023-00260091,and by LX Semicon.Figure 9.5.1:Problems of ALDO and DLDO operating at Low-VIN(top);Concepts of the Proposed Sub-1V ALDO(bottom).Figure 9.5.2:Overall Schematic of the Pr

223、oposed Circuit(top);Biasing Characteristics of RRPB(middle-left);Features of LIGC on TOV(s)(bottom-left);Explanation of Pseudo Impedance Buffer Concept(bottom-right).Figure 9.5.3:Frequency Response of TOV(s)(top-left)and Effect of TML(s)on TOV(s)(top-middle);Undershoot Response with RRPB(bottom-left

224、)and Overshoot Response(bottom-middle);Optimal Passive Component Values in the Proposed LDO(right).Figure 9.5.4:Simulated Frequency Response(left);Phase and Gain Margins(top-right);Measured Power-Supply-Rejection(bottom-right).Figure 9.5.5:Measured Load Transient Response(left)and Comparison with Pr

225、ior Works(right).Figure 9.5.6:Performance Summary and Comparison with ALDOs using External Capacitor.ISSCC 2025/February 18,2025/9:30 AM187 DIGEST OF TECHNICAL PAPERS 9 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 202

226、5 IEEEFigure 9.5.7:Chip micrograph.Re f e re nc e s:1 D.-H.Jung et al.,“A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS,”I SSCC,pp.414-415,Feb.2021.2 Y.-H.Lam et al.,“A 0.9V 0.35 m Adaptively

227、 Biased CMOS LDO Regulator with Fast Transient Response,”I SSCC,pp.442-626,Feb.2008.3 A.Maity et al.,“A Hybrid-Mode Operational Transconductance Amplifier for an Adaptively Biased Low Dropout Regulator,”I EEE Tra ns.Powe r Ele c troni c s,vol.32,no.2,pp.1245-1254,Feb.2017.4 X.Ming et al.,“A High-Eff

228、iciency and Fast-Transient Low-Dropout Regulator With Adaptive Pole Tracking Frequency Compensation Technique,”I EEE Tra ns.Powe r Ele c troni c s,vol.35,no.11,pp.12401-12514,Feb.2020.5 N.Adorni et al.,“A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply,”I EEE J SSC,vol.55,no.2,pp.404-413,Fe

229、b.2020.6 W.-C.Chen et al.,“94%Power-Recycle and Near-Zero Driving-Dead-Zone N-Type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient of Flash Memory in Smart Phone,”I SSCC,pp.436-437,Feb.2018.7 X.Ming et al.,“An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To

230、Sub-10-s Short-Period Load Transient,”I EEE J SSC,vol.59,no.2,pp.583-594,Feb.2024.188 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.6979-8-3315-4101-9/25/$31.00 2025 IEEE9.6 A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simult

231、aneously Charged in a Half Cycle Achieving 92.2%Efficiency and 131mW Output Power Quanrong Zhuang1,Junyi Sun1,Bo Li1,Jie Lu1,Xin Zhang2,Yi Shi1,Hao Qiu1 1Nanjing University,Nanjing,China 2IBM T.J.Watson Reseach Center,Yorktown Heights,NY Wireless power transfer to implanted devices is an elegant sol

232、ution that can obviate the need for batteries 15.As more functions are implemented in the implanted devices,more than one output voltages are typically requested for the optimal performance 6.For example,a low output voltage(VOUT2)is used for biopotential recording whereas a high output voltage(VOUT

233、1)is used in the back-end circuitry for neurostimulation.The requirements on VOUT1 and VOUT2 are different 7.The front-end recording circuitry requires a stable and accurately regulated VOUT2 whereas the back-end stimulation circuitry necessitates a high bandwidth to support a high load current at V

234、OUT1.An obvious design is to use two stages comprising a rectifier followed by a dual-output regulator 8,9.On the other hand,the single-stage dual-output(SSDO)design 1015 is advantageous with an improved power conversion efficiency(REC)and a reduced form factor.Figure 9.6.1(left)shows several repres

235、entative single-stage multi-output rectifier topologies.In 10,a 125kHz rectifier comprising four PMOS active diodes was proposed.Since the half-wave rectification is employed,it suffers from low output power(POUT)and high ripple voltages.Additionally,VOUT1 and VOUT2 must be close to each other,other

236、wise REC will degrade fast.The rectifier in 11 suffers from a low POUT due to its half-bridge topology.In 12,VOUT2 with the half-wave rectification still suffers from a high ripple voltage.Moreover,owing to a shared total charging time in a half cycle,that for VOUT1 is decreased and thus degrades it

237、s POUT.In 13,implemented by six PMOS active diodes,the rectifier employs the time-multiplexing charging for three outputs in a half cycle.As a result,VOUT1 suffers from a limited charging time and thus degrades its POUT.Furthermore,all above topologies are implemented using PMOS active diodes,which

238、could induce larger power loss including switching loss and conduction loss 16.Being aware of the shortcomings of these works,we proposed to implement a 6.78MHz SSDO rectifier using only three NMOS active diodes,which achieved a high peak REC of 92.2%.Since it supported the simultaneous charging of

239、VOUT1 and VOUT2 in a half cycle rather than in a time-multiplexing manner,a high POUT of 131mW was obtained.Furthermore,owing to the proposed charge distribution(CD)operation mode,the rectifier eliminated a large drop voltage during a large load transient at VOUT2.As a result,with two small off-chip

240、 output capacitors(150nF and 200nF),VOUT1 and VOUT2 were successfully regulated at 3.3V and 1.6V,respectively.The ripple voltages of VOUT1(VOUT1,ripple)and VOUT2(VOUT2,ripple)were as small as 50mV and 75mV,respectively.The proposed SSDO rectifier consists of a pair of cross-connected PMOS transistor

241、s(MP1 and MP2),three NMOS active diodes(MN1,MN2,and MN3),and two short switches(S1 and S2).MP1 and MP2 do not contribute to the switching loss as their input parasitic capacitances are considered as part of the resonant capacitor at the rectifier input.Their conduction loss is minimized through usin

242、g a large transistor size.As is shown in Fig.9.6.2,the rectifier can be reconfigured into four operation modes:dual-side charging(DSC)(1),high-side charging(HSC)(2),freewheeling(FW)(3),and CD(4)modes.The selectable modes depend on the condition of the load current at VOUT2(I2).When I2 is under light

243、 condition,the rectifier operates in DSC,HSC,and FW modes.In the DSC mode,MN2,MN3,and MP1 are turned on.VOUT1 and VOUT2 can be simultaneously charged in a half cycle through current IAC1/IAC2 and IAC3,respectively,and thus both increases.In the HSC mode,MN2 and MP1 are turned on,and only VOUT1 is ch

244、arged through IAC1/IAC2.In the FW mode,S1 and S2 are turned on and both VOUT1 and VOUT2 decrease.By detecting the voltage levels of VOUT1 and VOUT2,the controller generates corresponding logic states to regulate VOUT1 and VOUT2 into hysteresis windows VREF1L,VREF1H and VREF2L,VREF2H,respectively.Dur

245、ing the total regulation period,the rectifiers power loss is dominated by active diodes 11.Compared with previous topologies,we implemented the active diodes using NMOS rather than PMOS and furthermore its number is reduced to three,which results in less power loss and a higher REC.If I2 switches to

246、 a heavy condition,the voltage regulation(especially for VOUT2)becomes challenging.The worst case happens at the FW period where both VOUT1 and VOUT2 are decreasing.As is shown in Fig.9.6.3(top),since the transient of I2,VOUT2 starts to decrease in a faster path to reach VREF2L first.However,this in

247、stant cannot trigger the DSC mode,otherwise VAC1 and VAC2 will increase substantially to undesirably charge VOUT1 through body diodes of MP1 and MP2.The decreasing trend of VOUT1 does not stop until VOUT1 reaches VREF1L such that the FW mode ends.As a result,a large drop voltage of VOUT2 cannot be a

248、voided.On the other hand,this can be solved by the proposed CD mode together with another reference voltage(VCD)in the controller.As is shown in Fig.9.6.3(bottom),the FW mode ends when VOUT2 reaches VCD,which is followed by the DSC mode.VOUT2 stops decreasing and starts to increase.Furthermore,at th

249、e end of the DSC mode,by turning off MN2,a current path from VOUT1 to VOUT2 emerges and the proposed CD mode starts.Through this current path,the accumulated charge at VOUT1 during the DSC mode helps alleviate the problem of insufficient charging current for VOUT2.The duration of CD mode(TCD)is opti

250、mized to maintain a high gate-to-source voltage for MP1 to offer a small ON-resistance.After several cycles,VOUT2 reaches VREF2H,which then triggers the FW mode.Thus,by the proposed CD mode,a large drop voltage is eliminated and VOUT2 is successfully regulated within the hysteretic window VCD,VREF2H

251、.The proposed SSDO rectifier was fabricated in a 0.18m CMOS process and occupied a chip area of 1.63mm2.The maximum load currents I1 at VOUT1 and I2 at VOUT2 were designed as 33mA and 15mA,respectively,for a maximum POUT of 131mW.Under different combinations of light/heavy load conditions for I1 and

252、 I2,VOUT1 and VOUT2 were successfully regulated at 3.3V and 1.6V,respectively,within corresponding hysteresis windows(Fig.9.6.4).It is noted that,VOUT1,ripple and VOUT2,ripple were as small as 50mV and 75mV with two small output capacitors C1 of 150nF and C2 of 200nF,respectively.In the steady state

253、,GN1,GN2,and GN3 notified the rectifiers four operation modes.Measured load transient waveforms in Fig.9.6.5(top)demonstrated negligible load transient response and unnoticeable cross regulation between two outputs.When I2 changed from 1mA to 15mA at I1 of 33mA,owing to the proposed CD mode,a neglig

254、ible drop voltage was guaranteed.Figure 9.6.5(bottom left)shows the measured REC of the rectifier.By replacing PMOS to NMOS active diodes and reducing its number to three in the power stage,the proposed rectifier achieved a peak REC of 92.2%at POUT of 72.6mW.When I2 is under the heavy condition and

255、I1 changes from heavy to light conditions,a high REC is maintained owing to the proposed CD mode.Figure 9.6.5(bottom right)and Fig.9.6.6 show the performance comparisons.Compared to previous SSDO rectifiers,this work achieved the highest REC and POUT.The figure of merit(FoM)for VOUT1,ripple and VOUT

256、2,ripple,defined as I1/(f C1VOUT1)+I1/(f C2VOUT2)100%,is used for comparison.This work has the best FoM among the state-of-the-art designs that we have compared it with and are shown in Figs.9.6.5 and 9.6.6.Figure 9.6.7 shows the photographs of the proposed SSDO rectifier and experimental setup.Ac k

257、nowle dge me nt:This work was financially supported by the National Natural Science Foundation of China(62374082,62341408,T2221003),and the National Natural Science Foundation of China for Excellent Young Scholars(Overseas),the Engineering Research Center of Opto-Electro Materials and Chip Technique

258、s,Nanjing University,Nanjing 210023,and the Interdisciplinary Research Center for Future Intelligent Chips,Nanjing University,Suzhou 215163,China.Figure 9.6.1:Conventional single-stage dual-output and triple-output rectifier topologies(left)and the proposed dual-output rectifier topology(right).Figu

259、re 9.6.2:Reconfigurable four operation modes of the proposed rectifier(top)and waveforms under light load condition at VOUT2(bottom).Figure 9.6.3:Simulated operation waveforms during a large load transient at VOUT2 with and without the proposed CD mode.Figure 9.6.4:Measured steady-state waveforms un

260、der different combinations of load conditions at VOUT1 and VOUT2.Figure 9.6.5:Measured load transient waveforms,power efficiencies,and performance comparisons with other SSDO rectifiers.Figure 9.6.6:Performance summary and comparisons.ISSCC 2025/February 18,2025/10:05 AM189 DIGEST OF TECHNICAL PAPER

261、S 9 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 9.6.7:Die micrograph of the proposed SSDO rectifier(left)and photo of a PCB prototype(right).Re f e re nc e s:1 G.L.Barbruni et al.,“Miniaturised Wirele

262、ss Power Transfer Systems for Neurostimulation:A Review,”I EEE Tra ns.Bi ome d.Ci rc ui ts Sy s t.,vol.14,no.6,pp.1160-1178,Dec.2020.2 Q.Duan et al.,“A 40.68-MHz Active Rectifier Using an Inverter-Based Conduction-Time Generator for Wirelessly Powered Implantable Medical Devices,”I EEE TCAS-I I,vol.

263、69,no.11,pp.4334-4338,Nov.2022.3 S.-W.Hong,“A Resonant Current-Mode Wireless Power and Data Receiver for Loosely Coupled Implantable Devices,”I EEE J SSC,vol.55,no.12,pp.3200-3209,Dec.2020.4 H.Qiu et al.,“A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System with Efficiency Maximization by

264、Adaptive Magnetic Field Adder IC,”I EEE J SSC,vol.57,pp.2390-2403,Jun.2022.5 Q.Zhuang et al.,“A 6.78 MHz Wireless Power and Data Transfer System Achieving Simultaneous 52.6%End-to-End Efficiency and 4.0 Mb/s Forward Data Delivery with Interference-Free Rectifier,”I EEE Sy mp.VLSI Ci rc ui ts,pp.1-2,

265、Jun.2024.6 M.Kiani,“Wireless Power Transfer and Management for Medical Applications:Wireless Power,”I EEE SSC Ma ga zi ne,vol.14,no.3,pp.41-52,Summer 2022.7 R.Erfani et al.,“A Dual-Output Single-Stage Regulating Rectifier with PWM and Dual-Mode PFM Control for Wireless Powering of Biomedical Implant

266、s,”I EEE Tra ns.Bi ome d.Ci rc ui ts Sy s t.,vol.14,no.6,pp.1195-1206,Dec.2020.8 Y.Lu et al.,“A Dual-Output Wireless Power Transfer System with Active Rectifier and Three-Level Operation,”I EEE Tra ns.Powe r Ele c tron.,vol.32,no.2,pp.927-930,Feb.2017.9 C.-Y.Wu et al.,“A 13.56 MHz 40 mW CMOS High-Ef

267、ficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices,”I EEE J SSC,vol.49,no.11,pp.2397-2407,Nov.2014.10 Q.W.Low and L.Siek,“A Single-Stage Dual-Output Tri-Mode ACDC Regulator for Inductively Powered Appli

268、cation,”I EEE TCAS-I,vol.66,no.9,pp.3620-3630,Sep.2019.11 T.Lu et al.,“A 13.56 MHz Fully Integrated 91.8%Efficiency Single-Stage Dual-Output Regulating Voltage Doubler for Biomedical Wireless Power transfer,”I EEE CI CC,pp.1-2,Apr.2023.12 Z.Luo et al.,“A 90%-Efficiency 40.68 MHz Single-Stage Dual-Ou

269、tput Regulating Rectifier with ZVS and Synchronous PFM Control for Wireless Powering,”I SSCC,pp.454-455,Feb.2023.13 H.-S.Lee et al.,“A 90.8%-Efficiency SIMO Resonant Regulating Rectifier Generating 3 Outputs in a Half Cycle with Distributed Multi-Phase Control for Wirelessly-Powered Implantable Devi

270、ces,”I SSCC,pp.448-449,Feb.2024.14 D.-H.Yao et al.,“A 6.78-MHz Wireless Power Transfer System With Dual-Output Resonant Current-Mode Regulating Rectifier and Transmission Power Regulation,”I EEE TCAS-I,vol.70,no.12,pp.4986-4998,Dec.2023.15 Y.Liu et al.,“A 13.56-MHz Single-Input Dual-Output Wireless

271、Power and Data Transfer System for Bio-Implants,”I EEE J SSC,vol.59,no.8,pp.2557-2567,Aug.2024.16 Z.Luo et al.,“A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier with ZVS and Synchronous PFM Control for Wireless Powering,”I EEE J SSC,vol.59,no.8,pp.2418-2429,Aug.2024.17 Y.Che

272、n et al.,“A 2-W,90%Efficiency Single-Stage Dual-Output Wireless Power Receiver with 0.1 to 700-mA Output Current Range Through Dynamic Delay Compensation and Bootstrap Adaptive Body Biasing Circuit,”I EEE ASSCC,pp.1-3,Nov.2023.18 J.Lin et al.,“A Single-Stage Dual-Output Regulating Rectifier with Hys

273、teretic Current-Wave Modulation,”I EEE J SSC,vol.56,no.9,pp.2770-2780,Sep.2021.190 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DELIVERY/9.7979-8-3315-4101-9/25/$31.00 2025 IEEE9.7 A 6.78MHz 94.2%Peak Efficiency Class-E Transmitter with Adaptive Real-P

274、art Impedance Matching and Imaginary-Part Phase Compensation Achieving a 33W Wireless-Power-Transfer System Yuhao Xiong,Wenxing Cao,Xihao Liu,Shangzhou Zhao,Zhongming Xue,Zhuoqi Guo,Li Geng Xian JiaoTong University,Xian,China Wireless charging of portable devices has received explosive growth due to

275、 its convenience.However,high efficiency is usually achieved at a specific load point in current wireless power transfer(WPT)systems rather than in a wide impedance range.The load varies greatly when charging state changes as shown in Fig.9.7.1.And this variation will cause both real and imaginary p

276、arts of the transmitters(TX)load impedance to vary over a wider range reflected from the coil coupling.To overcome this drawback,some TX designs 15 utilize a Class-D architecture due to its ease of control.Nevertheless,Class-E power amplifiers have garnered interest benefit by their reduced switchin

277、g losses with zero-voltage-switching(ZVS),zero-voltage-derivative-switching(ZVDS)as well as smaller number of switches,which presents a higher potential for efficiency,especially at high frequency operation 6,7.In comparison to Class-D architectures,Class-E systems is more vulnerable to the fluctuat

278、ions in switching states and exhibits heightened sensitivity to variations in load conditions.To compensate the load imaginary part of the detuning problem,the dual-loop regulation bilateral bias capacitor is designed in 8,9.Nevertheless,using with discrete power MOSFETs as resonant capacitors leads

279、 to a large size.Moreover,the inherent nonlinearity of the MOS capacitor constrains dynamic range and accuracy of the control system,thereby posing challenges for the TX in achieving higher efficiency over a wider load range.A compact single-stage regulated Class-E is employed in 10 with adaptive ZV

280、S control to achieve enhanced end-to-end(E2E)efficiency across load and distance.However,the impedance characteristics of TX were not evaluated and only the ZVS switch state was considered.Under high input current conditions,the lack of ZVDS control can lead to a decrease in efficiency.To cope with

281、the complex impedance variation in practical application scenario,this work proposes a Class-E TX with an adaptive real-part impedance matching(RIM)technique and an imaginary-part phase compensation(IPC)controller in a 6.78MHz WPT system shown in Fig.9.7.2.The IPC controller compensate ZL into RL as

282、 seen by the front circuit,and RIM network converts RL to Zeq,which avoids hard switch(HS)and reverse conduction(RC)losses within the entire range of complex impedance.Figure 9.7.2(top)shows the pioneering analysis of switch-on drain voltage VSW and shunt capacitance current ICP versus load impedanc

283、e.These two surfaces intersect with the zero plane,which represents the impedance that satisfies the ZVS and ZVDS condition,respectively.The complex impedance plane is divided into 4 parts,corresponding the transient waveforms with HS or RC,and the generation of turn-on current spike,as shown in Fig

284、.9.7.2(right).The shape of this impedance curve is determined by design parameters duty cycle(D)and shunt capacitor(CP).Once the parameters are defined,the transient characteristics of the switching state can be predicted at any impedance variation,as well as the proximity between switching state an

285、d the optimal zero point.Figure 9.7.3(left)shows the detailed RIM technique,which is employed to derive PA design parameters and match ZVS network parameters over a certain load range.The passive matching network comprises a series inductance(LT)and a shunt capacitor(CT).The process displays a bidir

286、ectional nonlinear regression with impedance modeling and load conversion.After parameters D,CP,LT,and CT are affirmed,the load matching curve and ZVS trajectory are aligned on the complex impedance plane.Thus,the range of load is divided into three sections:specific designed load for ZVS and ZVDS,l

287、ight load for ZVS only,and heavy load for ZVS and near ZVDS.In consideration of the discrepancy in the imaginary part of the load impedance,the IPC controller is proposed shown in Fig.9.7.3(top-right).This controller identifies the load state by detecting the phase difference between the current flo

288、wing through the coil and the voltage on the resonant network.An adaptive digital algorithm is employed to regulate the value of the resonant capacitor,which is achieved by an 8-bit array controlled by the on-chip MOSFET switches.Figure9.7.3 (right-bottom)illustrates the compensation waveforms at ca

289、pacitive and inductive loads,respectively.After the system is initialized to the steady state,VSW reaches ZVS state.The changes in the imaginary impedance introduce RC and HC losses,as well as variations of VO.When compensation is enabled,VSW returns to ZVS state and VO returns to the design target.

290、Figure 9.7.4(top-left)shows the phase sampling operation.The inductor current passes through the small parallel capacitor,where it is converted to the voltage on the resistor.However,since this circuit introduces a non-ideal delayed d,an external adjustable delay trim is introduced in the voltage pa

291、th to compensate for the phase difference.This is implemented during the system initialization phase alignment and can achieve other target impedance adjustment functions under certain special designs.It is noted that the sinusoidal signal Vsin exhibits a drifting DC level,rendering traditional zero

292、-crossing detection phase techniques inapplicable 11.A differentiator phase detect technique is shown in Fig.9.7.4(bottom-left),which proceeds with differential operations by a wide-band amplifier with C1 and R2,and compresses the high-frequency gain by introducing two poles at high frequency throug

293、h capacitor R1 and capacitor C2.Additionally,a low-pass filter connected in series at the input to reduce the high-frequency noise interference.Figure9.7.4(right)depicts the phase difference detector and algorithm diagram,as well as corresponding waveforms.The square waves v and i,accompanied by pha

294、se information,are cross inputted to the DFF after an external configurable delay unit for balancing the precision and stability,thereby generating the phase difference flag.The initial capacitance is set to half of the full range to activate the power stage.Under the inductive load,the coil current

295、 lags the voltage,and the flag is 01,then the resonant capacitor is reduced by the successive approximation digital algorithm.Conversely,current phase is advanced at a capacitive load,and the flag is 10.The algorithm employs an asymmetric larger step to increase the capacitance and double the speed

296、of loop regulation.The prototype of the proposed controller was fabricated in a 0.18m HV BCD-on-SOI process.It consists of an 8b 200V on-chip power switch array,the analog phase detector,and the digital algorithm controller,occupying a total silicon area of 4.74mm2 and 8 off-chip 0805 capacitors as

297、coil resonant components,which contributes to a lower main circuit size than the schemes in 6 and 9.Figure 9.7.5(top)illustrates the measured waveforms of various TX load RL,VSW achieving ZVS turn-on state within the load range,as well as ZVS and ZVDS achieved under specific loads.Figure 9.7.5(middl

298、e)presents the measured steady-state waveforms of an TX inductive load with HS losses,a capacitive load with RC losses,and the compensated resistive load with ZVS and ZVDS state.Figure 9.7.5(left)shows phase detect waveforms in IPC controller with an alignment error of 88%overall efficiency from lig

299、ht to heavy load variations(5 to 50).Figure 9.7.5(bottom-middle)provides the measured TX efficiencies under various imaginary impedance conditions with and without compensation.By utilizing IPC technology,phase alignment and ZVS can be performed in the Class-E TX,resulting in an efficiency improveme

300、nt of 26.2%and 39.1%for capacitive and inductive loads,respectively.It is also evident that the compensation contributes to a considerable efficiency enhancement even when the capacitive load exceeds regulation range.Figure 9.7.5(bottom-right)illustrates that this work has the highest TX efficiency

301、over a wide outpower range as compared to the state-of-the-art designs shown in the figure.Figure 9.7.6(top)presents the measured E2E efficiency of 73.9%in proposed WPT system with a peak charging power of 33W,and a peak efficiency of 74.7%when POUT is 26W.The performance summary and comparison tabl

302、e with prior arts are shown in Fig.9.7.6(bottom).Among the state-of-the-arts design in the comparison table,the proposed Class-E TX can simultaneously cope with a wide range of both real and imaginary part of the Impedance deviations and exhibits the highest TX efficiency with the widest load range

303、from 3W to 29W.Figure 9.7.7 shows the die micrograph,the design parameters,and the WPT system measurement setup,with 9mm transmission gap between two coils.Ac knowle dge me nt:This work is funded by the National Natural Science Foundation of China under Grant U23A20367.Corresponding authors:Zhongmin

304、g Xue,Zhuoqi Guo and Li Geng.Figure 9.7.1:WPT system for battery charging(top),class-E TX state(middle)and prior-art techniques(bottom).Figure 9.7.2:VSW and ICP vs Zeq in 3D surface(top)and transient waveforms,the class-E TX with RIM and IPC controller(bottom-left).VSW/ICPat switching vs Zeqon Arbit

305、rary ConditionsHS Loss&Current SpikeClass-E TX with RIM Technique and IPC ControllerIPC controller compensate part ZLinto RLRIM network convert RLonto high efficiency trajectoryFull complex impedance range avoid HS and RC lossRC Loss&Current Spike?ReZImZVSW=0Icp=0into 4 partsCorrespondingTransient W

306、aveformComplex impedancezero planeVSW(V)ICP(V)Zero plane?VSW0ICP0?VSW0ICP0?VSW0?VSW0ICP0?VtxItxGaNCpVinLfRIMNetworkCLKDZeq=Conv(RL)ZL=jwLtx+jwZrefl+jw/Ctx =RLafter compensationIPCControllerZreflCtxLtxOn chipPassiveCtxLtxCrxLrxRXAC/DCLoad BatteryTXDC/ACVINZLResonant linkDC PowerROLfCpL0CsZLCLKDZeqVSW

307、ICPIm.Part COMP.W/O Re.variation foreff.degeneration Large size by extra discrete MOS?Prior Art:for Im.part impedance 8-9 Prior Art:For distance and load 10 Adaptive ZVSPower regulationW/O TX Load CHAR.EvaluatedAbsence ZVDS controlwith current spikeWPT system for battery chargingCharging processTX c

308、omplex impedance ZLDisturb by the variation from?Battery charging stage?RX parameters?Resonant link conditionClass-E TX ideal working conditionVoltage/CurrentcapacityImpedanceIncreaseImpedanceIncreaseConstant ImpedanceZVSControllerClkGaNModeVGVSWRegulatorVINRXLoadVGVSW.ZL=RoptVSW=0&ICP=0?2?0VSWtVGCB

309、LKVbiasPAClkLtxResonantNetworkCompensateFigure 9.7.3:RIM technique(left),the IPC controller and compensation waveforms(right).Figure 9.7.4:V/I phase sampling trim(top-left),DEV phase extract(bottom-left),phase diff detect and ALG diagram(right).Typical solutionCant handle drifting VDCProposed soluti

310、onConverted to signals with firm VbiasPhase diff detector and ALG diagram Operation waveformV/I phase sampling trim Vtx?trimVvsinV1VbiasVctxitx,0Visin?dVbiasVtxvvsinOPAVbias?trimV1DEV phase extractf3f(Hz)BasicProposed0fclkf2f1Gain(dB)VbiasR1C1VctxVisinOPAitx,0CapmaxCapminRegulation rangeHigh Voltage

311、 stress/sensitiveLow tuning capabilityFlagCLKregCap1 00 11 10 0LimitAlignOPAC1R1VDCVdevC2R2LPFVv/isin?i/vCMPCap1281271269797CLKDCLKregABENCapAB128130132Asymmetric step adjustment?v?i?v?i168168Phase diff windowInductive loadCapacitive loadPhase alignDLYvDLYiDLYvDLYiFlagFlagPhase alignVlimitDLYiDQClkD

312、LYvABDQClkDelayPD_CTRL1:0CMPCapmaxCapminVlimitMUX4-1+-=BUS lineENCLKreg?v?iFlagCapDelayCMPVdevFirm VbiasVsin?i/vRising edge for peak Drifting VDCGaNCtxLtxLTCTCpItxVtxVctxCLKDVinLfDEVvPhaseShiftDetectorDEViVtxVctxCLKregDigitalAdjust ALGVoltage phase extractCurrent phase extractPD_CTRLHV SwitchArrayIm

313、aginary-part phase compensation controllerVvsinVisin?v?iVGDA?diffCLK GenCLKD2?0D02?DOFFONVSWTargetsZVSZVDSZLrangeZLLTCTCpConstrainsVINV/I stressPOUTVswMatchingNetworkLTCTCpDZconv(ZL)=R+jwXZeq,opt=Ropt+jwLbIcpCLKDVINLfLoad conversionimpedance modeling LTCTBidirectional nonlinear regression processRIM

314、 techniqueVSWVSWVOVOSystem InitialInductive LoadIntroduceoadoad Compensation EnableSystem InitialCapacitive LoadIntroduced dCompensation EnableCompensation at capacitive load Compensation at inductive loadHS lossRC lossZVS&ZVDSZVS&ZVDSRe Zeq(?)Imag Zeq(?)CPDRconv(?)Xconv(?)ZVS only regionZVS&near ZV

315、DS regionZVS&ZVDS pointRe Zeq(?)Imag Zeq(?)light loadto heavy loadHeavy loadSwitch on the 2ndZVS pointNear ZVDSLight loadZVS achieveFit loadZVS&ZVDS achieveFigure 9.7.5:DEV waveforms in IPC(left),waveforms versus real impedance(top),waveforms versus imaginary impedance(middle),and statistics efficie

316、ncy result(bottom).Figure 9.7.6:Measured E2E efficiency and DC output power under different load RO(top),and comparison table with the state-of-the-arts(bottom).0510152025303540010203040506070800102030405060Output power(W)E2E Eficiency(%)RO(?)74.7%(26W)33W(73.9%)E2E efficiency vs.Output load VIN=35V

317、ISSCC199JSSC2410 ISSCC246 ISSCC232 TCAS-I211This WorkProcess?m0.5 CMOS SOI0.18 SOI0.18 BCD0.18 BCD0.35 CMOS0.18 HV SOITX TopologyDiff Class-EClass-EHybridClass-EDHalf BridgeClass-DClass-EFrequency MHz13.566.786.780.1-0.2*6.786.78Compensate TargetImaginary LoadLoad andDistanceVoltage StressPower andF

318、OD#PowerReal andImaginary LoadTuning MethodBilateral BiasCapacitorDuty ZVSControlDelay ZVSCompensationVoltage andQ Value3-modeModulationImpedanceMatch+CapacitorMatrixVIN V40*7.47.4211520-35VOUT VN.A.1048102712*121218Peak TX efficiency%9193*N.A.888894.2Txefficiency%(Power Range W)91(100)87(15-37)N.A.

319、88(40)74(4-11)88(3-29)Peak DC Output Power W(E2E Efficiency%)N.A.(N.A.)27(63)27(75.9)40(N.A.)7.3(57.3)33(73.9)Chip Area mm23.152.77615.63.534.74*Estimated from testing results#Foreign Object DetectionLtxROCOCrxLrxGaNCpVinLfRIMNetworkIPCControllerCtxPINPOUTZLPTX,OUTEFFTX=PTX,OUT/PIN EFFE2E=POUT/PIN+-

320、VOUT05101520253040506070809010001020304050TX Output power(W)TX Efficiency(%)ReZL(?)94.2%Class-E TX real impedance variation VIN=20V0102030405060708090100-100-80-60-40-2002040TX Efficiency(%)ImZL(?)W/imag CompensationW/O compensationCapacitive LoadInductive LoadOut of regulation range39.6%26.2%Class-

321、E TX imaginary impedance variation VIN=20VVCLKVSWVCLKVSWVCLKVSWZVS&ZVDSNear ZVDSSecond ZVS point40us20VZVS onlyRL=5?RL=25?RL=50?Efficiency vs.Re impedance VariationEfficiency vs.Im impedance VariationEfficiency vs.Output powerMeasured DEV waveform in IPCVCLK28ns43V112V149V20ns123V50VZVS&ZVDSICOILVCO

322、ILVSW26nsVCLKICOILVCOILVSWVCLKICOILVCOILVSWPhase alignedInductive Load ConditionCapacitive Load ConditionWith Totally CompensationWith RClossWith HS lossVCOIL lags ICOILICOIL lags VCOIL40us707580859095100330TX Efficiency(%)TX Output power(W)This WorkJSSC2410TCAS-I211TPE227ISSCC232TPE225ICOILVCOILICO

323、ILVCOIL?v?i50V40us32ns16nsAligned3ns?v?iWith Totally CompensationCapacitive Load Inductive LoadISSCC 2025/February 18,2025/10:30 AM191 DIGEST OF TECHNICAL PAPERS 9 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEE

324、EFigure 9.7.7:The die micrograph of the IPC controller(left),and the measurement setup(right).2.2mm1mm8bits HV SWITCHAnalogyDetectordriverTest padsDigitalALG1mm1.7mmUnusedGaN Switch GS065-008-1-LLf47uHCP253pFLT623nHCT1nFTX/RX Coil1.142uHDiodeGaNTXRXVOUTVINLT(Bottom)CTRIMNetworkCoils9mm gapIPCControl

325、lerRe f e re nc e s:1 X.Ge et al.,“A 6.78 MHz Single-Stage Wireless Power Transmitter Using a 3-Mode Zero-Voltage Switching Class-D PA,”I EEE TCAS-I,vol.68,no.6,pp.2736-2748,June 2021.2 F.Neri et al.,“Single-Chip Qi-Compliant 40W Wireless-Power-Transmission Controller using RMS Coil Current Sensing

326、and Adaptive ZVS for 4dB EMI and up to 1.7%Efficiency Improvements,”I SSCC,pp.456-457,Feb.2023.3 F.-B.Yang et al.,“Structure-Reconfigurable Power Amplifier(SR-PA)and 0X/1X Regulating Rectifier for Adaptive Power Control in Wireless Power Transfer System,”I EEE J SSC,vol.56,no.7,pp.2054-2064,July 202

327、1.4 T.Lu et al,“A 13.56MHz Wireless Power Transfer System with Hybrid Voltage-/Current-Mode Receiver and Global Digital-PWM Regulation Achieving 150%Transfer Range Extension and 72.3%End-to-End Efficiency,”I SSCC,pp.450-451,Feb.2024.5 Y.Shin et al.,“Accurate Method for Extracting the Coupling Coeffi

328、cient of an LCC-Series Wireless Power Transfer System,”I EEE Tra ns a c ti ons on Powe r Ele c troni c s,vol.37,no.9,pp.11406-11422,Sept.2022.6 F.Mao et al.,“A Differential Hybrid Class-ED Power Amplifier with 27W Maximum Power and 82%Peak E2E Efficiency for Wireless Fast Charging To-Go,”I SSCC,pp.4

329、44-445,Feb.2024.7 Y.Shao et al.,“Explicit Design of Impedance Matching Networks for Robust MHz WPT Systems with Different Features,”I EEE Tra ns a c ti ons on Powe r Ele c troni c s,vol.37,no.9,pp.11382-11393,Sept.2022.8 C.Yeh et al.,“A 70W and 90%GaN-Based Class-E Wireless-Power-Transfer System wit

330、h Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching,”I SSCC,pp.138-139,Feb.2018.9 C.-Y.Xie et al.,“A 100W and 91%GaN-Based Class-E Wireless-Power-Transfer Transmitter with Differential-Impedance-Matching Control for Charging Multiple Devices,”I

331、SSCC,pp.242-243,Feb.2019.10 X.Ma et al.,“A 27 W Wireless Power Transceiver with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control,”I EEE J SSC,vol.59,no.6,pp.1782-1793,June 2024.11 H.-Y.Chen et al.,“A 6.78 MHz and 90%Efficiency Resonant Wireless Power Supply Technique with

332、 the Dual Voltage/Current Tuning Inductance to Supply 30 cm Short-Distance Base Stations for 5G Communications,”I EEE Tra ns a c ti ons on Powe r Ele c troni c s,vol.36,no.10,pp.11774-11784,March.2021.192 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 9/UBIQUITOUS POWER DE

333、LIVERY/9.8979-8-3315-4101-9/25/$31.00 2025 IEEE9.8 A 50W 98%-Efficiency High-Power Wireless-Charging System with an Acoustic Noise-Reduced ASK Modulation Technique and Internal Hybrid Voltage-/Current-Mode ASK Demodulation Seongjin Oh,Hansol Kim,Hyunsu Kim,Gyeongho Namgoong,Woojin Park,Sangbeom Heo,Jaekyu Kim,Sungwoo Moon,Hyoung-Seok Oh,Hwayeal Yu Samsung Electronics,Hwaseong,Korea The near-field