用于XPU到XPU連接的4 Tbit每秒光計算互連小芯片.pdf

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1、4 Tb/s Optical Compute Interconnect Chiplet for XPU-to-XPU Connectivity2024 Hot Chips Saeed Fathololoumi,Intel CorporationAugust 20242Integrated Photonics Solutions2024 Hot Chips Evolution of Optical CommunicationsTelecom Age Long Reach Low Loss optical fiber(100s km)Fiber amplifier(C-band)Discrete

2、optical sub-assemblies Heavy reliance on DSPDatacom Age Low Power 30 pJ/bit Shorter Reach(1Tbps/mm shoreline 5 pJ/bit Rack-level reach(100ns10nsFECKPNone or light-FECOptical interface standardWavelength gridModulation speed and formatMSA20nm O-band FR100&200Gb/s PAM4None yetMSA emerging:100s GHz16-6

3、4Gb/s NRZ is popularHost interface standardIEEE/OIFUCIe/PCI-SIG6Integrated Photonics Solutions2024 Hot Chips Size Integration Yield Voltage Loss Components BER Loss Noise Data rate Multiplexing IntegrationIntegration Size 3D packaging 3.5pj/bit 80%reduction1.5Tbps/mm2Tbps per fiberIn addition to pow

4、er and cost,solution needs to address total BW,BW density and latencyOCI Scaling Vectors and KPIs Points7Integrated Photonics Solutions2024 Hot Chips Integrated Optics:Our Approach Greater photonic functionality integrated on the Photonic Integrated circuits(PICs)best done in silicon photonics Integ

5、ration of PICs with best of breed ICs using Advanced Packaging to create Optical Engines heterogenous integration trumps monolithic integration Tighter Integration of Optical engines with the host(xPU,Switch)enabling new systems and applicationsAn Intel OCI chiplet is a die-stack that provides optic

6、al I/O using Intel Silicon Photonics technology and can be co-packaged with the XPU.We refer to this approach as Co-Packaged Optics(CPO)when applied to networking applications and Optical Compute Interconnect(OCI)when applied to compute fabrics8Integrated Photonics Solutions2024 Hot Chips 8High-Spee

7、d Serial(Un-retimed direct drive)Ethernet,IB,PCIe,.Wide-slow D2D interfaceUCIeSerdesOn host:VSR/MR or moreIn chiplet:Purpose-built,optimized for optical channelShoreline bandwidth density500-800 Gbps/mm(per direction)Limited by Serdes1.2 Tbps/mm(per direction)Unconstrained by host interfacePower eff

8、iciency(end-to-end,including host I/O)10pJ/bSerdes at 3-5pJ/b+I/O chiplet30K lasers Performance(CMOS control):Performance(CMOS control):11M lasers BI on wafer12Integrated Photonics Solutions2024 Hot Chips OCIuCuCCPU pkg w/OCIOptical FiberSystem 1CPU pkg w/OCISystem 2Package and Platform Integration

9、Gen5/CXL2 links OCI(fully integrated optical engine with integrated lasers),8 SMF fiber pairs(no PMF required),8 wavelengths/fiber,64 lanes 32Gb/s=4Tbps(bidirectional)64 lanes!CPU pkg w/OCI in platform Concept CPU with Co-Packaged OCI13Integrated Photonics Solutions2024 Hot Chips uCCPUOptical Fiber

10、OSA8-wavelength integrated laserOutput power uniformity:0.7dBmWavelength spacing uniformity:15GHzMeasured Integrated Laser Spectrum 14Integrated Photonics Solutions2024 Hot Chips uCCPUOptical Fiber OscilloscopeData rate=32Gb/s Measured Transmitter Output Eye15Integrated Photonics Solutions2024 Hot C

11、hips First demonstration of CPU-to-CPU communication over co-packaged OCI and fiberCPU1 injects 32Gb/s/lane PRBS31 data,CPU2 receives and detects errorsGood OCI Tx performance,as measured by uniform laser wavelength spacing and clean eye diagram Good OCI Rx and link performance,as measured by positi

12、ve eye margin and 1e-13 BERCPU2 w/OCIOptical FibersPlatform-to-PlatformBER TestSystem 2 TX SpectrumCPU1 w/OCIPer Lane Eye Margin Measurements System 1 TX ScopeCPU to CPU Optical Communication16Integrated Photonics Solutions2024 Hot Chips 16Bandwidth scaling along multiple vectors:Wavelengths:16-in d

13、evelopment Modulation rate 32G64G128G compute 112G224G networking Demonstrated 128GBaud MRR-modulator#fibers(more bandwidth,more radix)Enabled by compact connectorArchitecture also supports 224G/lane Ethernet CPO High-speed linear interface Ethernet PMD like DR8 or FR4 at 200G/lane112Gbaud Tx eyeFut

14、ure Bandwidth Scaling17Integrated Photonics Solutions2024 Hot Chips Summary Demonstrated first fully functional OCI link between two CPUs SiPh drives power,bandwidth density and cost scaling SiPh is key enabler of co-packaged opticspluggable FR CPOOCI gen1OCI gen2Gb/s/mmEdge Bandwidth Density plugga

15、bleFR CPOOCI gen1OCI gen2pJ/bitPower E You!Notices&DisclaimersSoftware and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.Performance tests,such as SYSmark and MobileMark,are measured using specific computer systems,components,software,opera

16、tions and functions.Any change to any of those factors may cause the results to vary.You should consult otherinformation and performance tests to assist you in fully evaluating your contemplated purchases,including the performanceof that product when combined with other products.For more complete in

17、formation visit results are based on testing as of dates shown in configurations and may not reflect all publiclyavailable updates.See backup for configuration details.No product or component can be absolutely secure.Your costs andresults may vary.Intel technologies may require enabled hardware,software or service activation.Intel Corporation.Intel,the Intel logo,and other Intel marks are trademarks of Intel Corporation or its subsidiaries.Othernames and brands may be claimed as the property of others.