CACTI-CNFET：一種用于分析帶有碳納米管場效應晶體管的SRAM的時序、功率和面積的工具.pdf

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1、CACTI-CNFET:an Analytical Tool for Timing,Power,and Area of SRAMs with Carbon Nanotube Field Effect Transistors*Shinobu MiwaEiichiro Sekikawa Tongxin YangRyota ShioyaHayato YamakiHiroki HondaThe University of Electro-CommunicationsThe University of TokyoJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESI

2、GN AUTOMATION CONFERENCE(ASP-DAC 2025)1*This work was partially supported by JSPS(Japan Society for the Promotion of Science)KAKENHI Grant Numbers 18K19778,20H04153,23K18461,and 24K02913,and VLSI Design and Education Center(VDEC),the University of Tokyo in collaboration with NIHON SYNOPSYS G.K.CNFET

3、(Carbon Nanotube Field Effect Transistor)Transistor composed of nano-meter order carbon nanotubes(CNTs)Use CNTs,which have an electronic characteristic superior to silicon,as channel materials Operate at a high speed with a small supply voltage(e.g.,0.375V)Greater performance than silicon transistor

4、s 1 Gate delay:1/3.9 Energy efficiency:9.4xJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)2CNFET1 C.Qiu et al.,Scaling Carbon Nanotube Complementary Transistors to 5-nm Gate Lengths,Science(2017)Cross section of CNFETs 1CNFET ProcessorsJan 20-23,202530TH ASIA AND

5、 SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)32 M.Shulaker et al.,Carbon Nanotube Computer,Nature(2013)3 G.Hills et al.,Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI,IEEE TNano(2018)4 G.Hills et al.,Modern Microprocessor Built from

6、Complementary Carbon Nanotube Transistors,Nature(2019)2010201520202025The first CNFET processor 2(data:1b,frequency:1KHz)The first CNFET RISC-V processor 4(data:16b,frequency:10KHz)Performance comparison between 5nm FinFET and 5nm CNFET for an OpenSPARC T2 processor 3Challenges towards Practical Use

7、 of CNFET ProcessorsJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)4SWDeviceCircuitArchitectureD1:Establishment of manufacturing technologiesD2:Reduction of manufacturing costC1:Analyzing the impact of CNFET on circuit performanceC2:Performance optimization for C

8、NFET circuitsC3:Support of circuit design toolsA1:Analyzing the impact of CNFET on architecture performanceA2:Architectural optimization for CNFET A3:Support of architectural design toolsS1:Analyzing the impact of CNFET on software performanceS2:Tuning performance of applications running on CNFET pr

9、ocessors This work!Lack of CNFET Processor Design ToolsModern processors are designed with the help of various architecture-level design tools Performance simulator(e.g.,Gem5,Sniper,GPGPU-Sim)Power and area simulator(e.g.,McPAT,GPUWattch)Current development of CNFET processors is executed fully at t

10、he circuit level(i.e.,with some EDA tools and CNFET cell libraries)This gap hinders us in exploring various processor architectures that utilize the great potential of CNFET!Jan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)5Research Objectives and ContributionsOur

11、goal is to fill the gap between processes to design traditional CMOS and CNFET processorsAs a first step,we developed CACTI-CNFET First architecture-level analytical tool for SRAMs manufactured with the state-of-the-art(5nm)CNFET technology Help us make a quick decision on the architecture of CNFET

12、SRAMswithin a targeted processor Built at the top of CACTI so it can be used and extended easilyCACTI-CNFET is available on our GitHub repositoryJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)6SRAMUsed as various on-chip memories in processors(e.g.,caches,registe

13、r files,etc.)Composed of several submodules Cell array Row/column decoders Wordline/write drivers Sense amplifiersJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)76T SRAM cellWrite drivers&sense amplifiersInput/output dataColumn decoderCell arrayRow decoderWordlin

14、e driversRow addr.Column addr.SRAM architecture123456VddCACTIAnalytical tool for various memories(e.g.,SRAMs,CAMs,and DRAMs)Compute the performance,power,and area of a target memory from the given tech node and architectural description(e.g.,capacity and port count),w/some models Produce slightly in

15、correct outputs(within a 6%error 5)but enable a quick analysis of the target memoryUsed internally in some architecture-level processor design tools 6,7Support only conventional CMOS technology nodesJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)85 S.J.E.Wilton a

16、nd N.P.Jouppi,CACTI:an Enhanced Cache Access and Cycle Time Model,IEEE JSSCC,Vol.31,No.5(1996)6 J.Leng et al.,GPUWattch:Enabling Energy Optimizations in GPGPUs,ISCA(2013)7 S.Li et al.,McPAT:An Integrated Power,Area,and Timing Modeling Framework for Multicore and Manycore Architectures,MICRO(2009)Ove

17、rview of CACTI-CNFETMaintain CACTIs user interface and reuse the internal components as much as possibleThe tech parameters and timing/power/area models related to CNFETs are newly added or modified Jan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)9CACTI-CNFETCACTI

18、Tech parameters(Si MOSFETs)Timing/power/area models(Si MOSFETs)Tech parameters(CNFETs)Timing/power/area models(CNFETs)Simulation engineSRAMConfigurationTimingPowerAreaCACTI-CNFETSupported CNFET Technology Node5nm CNFET technology Used in the previous work 3 Projected from some device-level experimen

19、tal dataSome of key parameters are used in CACTI-CNFET as isJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)10ParametersValuesWidth (nm)21,(nm)10,15,8.5Gate height(nm)20Gate oxide(nm)1.9Gate oxide 10.6Space oxide 4.0CNT diameter (nm)1.8Inter-CNT pitch (nm)2Apparen

20、t mobility(cm2/Vs)427.8Supply voltage(V)0.375Key parameters of 5nm CNFET3 G.Hills et al.,Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI,IEEE TNano(2018)Derivation of Undisclosed ParametersSome parameters needed for CACTI-CNFET are not shown in t

21、he previous workThese parameters are derived from SPICE simulations and some theoretical formulasPlease read our paper if you would like to know the details of the derivation methodsJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)11ParametersValuesOn current(A/m)1

22、.72 103Off current(A/m)1.04 107Gate leakage current(A/m)9.09 1011Threshold voltage(V)0.262Drain saturation voltage(V)0.093Voltage difference of sense amplifier(V)0.154Parallel plate capacitance _(aF/m)176.52Fringe capacitance(aF/m)148.26Junction area capacitance(aF/m)0.00Junction sidewall capacitanc

23、e(aF/m)38.01Derived parameters of 5nm CNFETModel CorrectionSome models used in the original CACTI do not match CNFET SRAMsMake the following modifications to improve the estimation accuracy of CACTI-CNFET Change the channel width ratio of PMOS and NMOS from 2:1 to 1:1 Remove the effect of shared con

24、tact from the formula that computes bitlinecapacitance Implement the leakage power and energy consumption models for write driversJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)12Experimental SetupCompare CACTI-CNFET with SPICE simulation and OpenRAM 8Perform the

25、 evaluation for various SRAM subarrays with different numbers of rows and columnsEvaluation metrics Accuracy(delay,power,energy,and area)SpeedJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)138 M.R.Guthaus et al.,OpenRAM:An Open-source Memory Compiler,ICCAD(2016)L

26、eakage Power Estimation ResultsJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)14Show an error of 7.40%on averagePrediction for each submodule shows sufficient accuracy3248648096112128323.975.116.247.388.529.6610.80485.607.168.7210.2811.8413.4014.96647.269.2411.22

27、13.2015.1817.1719.15808.9111.3113.7116.1118.5220.9223.339610.5513.3816.2019.0221.8524.6827.5111212.2115.4518.7021.9525.2028.4531.7112813.8817.5521.2224.9028.5832.2635.943248648096112128324.2825.4156.5477.688.8139.94611.08486.087.6849.28710.8912.4914.115.7648.03810.1112.1914.2616.3418.4120.48809.7641

28、2.3114.8517.419.9422.4925.039611.4414.4617.4720.4923.526.5229.5411213.1216.6120.0923.5827.0630.5534.0412815.2819.2423.227.1531.1135.0739.023248648096112128327.946.064.864.043.432.962.58488.577.346.545.975.545.204.926410.769.498.658.067.607.236.94809.628.858.367.997.717.477.28968.418.087.867.707.567.

29、457.341127.507.487.457.437.407.387.3412810.149.649.309.058.868.708.57Validation results(top:HSPICE(W),middle:CACTI-CNFET(W),bottom:errors(%)RowsColumnsRowsRowsBreakdown of leakage power(128 columns)Cell array+precharge(+sense amplifiers)Row decoders+wordline driversWrite drivers32486480961121283216.

30、5524.0531.4539.4247.0155.2363.154822.2532.8443.1854.0864.6075.8186.756429.0942.5555.8869.7983.3497.41 111.508034.7151.2267.3284.28 100.81 117.95 134.809640.8460.2079.3499.12 118.74 138.85 158.8311247.0269.4391.35 114.24 136.63 159.71 182.7312853.7579.29 104.03 129.79 155.18 181.14 207.12324864809611

31、21283217.1324.8832.6240.3748.1155.8663.64823.934.945.9156.9167.9278.9289.936431.8946.1560.4274.6888.95103.2117.58038.7456.2673.7991.31108.8126.4143.99645.5566.3487.12107.9128.7149.5170.311252.3776.42100.5124.5148.6172.6196.612857.584.8112.1139.4166.7194221.33248648096112128323.543.433.732.412.341.14

32、0.71487.406.266.315.245.134.113.66649.638.488.137.026.735.965.368011.619.859.618.347.967.136.749611.5510.199.828.878.397.657.2011211.3810.069.978.998.738.077.611286.976.957.777.427.437.116.86Write Dynamic Energy Estimation ResultsJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE

33、(ASP-DAC 2025)15Show an error of 7.08%on averagePrediction for each submodule shows sufficient accuracyValidation results(top:HSPICE(fJ),middle:CACTI-CNFET(fJ),bottom:errors(%)RowsColumnsRowsRowsBreakdown of leakage power(128 columns)Cell array+precharge(+sense amplifiers)Row decoders+wordline drive

34、rsWrite drivers32486480961121283214.9521.3328.1034.5441.1847.7854.244820.3929.4739.1448.4157.8367.0276.416426.9138.7051.2263.3475.1987.3699.888032.1446.5761.8976.6991.52 106.14 121.069637.7054.6972.1990.20 107.69 124.70 142.1411242.9362.2382.19 102.63 121.93 142.33 161.5012848.1769.5192.40 114.23 13

35、6.17 157.34 179.1032486480961121283215.2422.0428.8435.6442.4449.2456.034820.8430.3239.7949.2758.7568.2277.76427.6739.8251.9864.1376.2888.44100.68033.3548.1863.0177.8492.68107.5122.3963956.5174.0291.53109126.5144.111244.6564.8485.03105.2125.4145.6165.812848.6271.4894.35117.2140.1162.9185.832486480961

36、12128321.923.322.643.183.053.053.32482.182.871.671.781.581.801.69642.812.901.481.251.451.230.71803.783.451.811.501.271.291.06963.453.332.541.471.251.491.351124.014.203.462.522.852.292.651280.922.842.112.612.873.563.75Read Dynamic Energy Estimation ResultsJan 20-23,202530TH ASIA AND SOUTH PACIFIC DES

37、IGN AUTOMATION CONFERENCE(ASP-DAC 2025)16Show an error of 2.36%on averagePrediction for each submodule shows sufficient accuracyValidation results(top:HSPICE(fJ),middle:CACTI-CNFET(fJ),bottom:errors(%)RowsColumnsRowsRowsBreakdown of leakage power(128 columns)Cell array+precharge(+sense amplifiers)Ro

38、w decoders+wordline driversWrite drivers32486480961121283241.0241.9943.2144.7346.5348.6351.044852.2853.2654.5356.0657.8459.9662.346463.2764.2565.5867.0668.8570.9773.408075.3476.3577.6379.1680.9583.0485.459685.5686.5287.7789.3391.1693.2795.6911295.5496.5397.7999.35 101.19 103.33 105.73128 105.45 106.

39、48 107.70 109.25 111.18 113.33 115.7032486480961121283244.5945.244646.8947.9349.150.424857.1257.7758.5359.4260.4661.6362.966469.6670.3171.0771.967374.1875.58082.3382.9783.7484.6385.6786.8588.179695.2695.996.6797.5798.699.78101.1112108.4109.1109.8110.7111.8113114.3128123123.7124.4125.3126.4127.5128.9

40、3248648096112128328.727.746.454.842.990.961.20489.278.467.336.004.522.790.996410.109.438.377.316.024.512.87809.278.677.876.925.834.583.189611.3310.8510.149.218.166.985.6611213.4912.9912.3211.4610.469.318.0812816.6616.1415.5414.7213.6612.5511.38Read Delay Estimation ResultsJan 20-23,202530TH ASIA AND

41、 SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)17Show an error of 8.33%on averagePrediction for each submodule shows sufficient accuracyValidation results(top:HSPICE(ps),middle:CACTI-CNFET(ps),bottom:errors(%)RowsColumnsRowsRowsBreakdown of leakage power(128 columns)Cell array+precharge(+s

42、ense amplifiers)Row decoders+wordline driversWrite driversArea Estimation ResultsUnderestimates the subarray area by 10.25-21.70%comparing OpenRAMs layouts The subarrays generated by OpenRAM have some extra circuits(e.g.,dummy cells)The generated subarrays include a significant fraction of the dead

43、spaceThe accuracy of CACTI-CNFET will be improved if these areas are modeledJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)18OpenRAM()CACTI-CNFET()Error(%)32x32116.9591.5721.7064x64314.47282.2510.25Area of SRAMsLayout of 32x32 CNFET SRAM(generated by OpenRAM)Dumm

44、y cellsDead space32486480961121283246.0060.8184.6493.98111.48132.41147.324835.6054.0883.23102.66119.39131.87147.926474.89105.57129.23155.92174.03204.34221.538064.8694.41127.42161.15187.10213.83233.649675.72113.19147.98188.21218.57240.78277.6411285.30131.84170.36210.24253.63286.62316.54128191.40188.8

45、0243.87289.79334.18374.16409.73324864809611212832143.7722.4132.42126.6021.4631.71126.844820.9831.95126.6020.7431.71126.6020.986434.57126.8420.9831.23126.6021.2231.7180126.6021.2231.23126.3620.9831.47126.6096145.2022.8932.90128.0322.4132.66128.0311221.2233.38130.8921.2231.95132.0821.2212831.71127.552

46、1.4631.71129.2221.2231.47324864809611212832 3.2E+05 2.7E+06 2.6E+06 7.4E+05 5.2E+06 4.2E+06 1.2E+0648 1.7E+06 1.7E+06 6.6E+05 4.9E+06 3.8E+06 1.0E+06 7.1E+0664 2.2E+06 8.3E+05 6.2E+06 5.0E+06 1.4E+06 9.6E+06 7.0E+0680 5.1E+05 4.4E+06 4.1E+06 1.3E+06 8.9E+06 6.8E+06 1.8E+0696 5.2E+05 4.9E+06 4.5E+06

47、1.5E+06 9.8E+06 7.4E+06 2.2E+06112 4.0E+06 3.9E+06 1.3E+06 9.9E+06 7.9E+06 2.2E+06 1.5E+07128 6.0E+06 1.5E+06 1.1E+07 9.1E+06 2.6E+06 1.8E+07 1.3E+07Speed30TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)19Extremely(3.2 1051.8 107times)faster than SPICE simulationMore useful for

48、analysis of larger memoryElapsed time for read delay analysis(top:HSPICE(s),middle:CACTI-CNFET(s),bottom:speedup)RowsColumnsRowsRowsNameRemarksCPUAMD Ryzen 9 7950X3D(16C32T,4.2GHz,128MB LLC)Memory64GB DDR5-4800HSPICEU-2023.03-SP1GCC8.5.0System configurationRelated WorkCNFET circuit analysis Reveal t

49、he impact of 5nm and 7nm CNFETs on an OpenSPARC T2 processor 3 Evaluate the impact of 7nm CNFET for various benchmark circuits 9 Analyze the 6T SRAM cell optimized for 5nm CNFET 10No architecture-level analytical tool is usedCACTI extensions Support non-uniform cache architecture 11 Add the function

50、ality to analyze I/O and PHY 12 Implement the 3D stacked DRAM model 13No study extends CACTI to support CNFETJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)203 G.Hills et al.,IEEE TNano(2018)9 C.Shi et al.,ASP-DAC(2023)10 R.Chen et al.,IEEE TVLSI(2022)11 N.Murali

51、manohar et al.,MICRO(2007)12 N.P.Jouppi et al.,ICCAD(2012)13 K.Chen et al.,DATE(2012)Conclusions and Future WorkConclusions Developed CACTI-CNFET,the first architecture-level analytical tool for CNFET SRAMs Showed that CACTI-CNFET can estimate the timing,power,and area of CNFET SRAMs with significan

52、t accuracyFuture work Validate CACTI-CNFET for the CNFET SRAM modules except for subarrays(e.g.,H-tree,predecoder,etc.)Extend to the other SRAMs(e.g.,single-ended SRAMs,4T,8T,and 10T SRAMs,etc.)Develop a complete set of architecture-level design tools for CNFET processorsJan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)21Jan 20-23,202530TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE(ASP-DAC 2025)22Thank you!