SESSION 5 - Wireless RF and mm-Wave Receiver Techniques.pdf

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1、ISSCC 2024SESSION 5Wireless RF and mm-Wave Receiver Techniques5-1:A 5-to-16GHz Reconfigurable Quadrature Receiverwith 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference1 of 43A 5-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Le

2、akage SuppressionHao Xu1,2,Junyan Bi1,Tenghao Zou1,Weitao He1,Yaxin Zeng1,Junjie Gu1,Ziyang Jiao1,Shubin Liu3,Zhangming Zhu3,Na Yan1,21Fudan University,Shanghai,China 2Jiashan-Fudan Joint Research Institute,Jiaxing,China 3Xidian University,Xian,China 5-1:A 5-to-16GHz Reconfigurable Quadrature Receiv

3、er with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference2 of 43Outline Motivation&Backgrounds Proposed RX architectureWide band low noise RF front-endMulti-phase clock generation circuitryWideband tunable analog basebandImproved I-Q isolation with s

4、eparate Gm Measurement result Conclusions5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference3 of 43Challenges of Multi-Function RF ReceiverVery wide frequency coverage rangeTrade-offs of power/ga

5、in/noise in RF front-endPower hungry on-chip multi-phase clock generationVery wide signal bandwidth Baseband power consumption grows quasi linearly with signal bandwidthDesired reconfigurability complicates designM.Agiwal et al.,2016RFINADCADCDSPLNACLKIN2N Phase fLODividerNfLO5-1:A 5-to-16GHz Reconf

6、igurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference4 of 43Outline Motivation&Backgrounds Proposed RX architectureWide band low noise RF front-endMulti-phase clock generation circuitryWideband tunable analog basebandImp

7、roved I-Q isolation with separate Gm Measurement result Conclusions5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference5 of 43Overall Receiver DiagramRFinCLKICLKICLKICLKQCLKQCLKQIoutpCLKinLO Signa

8、lCLKICLKICLKQCLKQfin5,16GHzFeedforward Compensated OTAVIN-VIN+VOUT+VIN-VOUT-VIN+VCMEnhanced IQ SeparationDelay LineVcontrolVcontrolRing OscillatorIoutnQoutpQoutnMulti-Phase Clock GenerationWide Band RF Front-endDifferent Scaling5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle L

9、O and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference6 of 43Outline Motivation&Backgrounds Proposed RX architectureWide band low noise RF front-endMulti-phase clock generation circuitryWideband tunable analog basebandImproved I-Q isolation with separate Gm Measurement

10、result Conclusions5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference7 of 43TF1TF2TF3VddVg3Vg2Vg4Vg1inC1inL1inL2sL1auxCoL1oL2oC2inbCauxCinkok1aM1bM2bM2aM1bM2aM1L2L3L12k23k13kL1L3L22aMMulti-Stage

11、LNA with Triple-Winding Transformer Bandwidth expansion with multi-resonance interstage matching networkLimited design space due to reciprocity of fluxCauxenables independent control of k12,k13,k23 improved gain&NFElectric coupling+magnetic coupling expanded design space for certain frequenciesCapac

12、itor assisting triple-winding transformer(CTTF),T.Zou,et al.,RFIC 2022&TCAS-I 2023Break the reciprocityZ.Chen,et al.,RFIC 2018 +=Gain(dB)FrequencyGain(dB)FrequencyGain(dB)FrequencyInput matchingOutput matchingT.Zou,et al.,RFIC 2022&TCAS-I 20235-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with

13、50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference8 of 43Expanded Design Space with CauxIndependent control of k12,k13,k23enabled by auxiliary electric couplingEquivalent negative resistor in the tank enhances gain at high frequency5-1:A 5-to-16GHz Re

14、configurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference9 of 43Implementation of LNA&RF GmLNA with voltage amplification+RF Gm for current mode mixerInter-stage matching with CTTF for bandwidth extensionIsolated I-Q pat

15、hs to suppress I/Q mismatch details in later sectionTF1TF2CTTF TF3Two-stage LNACurrent-reused GmTF4,QTF4,I5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference10 of 43Pre-Simulation Results of LNA&

16、RF GmPerformance*Freq.(GHz)516ALNA+Gm*(dBS)-19-16.5Ripple(dB)1.5S11(dB)65across PVT cornersDifferential-mode PM 63across PVT corners5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference24 of 43Simu

17、lated Results of the RX Signal Chain32-72dB adjustable gain,100-500MHz adjustable baseband bandwidthNF 18dBm5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference25 of 43Outline Motivation&Backgroun

18、ds Proposed RX architectureWide band low noise RF front-endMulti-phase clock generation circuitryWideband tunable analog basebandImproved I-Q isolation with separate Gm Measurement result Conclusions5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression

19、2024 IEEE International Solid-State Circuits Conference26 of 43CLKICLKIIRFRoCLKQCLKQZBB,IZBB,QVBB,IVBB,QIBB,IIBB,QCLKICLKQCLKICLKQCLKICLKQCLKIRFINGmIQCLKQConventional Zero-IF Receiver Architecture Typical receiver employs RF Gm driving I-Q paths simultaneously25%duty cycle clocks required to accompl

20、ish IQ down conversionClock overlap leads to complex freq.dependent IQ mismatchCLK with overlapTypical implementationSimplified diagram5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference27 of 43C

21、LKICLKIIRFRoCLKQCLKQZBB,IZBB,QVBB,IVBB,QIBB,IIBB,QCLKICLKQI-Q Direct-Signal FeedthroughfDC2fLO-2fLOVBB,Q_leakVBB,ItT/4T/23T/4T2x frequency componentVBB,I_leakVBB,QtT/4T/23T/4T2x frequency componentI-Q Clock Overlap-Equivalent Circuit Model I-Q leakage modulated by rectangular wave2fLOThe modulation

22、contains DC component mixed with VBB,I&VBB,QVBB,I(j)&VBB,Q(j)depend on frequency response of ZBB(j)ZBB(j)changes dramatically,especially with increasing fBBFourier transform5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International So

23、lid-State Circuits Conference28 of 430ReBB-BBI+jQImVBB,QQ0ReImBB-BBVBB,Q_leak0ReImBB-BBVBB,IIVBB,I_leak0ReBB-BBI+jQImVBB,QQ0ReImBB-BBVBB,Q_leak0ReImBB-BBVBB,IIVBB,I_leakFrequency Domain Interpretation(1)Lower Sideband DCUpper Sideband DC I-Q feedthrough generates an additional frequency component.Fr

24、eq.independent I-Q mismatch component generated at DC5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference29 of 430ReBB-BBI+jQImVBB,QQ0ReImBB-BBVBB,Q_leak0ReImBB-BBVBB,IIVBB,I_leak0ReBB-BBI+jQImVBB

25、,QQ0ReImBB-BBVBB,Q_leak0ReImBB-BBVBB,IIVBB,I_leakFrequency domain interpretation(2)Lower SidebandUpper Sideband I-Q feedthrough generates an additional frequency component.Non-conjugate gain and phase error between upper/lower sidebands5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty

26、-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference30 of 430ReBB-BBI+jQImVBB,QQ0ReImBB-BBVBB,Q_leak0ReImBB-BBVBB,IIVBB,I_leak0ReBB-BBI+jQImVBB,QQ0ReImBB-BBVBB,Q_leak-BB0ReImBBVBB,IIVBB,I_leakFrequency domain interpretation(3)Lower SidebandUpper Sideband I-Q f

27、eedthrough generates an additional frequency component.Non-conjugate gain and phase error between upper/lower sidebandsMore prominent with freq.dependent ZBB(j)5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Cir

28、cuits Conference31 of 43Complex l/Q Mismatch without l/Q Isolation ZBB(j)emphasizes complex I/Q mismatch at higher offset freq.Overhead in DSP for I/Q mismatch compensation Two possible design choicesFrequency-independent ZBB(j)difficult with growing fBBEnhance I-Q isolation reasonable with low desi

29、gn overheadQCLKICLKICLKICLKQCLKQCLKQZLZBB,QIZBB,IZLZLZLIRFRoGmGm5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference32 of 43Suppressed Complex l/Q Mismatch in Proposed Design Separate Gm into I-Q

30、pathsExtra power consumption in Gm not significant for current mode operation50%duty-cycle clocks simplified clock generation circuitComplex I/Q mismatch suppressed by over 10XQCLKICLKICLKICLKQCLKQCLKQZLZBB,QIZBB,IZLZLZLGmGmRFINLNAEnhanced IQ SeparationGmGm5-1:A 5-to-16GHz Reconfigurable Quadrature

31、Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference33 of 43Outline Motivation&Backgrounds Proposed RX architectureWide band low noise RF front-endMulti-phase clock generation circuitryWideband tunable analog basebandImproved I-Q isolation

32、 with separate Gm Measurement results Conclusions5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference34 of 43LNA+GmMPCLK+MixerAnalog Baseband1.8mm526um0.95 mm2 core area.28nm CMOS technology.Die M

33、icrograph&Power BreakdownPower(mW)fLO=16GHz,500MHz BWfLO=5GHz,500MHz BWfLO=16GHz,100MHz BWfLO=5GHz,100MHz BWLNA12.7 12.712.712.7Gm25.3 25.325.325.3MPCLK22.411.522.411.5Analog baseband49.049.026.226.2Total109.498.586.675.75-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and I

34、Q-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference35 of 43Conversion Gain Measurements Conversion gain and filtering across different LO frequencies.32 dB36 dB48 dB52 dB62 dB72 dB5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppr

35、ession 2024 IEEE International Solid-State Circuits Conference36 of 43Reconfigurability&S11 MeasurementsGain&BW Adjustable fLO=12GHzS11-4dB around 56GHzInaccurate EM modeling of matchingS11-8dB across 7-20GHz5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Sup

36、pression 2024 IEEE International Solid-State Circuits Conference37 of 43NF&Linearity MeasurementsNF at different LO frequenciesMeasured at 200MHz offset frequenciesLinearity at different LO frequenciesIn Band(IB):f1,2=fLO+20/25MHzOut of Band(OOB):f1,2=fLO+500/600MHz 5-1:A 5-to-16GHz Reconfigurable Q

37、uadrature Receiver with 50%Duty-Cycle LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference38 of 43Blocker Tolerance MeasurementsBlocker NF Gain=52 dB,fBLK=fLO+1GHz.Blocker 1dB Gain=52 dB,BW=500MHz.5-1:A 5-to-16GHz Reconfigurable Quadrature Receiver with 50%Duty-Cycle

38、 LO and IQ-Leakage Suppression 2024 IEEE International Solid-State Circuits Conference39 of 43I-Q Mismatch Measurements Gain Mismatch 1dB Phase Mismatch TLO/85.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE Inter

39、national Solid-State Circuits Conference16 of 49Proposed Single-Ended Passive HR MixerVRF,1VRF,0VRF,2VRF,3VRF,4VRF,5VRF,6VRF,7tVS(t)VRF(t)Ca=Cb2142VS+RSCbVRFCa8VBB?How lossy is this?VRF,0+2VRF,1+VRF,2Combination of bottom-plate and top-plate mixing.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with B

40、uilt-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference17 of 49Time Domain Operation I142VS+RsCbVRFVRF,41234Ca1Bottom-plate mixing5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+

41、16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference18 of 49Time Domain Operation II142VS+RsCbVRFVRF,41234CaVRF,12Top-plate mixing5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IE

42、EE International Solid-State Circuits Conference19 of 49Time Domain Operation III142VS+RsCbVRFVRF,21234Ca3Overwriting a stack of pre-charged capacitors5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE Internationa

43、l Solid-State Circuits Conference20 of 49Readout PhaseCbCa2 Falling Edge 2 Rising Edge VRF,2VRF,4VRF,15.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference21 of 49Readout

44、PhaseCbCaVRF,2VRF,4VRF,12 Falling Edge 2 Rising Edge 5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference22 of 49Readout PhaseCbCaVRF,2VRF,4VbVRF,1VaDuring 2 Clock Phase

45、V=Va+VbVRF,2VRF,4+VRF,1Va=1+2VCa=Cb25.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference23 of 49Readout PhaseCbCaVRF,1VaVa=1+2VCa=Cb22 Falling Edge VBBVBB=VRF,1+Va=2VRF,1

46、+VRF,21+2-VRF,4+5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference24 of 49Readout PhaseCbCaVRF,1VaVa=1+2VCa=Cb22 Falling Edge VBBVBB=VRF,1+Va=2VRF,1+VRF,21+2-VRF,4+VRF,

47、0=-VRF,4 used to address negative tap in this structure.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference25 of 49Implemented Effective LO142VS+RSCbVRFCa8=CVBBVS+RsLOef

48、f8VRFVBB,mJNo 3rd/5th harmonic blocker at BB.(dB)J+1.37dB Gain0,2,1,0,-1,0,0,01+2hn=2 2 fLO:5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference26 of 49Implemented Effect

49、ive LO142VS+RSCbVRFCa8=CVBBJ+1.37dB Gain(dB)How lossy is VRF/VS?VS+RsLOeff8VRFVBB,mJNo 3rd/5th harmonic blocker at BB.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference

50、27 of 49Harmonic Response VRF/VS(dB)Normalized Frequency(fLO)0123456780-5-10-15-20-25-30 VRF/VS(dB)Normalized Frequency(fLO)0123456780-5-10-15-20-25-30H1=-0.2dBH1=-1.8dB0127CCRSVSVRF142VS+RSCbVRFCa8Ca=Cb2C=Ca+CbVBBConventional 8-Path MixerProposed HR MixerJ Only 1.6dB loss penalty for desired signal

51、.J Mostly compensated by+1.37dB conversion gain from modified LO.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference28 of 49Harmonic Response VRF/VS(dB)Normalized Freque

52、ncy(fLO)0123456780-5-10-15-20-25-30 VRF/VS(dB)Normalized Frequency(fLO)0123456780-5-10-15-20-25-30H1=-0.2dBH1=-1.8dBH3=-22dBH5=-24dBJ Key feature of HR at the antenna.0127CCRSVSVRF142VS+RSCbVRFCa8Ca=Cb2C=Ca+CbVBBConventional 8-Path MixerProposed HR Mixer5.2:0.25-to-4GHz Harmonic-Resilient Receiver w

53、ith Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference29 of 49Transient Response07654321VRF(t)(mV)0300-300-15015007654321VBB,1(t)(mV)5010002575ttVS(t)ProposedConventionalProposedConventionalJ Mixer switches exposed to

54、low 3fLO voltage swing.0127CCRSVSVRF142VS+RSCbVRFCa8Ca=Cb2C=Ca+CbVBBConventional 8-Path MixerProposed HR Mixer5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference30 of 49

55、Transient Response07654321VRF(t)(mV)0300-300-15015007654321VBB,1(t)(mV)5010002575ttVS(t)ProposedConventionalProposedConventionalJ Complete 3rd harmonic blocker suppression at mixer output.0127CCRSVSVRF142VS+RSCbVRFCa8Ca=Cb2C=Ca+CbVBBConventional 8-Path MixerProposed HR MixerVBB,1+-VBB,1+-J Mixer swi

56、tches exposed to low 3fLO voltage swing.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference31 of 49Differential Implementation Evolution214CaCb650CbVBB,5124CaCb650CbVBB,

57、18RFpRFn5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference32 of 49Differential Implementation Evolution214CaCb650CbVBB,5124CaCb650CbVBB,18RFpRFnn Differential RF inputn

58、 Antiphase switching5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference33 of 49Differential Implementation Evolution214CaCb650CbVBB,5124CaCb650CbVBB,1RFpRFnn Redraw the

59、circuit485.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference34 of 49Differential Implementation Evolution214CaCb650CbVBB,5124CaCb650CbVBB,1RFpRFn45.2:0.25-to-4GHz Harmon

60、ic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference35 of 49Differential Implementation Evolution21CaCb65CbVBB,512CaCb65CbVBB,1RFpRFn404Virtual Groundare halvedSharing common switches halves RS

61、W,0&RSW,4.Four slicesSix LO phase/path5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference36 of 49Harmonic Rejection ExtensionRF+RF-1515CaVBB,5CaVBB,14Conventional 8-Path

62、 Passive Mixer 5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference37 of 49Harmonic Rejection ExtensionRF+RF-1515CaVBB,5CaVBB,14462260CbCbHarmonic Rejection ExtensionJ Pa

63、ssive mixers readily convert to HR mixers with minimal circuitry.Ca=Cb25.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference38 of 49System Block Diagram1:2Off-chipBalun2:1

64、approximated by 17:12Input Matching*Minimum-sized switches for biasingRFpRFn4fLO5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference39 of 49Die Micrographn Technologyl45n

65、m SOI GlobalFoundriesn Silicon Areal0.68 mm2n Power Supplyl1.2V for Clockl1.0V for BB LNA880 m770 m5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference40 of 49Outlinen Mo

66、tivation and Introductionn Active and Passive Harmonic Rejectionn Proposed Passive Harmonic Rejection Architecturen Measurement Resultsn Conclusion5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International So

67、lid-State Circuits Conference41 of 49Measured Gain,S11 and NFn The operation frequency range of 0.25GHz-4GHz with a conversion gain of 33dB.n The lower number of switches results in NF of 2.6-5.5dB across the LOs.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achievi

68、ng+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference42 of 49Measured IIP3n Out-of-Band IIP3 of 26dBm is achieved for an fLO=1GHz and f/BW=10.n+52/44 dBm IIP3 is obtained for the two-tone test near 3rd/5th harmonics.5.2:0.25-to-4GHz Harmonic-Resilient Receiv

69、er with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference43 of 49Measured Harmonic Blocker P1dB1GHzffreqfLO2fLO3fLO4fLO5fLO3fLO:14.0dBm5fLO:16.5dBm5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Anten

70、na and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference44 of 49-25-20-15-10-505103dBMeasured Harmonic Blocker NF3fLO:5.0dBm5fLO:6.5dBmfLO=1GHz5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm

71、 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference45 of 49Comparison TableActive HRPassive HRProposed HR5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Ci

72、rcuits Conference46 of 49Comparison Table3rd harmonic blocker noise figure reaches 7dB at 16x and 4x higher power compared to state-of-the-art active and passive HR receivers,respectively.Active HRPassive HRProposed HR5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Ac

73、hieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference47 of 49Outlinen Motivation and Introductionn Active and Passive Harmonic Rejectionn Proposed Passive Harmonic Rejection Architecturen Measurement Resultsn Conclusion5.2:0.25-to-4GHz Harmonic-Resilien

74、t Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference48 of 49ConclusionLORFBBHR MixerPowerFreq.RangeFlexibleLinearityNoisenThe proposed fully passive HR mixer offers harmonic rejection right at the Antenna

75、 as well as BB.nThis work achieves the highest HB1dB with only1dB noise figure degradation for 0dBm 3rd HB.nThis technique requires minimal extra switches and capacitors and benefits from technology scaling.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/

76、+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference49 of 49Acknowledgmentsn The authors thank the MIT MTL faculty for equipment assistance.n The chip fabrication was financially supported by MIT Center for Integrated Circuits and Systems(CICS).Thank you for your

77、 attention.5.2:0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving+14/+16.5dBm 3rd/5th IB Harmonic B1dB 2024 IEEE International Solid-State Circuits Conference50 of 49Please Scan to Rate This Paper5.3:A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a N

78、on-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference1 of 30A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOSMostafa Ay

79、esh,Soumya Mahapatra,Ce Yang and Mike Shuo-Wei ChenUniversity of Southern California,Los Angeles,CAabouelkausc.edu5.3:A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS 2024 IEEE International Solid-State

80、 Circuits Conference2 of 30Outlinen Motivationn Non-Uniform Discrete-Time ReceiverlNon-Uniform Sampling lNon-Uniform FIR Filtern System Implementationn Measurement Results n Conclusion5.3:A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 4

81、2dB Blocker Rejection in 28nm CMOS 2024 IEEE International Solid-State Circuits Conference3 of 30MotivationJ Low power consumption J Small areaL Destructive aliasingL Higher noise figureL Sharp BPFL Significant power consumptionL Large areaJ No aliasingJ Lower Noise FigureHomodyne ReceiverSub-Sampli

82、ng ReceiverLNARF InputADCSub-Sampling ClockBPFClk BufferQuadrature Generator/DividersLO0o90o180o270oClk Buffer180o0oLPFLNARF InputClk Buffer180o0oADCLPFfcfLO=fcfs 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference1 of 48MWTIC-LabA 22.430.7GHz Phased-Array Rec

83、eiver WithBeam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial RejectionYiming Yu,Bohan Sun,Mengqian Geng,Chenxi Zhao,Huihua Liu,Yunqiu Wu,Jingzhi Zhang,Kai KangUniversity of Electronic Science and Technology of China,Chengdu,China5.4:A 22.430.7GHz Phased-Array

84、 Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference2 of 48Self Introduction Education Ph.D.Degree,University of Electronic Science andTechnology of China(UESTC),2017 B.S.,UESTC,20

85、12 Experience 2018-2019;Lecturer,UESTC 2020-2021;Visiting Fellow,Princeton University 2021-Present,Associate Professor,UESTC Research Interests Millimeter-wave and terahertz integrated circuits On-chip multi-channel transceiver front-endYiming Yu5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Patt

86、ern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference3 of 48Outline Motivation&Background Proposed Phased-Array ReceiverBeam-Pattern Null-Steering(BPNS)TechniqueBeam-Tracking(BT)Method Circuit Implementati

87、on Measurement Results Conclusion5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference4 of 48Outline Motivation&Background Proposed Phased-Array Receiv

88、erBeam-Pattern Null-Steering(BPNS)TechniqueBeam-Tracking(BT)Method Circuit Implementation Measurement Results Conclusion5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-Sta

89、te Circuits Conference5 of 48Motivation&Background The phased-array technique is a promising solution for 5Gmm-Wave high-capacity wireless communication;Complicatedelectromagneticenvironmentmayresultinspatially diversified interference.Electromagnetic Environment BSBSBSUEsPhased Array SystemTRX5.4:A

90、 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference6 of 48LNALNALNALNASpatial-Notch FilterLOLOLOLOMotivation&BackgroundLOILOQLOILOQLOILOQAPFLNALNALNALNAAP

91、FAPFAPFXENSpatial-Notch FilterRFIN1RFIN2RFIN3RFIN4LOILOQ Digital Beamforming RX Spatial Notch FilterM.Huang,JSSC19L.Zhang,ISSCC22 Reject blockers at mm-Wave frequencies Support N-input-N-output MIMOs Limited scalability due to symmetrical layout requirement Support MIMO operation Fast response time

92、Spatial notch generation at IF(power-hungry VGAs etc.)5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference7 of 48Motivation&Background RF Beamforming

93、RX Beam TaperingA/D Lossy attenuators or power-hungry VGAs Main-lobe gain degradation Mature process method High scalabilityATT or VGATheoretical Analysis:88 Array5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial

94、Rejection 2024 IEEE International Solid-State Circuits Conference8 of 48Outline Motivation&Background Proposed ArchitectureBeam-Pattern Null-Steering(BPNS)TechniqueBeam-Tracking(BT)Method Circuit Implementation Measurement Results Conclusion5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern N

95、ull-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference9 of 48Proposed Phased-Array Receiver Two RF channels+a blocker-elimination(BE)circuit+abeam-tracking(BT)module+adigital control block;The BE circuit is to t

96、ackle thespatial in-band blockers;The BT module is to trackdesired signals and blockersincident angles.ArchitectureBTPD2PD1Signal ProcessingPD3TLIN3TLIN3TLIN4PD-HybridPGA2PGA3PGA1R3R1R1R2R2CouplerTLIN1TLIN1TLIN2TLIN2dBs BESPIUNIT1LNAPSDACDARF CH1LNAPSDACDARF CH2MixerA/DLOIF AMP-B Blockers Desired Si

97、gnalDACDACBE-VGA1BE-PS15.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference10 of 48Proposed Architecture:BPNS Technique BE Circuit Placed between two

98、adjacent RF channels;Extract blockers and adjust their phase and amplitude;Consist of two resistive couplers,a phase shifter,a VGA,etc.R1R1TLIN1TLIN1TLIN2TLIN2dBs BESPIUNIT1LNAPS1DACDARF CH1LNAPS1DACDARF CH2DACDACBE-VGA1BE-PS1Combiner and MixerRF CH0RF CHns-B 5.4:A 22.430.7GHz Phased-Array Receiver

99、With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference11 of 48Proposed Architecture:BPNS Technique Signal-Flow Analysis The desired signals after phase shifters in RF channelsare summed in pha

100、se at the output.j10RF Out1j10 Outputj10RF Out2 RF ChainRF Out1RF Out2RF CH1OutputRF CH2d=/2s-B BE5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference

101、12 of 48Sub In1Sub In2BE InRF CH1OutputRF CH2BEd=/2s-B BE OutProposed Architecture:BPNS Technique Signal-Flow Analysisj10RF Out1j10 Outputj10RF Out2 RF Chain The subtractor cancels the in-phase desired signals,andno signal flows into the BE circuit.j10Sub In1j10Sub In2No signal flow into BEj10BE Out

102、BE Circuit5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference13 of 48Proposed Architecture:BPNS Technique Blocker-Flow AnalysisRF Chainj10j10RF Out1j

103、10RF Out2 Blockers in RF chains are summed by the combiner withdifferent phases.RF Out1RF Out2RF CH1OutputRF CH2d=/2s-B BE5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-S

104、tate Circuits Conference14 of 48j10j10RF Out1j10j10Sub In1Sub In210jBE In-j10 BE out j10RF Out2Gmejm BE Proposed Architecture:BPNS TechniqueRF ChainBE Circuit TheblockeradjustedbytheBEcircuithasthesameamplitude but opposite phase with that summed in RF chains.Blocker-Flow AnalysisSub In1Sub In2BE In

105、RF CH1OutputRF CH2BEd=/2s-B BE Out5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference15 of 48Proposed Architecture:BPNS Technique The blockers are ca

106、ncelled after the combiner.RF ChainBE Circuitj10j10RF Out1j10j10Sub In1Sub In210jBE In-j10 BE out j10RF Out2Gmejm BE j10OutputNo Blocker Output Blocker-Flow AnalysisRF Out1RF Out2Sub In1Sub In2BE InBE OutRF CH1OutputRF CH2BEd=/2s-B 5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steer

107、ing and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference16 of 48 By adjusting the BE circuit,the BE factor(BEF)has the same amplitude but oppositephase with the generic array factor(GAF)at the blockers incident angle.With

108、1 BlockerRadiation Pattern4 elements with 1 BE circuitProposed Architecture:BPNS TechniqueLNAPS1DACDARF CH1LNAPS1DACDARF CH2LNAPS1DACDARF CH3LNAPS1DACDARF CH4CombinerBE-VGABE-PSBE()()f,X ()()BG()()B5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques A

109、chieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference17 of 48Radiation Pattern High spatial rejection is achieved after thecombiner at a specific angle.4 elements with 1 BE circuitWith 1 BlockerProposed Architecture:BPNS TechniqueLNAPS1DACDARF CH1LNAPS1

110、DACDARF CH2LNAPS1DACDARF CH3LNAPS1DACDARF CH4CombinerBE-VGABE-PSBE()()f,X ()()BG()()B5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference18 of 48Propo

111、sed Architecture:BPNS TechniqueWith 2 Blockers(N=4,M=2)The total BEF has the same amplitudesbut opposite phases with the GAFs atboth the two blockers incident angles.N elements with M BE circuits Multiple Blockers Process BE1LNAPSDACDARF CH1LNAPSDACDARF CH2BEMLNAPSDACDARF CHN-1LNAPSDACDARF CHNCombin

112、erOutputwith BEBE-VGA1BE-PS1()()f,()()BG1()()B1()()MBG()()MB 5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference19 of 48Proposed Architecture:BPNS Te

113、chnique Multiple Blockers Process N elements with M BE circuits Both the two blockers are suppressed at the output.With 2 Blockers(N=4,M=2)BE1LNAPSDACDARF CH1LNAPSDACDARF CH2BEMLNAPSDACDARF CHN-1LNAPSDACDARF CHNCombinerOutputwith BEBE-VGA1BE-PS1()()f,()()BG1()()B1()()MBG()()MB 5.4:A 22.430.7GHz Phas

114、ed-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference20 of 48Proposed Architecture:BPNS Technique For a large-scale phased-array RX,it cantackle multiple blockers simultaneo

115、uslyby integrating several BE circuits.s.t.Linear Array Factor with BE:BE FactorGeneric Array Factor()()()()()()BBBMFFF12,()()()()()()()()()()()()mBmmMNjj xujx ujjnuBmBmnFfGeeee e111,|,+=+=+=+()()()()()()Susinsin=mxN1,1N elements with M BE circuits Multiple Blockers Process BE1LNAPSDACDARF CH1LNAPSD

116、ACDARF CH2BEMLNAPSDACDARF CHN-1LNAPSDACDARF CHNCombinerOutputwith BEBE-VGA1BE-PS1()()f,()()BG1()()B1()()MBG()()MB 5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Cir

117、cuits Conference21 of 48Proposed Architecture:BT Method Block diagram Track unknown signal beam,as well as blocker;Consist of three parallel process paths.VBT1PD1PD2Signal ProcessingPGA1PGA2PGA3R3PD3R2BEVBT2VBT3Con.BitsLNAPS1DACDARF CH(i-1)LNAPS1DACDARF CH(i)PD-HybridR2SPIUNITR1R1s-B 5.4:A 22.430.7G

118、Hz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference22 of 48VBT1PD1PD2Signal ProcessingPGA1PGA2PGA3R3PD3R2BEVBT2VBT3Con.BitsLNAPS1DACDARF CH(i-1)LNAPS1DACDARF CH(i)P

119、D-HybridR2SPIUNITStep1:Step1:R1R1s-B()()Sin(itVA1)sin =()()SSin(iVAt)sin=+Proposed Architecture:BT Method Principle of the BT Module The incident angle(S)of the signal beam can be calculatedby the outputs of Paths 1&2 with a hybrid.M.Huang,et al.,JSSC19SBTSVA21/2(2cos()2SBTSVA22/2(2cos()2+BTBTSBTBTV

120、VVV1212/1arcsin/1=+=+5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference23 of 48VBT1PD1PD2Signal ProcessingPGA1PGA2PGA3R3PD3R2BEVBT2VBT3Con.BitsStep2

121、:LNAPS1DACDARF CH(i-1)LNAPS1DACDARF CH(i)PD-HybridR2SPIUNITStep2:Step2:R1R1s-B()()()()Sin(iBtVtAA1)ssnnii =+=+()()()()SBSin(iBAtVAt)is nsin +=+()()()()BBinBSAtAVtsinsin=+Proposed Architecture:BT Method Principle of the BT Module With the third path,the blockers incident angle(B)canalso be calculated

122、 during the desired signal transmission.BTSBBVA32(2sin()2()()BTiniiniVVjEnvelopeV11()()BTiniiniVEnvelojVVpe21+BBSAA,5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State C

123、ircuits Conference24 of 48Outline Motivation&Background Proposed ArchitectureBeam-Pattern Null-Steering(BPNS)TechniqueBeam-Tracking(BT)Method Circuit Implementation Measurement Results Conclusion5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achi

124、eving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference25 of 48Circuit ImplementationSimplified Architecture Two RF channels:a high-linearity LNA&6-bit phase shifter(PS);One BE circuit:two resistive couplers,subtractor,6-bit PS and 6-bit VGA;OneBTmodule:Hybr

125、id,resistivecouplers,power detectors(PDs),andprogrammable gain amplifiers(PGAs);Power combiner,and SPI,etc.PDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3Vout5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB O

126、TA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference26 of 48Circuit Implementation:High-Linearity LNA k1k1M1AM1BCC1CC1VG1 k2k2VG2VDDk0SVG0GGVout+Vout-VDD A CG amplifier with a balun load+a CSstructure with cross-coupled capacitorsand source inductors;IP1-dB:-8dBm,Gain:

127、14.28dB,NF:3.57dB,BW:2435.5GHz Simplified ArchitecturePDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3Vout5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International S

128、olid-State Circuits Conference27 of 48Circuit Implementation:Wideband PS Vector-sum architecture I/Q signal generator+VGAs+Adder+DACSimplified ArchitectureI/Q Signal GeneratorVGAVGAI+I-Q+Q-AdderDACBit0Bit5Vin+Vin-Vout+Vout-PDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3Vout5.4

129、:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference28 of 48Circuit Implementation:Wideband PSVGAs Resolution:6bits;Average Gain:0.8dB;BW:2442GHz.DACIN+I

130、N-Ultra-Wideband HybridSimplified ArchitecturePDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3VoutM1M2M3M4VCI/QVout+Vout-I+I-Q+Q-IQVI/QVCI/QVCI/QVbiasVDDVIVQVCIVCQ5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2

131、dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference29 of 48PDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3VoutCircuit Implementation:Wideband VGA CC1CC1 Vin+Vin-VaVaVbVbVout k2VDDk1k1VDDk2 k3VDDk3Vbias Variable-gain structure+differential CS

132、structure with neutralization capacitors;IP1dB:-7dBm,Gain Tuning Range:16dB,BW:22.936.5GHzSimplified Architecture5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circ

133、uits Conference30 of 48Circuit Implementation:PD&PGA Square-law power detector;Two-stage structure with three parallelgain controlling paths(10100dB).+-+R4R2R3S1S2S3Vin+Vin-Vout+Vout-VrefS1S2S3+-+R6R7R8S4S5S6VrefR1R1R4R2R3R5R5R6R7R8S4S5S6OPAOPAVinVbias2Vbias2VPD+Vbias1VDDVPD-PDPGASimplified Architec

134、turePDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3Vout5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference31 of 48Circuit Impl

135、ementation:Hybrid&CombinerPD-HybridFully Symmetrical Meander-Line CombinerSimplified ArchitectureC3C3PINISOTHRCPL170m180 mBERF CH1RF CH2GSGW=2.5 L=0 0/4/4W=2.5 L=0 0/4/4W=2.5 L=0 0/4/4W=2.5 L=0 0/4/4W=6W=6W=2.5 L=0 0/4/4W=2.5 L=0 0/4/4W=2 L=0 0/4/4W=2 L=0 0/4/4W=6 L=324324W=6 L=324324W=6W=6W=6Subtra

136、ctor174m94 mPDViniLNALNAPSVGAPSComb.PGAPDBEHyb.BT-1BT-2BT-3SPIVini+1PSVBT1VBT2VBT3Vout5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference32 of 48Outl

137、ine Motivation&Background Proposed ArchitectureBeam-Pattern Null-Steering(BPNS)TechniqueBeam-Tracking(BT)Method Circuit Implementation Measurement Results Conclusion5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatia

138、l Rejection 2024 IEEE International Solid-State Circuits Conference33 of 48Measurement Results Fabricated in a 65-nm Bulk CMOS process;Chip Area:3.01.7mm2;Total Power Consumption:212.1mW(70mW/RF Element).D AD ALN ALN APSPSD AD APSPSLN ALN ASPISPIBEBEBTBTW PDW PDW PDW PD3.0mmRF Chains 140mWBE Circuit

139、 70mWBT Module 2.1mWPDC Breakdown5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference34 of 48Measurement Results On-Chip Measurement SetupS-parameter

140、Measurement SetupVector Network AnalyzerDUTDC PowerGSGGSG1.85mm CableFPGAControl ModuleModulation Measurement SetupDUTGSGGSG1.85mm CableSpectrum AnalyzerMixerVector Signal GeneratorSignal Generator1.85mm Cable1.85mm CableDC PowerFPGAControl&Process Module5.4:A 22.430.7GHz Phased-Array Receiver With

141、Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference35 of 48Measurement Results Single-channel Testing:gain,NF,and IP1dB 3-dB gain-bandwidth is 8.3GHz from 22.4 to 30.7GHz；At 24 31GHz,NF and IP1d

142、Bare 5.1 6.5dB and-8.4 -7.5dBm,respectively.5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference36 of 48Measurement Results Single-channel Testing:pha

143、ses and RMS errors RMS Amplitude Error 0.38dBRMS Phaee Error 0.651 2628GHz RMS phase error is 0.65at 25.6 28.8GHz；RMS gain error is 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference37 of 48Measurement Results Single-channel Testing:Modulation64QAM 2.4Gb/sPin

144、:-13dBm Freq:28GHzEVM:-34.25dB0256QAM,3.2Gb/sPin:-13dBm Freq:28GHzEVM:-34.19dB The tested EVMs are-34.25dB for 64QAM and-34.19dB for 256QAM with-13dBm input power；The supported data rate is up to 3.2Gb/s.5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techni

145、ques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference38 of 48Measurement Results Assemble two RX chips with a PCB-based series-fed patchantenna array on a PCB.Horn AntennaSignal GeneratorRX1.7mFPGA-90+90Absorbent Rubber MaterialAbsorbent Foam Mate

146、rialSpectrum AnalyzerRX prototypeMeasurement SetupSMAWilkinson CombinerPatch Antenna ArrayChip2Chip15.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conferen

147、ce39 of 48Measurement Results Radiation Pattern with enabling BE circuitsOne-Blocker RejectionTwo-Blocker Rejection The tested blocker rejections are 37dB,the RXs sidelobe level is decreased by 15.226.2dB at blockers angles.5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and

148、Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference40 of 48Measurement Results Radiation Pattern with enabling BE circuits The proposed BPNS technique can also support wide-angle blocker rejection.Wide-Angle Rejection5.4:A 22

149、.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference41 of 48Measurement Results Radiation Pattern with enabling BE circuitsBy tuning the PSs and VGAs in the B

150、E circuits,the beampatterns null is shifted from 22.5to 63accordingly;The corresponding spatial rejection is higher than 30.2dB.Null-Steering Validation5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2

151、024 IEEE International Solid-State Circuits Conference42 of 48Measurement Results Beam Steering The phased-array RXs measured beam scanning range is 36(limited by used antenna array).5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB

152、 OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference43 of 48Measurement Results Measured characteristic of the BT module The tested beam-angle indicator(0)by the BT module agreeswell with the theoretical value.OTA measured with one incident beam5.4:A 22.430.7GHz Phas

153、ed-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference44 of 48Measurement ResultsReferenceThis WorkJSSC 2022 2ISSCC 2022 5CICC 2021 6JSSC 2019 4ISSCC 2018 7Technology65nm CMO

154、S130nm SiGeBiCMOS40nm CMOS65nm CMOS45nm CMOS SOI130nm SiGe BiCMOSArchitectureRF BF+BPNSRF BF+Beam TaperingDigital BF+RF SNFRF BF+RF SSADigital BF+IF ASFIF BF+RF&IF SSAFrequency(GHz)22.4 30.724 3023 2924 3227 4123 30Element No.4(2/Chip)84448NF(dB)5.1 6.53.14.84.34.3 6.34.2 6.3IP1dB(dBm)-7.5 -8.4-31-1

155、4-23.1N/AN/ARMS phase Error 0.65*1.35N/A0.51#N/AN/ARMS Gain Error(dB)0.38*0.5N/A30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference45 of 48Outline Motivation&Background Proposed ArchitectureBeam-Pattern Null-Steering(BPNS)TechniqueBeam-Tracking(BT)Method Circu

156、it Implementation Measurement Results Conclusion5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference46 of 48Conclusion A wideband phased-array RX is d

157、emonstrated for 5G new radio;A beam-pattern null-steering(BPNS)technique is proposed totackle spatial in-band blockers by tuning nulls of radiationpatterns;A beam-tracking(BT)method is developed to detect incidentangles of both desired signal and blocker;The phased-array RX achieves-8.4dBm IP1dBand

158、an OTA-tested spatial rejection of 30.2dB without sacrificing array gain;It also achieves-34.25dB EVM for 64QAM and-34.19dB EVM for256QAM(3.2Gb/s data rate)with-13dBm input power 28GHz.5.4:A 22.430.7GHz Phased-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2

159、dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference47 of 48References1 J.G.Lee,et al.,A 60-GHz Four-Element Beam-Tapering Phased-Array Transmitter With a Phase-Compensated VGA in 65-nm CMOS,IEEE TMTT,vol.67,no.7,pp.2998-3009,Jul.2019.2 B.Sadhu,et al.,A 24-30-GHz 2

160、56-Element Dual-Polarized 5G Phased Array Using Fast On-ChipBeam Calculators and Magnetoelectric Dipole Antennas,IEEE JSSC,vol.57,no.12,Dec.2022.3 L.Zhang,et al.,“Arbitrary Analog/RF Spatial Filtering for Digital MIMO Receiver Arrays,”IEEEJSSC,vol.52,no.12,pp.3392-3404,Dec.2017.4 M.Huang et al.,A mm

161、-Wave Wideband MIMO RX with Instinctual Array-Based Blocker/SignalManagement for Ultralow-Latency Communication,IEEE JSSC,vol.54,no.12,pp.3553-3564,Dec.20195 L.Zhang et al.,A 23-to-29GHz Receiver with mm-Wave N-input-N-output Spatial Notch Filteringand Autonomous Notch-Steering Achieving 20-to-40dB

162、mm-Wave Spatial Rejection and-14dBm in-Notch IP1dB,ISSCC,pp.82-84,Feb.2022.6 W.Zhu et al.,A Dual-Mode 2432 GHz 4-Element Phased-Array Transceiver Front-End with SSABeamformer for Autonomous Agile Unknown Signal Tracking and Blocker Rejection within 30.2dB OTA-Tested Spatial Rejection 2024 IEEE Inter

163、national Solid-State Circuits Conference48 of 48Acknowledgement This work was supported in part by the National NaturalScience Foundation of China under Grant 62025106 and Grant62171102 and in part by the Natural Science Foundation ofSichuan under Grant 2022NSFSC0560.Thank you!5.4:A 22.430.7GHz Phas

164、ed-Array Receiver With Beam-Pattern Null-Steering and Beam Tracking Techniques Achieving 30.2dB OTA-Tested Spatial Rejection 2024 IEEE International Solid-State Circuits Conference49 of 48Please Scan to Rate This Paper5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming

165、 less than 25mW 2024 IEEE International Solid-State Circuits Conference1 of 28A Stacking Mixer-First Receiver(MF-RX)Achieving 20dBm Adjacent-Channel IIP3 Consuming less than 25mWStef van Zanten,Ronan van der Zee and Bram NautaUniversity of Twente,Enschede,The Netherlands5.5:A Stacking Mixer-First Re

166、ceiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference2 of 28OutlineIntroductionCapacitive Feedback ConceptMF-RX Prototype ImplementationMeasurement ResultsConclusions5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Cha

167、nnel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference3 of 28OutlineIntroductionCapacitive Feedback ConceptMF-RX Prototype ImplementationMeasurement ResultsConclusions5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW

168、 2024 IEEE International Solid-State Circuits Conference4 of 28Mixer-First Receiver(MF-RX)Highly flexible Linear alternative toLNTA-based RX First-order baseband filtering Switches limit linearity Improve selectivity5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming l

169、ess than 25mW 2024 IEEE International Solid-State Circuits Conference5 of 28MF-RX Selectivity ImprovementCascadingstagesLien,JSSC19Higher-order BB impedancePini,JSSC20Krishnamurthy,SSC-L21Goal:Third-order filtering at low-power.5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3

170、 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference6 of 28OutlineIntroductionCapacitive Feedback ConceptMF-RX Prototype ImplementationMeasurement ResultsConclusions5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEE

171、E International Solid-State Circuits Conference7 of 28MF-RX Selectivity Overview and TerminologyRegular MF-RX-20 dB/decade slope5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference8 of 28Positive Cap

172、acitive Feedback Lien,JSSC19Increases ZBB IBIncrease CB restore BW usingpositive feedback roll-off OOBExtent of increased slope coupled to NF increase5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Confere

173、nce9 of 28Negative(Miller)Capacitive FeedbackDecreases ZBB OOBImproves OOB rejectionOr,smaller C area for same BWBut,needs large loop BW5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference10 of 28Pro

174、posed Dynamic Capacitive FeedbackTransition(1)IB positive into(2)OOB negativefeedbackAdvantagesSteep slope(-60 dB/dec)Breaks trade-off IB NF increaseLowers required loop BWImproved selectivity even beyond loop BW5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less

175、than 25mW 2024 IEEE International Solid-State Circuits Conference11 of 28Capacitive Stacking MF-RXStacking MF-RXPurushothaman,JSSC20 Provides Av 2Improves NFCB CRWeinreich,JSSC23Reduces RF lossCBdefines BWAllows for capacitivefeedback at baseband5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdj

176、acent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference12 of 28OutlineIntroductionCapacitive Feedback ConceptMF-RX Prototype ImplementationMeasurement ResultsConclusions5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less

177、 than 25mW 2024 IEEE International Solid-State Circuits Conference13 of 28Dual Path Feedback Implementation5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference14 of 28Dual Path Feedback Transfer Func

178、tionMagnitude increases with 40 dB/decPhase rotates-180 degreesA(f)OOB PathIB Pathfc|A(f)|dBfBBHz A(f)degfc-loopO(RHP)O(LHP)X X(HPF)X(loop BW)5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference15 of

179、 28Proposed MF-RX Overview5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference16 of 28Signal Flow In-Band5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 2

180、5mW 2024 IEEE International Solid-State Circuits Conference17 of 28Signal Flow Out-of-Band5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference18 of 28Transistor-Level Implementation5.5:A Stacking Mix

181、er-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference19 of 28Stability and PVT Robustness|T(f)|dBfBBHz T(f)degIm-T(f)Re-T(f)Open Loop TF across corners(fast,typical,slow)at 27 CNyquist plot of-T(f)acrosscorners and T-4

182、0,27,80 C5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference20 of 28Die Micrograph and Power Breakdown22 nm FDSOI technology0.35 mm total area(excluding padring)0.22 mm active areaStatic power break

183、down:Main AmplifierFeedback NetworkBiasingTotal:9.7 mW5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference21 of 28OutlineIntroductionCapacitive Feedback ConceptMF-RX Prototype ImplementationMeasureme

184、nt ResultsConclusions5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference22 of 28Transfer Function and Small-Signal LinearitySC21at 3 GHz fLOIIP3vs.offset f1tone|SC21|dBIIP3 dBmfBBHzOffset f1 BWfcLoo

185、p onLoop offLoop onLoop offAdjacent channel IIP37 22 dBm5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference23 of 28Transfer Function&S11vs.LO FrequencyfLOGHz|SC21|dB|S11|dB5.5:A Stacking Mixer-First

186、 Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference24 of 28Noise Figure MeasurementsNF vs.fBBMin.NF vs.fLONF dBNF dBfBBMHzfLOGHz5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25m

187、W 2024 IEEE International Solid-State Circuits Conference25 of 28Summary and Performance ComparisonThis WorkMontazerolghaemISSCC 2023RazaviJSSC 2022KrishnamurthySSC-L 2021PiniJSSC 2020Lien JSSC 2018ArchitectureMF-RXLNTA basedLNTA basedMF-RXMF-RXMF-RXTechnology22 nm FDSOI40 nm28 nm28 nm28 nm45 nm SOI

188、RF InputSingle-endedSingle-endedSingle-endedSingle-endedDifferentialDifferentialfRF GHz1.2 60.4 7.30.4-60.2 3.50.5 20.2 8Gain dB323854163221BB BW MHz201500.1 801513010NF dB4.7 5.53.2 5.8 3.21,26.6 125.572.3 5.49NF Degr.fcdB+5+2.81+0.21,2N/A+6.81,8+0.21,8Adjacent channel IIP3 dBm(2fc)20 25101-261,523

189、121161Power mW9.7+2.5mW/GHz100+13mW/GHz23 4913 39689 14921.6+7.8mW/GHz50+30mW/GHz1Estimated from plots.2NF for 40 MHz channel-bandwidth case,at 5 GHz LO.3Low-noise mode.4Harmonic rejection mode.540 MHz channel-bandwidth case.6Excluding harmonic traps.7NF at 2 GHz LO.8Simulation data.9NF reported for

190、 0.5 6 GHz LO.20 dBmadjacentchannelIIP3 at lowestpower5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference26 of 28OutlineIntroductionCapacitive Feedback ConceptMF-RX Prototype ImplementationMeasureme

191、nt ResultsConclusions5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference27 of 28Conclusions Dynamic capacitive feedback enhances MF-RX selectivity A stacking MF-RX with low losses provides passive v

192、oltage gain Improved selectivity yields good adjacent channel IIP3at low power5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference28 of 28Acknowledgments GlobalFoundries for providing silicon fabrica

193、tionthrough the 22FDX university program.My colleagues from the ICD group at the University of Twente for their support.This project has received funding from the European Research Council(ERC)under the European Unions Horizon 2020 research and innovation programme(grant agreement No 834389).5.5:A Stacking Mixer-First Receiver Achieving 20dBmAdjacent-Channel IIP3 Consuming less than 25mW 2024 IEEE International Solid-State Circuits Conference29 of 28Please Scan to Rate This Paper