Session 4Analog Techniques.pdf

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1、Session 4 Overview:Analog Techniques ANALOG SUBCOMMITTEEAnalog t echniques t o improve circuit performance,power efficiency,and cost-effect iveness are present ed.The first paper int roduces a high-speed ADC front-end,followed by t he second paper showing a fully int egrat ed frequency management mo

2、dule.The next t wo papers describe new analog conduct ion angle cont rol t echniques for ult ra-low-power cryst al oscillat ors,and a highly power-efficient RC oscillat or wit h an improved t emperat ure coefficient follows.The last paper present s a CMOS-based volt age reference in a 3nm FinFET t e

3、chnology.Session Chair:Jiawei Xu Fudan Universit y,Shanghai,China Session Co-Chair:Drew Hall Universit y of California,San Diego,CA 74 2025 I EEE I nt ernat ional Solid-St at e Circuit s ConferenceISSCC 2025/SESSION 4/ANALOG TECHNIQUES/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 I EEE4:50 PM 4.4 A 0.36

4、nW/0.9V 32kHz Crystal Oscillator Using Analog Regulation for Cross-Current Avoidance Tobias Chlan,Technical Universit y Munich,Munich,Germany I n Paper 4.4,t he Technical Universit y Munich shows an ult ra-low-power 32.768kHz oscillat or wit h an analog amplit ude regulat ion for sub-nano power cons

5、umpt ion of 0.36nW at 0.9V.The 0.047mm2 design in 0.18um CMOS t echnology enables a large supply volt age range from 0.9 t o 2V wit h process t racking.5:05 PM 4.5 A 0.4W/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/C from-40 to 1

6、25C Yueduo Liu,Universit y of Elect ronic Science and Technology of China,Chengdu,China I n Paper 4.5,t he Universit y of Elect ronic Science and Technology of China present s an open-loop reference-replicat ion-based RC oscillat or.The prot ot yped 10MHz RC oscillat or in 65nm CMOS achieves a power

7、 efficiency of 0.4W/MHz,a t emperat ure coefficient of 9.83 ppm/C from 40 t o 125C,and a die area of 0.0085mm2.5:20 PM 4.6 A 0.8V,31ppm/C,-40dB DC-to-GHz Power-Supply-Rejection Standard-Vth Core-MOS-Only Voltage Reference with a 294m2 Area Bei-Shing Lien,TSMC,Hsinchu,Taiwan I n Paper 4.6,TSMC presen

8、t s a single-Vt h CMOS-based volt age reference in a 3nm FinFET t echnology.The circuit provides a ripple-less reference volt age wit h a line regulat ion of 0.04%/V,a power-noise reject ion of 39dB SNDR for 1 to 32GHz in 22nm FDSOI Josef Heel,Universit y of Twent e,Enschede,The Net herlands I n Pap

9、er 4.1,t he Universit y of Twent e present s a 12.8GS/s 4 t ime-int erleaved t rack-and-hold front-end.Fabricat ed in 22nm FDSOI,t his ADC front-end achieves 40.9dB SNDR and 49.6dB SFDR at 30.2GHz input frequency for RF sampling applicat ions wit hout t he need for skew calibrat ion.476 2025 IEEE In

10、ternational Solid-State Circuits ConferenceISSCC 2025/SESSION 4/ANALOG TECHNIQUES/4.1979-8-3315-4101-9/25/$31.00 2025 IEEE4.1 A 12.8GS/s Sub-Sampling ADC Front-End wit h 38GHz Input Bandwidt h and 39dB SNDR for 1 t o 32GHz in 22nm FDSOI Josef Heel1,Harijot Singh Bindra1,Simon Louwsma2,Alessandro Dez

11、zani3,Bram Nauta1 1University of Twente,Enschede,The Netherlands 2Teledyne DALSA Semiconductors,Enschede,The Netherlands 3Teledyne e2v,Grenoble,France The demand for higher data rates combined with the crowded wireless spectrum results in a trend towards millimeter-wave frequencies.RF-sampling archi

12、tectures offer advantages in terms of flexibility,simplicity and robustness.However,presenting the ADC directly with tens of GHz at the input poses significant challenges especially to the front-end,leading to a demand for high-bandwidth-and fidelity implementations.This work targets RF-sampling of

13、X-band to Ka-band frequencies while maximizing signal purity and a Nyquist bandwidth of 6.4GHz to allow flexibility and multi-channel reception,but minimizing system complexity and data-rate overhead.The focus is on the lower Ka-band around 27 to 31GHz used for high-throughput Earth-to-Satellite com

14、munication applications.Direct-sampling a signal at fIN 30GHz with fS 60GS/s offers maximum flexibility.Recent ADCs for wireline applications 1 have demonstrated 6.0 ENOB at fIN=28GHz and fS=105GS/s,but require skew calibration between interleaved ADC lanes 1-3.Additionally,the high data rate(500Gb/

15、s)is difficult to handle and overly power-intensive,given that typical channel bandwidths are significantly lower for long-range wireless applications.Considering a reduced-rate approach,recent work 4 with fS=12GS/s has demonstrated a remarkable resolution of 8.7ENOB at fIN=5.71GHz.However,the perfo

16、rmance is usually optimized only for the first Nyquist zone,and rapidly deteriorates above that.This limits their usability for RF sub-sampling.To achieve flexibility and high signal purity at fIN 30GHz but avoid calibration and data rate overhead,we propose a sub-sampling approach with fS=12.8GS/s,

17、one actively bootstrapped first-rank Track-and-Hold(TH1)and a 4 interleaved second-rank TH2(Fig.4.1.1).Maximizing TH-bandwidth BWTH rather than fS allows to use a non-interleaved TH1,which alleviates the need for skew and bandwidth calibration.This well-known technique 5 is rarely used for multi-GS/

18、s applications because it halves the usable TH1 tracking time.However,it becomes attractive in a sub-sampling system where more tracking time is available,but where the sensitivity to skew/bandwidth mismatch increases in higher Nyquist zones.Additionally,a single TH1 performs the critical first freq

19、uency translation with less loading of the input than an interleaved TH1.This allows to implement bootstrapping to enhance sampling linearity while maintaining BWTH 35GHz despite its additional loading.The apparent downside of sub-sampling compared to direct-sampling is aliasing both interferers and

20、 noise in-band 6.However,the roll-off requirements for the anti-alias bandpass filter are relaxed by the large Nyquist bandwidth of 6.4GHz 7.The extended TH1 tracking time allows to choose a larger sampling capacitor,resulting in reduced thermal noise.To demonstrate the merits of the outlined approa

21、ch,a prototype ADC front-end up to TH2 is manufactured in 22nm FDSOI.It achieves BWTH=38GHz and 40.9dB SNDR(equivalent to 6.5 ENOB)at fIN=30.2GHz,which lies in the 5th Nyquist zone.The pseudo-differential input path and TH1 are crucial for both bandwidth and linearity.To alleviate signal attenuation

22、 and minimize reflections(S11)due to capacitive loading of the 50 input,a three-stage input network is employed(Fig.4.1.2,top).Stage 1 consists of a-LPF formed by an inductor LS and CPAD/CESD about 35fF each.It is designed for Z0=50 and theoretically pushes fC to 100GHz for that section.Stage 2 cons

23、ists of a bridged T-coil to reduce the impact of CBUF 120fF while maintaining good return loss.Stage 3 employs a peaking inductor LP to compensate the roll-off associated with traditional T-coil implementation without significant return-loss degradation.Electromagnetic simulation indicates a bandwid

24、th of 45GHz at the buffer input and S11 35GHz and maintain high linearity.Bootstrapping is beneficial in both respects because a constant VGS on the TH1 switch not only increases linearity,but also eliminates the loading of the signal path caused by the switchs CGS,allowing to use comparably larger

25、devices with lower RON.However,for the bootstrapping to be effective,it needs(at least)the same bandwidth as the signal path.Traditional capacitive bootstrapping 8 is not optimal because the critical path involves multiple RF nodes and a large bootstrapping capacitor,which all contribute parasitic l

26、oading.Therefore,we propose an active bootstrapping 9 approach with two stacked push-pull source-followers fully integrated in CMOS(Fig.4.1.2).Individual biasing with replica devices ensures that the bootstrap signal VA always stays about 0.7V above the buffered input signal VM to maximize switch ga

27、te overdrive while avoiding over-stressing the gate oxide during switching transients.The AC-coupling allows VCM=0V at the input while independently optimizing the buffer biasing.This leads to about 40GHz bandwidth for both signal-and bootstrapping path for CS1 90fF,which consists of routing parasit

28、ics and the interstage buffer input capacitance.The TH1 sampling switch is implemented as an NMOS pair with cross-coupled always-off devices to compensate for capacitive hold-feedthrough(Fig.4.1.3).To avoid voltage stress and unnecessary slewing,VG,OFF during hold is set to 0.2V.The interstage buffe

29、r decouples the held voltage of TH1 from TH2 and is implemented as a power-efficient push-pull source follower with a backgate bootstrap to reduce attenuation caused by the backgate effect.Buffers and switches in TH1/2 are designed according to standard voltage/electromigration reliability rules(10y

30、/100C)for this technology.TH2 is implemented as four parallel PMOS pairs with cross-coupled always-off devices.Due to the lower input frequency compared to TH1,bootstrapping was not required to maintain overall linearity.However,1.2V swing clocks are employed to optimize RON versus leakage during ho

31、ld.The clock alignment between TH1 and TH2 is crucial to avoid overlap given a tracking time of only 39ps.To achieve minimal skew,the TH1 clock is gated locally with a 1-out-of-4 signal generated by a flip-flop ring reset to 0111b and running at full fS=12.8GHz(Fig.4.1.3).TH1 and TH2 clock paths are

32、 carefully designed to match delay variations,where simulation indicates less than 4ps change over corners/temperature.The jitter-critical TH1 clock path is similar to 10,but implemented in single-ended CMOS only.Driving a CMOS input directly with a 800mVpp sinusoid gives a higher slew rate than a C

33、ML buffer using the same core voltage,reducing the intrinsic jitter to about 15fsrms according to simulation.To maximize power supply integrity,a separate clean clock supply is provided.A prototype is realized in 22nm FDX technology of GlobalFoundaries with an active area of 0.12mm2,which includes i

34、nductors and TH1/2,but excludes decimator and pads.Its performance is evaluated by decimating the analog TH2 output samples on-chip by NDEC=85,capturing the 150.6MS/s output with an oscilloscope and resampling the data on a PC.After only off-chip foreground offset calibration is performed once per s

35、ample,SNDR and other metrics are derived from a 4096-point FFT(Fig.4.1.7).Both signal and clock paths(cables,balun,probes)are carefully de-embedded by VNA measurements to present the chip with signals as if it was driven with ideal 50 sources at full scale.No other measurement non-idealities like no

36、ise and distortion from the signal generators/oscilloscope/decimator are removed.Figure 4.1.4 shows dynamic performance of sample 1 over fIN in about 1GHz steps,achieving 40dB SNDR(39dB for all samples)from 1 to 32GHz,with 40.9dB SNDR at 30.2GHz.The SNDR is mostly noise-limited except for some point

37、s around 20GHz,where additional distortion is assumed to be caused by supply integrity issues at the main buffers.The SFDR is limited by THD and not by interleaving spurs,demonstrating the merits of the single first-rank TH to avoid skew/bandwidth calibration.A sweep over fS indicates a 1.3dB SNDR f

38、luctuation from 4.8 to 15.2GS/s.The SNR decrease towards lower fS can be attributed to signal loss caused by leakage and to additional low-frequency noise/jitter components impacting more at an increased FFT record length.The-3dB bandwidth is measured at 38GHz,and the input match stays below S11 -12

39、dB up to 38GHz.Power consumption is about 87mW including all blocks except the decimator with its output buffer.All samples are measured with identical settings except the global reference bias current,which was slightly adjusted per sample for equal power consumption to ensure best comparability.Di

40、fferences between four samples and a 10%variation on all supplies showed 1dB SNDR fluctuation at 30.2GHz input,and 4%bandwidth fluctuation,demonstrating the robustness of the approach(Fig.4.1.5).A comparison with other state-of-the-art TH implementations 11-13 is given in Fig.4.1.6.This work stands

41、out with the best SNDR for inputs around 30GHz at a power consumption 39dB SNDR at a more moderate output rate,thereby saving additional digital power consumption.This demonstrates the merits of the presented approach for wide bandwidth applications like SatCom or software-defined radio.Ac knowl e d

42、ge me nt:The authors would like to thank GlobalFoundries for providing silicon fabrication through the 22FDX university program.Furthermore,we thank Salim Renane for providing funding from Teledyne e2v,and Alexander Delke and Arnoud Rop for CAD/measurement support.Figure 4.1.1:Typical applicat ion(t

43、 op)and block diagram of t his ADC front-end wit h addit ional facilit ies for measuring t he int erleaved TH out put (bot t om).Figure 4.1.2:Proposed input net work for bandwidt h ext ension(t op)and act ive boot st rapping TH1 wit h simulat ion result s of bot h combined(bot t om).0100ps200ps0.00.

44、61.3015GHz30GHz45GHz1050proposed implementationVDD1.2V1.8V0.8VCPADLSRTLPCBUFCB50?50?-LPFfc 100 GHzZ0?50?90fF peaking inductorbridgedT-coil mainbufferLSCS1auxiliarybufferAVAVMVMVGVGVTH1VTH1VINVINVAVMVGVTH1VINVINVGVTH1VINVshort pathCS1VINVOUTlong pathCBCS1VG,OFF4mA10mAAC simulationmagnitude(dB)voltage

45、(V)transient simulation-3dB?40 GHzVDDCESDproposed input networktraditional bootstrappingactive bootstrapingTH1BPFAA12.8 GHzclockLNABPFinput networkKa-bandsub-ADCsub-ADCsub-ADCsub-ADCto DSPauxiliarybufferterm.clock buf.this ADC front-endTH2 clk.div.decimatormeas.buffer mainbuffer SIGINinterstagebuffe

46、rN1CLKINCLKOUTSIGOUT?1?1?2aTH2b?2b?2c?2ddec.clk.div.:NDECLSTH2aTH2dterm.clock generationTH2cR adj.38 GHz bandwidthCS1 clock phasesT HT HT H?1?2a?2bTH2 sample abcdabcdabcdabcdabcdabcdbabcDecimator outFigure 4.1.3:Implement at ion det ails of t his ADC front-end.To ensure fast rise/fall t imes on t he

47、 TH1 gat e but avoid volt age st ress,shift ed core-level clocks drive a t hick-oxide high-side swit ch and a cascoded t hin-oxide low-side swit ch.Figure 4.1.4:Dynamic performance measurement s over fIN and fS,wit h a low-frequency(fIN=1GHz)and a high-frequency(fIN=30.2GHz)out put spect rum.VG,OFF(

48、0.2V)VG1.2V1.2V1.2V10.6V4x1.8V1N0.8V0.8V1.2VR1.2VGSGSG0.2VTSPC FF ringinputnetworkterm.D Q0D Q1D Q1D Q1GSSGGSGdecimatormeas.bufferRTH1TH2main buf.interst.buf.neg.sideaux.buf.CS1?90fF(buffer input+routing parasitics)CS2?100fF(decimator input+routing parasitics)Clock pathFigure 4.1.5:Performance measu

49、rement s for different samples and supply condit ions,TH-bandwidt h,RF input mat ching and power consumpt ion.Figure 4.1.6:Comparison of st at e-of-t he-art THs and ADCs.ADC and TH power are not comparable,but SNDR is t ypically front-end limit ed for RF frequencies.TCAS-II16 Tretter BCICTS Du18 JSS

50、C22 Thomas JSSC18 Kull VLSI18 Kull ISSCC24 Li ISSCC24 Whitcombe Unit This work 11 12 13 3 14 10 1 2 Type-TI front-end Front-end Sampler TI front-end Full ADC Full ADC Full ADC Full ADC Topology-RF term.,2-stage sampler RF term.,1-stage sampler RF term.,1-stage sampler RF term.,1-stage sampler TI-SAR

51、 TI-SAR TI-SAR TI-time/voltage hybrid Channels-4 1 1 4 16 48 192 48 Calibration1 O No No No O,G,S,B O,G,S,B O,G,S O,G,S fS GS/s 12.8 25 25.6 128 72 32 105 40 BW(-3dB)GHz 38 55 40(-1dB)57 21 26 40 n.a.SNDRHF2 dB 40.9 30 38.1 153 30.4 37.8 37.9 32.3 SFDRHF2 dB 49.6 n.a.45.7 303 44.1 48.2 n.a.45.9 THD

52、dB-47.2-34-42.6 n.a.-45.7-51.3 n.a.n.a.fIN,HF GHz 30.2 32 25 30 36.1 39.8 28 20 Power mW 87 73 913 3500 n.a.5 n.a.5 n.a.5 n.a.5 Input swing mVppd 700 4004 500 1000 500 600 n.a.500 Techn.22nm FDSOI 28nm CMOS 130nm BiCMOS 90nm BiCMOS 14nm FinFET 14nm FinFET 16nm FinFET 22nm FinFET Active area mm2 0.12

53、 0.03 1.5 0.2 0.15 0.16 n.a.0.103 Supplies V 1.8/1.2/0.8 1.75/1.4 5.5/3.5 4.85 0.9/0.8 0.95/0.8 n.a.0.85 1 calibration:O=offset,G=gain,S=time skew,B=bandwidth mismatch.2 when available,SNDR/SFDR is compared close to fIN=30 GHz.3 SNR taken for SNDR(noise-limited).SFDR varies over channels,so approxim

54、ate value given.4 also 800mV possible,but less comparable to this work.5 no power numbers for the standalone ADC front-end available.Power of full ADC is not comparable to this work.ISSCC 2025/February 17,2025/3:35 PM77 DIGEST OF TECHNICAL PAPERS 4 2025 IEEE International Solid-State Circuits Confer

55、enceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 4.1.7:Measurement set up illust rat ion including a micrograph of t he prot ot ype chip fabricat ed in 22nm FDSOI.inputnetworkPCBclkctrl.TH1LSLPT-coilTH2deci-matorMarkiBAL-0036balunpower supplyAnritsu MG3624

56、1Ainputsignalclock30.2 GHzGSGSG probeKeysight E8267D-544Tektronix MSO64BGSGSG probeFFTre-sampleand computeFFT on PC:SNDR,SNR,THD,SFDR,bandwidthclock supplymaster bias currentserialcontrol12.8 GHz0.8V0.8V 1.2V 1.8V20uA920um980umRe f e re nc e s:1 G.Li et al.,“A 600Gb/s DP-QAM64 Coherent Optical Trans

57、ceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS,”2024 IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2024,pp.338-340,doi:10.1109/ISSCC49657.2024.10454499.2 A.Whitcombe et al.,“A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Inp

58、ut Tracking,”2024 IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2024,pp.392-394,doi:10.1109/ISSCC49657.2024.10454355.3 R.L.Nguyen et al.,“A 200GS/s 8b 20fJ/c-s Receiver with 60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET,”2024 IEEE Inte

59、rnational Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2024,pp.344-346,doi:10.1109/ISSCC49657.2024.10454385.4 Y.Cao,M.Zhang,Y.Zhu,R.P.Martins and C.-H.Chan,“A 12GS/s 12b 4 Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer,”2024 IEEE

60、 International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2024,pp.388-390,doi:10.1109/ISSCC49657.2024.10454350.5 K.Poulton,J.J.Corcoran and T.Hornak,“A 1-GHz 6-bit ADC system,”in IEEE Journal of Solid-State Circuits,vol.22,no.6,pp.962-970,Dec.1987,doi:10.1109/JSSC.1987.1052844.6 R.G

61、.Vaughan,N.L.Scott and D.R.White,“The theory of bandpass sampling,”in IEEE Transactions on Signal Processing,vol.39,no.9,pp.1973-1984,Sept.1991,doi:10.1109/78.134430.7 D.Jakonis,K.Folkesson,J.Dbrowski,P.Eriksson and C.Svensson,“A 2.4-GHz RF sampling receiver front-end in 0.18um CMOS,”in IEEE Journal

62、 of Solid-State Circuits,vol.40,no.6,pp.1265-1277,June 2005,doi:10.1109/JSSC.2005.848027.8 A.M.Abo and P.R.Gray,“A 1.5-V,10-bit,14.3-MS/s CMOS pipeline analog-to-digital converter,”in IEEE Journal of Solid-State Circuits,vol.34,no.5,pp.599-606,May 1999,doi:10.1109/4.760369.9 A.Ramkaj,M.Perrott,B.Har

63、oun and B.Murmann,“High-Linearity High-Bandwidth(20GHz)T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design,”2023 IEEE International Symposium on Circuits and Systems(ISCAS),Monterey,CA,USA,2023,pp.1-5,doi:10.1109/ISCAS46773.2023.10181490.10 L.Kull et al.,“A 10-Bit

64、 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration,”2018 IEEE Symposium on VLSI Circuits,Honolulu,HI,USA,2018,pp.275-276,doi:10.1109/VLSIC.2018.8502268.11 G.Tretter,D.Fritsche,M.M.Khafaji,C.Carta and F.Ellinger,“A 55-GHz-Bandwidth Track-and-Hold Amplifie

65、r in 28-nm Low-Power CMOS,”in IEEE Transactions on Circuits and Systems II:Express Briefs,vol.63,no.3,pp.229-233,March 2016,doi:10.1109/TCSII.2015.2503579.12 X.-Q.Du,M.Grzing and M.Berroth,“A 25.6-GS/s 40-GHz 1-dB BW Current-Mode Track and Hold Circuit with more than 5-ENOB,”2018 IEEE BiCMOS and Com

66、pound Semiconductor Integrated Circuits and Technology Symposium(BCICTS),San Diego,CA,USA,2018,pp.56-59,doi:10.1109/BCICTS.2018.8550855.13 P.Thomas,J.Finkbeiner,M.Grzing and M.Berroth,“Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s,”in IEEE Journal o

67、f Solid-State Circuits,vol.57,no.9,pp.2599-2610,Sept.2022,doi:10.1109/JSSC.2022.3192546.14 L.Kull et al.,“A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and 30 dB SNDR at Nyquist in 14-nm CMOS FinFET,”in IEEE Journal of Solid-State Circuits,vol.53,no.12,pp.3508-3516,Dec.2018,do

68、i:10.1109/JSSC.2018.2859757.78 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 4/ANALOG TECHNIQUES/4.2979-8-3315-4101-9/25/$31.00 2025 IEEE4.2 A 1.8-t o-3.0GHz Fully Int egrat ed All-In-One CMOS Frequency Management Module Achieving-47/+42ppm Inaccuracy from -40 t o 95C and

69、-150/+70ppm Aft er Accelerat ed Aging Runtao Huo1,Tong Zhang1,Weihao Jie1,Yanling Zheng1,Deyong Li1,Li Gao2,Yang Zhao1,Honglan Jiang1,Yongfu Li1,Patrick Mercier3,Hui Wang1 1Shanghai Jiao Tong University,Shanghai,China 2South China University of Technology,Guanzhou,China 3University of California,San

70、 Diego,CA Accurate and stable frequency-management modules(FMMs)are a critical component in wired/wireless communication systems since they determine key metrics such as data rate and bit-error rate.Conventional FMMs utilize a crystal reference to stabilize a frequency synthesizer with configurable

71、output frequencies,as shown in Fig.4.2.1(top).However,using a bulky off-chip crystal can,in some cases,add too much cost and/or size for small IoT applications.Replacing the crystal with other off-chip references based on MEMS/BAW/SAW-type structures 1 doesnt quite solve this problem;the best soluti

72、on would be full on-chip integration.However,on-chip frequency references,commonly implemented with RC cores(Fig.4.2.1 bottom left),have difficulty in meeting the frequency accuracy requirement of typical wired/wireless protocols 2.Moreover,RC-based references exhibit an unacceptable frequency sprea

73、d due to their poor aging performance,for example with worse than a 1030ppm spread after accelerated aging even with methods such as redundancy design and employment of different CMOS resistors 3,4.Importantly,prior work has struggled simply to build an on-chip reference suitable for crystal-replace

74、ment,and has not taken the further step of integrating the on-chip reference into a synthesizer to build a fully-integrated FMM a step necessary to prove the viability of full on-chip integration for low-cost IoT applications.This work presents a fully integrated direct-frequency-synthesis FMM(DFS-F

75、MM,shown in Fig.4.2.1 bottom right)that achieves a compact,low-cost,crystal-free implementation by:1)fully integrating an on-chip temperature-stabilized LC-based reference(fLC=1024MHz)with low-noise AC-coupled varactor tuning and tail-resistor biasing that achieves 10 better aging performance compar

76、ed to RC counterparts;2)directly operating the synthesizer at fLC that grants 10 wider loop bandwidth for 20dB ring-oscillator(RO)noise suppression;3)leveraging the high loop bandwidth to achieve fast frequency hopping via a 7s settling time;and 4)exploiting the high-frequency sinusoidal reference t

77、ogether with high-gain direct-reference sampling without requiring a divider(of high division ratio M)in the feedback loop that would otherwise consume additional power while also amplifying the in-band noise by M2 as in conventional PLLs,ultimately achieving a 3dB improved FoMJIT compared to state-

78、of-the-art RO-based PLLs.As shown in Fig.4.2.2(top),a temperature-compensated LC reference is utilized.Its 1024MHz output,CKLC,is directly sampled by the output of a digital-to-time converter(DTC)via CKDTC.The samplers output is then amplified by a Gm stage and filtered by a loop filter consisting o

79、f RLF and CLF1,LF2,which ultimately tunes the voltage-controlled RO generating the final FMM output,CKOUT.The proposed DFS structure enables direct high-gain reference sampling without requiring any slope generators as in most conventional reference-sampling PLLs,while achieving fine output-frequenc

80、y control with low-division-ratio feedback as in sub-sampling PLLs for improved noise performance.The synthesizer is designed with an ultra-wide bandwidth of 75MHz and uses a 4mW pseudo-differential RO.In addition,a phase-frequency detector with a dedicated dead zone and a charge pump is employed to

81、 ensure a wide locking range.To implement an FMM at 2.4GHz with a channel spacing of 1MHz,CKOUT is first divided by 2 to obtain quadrature phases to drive a combination of a phase interpolator and a DTC that modulates the phase of CKOUT.As shown in Fig.4.2.2(center-left),the phase of the clock at th

82、e input of the phase interpolator,CKPI with a frequency fPI that is half of fOUT,is delayed by N/(2048fPI)where N is the channel to be selected in each CKLC cycle such that the rising edge of CKDTC always aligns with that of CKLC,thus fPI=(1+N/2048)fLC.As a result,fOUT=fLC(2+N/1024),corresponding to

83、 a minimum channel spacing of 1MHz.This approach is employed since the LC reference cannot on its own generate sufficient fine channel with adequate linearity.Figure 4.2.2(bottom-left)shows the implementation of the temperature-compensated 1024MHz LC reference,where cross-coupled pairs with reused b

84、ias currents are used to save power while current-limiting resistors,RCL,optimize noise performance compared to tail current sources 5.Moreover,a frequency-tuning circuit with improved low-frequency noise performance is implemented with AC-coupled varactors.As shown in Fig.4.2.2(bottom-center),high-

85、frequency noise is suppressed by the parasitic node capacitance at VLC 6,while the AC coupling filters out low-frequency noise such as flicker noise from the LC tank,achieving an additional 10dB improvement at a 10kHz offset in simulation.Temperature compensation is obtained by modulating VLC.Specif

86、ically,as shown in Fig.4.2.2(bottom-right),the difference between a PTAT and CTAT current IPTAT,CTAT is fed to a resistive TIA biased at VCALI for the generation of VLC.Center frequency calibration and first-order temperature compensation are achieved by trimming the LC at two temperature points thr

87、ough IPTAT and VCALI.Moreover,a CTAT voltage,VCTAT,generated by the bandgap placed close to the LC tank,represents the chip temperature for a polynomial batch-calibration engine.The 3rd-order calibration engine modulates VCALI and eventually compensates for the high-order TC of the LC reference thro

88、ugh VLC.As shown in Fig.4.2.3(top),the quadrature divider generates clocks with a simulated accuracy better than 0.2ps,which are then interpolated by a phase interpolator array to achieve a resolution of 26ps.An RC-based passive 3b phase interpolator scheme 7 is utilized in this work to avoid nonlin

89、earities such as channel length modulation and current source noise experienced by other schemes that charge capacitors with current sources,ultimately achieving an INL of 1.4ps and phase noise of-130dBc/Hz at 1kHz offset in simulation.The phase interpolator output is buffered and fed to a DTC for a

90、n extra 6b fine phase modulation.As shown in Fig.4.2.3(center),the DTC employs a 6b thermometer-weighted capacitor DAC and achieves a simulated INL of 0.45ps.To match the DTC delay range with the duration corresponding to the phase interpolators one LSB,the gain of the DTC is trimmed based on a look

91、up table by adjusting the current-limiting source transistor,MCS,achieving a simulated LSB of 0.4ps while making the impact of its nonlinearity and gain error on the overall phase modulators linearity negligible.As shown in Fig.4.2.3(bottom),the output of the DTC then drives a phase generator for th

92、e generation of differential non-overlapping sample-and-hold clocks for the reference sampler,where bootstrapped switches Msmp-p,smp-n are employed for proper sampling of CKLC-P,LC-N,which has a peak-to-peak voltage of 0.6V.On the other hand,switches Mhld-p,hld-n handle well-defined DC voltages duri

93、ng the steady state and are implemented with transmission gates.Csmp is 150fF to minimize the kT/C noise while ensuring adequate power and area overhead.Finally,a 1.8mS Gm stage followed by a compact loop filter completes the PLL,achieving an ultra-wide BW with over 45dB at 100kHz offset RO phase-no

94、ise suppression as shown in Fig.4.2.3(bottom-right).As shown in Fig.4.2.4(top-left),the frequency inaccuracies of the LC reference and the overall DFS-FMM measured from 18 samples are both-47/+42ppm from-40C to 95C,corresponding to a TC of 0.66ppm/C,showing that the ultra-wide-band synthesizer contr

95、ibutes negligible temperature variation.As shown in Fig.4.2.4(top-center and right),the proposed DFS-FMM shows a worst-case frequency error and nominal frequency spread of-150/+70ppm and-120/+70ppm,respectively,when measured from the same 18 samples after one week of accelerated aging at 150C.Figure

96、 4.2.4(bottom-left)shows that the measured rms period jitter of the LC reference is 0.82ps and the measured Allan deviation floor of the LC reference is 0.07ppm(Fig.4.2.4,bottom-center).Figure 4.2.4(bottom-right)shows that the proposed DFS-FMM settles within 7s.Figure 4.2.5(top and center)shows the

97、measured phase noise of both the LC reference and the overall DFS-FMM.Within the loop bandwidth,the DFS-FMMs phase noise is approximately 7.4dB higher than the LC reference phase noise at the corresponding frequencies while the DFS-FMMs out-of-band noise overlaps with the RO phase noise.The measured

98、 JitterRMS of the proposed LC reference,synthesizer,and DFS-FMM when integrated from 10kHz to 100MHz is 916fs,172fs,and 932fs,respectively.The measured spur of the DFS-FMM is-53.6dBc(Fig.4.2.5,bottom).Figure 4.2.6 summarizes the performance of the proposed DFS-FMM and compares its reference and synt

99、hesizer to the state-of-the-art counterparts.As shown in Fig.4.2.6(Table I),the proposed DFS-FMM represents a fully integrated DFS-FMM and achieves state-of-the-art frequency accuracy with excellent frequency-hopping-time capabilities.Compared to the standalone references and synthesizers,Fig.4.2.6(

100、Tables II and III)show that the reference implemented in the proposed DFS-FMM sets new benchmarks in frequency accuracy and long-term stability for CMOS references,while the synthesizer occupies an over 5 smaller area with a comparable FoMJIT and spur performance compared to LC-based synthesizers an

101、d achieves an over 3dB better FoMJIT compared to RO-based synthesizers.Figure 4.2.1:Convent ional implement at ion wit h separat e frequency-reference generat ion and frequency synt hesis and t he proposed fully int egrat ed low-cost DFS-FMM.Figure 4.2.2:Schemat ic of t he proposed DFS-FMM,t he prin

102、ciple of fract ional-N synt hesis for a 1MHz fine-channel st ep,and implement at ion of t he LC Reference.Figure 4.2.3:Schemat ic of t he phase modulat or(t op),implement at ion of t he reference sampler(bot t om-left),and PN profile wit h ult ra-wide-BW synt hesizer(bot t om-right).Figure 4.2.4:Top

103、:measured frequency error of t he LC reference and DFS-FMM before,aft er,and during t he accelerat ed aging.Bot t om:measured period jit t er of t he LC reference,Allan deviat ion of t he LC reference,and frequency-hopping t ime of t he DFS-FMM.Figure 4.2.5:Measured LC reference PN(t op),DFS-FMM PN(

104、cent er),and measured spur of t he proposed DFS-FMM(bot t om).Figure 4.2.6:Performance summary of t he proposed DFS-FMM and comparison wit h st at e-of-t he-art st andalone reference and st andalone synt hesizer.ISSCC 2025/February 17,2025/4:00 PM79 DIGEST OF TECHNICAL PAPERS 4 2025 IEEE Internation

105、al Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 4.2.7:Die micrograph and power breakdown of t he proposed DFS-FMM.Re f e re nc e s:1 D.Griffith et al.,“An Integrated BAW Oscillator with 30ppm Frequency Stability Over Temperat

106、ure,Package Stress,and Aging Suitable for High-Volume Production,”ISSCC,pp.58-60,Feb.2020.https:/doi.org/10.1109/ISSCC19947.2020.9062945 2.Grleyk et al.,“A 16 MHz CMOS RC Frequency Reference With 90 ppm Inaccuracy From 45 C to 85 C,”IEEE JSSC,vol.57,no.8,pp.2429-2437,Aug.2022.https:/doi.org/10.1109/

107、JSSC.2022.3142662 3 S.Pan et al.,“A 0.028mm2 32MHz RC Frequency Reference in 0.18 m CMOS with 900ppm Inaccuracy from 40C to 125C and 1600ppm Inaccuracy After Accelerated Aging,”ISSCC,pp.56-58,Feb.2024.https:/doi.org/10.1109/ISSCC49657.2024.10454366 4 K.-S.Park et al.,“A Temperature-and Aging-Compens

108、ated RC Oscillator With 1030-ppm Inaccuracy From-40 C to 85 C After Accelerated Aging for 500 h at 125 C,”IEEE JSSC,vol.58,no.12,pp.3459-3469,Dec.2023.https:/doi.org/10.1109/JSSC.2023.3320709 5 H.R.Kooshkaki et al.,“A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than-66d

109、Bc Fractional and Reference Spurs for NB-IoT,”CICC,pp.1-4,Apr.2020.https:/doi.org/10.1109/CICC48029.2020.9075944 6 A.Tharayil Narayanan et al.,“A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of-250 dB,”IEEE JSSC,vol.51,no.7,pp.1630-1640,July 2016.https:/doi.org/10.1

110、109/JSSC.2016.2539344 7 A.Jakobsson et al.,“A Low-Noise RC-Based Phase Interpolator in 16-nm CMOS,”IEEE TCAS-II,vol.66,no.1,pp.1-5,Jan.2019.https:/doi.org/10.1109/TCSII.2018.2823902 8 A.S.Delke et al.,“A Single-Trim Frequency Reference System With 0.7 ppm/C From 63 C to 165 C Consuming 210 W at 70 M

111、Hz,”IEEE JSSC,vol.58,no.9,pp.2585-2596,Sept.2023.https:/doi.org/10.1109/JSSC.2023.3261600 9 A.S.Delke et al.,“A Single-Trim Frequency Reference Achieving 120 ppm Accuracy From 50 C to 170 C,”IEEE JSSC,vol.56,no.11,pp.3434-3444,Nov.2021.https:/doi.org/10.1109/JSSC.2021.3090682 10 K.Jung et al.,“A Tem

112、perature Compensated RF LC Clock Generator With 50-ppm Frequency Accuracy From 40 C to 80 C,”IEEE TMTT,vol.67,no.11,pp.4441-4449,Nov.2019.https:/doi.org/10.1109/TMTT.2019.2936352 11 Y.Huang et al.,“A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and-74.2d

113、Bc Reference Spur,”ISSCC,pp.130-132,Feb.2024.https:/doi.org/10.1109/ISSCC49657.2024.10454291 12 X.Shen et al.,“A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving-37.6 0.9-dBc Integrated Phase Noise,261.9-fs RMS Jitter,and-240.6-dB FoM,”ESSCIRC,pp.257-260,S

114、ept.2023.https:/doi.org/10.1109/ESSCIRC59616.2023.10268691 13 C.Hwang et al.,“A 188fsrms-Jitter and 243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector,”ISSCC,pp.378-380,Feb.2022.https:/doi.org/10.1109

115、/ISSCC42614.2022.9731646 14 S.M.Dartizio et al.,“A 59.3fs Jitter and-62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector,”CICC,pp.1-2,Apr.2024.https:/doi.org/10.1109/CICC60959.2024.10529002 15 Y.Jo et al.,“A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single

116、LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier,”ISSCC,pp.1-3,Feb.2023.https:/doi.org/10.1109/ISSCC42615.2023.1006774880 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 4/ANALOG TECHNIQUES/4.3979-8-3315-4101-9/25/$31.00 2025 IEEE4

117、.3 A 0.36nW,820m2,32kHz Conduct ion-Angle-Adapt ive Cryst al Oscillat or in 28nm CMOS for Real-Time Clock Applicat ions Peng Wang*1,Manyu Wang*1,Guangnan Dai1,Yujia Cao1,2,Sining Pan2,Yihan Zhang1 1Hong Kong University of Science and Technology,Hong Kong,China 2Tsinghua University,Beijing,China *Equ

118、ally Credited Authors(ECAs)32.768kHz(32kHz)crystal oscillators(XOs)are widely used in real-time clocks(RTC)embedded in various electronic systems.Their performance is critical in battery-powered Internet-of-Things(IoT)sensor nodes when serving as wake-up timers.Extending the battery life requires an

119、 ultra-low-power(ULP)XO,as it must stay always-on.It also requires good frequency stability;otherwise,the system has to extend its communication guard times for synchronization,in which power-hungry transceivers need to stay active,leading to extra waste in power 1.These demands have motivated much

120、recent research to seek alternatives to the classic inverter-based Pierce oscillator,which is simple in design but typically consumes 10 to 100nW of power 2-5.Pulse-injection XOs(PIXOs)are popular due to their sub-nW power consumption.Their power reduction comes from using a tiny conduction angle in

121、 the form of short pulses for Class-C-like operations.However,positioning current injections to the optimum timing typically requires generating an accurate delay,making pulse generators area-consuming 6-10.Moreover,these methods cannot initiate the oscillation,as the zero-crossing instants,which ar

122、e the starting times of the delay,are only available once an oscillation is present.These PIXOs,hence,need to embed separate start-up circuits to build up the initial oscillation,necessitating extra control logic and facing robustness challenges under accidental but strong interferences.A compact an

123、d easy-to-use ULP XO remains in demand from the cost-sensitive IoT market.This work presents a conduction-angle-adaptive XO(CAAXO)that achieves 0.36nW power consumption at an area of 820m2 while preserving an intrinsic start-up capability.It uses an amplitude-modulated and digitally defined conducti

124、on angle to operate the Pierce inverter in a Class-C fashion.Compared to PIXOs,the proposed technique saves area and power by using a larger to avoid generating accurate delays.Figure 4.3.1 outlines the CAAXOs approach.After the Pierce oscillator initiates the oscillation,it will be power-gated at t

125、imes when current injection efficiency P/N is low,creating an adaptive centered near the peaks(90)and valleys(270)of the oscillation waveform where maximum P/N occurs.P/N arises from the linear and periodically time-varying nature of oscillators and can be found in a way similar to the impulse-sensi

126、tivity function 11.System-level simulation shows an 80%power efficiency for 120(conduction time tC10s)and 90%for 80(tC6.8s)when using a-modulated subthreshold inverter.This observation indicates that a substantial power saving happens without pushing too low,permitting simple designs.Figure 4.3.2 sh

127、ows the complete transistor-level schematic of the proposed CAAXO.At the core of the CAAXO are transistors MIP/N that form an inverter,power-gating switches MGP/N,and 4 negative feedback paths,PGP/N and PIP/N for the proposed-adaptive mechanism.Function-wise,the role of PGP is to sense the oscillati

128、on amplitudes at nodes VIN and VOUT,which are roughly equal at steady state and denoted as VA,to produce a duty-cycle-modulated digital signal VGP that reduces as VA grows.The inclusion of PIP provides amplitude-based gm suppression for further power reduction.PGN and PIN work in identical ways but

129、with opposite polarity.Aside from the CAAXOs core,this design also includes on-chip load capacitors in the form of two 7bit digitally trimmed capacitor arrays CPL/R,each supporting a maximum of 12.3pF,enough to accommodate crystals with a nominal CL up to 6pF(CL=CPL/CPR).Pseudo-resistor RP provides

130、a defined dc voltage for VIN.BUFOUT(power not included)brings VOUT off-chip as a digital CLK32K,the 32kHz clock output.Figure 4.3.3 explains the working principle of PGP and PIP in detail.PGP produces a decrease in by level-shifting VIN with an amplitude-dependent VDC,which stays negative when VA is

131、 0 but increases rapidly as VA grows.The resultant signal VSP is then digitized by an inverter chain with a threshold voltage around VDD/2 to produce VGP.Hence,before VA reaches a threshold VA,TH,stays at 360,degenerating the circuit back to a Pierce oscillator for start-up.When VA grows beyond VA,T

132、H,VSP will see an increasing fraction of the waveform being higher than the threshold voltage of the inverter,creating a reduced.The implementation of this mechanism relies on capacitor C1P and two MOS diodes,D1P and DRP.First,C1P and D1P form a charge pump(CP),with VIN and VOUT being the two inputs

133、.At steady state,C1P will store a 2VA-VD(VD being the forward voltage of D1P)dc voltage difference from VOUT to VSP,as VIN and VOUT are 180 out-of-phase from parallel oscillation.The ac component of VIN will couple directly to VSP.Hence,the CP ideally creates an ac-to-dc gain of 2 and an ac-to-ac ga

134、in of 1.Second,diode DRP is connected between VSP and VSS under reverse bias to create a negative dc voltage shift,VSP0.Because DRP is matched to D1P but 5 in width,the resultant VSP0 only relies on the shape of the diodes I-V characteristics.The MOS diode chosen in this work 12 creates a stable VSP

135、0 of 447mV across a-20C-to-85C temperature range in simulation,irrespective of its 200 variance in absolute current.Finally,INV1P is sized close to its minimum for a reduced input capacitance and a negligible gate leakage current.Note that PGP operates poorly with small s,as a small means placing th

136、e bottom of the sine wave at node VSP near the INV1Ps threshold.This compromises the circuits robustness by creating a long transition time in INV1P and making more sensitive to the noise at VSP.It also increases the likelihood of VA exceeding VA,MAX,beyond which PGP will lock to 0,eliminating the n

137、egative feedback effect.Mitigating this issue necessitates the addition of path PIP.Path PIP implements an amplitude control mechanism for two main benefits.First,it limits VA below VA,MAX to keep the negative feedback in PGP always effective,enhancing CAAXOs robustness.Second,a low VA at the steady

138、 state reduces the power dissipated by the crystals RM,leading to further power saving.PIPs circuit implementation uses an identical CP consisting of C2P and D2P to subtract 2VA from MIPs VGS,suppressing its gms fundamental component gm(1)3 at 32kHz as VA grows.MLP is added to compensate for the gat

139、e leakage from MIP,which helps boost MIPs gm during start-up at low temperatures.Simulation predicts that its addition boosts MIPs VGS by 103mV at-20C when no oscillation is present.Without it,a rise in VBP becomes unavoidable to balance an exponentially reduced ID2P and a roughly constant IGIP when

140、 the temperature drops.The proposed CAAXO circuit was fabricated in 28nm CMOS technology,with its core occupying only 820m2(5390um2 including the on-chip CPL/R)of silicon area.The die photo with an annotated layout is shown in Fig.4.3.7.Measurement results from 10 samples are collected for performan

141、ce evaluation.The nominal operating voltage of 0.38V is chosen as the minimum VDD that ensures proper operation from-20C to 85C.With no additional CL,the output frequency is 32781.30.8Hz when driving ECS-2X6-FLX crystals(CL,NOM=6pF)with 0.360.05nW(worst case:0.44nW)power consumption.Figure 4.3.4 sho

142、ws the CAAXOs performance with temperature varying from-20C to 85C and VDD sweeping from 0.3V to 0.7V(25C).Measurements indicate an average of 144ppm frequency deviation across temperature,mainly due to the temperature coefficient of the crystal,and an average line sensitivity of 16ppm/V.The measure

143、d power and frequency under different CLs are plotted in Fig.4.3.5.A larger CL attenuates the output frequencys sensitivity to variations in parasitic capacitances and can help reduce the cost of calibration 13.Long-term frequency-stability evaluation demonstrates an Allan deviation floor lower than

144、 7ppb.Figure 4.3.6(top)shows the captured time-domain waveforms during start-up and steady-state operation.A 150ms start-up time is observed under a 0.38V supply.Waveforms at node VGP and VGN show a 74 P and a 67 N.These are acquired from an on-chip replica that is identical in design but larger in

145、area to accommodate signal probes inside the core.Figure 4.3.6(bottom)summarizes the key performance metrics of the fabricated CAAXO and compares them with previously published ULP XOs.Benefiting from a robust efficiency boost across a wide range of,the CAAXO achieves the lowest power consumption am

146、ong the state-of-the-art entries in the table and is simple in its design.Specifically,its core consumes 5 lower power at a 3.4 smaller silicon area than 10,which also uses 28nm technology.In addition,its intrinsic start-up capability provided by amplitude-based regulation is unique among ULP XOs op

147、erating in the sub-nW power regime.These features make CAAXO a competitive choice for future RTC applications in IoT sensor nodes:its record-low power extends the systems battery life,its tiny area leads to low manufacturing cost,and its single-supply nature with intrinsic start-up capability makes

148、it easy to use,holding the promise to serve as a pin-to-pin replacement of the classic Pierce oscillator.Figure 4.3.1:Overview of t he exist ing XO t opologies and t he proposed conduct ion-angle-adapt ive cryst al oscillat or(CAAXO).Figure 4.3.2:The complet e schemat ic of t he proposed CAAXO.32.76

149、8kHz Crystal(ECS-2X6-FLX,off-chip,CL,NOM=6pF)Pseudo-ResistorMOS DiodeC1P(400fF)CPSETL6:0RPVINVDDVDDVSSVSSVDDVOUTMGPC2P(500fF)C1N(400fF)C2N(500fF)D1PINV1PINV2PD2PMIPMGNMINMLPMLND1NDRN(5x D1N)DRP(5x D1P)D2NINV1NINV2NCPSETR6:0PGPPIPPINPGNCPLCPRCLK32KBUFOUTVSPVSNVBPVBNVGPVGNNPMOS DiodePseudo-ResistorCMR

150、MLMC0CPCPPierce Oscillator?Small area?Power:10100nW?Start-up capability?High stabilityPulse Injection XO(PIXO)CPCPCTRLPulse Gen.?Power 1 nW?Needs start-upassistanceLarge area?High stability?VDDVINVOUTVSSCPCPPGNGVINNGPGVOUTP()N()0901802700901802700901802700901802700?Small area?Start-up capability?Hig

151、h stabilityPower 1nW?Proposed Conduction-Angle-Adaptive Crystal Oscillator(CAAXO)100908070605040Efficiency (%)Simulated vs.for a Power Gated InverterConduction Angle ()180160140120100806040200 90%80%Figure 4.3.3:Det ailed operat ing principle for t he negat ive-feedback pat hs PGP and PIP.Figure 4.3

152、.4:Measurement result s of t he CAAXO from 10 samples across t emperat ure(-20C t o 85C)and supply volt age(0.3V t o 0.7V).AAGP/2DDV/2DDACVDCVSPV/2DDVOUTVIN/2DDDA THA,THV=360?ACVDCVHA with V?,?ACVDC0.5V)for energy efficiency since switching losses are quadratically dependent on supply voltage.Such s

153、upply voltages are suitable for self-sustaining systems(e.g.energy harvesting)but require additional power regulation circuitry for battery-or other power-supply-driven applications.Their impact on overall energy has not been considered in recent publications 1-5.This work presents a new sustaining

154、amplifier and regulation concept to avoid inverter cross-currents,which directly operates from 0.9-to-2V supply with an overall power consumption as low as 0.36nW.Figure 4.4.1 shows an overview of the oscillator circuit,which includes a modified Pierce driver,a detector-based amplitude regulation,a

155、current source,and a regulated output driver.To reduce both the inverters cross-current and the oscillators amplitude VAmp,a detector-based regulator concept and a non-linear feedback diode to force the inverter into optimal low-power common-mode operation points(CM-OP)are introduced.As shown in Fig

156、.4.4.2,the diode DF is placed into the Pierce stages feedback path to add a voltage shift VShift between the resonators nodes VOSC+and VOSC-.A diode current IDF flows when the diode is forward-biased,increasing the voltage difference between the two resonator nodes during phase t1.A feedback resisto

157、r RF stabilizes the oscillation by compensating the diodes current with an additional resistive current IRF,when the diode is reversed biased.It balances and limits the voltage shift VShift between the resonator nodes(mode IDFIRF)in the second phase t2.In phase t1,the diode raises the drain potentia

158、l of the n-MOS MnPierce such that it can reach saturation and allows current flow from VDD.During phase t2,the drain potential is small compared to its gate-source voltage,pulling VOSC+towards ground.As the diode operates in reverse direction,the resistor RF pushes input VOSC-and output VOSC+back to

159、 similar voltage levels.The p-MOS MpPierce is turned off in this phase,and no cross-current can flow in the Pierce circuit.When VOSC-and VOSC+reach a similar voltage,the diodes impedance gets small again,repeating the start of phase t1.The operation mode can be chosen by adjusting the external resis

160、tor RF:starved Pierce(IDFIRF),where the diode is dominant and induces a voltage shift VShift.A resistance of 120M is used for the XO(150M for the MEMS)to enable the oscillator in the starved and shifted Pierce mode.If RFIRF to IDF100ppm/C).Herein we propose an open-loop reference-replication-based R

161、C oscillator that can concurrently calibrate the temperature-sensitive path delay and comparator offset.Also,dynamic loop control allows substantial power savings.The prototyped 10MHz RC oscillator in 65nm CMOS consumes 4.06W,corresponding to a power efficiency of 0.4W/MHz.The achieved TC is 7.52 pp

162、m/C from-40 to 125 C,and the die area is 0.0085mm2.Figure 4.5.1(top-left)shows a typical open-loop RC oscillator.The charging voltage(VC)is periodically compared with the reference voltage(VREF)via a comparator to create a stable output frequency that depends on a fraction of the RC time constant.Wh

163、ile the comparator offset(VOS)as well as the path delay(Td)are important factors affecting the frequency stability of RC oscillators in the MHz range.Typically,the comparators input pair has to be precisely matched to minimize the offset,whereas the comparator has to consume a large power to ensure

164、its temperature-dependent delay is insignificant compared to the RC time constant.Also,the reduced supply voltage,along with the advanced process nodes,increases the temperature-sensitive Td and VOS significantly,causing the period of the conventional RC oscillator(TC)to deviate far from the ideal p

165、eriod(T0),leading to poor temperature and voltage stability.Otherwise,a higher supply voltage and more power-hungry blocks are usually required,degrading the energy efficiency.In 14,a chopping scheme was proposed to compensate for the impact of offsets.Building on this structure,21 and 22 introduced

166、 path-delay compensation technology.However,the chopping scheme combines two charging cycles into one,which results in halved output frequencies while maintaining consistent power consumption.In 23,a charge-acceleration technique was proposed to address the offset,but the delay issue was ignored.Her

167、ein we introduce an offset-and path-delay cancellation scheme based on reference replication and realignment(Fig.4.5.1 bottom).VC and VREF are selectively connected to the positive port of the comparator via a multiplexer,and a replica voltage(VR)is generated as a new reference voltage and connected

168、 to the negative port.By realigning VR in each cycle and comparing it with VREF,VOS and Td can be converted into voltage and preserved in VR.Subsequently,VR is fixed and compared with VC.In this case,the temperature-sensitive VOS and Td can be canceled,and thus the oscillation period of the proposed

169、 RC oscillator(TP)equals T0,which is only related to the TC of R and C.Figure 4.5.2 shows the workflow of the proposed RC oscillator in one cycle,mainly composed of 3 steps.In the 1st step,VREF is connected to the positive port of the comparator,and VC starts charging from GND.The reset logic closes

170、 switch S2 and enables VR to charge and replicate VREF.Due to the existence of the comparator offset,VR will be charged to VREF+VOS,and the offset information is preserved in VR.After a delay of Td,VR reaches its maximum value VR,max.In the 2nd step,the reset logic closes switch S3 and enables VR to

171、 discharge to extract the path delay.When VR passes through VREF+VOS again,the comparator toggles and VR reaches its minimum value VR,min after a delay of Td.Thus,the discharge of VR during Td converts the delay information into voltage and is preserved in VR.In the 3rd step,the value of VR is fixed

172、 to VR,min,and the multiplexer selects VC to connect to the positive port of the comparator.Then,VC continues to charge and is compared to VR.VC will be accurately charged to VREF,since VR now has already preserved the offset and delay information.Finally,the TP expression can be obtained.After cons

173、idering the nonlinearity of the capacitor charging,the relationship between the period with VOS and Td can be calculated.Compared with the conventional structure,the proposed one has significantly improved robustness,as shown in Fig.4.5.1(top right).The circuit implementation and timing diagram are

174、detailed in Fig.4.5.3.It is mainly composed of a VREF generator,an RC branch,a pulse generator,REF replication,a 1bit counter,and the comparator.The dynamic switches in the VREF generator are triggered by the output signal.When=1,VREF is generated by the voltage division of the resistors R1 and R2(R

175、1=R2=65k,and VREF=VDD/2=400mV).When=0,the dynamic switch is turned off and VREF remains at a fixed value to achieve power savings(measured 87.7%power saving,4.3W).Since the pulse width of depends on Td(4Td12ns in this design),the duty cycle of the output is 12%,and it can be simply adjusted by the e

176、xternal circuit.To minimize the mismatch,the charging speed of VC is set equal to the discharge speed of VR by properly setting it as VR tracks VREF(C2=C3,R3=R4=R5).The resistors R3,R4 and R5 are implemented as a series of two poly resistors with different temperature coefficients(1942ppm/C N+poly r

177、esistor with silicide and 321ppm/C P+poly resistor without silicide)to achieve first-order temperature compensation.The discharge switch is controlled by a 0.4ns pulse generated by the pulse generator.Since the comparator offset and path delay can be compensated by the reference replication scheme,t

178、he requirements of the comparator can be reduced.By using a 300k resistor R6 as the tail current source,the area and power consumption overhead of the bandgap are eliminated,and 1.26W power consumption is achieved.A Schmitt trigger is subsequently connected to the comparator to prevent glitches and

179、limit cycles.A 10MHz RC oscillator prototyped in 65nm CMOS occupies 0.0085mm2,as shown in Fig.4.5.7.It consumes 4.06W at 0.8V and 25C.Figure 4.5.4(top)shows the measured frequency as a function of temperature for 6 samples.Over 40 to 125C,the frequency error with the linear mapping is 0.12%,correspo

180、nding to an average TC of 9.83ppm/C that aligns with the simulation and is limited by the first-order compensation of the resistors.We can further enhance it by using advanced processes or high-order compensation of resistors.Figure 4.5.4(bottom)shows that over the 0.6-to-1V supply range,the frequen

181、cy error is 0.35%,corresponding to a supply sensitivity of 1.4%/V.The power supply affects the path delay,while the proposed structure has a first-order compensation in delay,causing the frequency to vary parabolically with the voltage.The measured Allan Deviation floor is 20ppm after 0.1s(Fig.4.5.5

182、).The total power consumption and area breakdown are also plotted in Fig.4.5.5.Figure 4.5.6 summarizes the performance of our RC oscillator and benchmarks it with the state-of-the-art.This work outperforms them in terms of temperature coefficient(to 9.83 ppm/C)and energy efficiency(0.4W/MHz),while s

183、howing the best timers stability FoM of 174dB and power-jitter FoM of 285dB among the entries in the table.Ac knowl e dge me nt:This work was partially supported by the National Key Research and Development Program of China under Grant 2023YFB4403900.(Corresponding author:Shiheng Yang).Figure 4.5.1:

184、Comparison bet ween a convent ional RC oscillat or(t op left)and t he proposed RC oscillat or(bot t om).Figure 4.5.2:Workflow of t he reference-replicat ion scheme.Figure 4.5.3:Overall implement at ion of t he proposed RC oscillat or.Figure 4.5.4:Measured t emperat ure(t op)and supply st abilit y(bo

185、t t om)from 6 samples aft er 1-point t rim.Figure 4.5.5:Measured Allan Deviat ion and jit t er(t op);power and area breakdown(bot t om).Figure 4.5.6:Performance summary and comparison wit h recent st at e-of-t he-art RC frequency references.ISSCC 2025/February 17,2025/5:05 PM85 DIGEST OF TECHNICAL P

186、APERS 4 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 4.5.7:Die micrograph.Re f e re nc e s:1 Y.Ji et al.,“A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/C and 3.3pJ/Hz

187、 in-40C to 125C Temperature Range,”ISSCC,pp.1-3,Feb.2022.http:/doi.org/10.1109/ISSCC42614.2022.9731730 2 J.Lee et al.,“An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-m CMOS,”IEEE JSSC,vol.55,no.9,pp.2489-2497,Sep.2020.http:/doi.org/10.1109/JSSC.2020.2987681 3 K.-M.Lei et

188、 al.,“A 0.35-V 5,200-m2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator,”IEEE JSSC,vol.56,no.9,pp.2701-2710,Sep.2021.http:/doi.org/10.1109/JSSC.2021.3067051 4 H.Jiang et al.,“A 0.14mm2 16M

189、Hz CMOS RC Frequency Reference with a 1-Point Trimmed Inaccuracy of 400ppm from-45C to 85C,”ISSCC,pp.436-438,Feb.2021.http:/doi.org/10.1109/ISSCC42613.2021.9365795 5 X.An et al.,“A 0.01 mm2 10MHz RC Frequency Reference with a 1-Point On-Chip-Trimmed Inaccuracy of 0.28%from 45oC to 125oC in 0.18 m CM

190、OS,”ISSCC,pp.60-62,Feb.2023.http:/doi.org/10.1109/ISSCC42615.2023.10067530 6 W.Choi et al.,“A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and 200 ppm Inaccuracy from-40C to 85C,”ISSCC,pp.434-436,Feb.2021.http:/doi.org/10.1109/ISSCC42613.2021.9366021 7.Grleyk,S.Pan and K.A.A.Makinwa,“A 16MH

191、z CMOS RC Frequency Reference with 400ppm Inaccuracy from 45C to 85C After Digital Linear Temperature Compensation,”ISSCC,pp.64-66,Feb.2020.http:/doi.org/10.1109/ISSCC19947.2020.9063029 8 A.Khashaba et al.,“A 34W 32MHz RC Oscillator with 530ppm Inaccuracy from 40C to 85C and 80ppm/V Supply Sensitivi

192、ty Enabled by Pulse-Density Modulated Resistors,”ISSCC,pp.66-68,Feb.2020.http:/doi.org/10.1109/ISSCC19947.2020.9062942 9 A.Khashaba et al.,“A 32-MHz,34-W Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors,”IEEE JSSC,vol.57,no.5,pp.1470-1479,May 2022.http:/doi.org/10.1109/J

193、SSC.2021.3121014 10 W.Choi et al.,“A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With 200 ppm Inaccuracy From 40 C to 85 C,”IEEE JSSC,vol.57,no.8,pp.2418-2428,Aug.2022.http:/doi.org/10.1109/JSSC.2021.3135939 11 J.Jung et al.,“A 1.08-nW/kHz 13.2-ppm/C Self-Biased Timer Using Temperat

194、ure-Insensitive Resistive Current,”IEEE JSSC,vol.53,no.8,pp.2311-2318,Aug.2018.http:/doi.org/10.1109/JSSC.2018.2824307 12 M.Ding et al.,“A 33-ppm/C 240-nW 40-nm CMOS Wakeup Timer Based on a Bang-Bang Digital-Intensive Frequency-Locked-Loop for IoT Applications,”IEEE TCAS I,vol.67,no.7,pp.2263-2273,J

195、uly 2020.http:/doi.org/10.1109/TCSI.2020.2979319 13.Grleyk et al.,”A CMOS Dual-RC frequency reference with 250ppm inaccuracy from 45C to 85C,”ISSCC,pp.54-56,Feb.2018.http:/doi.org/10.1109/ISSCC.2018.8310180 14 A.Paidimarri et al.,“An RC Oscillator With Comparator Offset Cancellation,”IEEE JSSC,vol.5

196、1,no.8,pp.1866-1877,Aug.2016.http:/doi.org/10.1109/JSSC.2016.2559508 15 S.-Y.Lu et al.,“A Low-Power,Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-m CMOS,”IEEE JSSC,vol.54,no.2,pp.392-402,Feb.2019.http:/doi.org/10.1109/JSSC.2018.2877927 16 A

197、.Savanth et al.,“A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator,”IEEE JSSC,vol.54,no.11,pp.3097-3106,Nov.2019.http:/doi.org/10.1109/JSSC.2019.2930360 17 S.Dai et al.,“A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sen

198、sors,”CICC,pp.1-4,Sep.2015.http:/doi.org/10.1109/CICC.2015.7338396 18 H.Jiang et al.,“A 0.4-V 0.93-nW/kHz Relaxation Oscillator Exploiting Comparator Temperature-Dependent Delay to Achieve 94-ppm/C Stability,”IEEE JSSC,vol.53,no.10,pp.3004-3011,Oct.2018.http:/doi.org/10.1109/JSSC.2018.2859834 19 D.G

199、riffith et al.,“A 190nW 33kHz RC oscillator with 0.21%temperature stability and 4ppm long-term stability,”ISSCC,pp.300-301,Feb.2014.http:/doi.org/10.1109/ISSCC.2014.6757443 20 T.Jang et al.,“A 4.7nW 13.8ppm/C self-biased wakeup timer using a switched-resistor scheme,”ISSCC,pp.102-103,Feb.2016.http:/

200、doi.org/10.1109/ISSCC.2016.7417927 21 Y.Wang et al.,“A 255nW 138kHz RC oscillator for ultra-low power applications,”IWS,pp.1-4,Mar.2016.http:/doi.org/10.1109/IEEE-IWS.2016.7585431 22 Y.Liu et al.,“A Low-Power RC Oscillator with Offset and Path Delay Cancellation,”ICTA,pp.12-13,Nov.2021.http:/doi.org

201、/10.1109/ICTA53157.2021.9662022 23 Y.Liu et al.,“A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS,”IEEE TCAS-I,vol.71,no.2,pp.515-525,Feb.2024.http:/doi.org/10.1109/TCSI.2023.332635186 2025 IEEE International

202、Solid-State Circuits ConferenceISSCC 2025/SESSION 4/ANALOG TECHNIQUES/4.6979-8-3315-4101-9/25/$31.00 2025 IEEE4.6 A 0.8V,31ppm/C,-40dB DC-t o-GHz Power-Supply-Reject ion St andard-Vt h Core-MOS-Only Volt age Reference wit h a 294m2 Area Bei-Shing Lien*,Szu-Lin Liu*,Wei-Lin Lai,Yi-Chen Lu,Yung-Chow P

203、eng,Kenny Cheng-Hsiang Hsieh TSMC,Hsinchu,Taiwan *Equally Credited Authors(ECAs)PVT-independent voltage references(VRs)are critical analog blocks for data converters and sensors in system-on-chips(SoCs).As advanced technology nodes continue to scale down,the demand for core-device-only reference cir

204、cuits that can operate at core-domain supply voltages(VDDs)is becoming increasingly important for area-shrinkage and reliability considerations.Working at sub-1V VDD is a significant design barrier for BJT-based VRs due to the headroom limitation of the emitter-base junction voltage(VEB)of BJTs and

205、the drain-source saturation voltage of the current sources.Reference 1 presents a 0.7V BJT-based VR using deep-n-well(DNW)base-structure PNP devices with lower VEB requirements,but DNWs usually are not compatible with a standard logic CMOS process.Charge-pump 2 and switched-capacitor 3 techniques ca

206、n reduce the supply of BJT-based reference circuits to 0.5V to 0.85V.However,switching-mode VRs typically require large filters to remove output ripples,which results in an extra area penalty.CMOS-only voltage references(CMOS-VRs)are promising architectures for low-voltage applications,since a MOS t

207、ransistor working in the sub-threshold region can provide I-V characteristics with similar temperature-dependence to that of a BJT,while the gate-source voltage(VGS)being only 1/5 the VEB of a conventional DNW-less bipolar device.Figure 4.6.1(top-left)shows a widely used stacked CMOS-VR design conce

208、pt for a technology with multiple threshold-voltages(Vths),as proposed in 4,where the top device(M2)is a low-Vth type transistor that provides a sub-threshold current,and the bottom device(M1)is a high-Vth type transistor that is biased at this low current and generates the reference voltage(VREF).I

209、n advanced FinFET nodes with negligible body effect,the VREF of such stacked two-Vth CMOS-VRs is:where VT is the thermal voltage,Vth1,2,k1,2,W1,2,and L1,2 are the threshold-voltages,the transistor mobility-gate-capacitance products,the equivalent fin-channel widths,and the gate-lengths of M1 and M2,

210、respectively.From this equation,we can observe several design challenges of the two-Vth CMOS-VRs:(1)The VREF accuracy and its temperature-coefficient(TC)strongly depend on whether the process variations related to the mobilities,the gate-capacitances,and the threshold levels of the two Vth-type tran

211、sistors can always track with each other well,which is difficult in long-term process control.(2)The VREF levels in 4 and the two-Vth CMOS-based variants 5-7 are 0.9)is significantly higher than that of the different-Vth transistors(0.4),which indicates that single-Vth architecture has better stabil

212、ity against random process changes.Compared with previous sub-1V two-Vth CMOS-VRs 4-7,this CMOS-VR increases the VREF level to 0.58V due to VGS,S3 contribution and therefore solves the low input-common-mode design issue.Based on the single-Vth and the unit-cell design concepts used in this work,the

213、VREF can be described as:where IdS1,S2,WS1,S2 and LS1,S2 are the bias-currents,the equivalent fin-channel widths,and the equivalent gate-lengths of MS1 and MS2,respectively.In our design,we choose LS1=5LS2 and IdS1/WS1=IdS2/WS2,hence the temperature-slope of VPTAT can be determined by the ratio of s

214、eries FinFET unit-cells of MS1 and MS2.By changing the current density of MS3(IdS3/WS3),we can adjust the temperature-slope of the VCTAT component(VGS,S3)and optimize the VREF TC of the CMOS-VR.This TC trimming is achieved by four binary switch pairs to increase or reduce the number of parallel FinF

215、ET unit-cells in MS3(Fig.4.6.2,right).In this work,the bias currents of sub-threshold PTAT and CTAT blocks are generated from an independent const-gm circuit,where the const-gm circuit and the current-mirror devices(MP1 and MP2)operate in the saturation region to improve local mismatch and noise imm

216、unity.The trimmable resistor(Rtrim)is further designed in the const-gm circuit to fix bias-current mean-shift in case of severe global process variation.Line regulation(LR)and power-supply rejection(PSR)are essential but challenging specifications in core-device-only and sub-1V reference circuits in

217、 advanced FinFET nodes,because the transistors intrinsic output impedance substantially decreases as the maximum available gate-length decreases.Additionally,the transistors headroom is also reduced with lower VDD.On the other hand,the supply-noise frequency in modern SoCs can vary significantly fro

218、m hundreds of kHz to hundreds of MHz,whereas previous studies have only measured PSR at frequencies up to several tens of MHz 4,10.In this work,we design a self-regulated 5T-LDO to solve these issues.The working principle is illustrated in Fig.4.6.3(middle).MSF and its active load MBN2 form a level

219、shifter that converts the stable VREF to VREF_SF.MSENSE and its active load MBN1 then act as a common-gate error amplifier,sensing the delta-voltage between VREF_SF and the actual supply level of the CMOS-VRs main circuit(VDD_REG).The output of this error amplifier(VGATE)thus controls the power devi

220、ce(MPOWER)to regulate VDD_REG from a noisy external VDD.VGATE is the only high-impedance node in the amplification loop,making this single-pole amplifier stable even without compensation.The loop gain and the phase margin are shown in Fig.4.6.3(right).With a 2.5uA bias-current of each branch,this 5T

221、-LDO provides a 30dB DC gain,a 270MHz bandwidth,and a 70 phase margin.In a traditional two-stage LDO with Miller compensation(Fig.4.6.3,left),the high-frequency supply noise can couple to the input net of MPOWER through the path of the source-drain parasitic capacitor of MPOWER(CC)and the Miller com

222、pensation capacitor(CM),and then re-enters the MPOWER amplification path and degrades high-frequency PSR.Combining the noise rejection capability provided by the saturation current mirrors and the self-regulated 5T-LDO,our CMOS-VR can achieve good wideband-PSR and save the area of compensation capac

223、itors.Since the CMOS-VRs supply is regulated from the 5T-LDO,and the input reference of the 5T-LDO is generated from the CMOS-VR,to prevent the chicken-egg problem,a pulse-reset signal is used to pull down VBP and VGATE to ensure the circuits start-up.The standard-Vth core-device-only CMOS-VR is fab

224、ricated in a 3nm FinFET CMOS process.The overall current consumption of this CMOS-VR is 15A from a typical 0.8V supply.Figure 4.6.4(top)shows the measured VREF from-40C to 125C with the average value of 582mV.The untrimmed inaccuracy from 48 samples is within 2.1%(which projects to 3.4%3-variation)w

225、ith the median TC of 31ppm/C,(Fig.4.6.4,bottom).After TC trimming,the inaccuracy can be further reduced to 1%with similar TC.The DC LR is 0.04%/V from 0.75V to 0.85V(Fig.4.6.5,top).The-40dB high-frequency PSR validations in previous works are only to 10MHz 2,4-7 and at 80MHz 10.This work achieves PS

226、R-50dB from 10KHz to 100MHz,and it is still below-40dB from 100MHz to 1GHz(Fig.4.6.5,bottom).Figure 4.6.6 compares the performance of this work with the state-of-the-art sub-1V voltage references.The proposed single-Vth and unit-cell-based CMOS-VR provide a ripple-less reference with-40dB power-nois

227、e rejection from DC to GHz,offering competitive temperature coefficients and accuracy within the standard industrial temperature range.The size of this CMOS-VR is 294m2(Fig.4.6.7).Figure 4.6.1:The t radit ional t wo-Vt h reference cell(t op-left),t he proposed single-Vt h reference cell(bot t om-lef

228、t),and t heir VGS correlat ion simulat ions(right).Figure 4.6.2:The schemat ic of t he proposed single-Vt h CMOS volt age reference(t op),wit h t he unit-cell design in serial and parallel connect ions(bot t om).Figure 4.6.3:The t radit ional t wo-st age LDO using Miller compensat ion(left),and t he

229、 proposed five-t ransist or LDO(5T-LDO,middle).The gain response and phase margin of t he 5T-LDO(right).Figure 4.6.4:The measured reference out put from-40C t o 125C(t op),t he measured reference-out put-inaccuracy cumulat ive dist ribut ion plot (bot t om-left),and t he measured t emperat ure-coeff

230、icient cumulat ive dist ribut ion plot (bot t om-right).Figure 4.6.5:The measured reference out put from 0.75V t o 0.85V(t op),and t he measured reference-out put power-supply reject ion from 10KHz t o 1GHz(bot t om).Figure 4.6.6:The performance comparison t able of sub-1V volt age references.ISSCC

231、2025/February 17,2025/5:20 PM87 DIGEST OF TECHNICAL PAPERS 4 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 PAPER CONTINUATIONS AND REFERENCES979-8-3315-4101-9/25/$31.00 2025 IEEEFigure 4.6.7:The die micrograph.Re f e re nc e s:1 Y.W.Chen et al.,A 0.7V,2.35%3-Accuracy Bandgap Refe

232、rence in 12nm CMOS,ISSCC,pp.306-307,Feb.2019.https:/doi.org/10.1109/ISSCC.2019.8662339 2 A.Shrivastava et al.,A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems,ISSCC,pp.94-95,Feb.2015.https:/doi.org/10.1109/ISSCC.2015.7062942 3 A.Feldman et al.,A 0.0106 mm2 8n

233、W Resistor-Less BJT Bandgap Reference in 65nm,ESSCIRC pp.85-88,Sept.2023.https:/doi.org/10.1109/ESSCIRC59616.2023.10268740 4 M.Seok et al.,A Portable 2-Transistor Picowatt Temperature Compensated Voltage Reference Operating at 0.5V,IEEE JSSC,vol.47,no.10,pp.2534-2545,Oct.2012.https:/doi.org/10.1109/

234、JSSC.2012.2206683 5 C.Z.Shao et al.,A 1.8-nW,73.5-dB PSRR,0.2-ms Startup Time,CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes,IEEE JSSC,vol.56,no.6,pp.1795-1804,Jun.2021.https:/doi.org/10.1109/JSSC.2020.3028506 6 L.Magnelli et al.,A 2.6nW,0.45V Temperature-Compensat

235、ed Subthreshold CMOS Voltage Reference,IEEE JSSC,vol.46,no.2,pp.465-274,Feb.2011.https:/doi.org/10.1109/JSSC.2010.2092997 7 J.Wang et al.,A Picowatt CMOS Voltage Reference Operating at 0.5-V Power Supply With Process and Temperature Compensation for Low-Power IoT Systems,IEEE TCAS-II,vol.70,no.4,pp.

236、1336-1340,Apr.2023.https:/doi.org/10.1109/TCSII.2022.3231216 8 J.M.Lee et al.,A 29nW Bandgap Reference Circuit,ISSCC,pp.100-101,Feb.2015.https:/doi.org/10.1109/ISSCC.2015.7062945 9 Y.Ji et al.,A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect,ISSCC,pp.308-309,Feb.2019.https:/doi.org/10.1109/ISSCC.2019.8662538 10 N.Alhassan et al.,An All-MOSFET Voltage Reference With 50-dB PSR at 80 MHz for Low-Power SoC Design,IEEE TCAS-II,vol.64,no.8,pp.892-896,Aug.2017.https:/doi.org/10.1109/TCSII.2016.2614527