T6 - Recent Advances in Circuit-techniques for Resilience to Side-Channel Attacks.pdf

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1、 2024 IEEE International Solid-State Circuits ConferenceRecent Advances in Circuit-techniques for Resilience to Side-Channel AttacksSpeaker:Shreyas SenElmore Associate Professor,ECE,Purdue Universityshreyaspurdue.eduCoordinator:Sanu MathewAcknowledgements:Archisman Ghosh,Debayan Das,Ingrid Verbauwhe

2、de,Santosh Ghosh and many more Feb 18,2024S.Sen1 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceOutlineWhy do Side-Channels Matter?Side-Channel FundamentalsRole of Circuits in SCA CountermeasuresSwitch CapacitorBuckSerie

3、s LDOShunt LDOArchitecturalClocking Slew+EM CountermeasuresAttack DetectorsSummary and SCA MetricsS.Sen2 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceRecent real-world Side-Channel AttacksS.Sen3 of 72ISSCC 24 Tutorial

4、6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceRecent physical Side-Channel AttacksPlatypus:Software-based power SCA on Intel CPUsLipp et al.,PLATYPUS:Software-Based Power Side-Channel Attacks on x86,IEEE S&P 2021,https:/ Hue Smart Bulb Hack:D

5、DoS attack Ronen et al.,IoT Goes Nuclear:Creating a ZigBee Chain Reaction,IEEE S&P 2017,https:/ieeexplore.ieee.org/document/7958578S.Sen4 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceRecent physical Side-Channel Attack

6、sGoogle Titan Security KeyLomne et al.,A Side Journey to Titan,IACR eprint 2021,https:/ieeexplore.ieee.org/document/7958578EM SCA on an iPhone 5Lisovets et al.,Lets Take it Offline:Boosting Brute-Force Attacks on iPhones User Authentication through SCA,IACR eprint 2021,https:/eprint.iacr.org/2021/46

7、0.pdfS.Sen5 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceAES-256 is not enough!AES-256 key recovered in just 5 minutes from a 1-meter distanceComplexity of breaking AES-256 reduced from 2256to 213From AES-128 to AES-25

8、6,SCA resistance increases linearly(2x)S.Sen6 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceReference:https:/www.fox- 2024 IEEE International Solid-State Circuits ConferenceOutlineWhy do Side-Channels Matter?Side-Channel FundamentalsAttack,Leakage,Countermeasure Fundamentals

9、Role of Circuits in SCA CountermeasuresSwitch CapacitorBuckSeries LDOShunt LDOArchitecturalClocking Slew+EM CountermeasuresAttack DetectorsSummary and SCA MetricsS.Sen7 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceSecu

10、re Computation:Side-channel AnalysisComputationally Secure Cryptographic AlgorithmElectromagnetic RadiationPower ConsumptionTimingCache hits/missesS.Sen8 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceClassic Side-channe

11、l Analysis Set-upCiphertext(public domain)Statistical EM/Power Model(Hamming Distance)Oscilloscope/ADC Trace CaptureCPA/CEMA Collect EM/power Traces(T)Build Hamming Weight/Distance Matrix(H)Correlate the measured&expected traces:Correlation co-efficient,:Standard Deviation,:Covariance=,EM/PowerSide-

12、ChannelsS.Sen9 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceSCNIFFER:Automated EM SCA Attack DemoIEEE ACCESS 2020 S.Sen10 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International

13、Solid-State Circuits ConferenceRecent ML SCA Attacks increase Threat Leakage GuessActual TraceCorrect KeyNon-Profiled AttacksAttack time10K Traces to attack Training PhaseTrace Input DNNCompareUpdate weightsPredicted LabelCorrect Label10K Traces to Train Trace Input TrainedDNNPredicted Label1-10 Tra

14、ces to attackTimeAttack PhaseProfiled Attacks:DL SCADAC 2019,TVLSI 2019S.Sen11 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceMaxwell and Accelerating ElectronsS.Sen12 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits

15、 for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceGenesis of the Power/EM LeakageState Switching Changing Currents Acceleration of charges()=22 0,2=22 02=22 0E,H fields propagate together and EM fields exist.Transistor switching creates changing currents leading to EM radiat

16、ion.Crypto engines like AES/SHA/ECC consist of multiple digital gatesBut what does the generated EM fields depend on?Metals carrying the current!VDDVINVOUTLoad CapReqVDDCharging0 1 State transitionDischarging1 0 State transitionReqS.Sen13 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA

17、Resilience 2024 IEEE International Solid-State Circuits ConferenceMetals in CMOS&EM LeakageHigher Metals are disproportionately largerLeads to significant EM leakageS.Sen14 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceReference:A 32nm Logic Technology Featuring 2nd-Generati

18、on High-k+Metal-Gate Transistors,Enhanced Channel Strain and 0.171m2 SRAM Cell Size in a 291Mb Array,Intel CorporationSwitching ActivityTransformation through Metal-Interconnect StackEM FieldsEM leakage from higher metal layer has higher probability of detection.2024 IEEE International Solid-State C

19、ircuits ConferenceCountermeasure FundamentalsReduce SignalRandomizeTransformAttenuateIncrease NoisePhysical ArchitecturalAlgorithmicS.Sen15 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceOutlineWhy do Side-Channels Matte

20、r?Side-Channel FundamentalsRole of Circuits in SCA CountermeasuresSwitch CapacitorBuckSeries LDOShunt LDOArchitecturalClocking Slew+EM CountermeasuresAttack DetectorsSummary and SCA MetricsS.Sen16 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-S

21、tate Circuits ConferenceSOTA:Countermeasures:Abstraction LevelsHypothesis on Circuit-level Physical Countermeasures:Generic Higher ProtectionLower OverheadsS.Sen17 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceDevicesCircuit(Generic)Logical(Design Specific)Architectural(Desi

22、gn Specific)WDDL,SABL,Gate-level maskingShuffling,Software maskingSw.Cap,IVR,Ser.LDOProtected Crypto Core 2024 IEEE International Solid-State Circuits ConferenceSOTA:Circuit-level CountermeasuresRecent Progress in SSCSStarted in 2009,2017-2022 has seen significant progressMTD increased from 1B Focus

23、 is to review this recent SSCS progress on circuit-level countermeasures for SCAS.Sen18 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferencePrevious Work:Logic-Level TechniquesSense Amplifier Based Logic(SABL)Introduced in 20

24、02(ESSCIRC)Dynamic and Differential Logic(DDL)One switching event per cycle Independent of input valueDesign and characterization of complete new standard cell libraryWave Dynamic Differential Logic(WDDL)Introduced in 2004(DATE)Readily implantable on any ASIC or FPGARelies on symmetric Capacitors,mi

25、smatch hurts S.Sen19 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferencePrev.Work:Architectural Time DistortionRandom Insertion of Dummy Operations:Dummy operations(not present in actual algorithm)are performed at random tim

26、es,keeping the total execution time constantAffects the throughputShuffling of Operations:Independent operations such as,16 AES S-box lookups for AES-128 can be performed in arbitrary orderDoes not affect throughput as muchNumber of operations that can be shuffled are limited depending on the algori

27、thm and the architecture of the implementationS.Sen20 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceOperation 1Operation 2TimeTimeAmplitudeAmplitudeDummy OperationDummy OperationOperation 1Operation 2Dummy OperationConstant Execution TimeTimeTimeAmplitudeAmplitudeOperation 2

28、Operation 1Operation 2Operation 1Constant Execution Time 2024 IEEE International Solid-State Circuits ConferenceOutlineWhy do Side-Channels Matter?Side-Channel FundamentalsRole of Circuits in SCA CountermeasuresSwitch CapacitorBuckSeries LDOShunt LDOArchitecturalClocking Slew+EM CountermeasuresAttac

29、k DetectorsSummary and SCA MetricsS.Sen21 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceCaution:Measurement VariabilityThere is huge measurement variability,which makes it hard to compare the numbers from different IC i

30、mplementations:Power SCA Attack:Resistance used100mOhm to 10 Ohm 1002=10k variation in MTDEM SCALocation of Measurement on ICEM Probe size and qualityMeasurement Noise of Test SystemAveragingExpertise of AttackerDesigners are generally not the best attackersNevertheless,each design explores interest

31、ing ideas for SCA resilience,at the circuit-level for the first time,that designers/attackers can learn from In future,community could evaluate in a unified implementation/attack setupS.Sen22 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State

32、Circuits ConferenceSwitch Capacitor Circuits for SCAS.Sen23 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceSwitch Capacitor Current EqualizerPhase 1:Load cap charged to supply voltagePhase 2:AES(crypto)operationPhase 3:O

33、utput node(Load capacitor)discharged to a fixed voltage clearing the residuePerf.(throughput)vs.area trade-off,due to the voltage droop across the load capacitorReduced switching frequency=less residue,at the expense of area(iso-droop)S.Sen24 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for

34、SCA ResilienceSupplyLogicShuntAESSupplyLogicShuntAESSupplyLogicShuntAESPhase 1Phase 2Phase 3ISSCC 09,JSSC 10 2024 IEEE International Solid-State Circuits ConferenceTradeoff in SC SCA:Reset Info vs.LossIntegrated information remains as residual voltageCritical to reset(10 x MTD benefit without reset

35、OJCAS 23)Energy Loss Reset to middle level Analog circuitry and overheadS.Sen25 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceTime Varying Transfer Function(TVTF)26 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits f

36、or SCA ResilienceAESS1:Cap.chargeS2:Supply to AESLoad CapVDDS1,S2ControlledBy TVTFISSCC 21,JSSC 22,OJCAS 23 Fixed Switching Not effectiveRandom Time VarianceUneven Cap 2024 IEEE International Solid-State Circuits ConferenceSCA Protection:Deterministic TVTFMulti-Phase Deterministic SC:Integration of

37、Power trace on multiple CapNon-linearityDoesnt increase MTD significantly(10 x)(iso-cap more phases hurt MTD due to lower cap/phase)Memory-effectDoes not help as distortion doesnt remove informationMulti-Phase Randomly connected SC Array TVTFMTD will depend on the pattern of repetition of the shuffl

38、ed capacitors(see figure)and thus we employ 2-stage LFSRPLFSR200M 105KS.Sen47 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceAttack Point ConfigurationPMOS slicesat Saturation(e.g.Current:I)PMOS slicesPushed to Linear(e.g.Current:I),SMC turns ON slices(e.g.15 20),PMOS attenua

39、tionVAESVDD AES32GlobalFeedbackSMCLoopID VSD=VDD-VAES Linear SaturationHackedSignatureAttenuatedSignatureCLKNo.of CS Slices161517VDD VAES 1.2V0.9V0.8V0.74V0.68V0.5V0.8V181920Attack PointSignature0.62V0.56VMeasured Power Signature(AC Coupled)Measured Power Signature(AC Coupled)Malicious voltage dropA

40、ttack CS in linear regionNormal operation CS in saturationCICC 22 2024 IEEE International Solid-State Circuits ConferenceMalicious Voltage Drop Attack detectionAttack detector(AD)circuit introduced to thwart such intelligent attack AD checks the voltage difference between scaled external VDD and int

41、ernal VDD.Triggers attack detection expected behavior is changed.Attack detected 1ms S.Sen48 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceFrequencyDviderFrequencyDviderAsynchronousCounterAsynchronousCounterIntelligentMaliciousVoltage DropDetector CircuitCounter EnableCounte

42、r EnableFreq.DividedRO_Out2Freq.DividedRO_Out1RingOscillatorVDDAES RO OutputTQT F/FTQT F/FTQT F/FVDDFrequency DividerOutputUpper Limit 16bLower Limit 16bCompare EN 1bTime to Count 16bCICC 22 2024 IEEE International Solid-State Circuits ConferenceArchitectural/Arithmetic CountermeasuresS.Sen49 of 72I

43、SSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceArchitectural 2024 IEEE International Solid-State Circuits ConferenceHeterogeneous Sbox ShufflingS-boxes Consume 30%of AES powerSignificant Leakage point RandomizationRandomized byte-order shuffling using Heterogeneous Sboxes time-vari

44、ant dataflowtwo distinct GF 1.92x current variationLinear Masked MixColumnsDual-Rail Key AdditionMTD:1200 x(12M,CPA)S.Sen50 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceVLSI 19,JSSC 20 2024 IEEE International Solid-State Circuits ConferenceNon-Linear LDO+Arithmetic Transfor

45、mTime vs.Freq.Domain CPA Linear LDOs pushes leakage to higher freq.CountermeasuresHigh BW non-linear digital low-dropout(NL-DLDO)static+dynamic clampRandomize thresholdsArithmetic Tech VLSI 19MTD:250,000 x R-NL-DLDO:1900 xArithmetic:1100 x1B CPA,CEMAS.Sen51 of 72ISSCC 24 Tutorial 6:Recent Advances i

46、n Circuits for SCA ResilienceVLSI 21,JSSC 22 2024 IEEE International Solid-State Circuits ConferenceRandom Additive MaskingPhysical Security Techniques are not Provably SecureRandom Additive Masking isNon-linear Sbox operations incur significant area overheads for masked multiplication and inversion

47、 120%in Area,Power(100-300%as per ACNS 2008)CountermeasuresAdditive MaskingRequires Attack DetectionQuickly trade-off throughput for a higher level of SCA-resistanceMTD:40000 x(1B CPA,CEMA)S.Sen52 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceISSCC 22 2024 IEEE International

48、 Solid-State Circuits ConferenceMultiplicative MaskingMultiplicative vs.Additive Masking 1.8x lower areaMM vulnerable to zero-value attacksa balanced zero-value detector to detect and counteract these attacks10%area,power overheadMTD:34000 x 850M CPA 1B CEMAS.Sen53 of 72ISSCC 24 Tutorial 6:Recent Ad

49、vances in Circuits for SCA ResilienceVLSI 22 2024 IEEE International Solid-State Circuits ConferenceRouting and EM CountermeasuresS.Sen54 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceRouting/EM Techniques 2024 IEEE International Solid-State Circuits ConferenceDifferent EM P

50、robes CEMA,L-CEMADifferent EM SCA Probes(10mm,1mm and 100um diameter)S.Sen55 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceISSCC 20,JSSC 21ESSIRC 22ISSCC 21,JSSC 22 2024 IEEE International Solid-State Circuits ConferenceReduced EM Leakage Power Grid DesignBreak-up power grid

51、 metal lines into Current ElementsDifferent arrangement of opposing current elementsQuad or 8 Pole Routing has strong promiseS.Sen56 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceMWCL 21 2024 IEEE International Solid-State Circuits ConferenceFine-Grain EM MeasurementsExperim

52、ental Measurement of some EM shielding techniques8 designs in 2 ICsLearningsEM signal!=SCA informationProtection is present but modestMTD:1.15x-2.67xS.Sen57 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceCICC 21 2024 IEEE International Solid-State Circuits ConferenceReduced E

53、M Leakage Std Cell DesignBreak-up power grid metal lines into Current ElementsDifferent arrangement of opposing current elementsQuad or 8 Pole Routing has strong promiseS.Sen58 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceTCAD 22 2024 IEEE International Solid-State Circuits

54、 ConferenceClock Port CountermeasuresS.Sen59 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceClock Slew&RandomizationClock Port CountermeasuresRandomization can be undoneSlew brings new dimensionPower trace Variance incre

55、asesSlew+RandomizationHard to be undone S.Sen60 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceCICC 23 2024 IEEE International Solid-State Circuits ConferenceFunctional Correctness using Clock SlewCombinational path delay does not change w.r.t.slew no functional failure due t

56、o setupIncreased hold time clk-q delay increases,Positive slack ensured,No functional failure After certain frequency clock will not be reaching toggle point Functional failure ,Can be mitigated by increasing buffers driving capability S.Sen61 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for

57、 SCA ResilienceFFCombinational CircuitFFData inD1_outComb_outD2 _outclkData inD1 _outComb_outD2 _outTsetup_normalPropagation delay of combinational circuit(Tdelay_critical_normal)clkData inD1 _outComb_outD2 _outTsetup_slewed=Tsetup_normalTdelay_critical_slewed=Tdelay_critical_normalThold_slewed(=Tho

58、ld_normal+D D1)Thold_normalclkTclk_q4.2Critical Path(ns)3.93.960.24.024.084.140.40.80.6Slew(GV/s)Critical path does not change with slewNo setup time violationNo Setup Time Violation0.20.40.80.6Slew(GV/s)Time(ns)0.20.40.60.81Minimum Positive Slack maintainedNo hold time violationin the design spaceN

59、o Hold Time ViolationCICC 23 2024 IEEE International Solid-State Circuits ConferenceFunctional Correctness using Clock SlewS.Sen62 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience128-bit scan chainPlaintextInput PlaintextTriggerCT_outParallel to Serial Converter DQAdd Round Ke

60、y128Sub BytesMix ColumnShift RowKey ExpandKeyRound CounterLast Round12841632128Targeted for attackCLK256AES-256Parallel ArchitectureCoarse Random.Frequency GeneratorSlewed CLK GenFine Random.256128128128Clock randomization can be post-processed and attacked using CNN/trace alignment or frequency dom

61、ain attacksSlew+RandomizationHard to be undoneSlew can be added with other countermeasures for enhanced capabilitySlew using weaker buffer introduces extremely low overhead as a countermeasureCICC 23 2024 IEEE International Solid-State Circuits ConferenceSCA Attack DetectorsS.Sen63 of 72ISSCC 24 Tut

62、orial 6:Recent Advances in Circuits for SCA ResiliencePower/EM Attack Detectors 2024 IEEE International Solid-State Circuits ConferenceAttack Detector to Reduce OverheadPhysical countermeasures reduce overhead from logical/architectural countermeasuresPower overhead can be further reduced by intermi

63、ttent attack detection and detection-only-mitigation approach.S.Sen64 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceDSACSignatureReduced Local EM Leakage PowerPinAttenuated Local MetalLayer Routing DigitalSAM7-M9AES(M1-M6)CountermeasureAlways ONAttackDetectionSystemCounterme

64、asure(DSAC)Crypto Engine(AES-256)Crypto EngineOperationAttack detection systemIntermittently ON(duty cycle:350 x Current-Domain Signature Attenuation,ISSCC,pp.424-426,2020.A.Ghosh,et al.,An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source

65、andRO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control,ISSCC,pp.500-501,2021.M.Wang,et al.,“Galvanically Isolated,Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated ChargePump based Power Management”,CICC,pp.1-2,2022R.Kumar,et al.,“A SCA-Res

66、istant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear DigitalLDO Cascaded with Arithmetic Countermeasures.”,VLSI Circuits,pp.1-2,2020R.Kumar,et al.,“A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS.”,VLSI Circuits,pp.1-2,2022(DigitalMult

67、iplicative Masking)R.Kumar,et al.,“An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS.”,ISSCC.Pp.1-3,2022(Digital Boolean Masking)S.Sen75 of 72ISSCC Tutorial Template&Guide 2024 IEEE International Solid-State Circuits ConferenceReferences(SCA IC papers)D.Da

68、s et al.,“Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS.”CICC 2020:1-4A.Ghosh et al.,“Syn-STELLAR:An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation.”,IEEE J.Solid State Circuits 57(1):167-181(2022)A.Ghosh et

69、al.,“A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector forEM/Power SCA Resilient Parallel AES-256.”,CICC 2022:1-2A Singh et al.,“Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering”,ESS

70、IRC 2017.A Singh et al.,“Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering”,JSSC2019.W.Yang et al.,“An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything(IoE)Devices”,IS

71、SCC 2018.M.Kar et al.,“Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator”,JSSC2018.A Singh et al.,“Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO”,JSSC 2019.R.Kuma

72、r et al.,“A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS”,JSSC2020.R.Kumar et al.,“A 4900m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes,Linear MaskedMixColumns and Dual-Rail Key Addition”,VLSI 2019.R.K

73、umar et al.,“A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS”,JSSC2022.M.Wang et al.,“Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks”,ES

74、SIRC 2022.S.Sen76 of 77ISSCC 24 Tutorial 6:Recent Advances Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceReferences(SCA Other Papers discussed)S.Sen77 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA ResilienceD.Das et al.,“High efficiency power side-

75、channel attack immunity using noise injection in attenuated signature domain.”,HOST 2017:62-67 B.Chatterjee et al.,“RF-PUF:IoT security enhancement through authentication of wireless nodes using in-situ machine learning.”,HOST 2018:205-208 D.Das et al.,“In-field Remote Fingerprint Authentication usi

76、ng Human Body Communication and On-Hub Analytics.”,EMBC 2018,5398-5401D.Das et al.,“ASNI:Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity.”,IEEE Trans.Circuits Syst.I Regul.Pap.65-I(10):3300-3311(2018)D.Das et al.,“STELLAR:A Generic EM Side-Channel Attack Prot

77、ection through Ground-Up Root-cause Analysis.”,HOST 2019:11-20D.Das et al.,“X-DeepSCA:Cross-Device Deep Learning Side Channel Attack.”,DAC 2019:134A.Golder et al.,“Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack.”,IEEE Trans.Very Large Scale Integr.Syst.27(12):

78、2720-2733(2019)B.Chatterjee et al.,“RF-PUF:Enhancing IoT Security Through Authentication of Wireless Nodes Using In-Situ Machine Learning.”,IEEE Internet Things J.6(1):388-398(2019)D.Das et al.,“Killing EM Side-Channel Leakage at its Source.”MWSCAS 2020:1108-1111S.Maity et al.,“A 415 nW Physically a

79、nd Mathematically Secure Electro-Quasistatic HBC Node in 65nm CMOS for Authentication and Medical Applications.”,CICC 2020:1-4J.Danial et al.,“SCNIFFER:Low-Cost,Automated,Efficient Electromagnetic Side-Channel Sniffing.”,IEEE Access 8(2020)D.Das&S.Sen,“Electromagnetic and Power Side-Channel Analysis

80、:Advanced Attacks and Low-Overhead Generic Countermeasures through White-Box Approach.”,Cryptogr.4(4):30(2020)J.Blackstone et al.,“iSTELLAR:intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing.”ICCAD 2021D.H.Seo et al.,“PG-CAS:Patterned-Ground Co-Planar Capacitive Asymmetr

81、y Sensing for mm-Range EM Side-Channel Attack Probe Detection.”,ISCAS 2021:1-5D.H.Seo et al.,“Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing.”,DATE 2021:1016-1019 2024 IEEE International Solid-State Circuits ConferenceReferences(SCA Other

82、Papers discussed)D.Das et al.,“EM/Power Side-Channel Attack:White-Box Modeling and Signature Attenuation Countermeasures.”,IEEE Des.Test 38(3)(2021)D.Das et al.,“EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation.”IEEE Trans.Comput.Aided Des.Integr.Circuits Syst.41

83、(11):4927-4938(2022)A.Ghosh et al.,“EM SCA&FI Self-Awareness and Resilience with Single On-chip Loop&ML Classifiers.”,DATE 2022:592-595A.Ghosh et al.,“Electromagnetic analysis of integrated on-chip sensing loop for side-channel and fault-injection attack detection”,IEEE Microwave and Wireless Compon

84、ents Letters 32(6),784-787J.Danial et al.,“EM-X-DL:Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures.”,ACM J.Emerg.Technol.Comput.Syst.18(1):4:1-4:17(2022)A.Ghosh et al.,“Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure.”IEEE OJ

85、CAS(2023)D.H.Seo et al.,“PG-CAS:Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing.”,IEEE Open J.Circuits Syst.4:271-282(2023)D.H.Seo et al.,“Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capaci

86、tive Asymmetry Sensing.”,IEEE Trans.Comput.Aided Des.Integr.Circuits Syst.42(12):4583-4596(2023)S.Sen78 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience 2024 IEEE International Solid-State Circuits ConferenceSOTA:Circuit-level CountermeasuresRecent Progress in SSCSStarted in 20092017-2022 has seen significant progressMTD increased from 1B Focus is to review this recent SSCS progress on circuit-level countermeasures for SCAS.Sen79 of 72ISSCC 24 Tutorial 6:Recent Advances in Circuits for SCA Resilience